semiconductor packages

Abstract

A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer includes a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction perpendicular to the upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0069093 filed on June 12, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package. Background Art

[0004] With the rapid development of the electronics industry, the importance of electronic devices with high performance, fast operating speed, and miniaturized electronic components has increased. These features can be provided by stacking and mounting several semiconductor chips on a single package substrate or by stacking another package on a package. For example, a semiconductor package of the package-in-package (PIP) type or a semiconductor package of the package-on-package (POP) type can be provided. Summary of the Invention

[0005] The technical purpose of the present invention is to provide a semiconductor package, which increases the memory packages installed in the semiconductor package by arranging multiple logic semiconductor chips directly electrically connected to an interposer on the lower surface of the interposer and arranging multiple memory packages directly electrically connected to the interposer on the upper surface of the interposer.

[0006] Another technical object of the present inventive concept is to provide a semiconductor package with enhanced reliability by disposing a heat transfer unit on an upper surface of a substrate facing a plurality of logic semiconductor chips and efficiently discharging heat generated from the plurality of logic semiconductor chips to an external area.

[0007] According to an exemplary embodiment of the present invention, a semiconductor package is provided, comprising a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction perpendicular to the upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

[0008] According to an exemplary embodiment of the present disclosure, a semiconductor package includes a substrate including a first heat transfer unit disposed on an upper surface of the substrate. An interposer is disposed on the substrate. The interposer includes a first surface facing the substrate and a second surface facing away from the substrate. The interposer is connected to the substrate. A logic semiconductor chip is disposed on the first surface of the interposer. The logic semiconductor chip overlaps the first heat transfer unit in a first direction perpendicular to the upper surface of the substrate. The logic semiconductor chip is spaced apart from the first heat transfer unit in the first direction. The logic semiconductor chip is connected to the interposer. A first memory package is disposed on the second surface of the interposer. The first memory package is connected to the interposer.

[0009] According to an exemplary embodiment of the present inventive concept, a semiconductor package is provided. The semiconductor package includes a substrate including first solder balls disposed on a lower surface of the substrate. An interposer is disposed on an upper surface of the substrate. The interposer includes a first surface facing the substrate and a second surface facing away from the substrate. Second solder balls are configured to connect the upper surface of the substrate and the first surface of the interposer. A first logic semiconductor chip is disposed on the first surface of the interposer. The first logic semiconductor chip is spaced apart from the upper surface of the substrate in a first direction perpendicular to the upper surface of the substrate. Third solder balls connect the first surface of the interposer and the first logic semiconductor chip. A first memory package is disposed on the second surface of the interposer. The first memory package includes a plurality of memory semiconductor chips stacked in the first direction. A second memory package is spaced apart from the first memory package in a second direction parallel to the upper surface of the substrate. Fourth solder balls are configured to connect the second surface of the interposer to each of the first and second memory packages. A first heat transfer unit is disposed on the upper surface of the substrate and overlaps the first logic semiconductor chip in the first direction. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

[0010] The objects that the present inventive concept intends to solve are not limited to the above objects, and other objects not mentioned above may be clearly understood by those skilled in the art based on the description provided below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a top plan view illustrating a substrate, a memory package, and a second heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0013] Figure 2 is a top plan view illustrating a substrate and a heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0014] Figure 3 According to an exemplary embodiment of the present invention, Figure 1 and Figure 2 A cross-sectional view taken along line AA'.

[0015] Figure 4 is a cross-sectional view illustrating a memory package of a semiconductor package according to an exemplary embodiment.

[0016] Figure 5 is a top plan view illustrating a substrate and a heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0017] Figure 6 According to an exemplary embodiment of the present invention, Figure 5 A cross-sectional view taken along line BB'.

[0018] Figure 7 is a top plan view illustrating a substrate and a heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0019] Figure 8 According to an exemplary embodiment of the present invention, Figure 7 A cross-sectional view taken along line CC'.

[0020] Figure 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0021] Figure 10 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0022] Figure 11 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0023] Figure 12 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0024] Figure 13 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] In the following, reference will be made to Figures 1 to 4 Semiconductor packages according to some exemplary embodiments of the inventive concept are described.

[0026] Figure 1 is a top plan view illustrating a substrate, a memory package, and a second heat transfer unit of a semiconductor package according to an exemplary embodiment. Figure 2 is a top plan view illustrating a substrate and a heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept. Figure 3 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 4 is a cross-sectional view illustrating a memory package of a semiconductor package according to an exemplary embodiment.

[0027] Reference Figures 1 to 4A semiconductor package according to an exemplary embodiment includes a substrate 100, an interposer 110, a first logic semiconductor chip 121, a second logic semiconductor chip 122, first to fifth memory packages 131, 132, 133, 134, 135, a first heat transfer unit 140, a connector 145, a second heat transfer unit 150, and first to fourth solder balls 161, 162, 163, 164.

[0028] In an exemplary embodiment, the substrate 100 may be a PCB (Printed Circuit Board) or a ceramic substrate. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0029] In an exemplary embodiment in which the substrate 100 is a PCB, the substrate 100 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the substrate 100 may include at least one material selected from FR4, tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine BT, polyamide staple fiber mat (thermount), cyanate ester, polyimide, and liquid crystal polymer. The surface of the substrate 100 may be covered with solder resist. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0030] The substrate 100 may include a lower surface 100a and an upper surface 100b facing each other. For example, the lower surface 100a and the upper surface 100b may be spaced apart in a first direction Z (hereinafter, "Z direction"). The Z direction may be perpendicular to the upper surface 100b of the substrate 100.

[0031] The first solder balls 161 may be disposed on the lower surface 100a of the substrate 100. For example, Figure 3 As shown in the exemplary embodiment of the present invention, the first solder ball 161 may include a plurality of discrete solder balls spaced apart from each other. The plurality of discrete solder balls may be spaced apart from each other in a second direction X (hereinafter, "X direction") perpendicular to the first direction Z and / or a third direction Y (hereinafter, "Y direction") perpendicular to each of the Z direction and the X direction. For example, the X direction may extend parallel to the upper surface of the substrate 100. In an exemplary embodiment, the first solder ball 161 may contact a conductive socket provided on the lower surface 100a of the substrate 100. The first solder ball 161 may protrude from the lower surface 100a of the substrate 100 (for example, in the Z direction). The first solder ball 161 may be configured to electrically connect the substrate 100 to another external socket, such as a conductive socket in contact with the first solder ball.

[0032] In an exemplary embodiment, the first solder ball 161 may include at least one selected from tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0033] The interposer 110 may be disposed on the upper surface 100b of the substrate 100. The interposer 110 may include a first surface 110a facing the upper surface 100b of the substrate 100 and a second surface 110b opposite to the first surface 110a (eg, facing away from the substrate). Figure 3 As shown in the exemplary embodiment of FIG, the first surface 110a can be located on the bottom side of the interposer 110 (eg, in the Z direction), and the second surface 110b can be located on the top side of the interposer 110 (eg, in the Z direction).

[0034] In an exemplary embodiment, the interposer 110 may include at least one selected from silicone, glass, ceramic, or plastic. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0035] The interposer 110 may be electrically and physically connected to the substrate 100 through the second solder balls 162 .

[0036] The second solder balls 162 may be disposed between the first surface 110a of the interposer 110 and the upper surface 100b of the substrate 100. Figure 3 As shown in the exemplary embodiment of FIG, second solder balls 162 may include a plurality of discrete solder balls spaced apart from one another (e.g., in the X direction and / or the Y direction). The top of second solder balls 162 (e.g., in the Z direction) may directly contact first surface 110a of interposer 110, and the bottom of second solder balls (e.g., in the Z direction) may directly contact upper surface 100b of substrate 100. Second solder balls 162 may contact conductive sockets disposed on upper surface 100b of substrate 100. Furthermore, second solder balls 162 may contact conductive sockets disposed on first surface 110a of interposer 110.

[0037] In an exemplary embodiment, the second solder ball 162 may be at least one selected from tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), or a combination thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0038] A plurality of logic semiconductor chips may be disposed on the first surface 110 a of the interposer 110 .

[0039] For example, the first logic semiconductor chip 121 may be disposed on the first surface 110a of the interposer 110. The first logic semiconductor chip 121 may be disposed between the upper surface 100b of the substrate 100 and the first surface 110a of the interposer 110. The second solder balls 162 may be disposed on at least one side of the first logic semiconductor chip 121. For example, Figure 3 In the exemplary embodiment of FIG. 1 , the second solder ball 162 is disposed at one side of the first logic semiconductor chip and is spaced apart from the first logic semiconductor chip in the X direction. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0040] The first logic semiconductor chip 121 may be spaced apart from the upper surface 100 b of the substrate 100 in the Z direction. The first logic semiconductor chip 121 may not be directly electrically and physically connected to the upper surface 100 b of the substrate 100. However, the first logic semiconductor chip 121 may be electrically connected to the substrate 100 through the interposer 110.

[0041] The second logic semiconductor chip 122 may be disposed on the first surface 110a of the interposer 110. The second logic semiconductor chip 122 may be spaced apart in the X direction from the first logic semiconductor chip 121 located between the upper surface 100b of the substrate 100 and the first surface 110a of the interposer 110. The second solder balls 162 may be disposed on at least one side of the second logic semiconductor chip 122 (e.g., in the X direction).

[0042] The second logic semiconductor chip 122 may be spaced apart from the upper surface 100b of the substrate 100 in the Z direction. The second logic semiconductor chip 122 may not be directly electrically and physically connected to the upper surface 100b of the substrate 100. However, the second logic semiconductor chip 122 may be electrically connected to the substrate 100 through the interposer 110.

[0043] In an exemplary embodiment, each of the first and second logic semiconductor chips 121 and 122 may be a microprocessor. For example, each of the first and second logic semiconductor chips 121 and 122 may be a central processing unit (CPU), a controller, an application-specific integrated circuit (ASIC), or the like.

[0044] The first logic semiconductor chip 121 and the second logic semiconductor chip 122 may be electrically and physically connected to the interposer 110 through the third solder balls 163. Figure 3As shown in the exemplary embodiment of FIG. 1 , the third solder balls 163 may include a plurality of discrete solder balls spaced apart from one another (e.g., in the X direction and / or the Y direction). The tops of the third solder balls 163 (e.g., in the Z direction) may directly contact the first surface 110 a of the interposer 110 , and the bottoms of the third solder balls (e.g., in the Z direction) may directly contact the surfaces of the first and second logic semiconductor chips 121 and 122 , respectively.

[0045] although Figure 3 The illustrated exemplary embodiment includes two logic semiconductor chips disposed on the first surface 110 a of the interposer 110 , but exemplary embodiments of the present inventive concept are not limited thereto. For example, in some exemplary embodiments, only one logic semiconductor chip may be disposed on the first surface 110 a of the interposer 110 . In other exemplary embodiments, three or more logic semiconductor chips may be disposed on the first surface 110 a of the interposer 110 , spaced apart from each other in the X and / or Y directions.

[0046] The third solder balls 163 may be disposed between the first surface 110a of the interposer 110 and the first logic semiconductor chip 121. The third solder balls 163 may also be disposed between the first surface 110a of the interposer 110 and the second logic semiconductor chip 122.

[0047] The third solder balls 163 may contact conductive sockets provided on the first surface 110a of the interposer 110. The third solder balls 163 may also contact conductive sockets provided on each of the first and second logic semiconductor chips 121 and 122.

[0048] The third solder ball 163 may include at least one selected from tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), or a combination thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0049] The first heat transfer unit 140 may be disposed on the upper surface 100b of the substrate 100. The first heat transfer unit 140 may be exposed on the upper surface 100b of the substrate 100. The first heat transfer unit 140 may be disposed to face each of the first logic semiconductor chip 121 and the second logic semiconductor chip 122. For example, the first heat transfer unit 140 may overlap each of the first logic semiconductor chip 121 and the second logic semiconductor chip 122 in the Z direction. The first heat transfer unit may include a plurality of first heat transfer units. For example, Figure 2As shown in the exemplary embodiment of FIG, the first heat transfer unit 140 may include six discrete first heat transfer units disposed on the upper surface 100b of the substrate and spaced apart in the X direction and / or the Y direction. However, exemplary embodiments of the present inventive concept are not limited thereto, and the number of heat transfer units may vary.

[0050] The first heat transfer unit 140 may be spaced apart from each of the first and second logic semiconductor chips 121 and 122 in the Z direction. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in some other exemplary embodiments, the first heat transfer unit 140 may be in direct contact with each of the first and second logic semiconductor chips 121 and 122.

[0051] The first heat transfer unit 140 may be electrically insulated from the conductive socket and wiring provided inside the substrate 100. In addition, the first heat transfer unit 140 may be electrically insulated from the interposer 110.

[0052] although Figure 2 The exemplary embodiment depicts six first heat transfer units 140 spaced apart from each other in the X and Y directions, but exemplary embodiments of the present inventive concept are not limited thereto. For example, in an exemplary embodiment, the first heat transfer units 140 may be disposed on the upper surface 100 b of the substrate 100 to overlap with the plurality of logic semiconductor chips disposed on the first surface 110 a of the interposer 110 .

[0053] The second heat transfer unit 150 may be disposed on an edge side surface of the substrate 100. The second heat transfer unit 150 may be exposed to the lower surface 100a of the substrate 100, the upper surface 100b of the substrate 100, and the side surface of the substrate 100.

[0054] The second heat transfer unit 150 may be spaced apart from the first heat transfer unit 140 in the X direction. In an exemplary embodiment, the second heat transfer unit 150 may not overlap with the interposer 110 in the Z direction. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in other exemplary embodiments, at least a portion of the second heat transfer unit 150 may overlap with the interposer 110 in the Z direction.

[0055] The second heat transfer unit 150 may be electrically insulated from the conductive socket and wiring provided inside the base plate 100 .

[0056] although Figure 2 Six second heat transfer units 150 are depicted as being spaced apart from each other in the X direction and / or the Y direction, but exemplary embodiments of the present inventive concept are not limited thereto. For example, the second heat transfer units 150 may be disposed on edge side surfaces of the substrate 100 to correspond to the first heat transfer units 140 disposed on the upper surface 100 b of the substrate 100 .

[0057] The connector 145 may be provided inside the base plate 100. The connector 145 may connect the first heat transfer unit 140 and the second heat transfer unit 150.

[0058] The connector 145 may be electrically insulated from the conductive socket and wiring provided inside the substrate 100 .

[0059] In an exemplary embodiment, each of the first heat transfer unit 140, the connector 145, and the second heat transfer unit 150 may include at least one of copper (Cu) and nickel (Ni). However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in other exemplary embodiments, each of the first heat transfer unit 140, the second heat transfer unit 150, and the connector 145 may include a material having a high heat transfer rate that does not include copper (Cu) and nickel (Ni).

[0060] The first heat transfer unit 140, the connector 145, and the second heat transfer unit 150 can discharge heat generated from each of the first and second logic semiconductor chips 121 and 122 to the outside of the semiconductor package. For example, the heat generated from each of the first and second logic semiconductor chips 121 and 122 can be sequentially transferred from the first heat transfer unit 140, which overlaps with the first and second logic semiconductor chips in the Z direction, to the electrically insulated connector 145 inside the substrate and the second heat transfer unit 150 on the edge side surface of the substrate. The heat can then be effectively discharged to the outside of the semiconductor package.

[0061] A plurality of memory packages 130 may be disposed on the second surface 110b of the interposer 110. In exemplary embodiments, the plurality of memory packages 130 may be spaced apart from each other in the X direction and / or the Y direction.

[0062] For example, Figure 3 As shown, the first to fifth memory packages 131, 132, 133, 134, 135 may be disposed on the second surface 110b of the interposer 110 and spaced apart from each other in the X direction. Figure 1 As shown, additional memory packages may be disposed on the second surface 110 b of the interposer and spaced apart from the first to fifth memory packages 131 , 132 , 133 , 134 , 135 in the Y direction.

[0063] The plurality of memory packages 130 may be electrically and physically connected to the interposer 110 through the fourth solder balls 164, respectively. Figure 3 As shown in the exemplary embodiment of FIG. 5 , the fourth solder ball 164 may include a plurality of discrete solder balls spaced apart from each other (eg, in the X direction and / or the Y direction).

[0064] although Figure 1 The exemplary embodiment includes 15 memory packages 130 disposed on the second surface 110 b of the interposer 110 , but exemplary embodiments of the present inventive concept are not limited thereto. For example, the number of memory packages 130 disposed on the second surface 110 b of the interposer 110 may vary.

[0065] Will refer to Figure 4 Exemplary embodiments of a plurality of memory packages 130 are exemplarily described.

[0066] Reference Figure 4 The first memory package 131 may include a buffer semiconductor chip 10 , first to fourth memory semiconductor chips 21 , 22 , 23 , 24 , first to fifth connection terminals 31 , 32 , 33 , 34 , 35 , first to fourth vias 41 , 42 , 43 , 44 and a mold layer 50 .

[0067] The buffer semiconductor chip 10 may be disposed at a lowermost portion (eg, in the Z direction) of the first memory package 131 .

[0068] The first to fourth memory semiconductor chips 21, 22, 23, 24 may be sequentially stacked on the buffer semiconductor chip 10 in the Z direction. Figure 4 The exemplary embodiment shown in FIG includes four memory semiconductor chips stacked on the buffer semiconductor chip 10, but exemplary embodiments of the present inventive concept are not limited thereto. For example, the number of memory semiconductor chips stacked on the buffer semiconductor chip 10 is not limited, and may include less than four memory semiconductor chips or five or more memory semiconductor chips.

[0069] In an exemplary embodiment, each of the first to fourth memory semiconductor chips 21, 22, 23, and 24 may be a volatile memory semiconductor chip such as a dynamic random access memory DRAM or a static random access memory SRAM, or a nonvolatile memory semiconductor chip such as a phase change random access memory PRAM, a magnetoresistive random access memory MRAM, a ferroelectric random access memory FeRAM, or a resistive random access memory RRAM. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0070] The first connection terminal 31 may be provided on the lower surface of the buffer semiconductor chip 10. For example, Figure 4 As shown in the exemplary embodiment of FIG. 1 , the first connection terminals 31 may be provided on the lower surface (eg, in the Z direction) of the buffer semiconductor chip 10 . The first connection terminals 31 may include a conductive material and may be electrically connected to the fourth solder balls 164 .

[0071] The second connection terminal 32 can be arranged between the buffer semiconductor chip 10 and the first memory semiconductor chip 21 (for example, in the Z direction). The third connection terminal 33 can be arranged between the first memory semiconductor chip 21 and the second memory semiconductor chip 22 (for example, in the Z direction). The fourth connection terminal 34 can be arranged between the second memory semiconductor chip 22 and the third memory semiconductor chip 23 (for example, in the Z direction). The fifth connection terminal 35 can be arranged between the third memory semiconductor chip 23 and the fourth memory semiconductor chip 24 (for example, in the Z direction). The second to fifth connection terminals 32, 33, 34, 35 may include conductive material. In an exemplary embodiment, each of the first to fifth connection terminals may include a plurality of connection terminals spaced apart in the X direction. For example, in Figure 4 In the illustrated exemplary embodiment, the first to fifth connection terminals 31 , 32 , 33 , 34 , 35 each include three connection terminals.

[0072] The first via 41 may be provided to penetrate the buffer semiconductor chip 10 in the Z direction. The first via 41 may be connected to each of the first connection terminal 31 and the second connection terminal 32. For example, Figure 4 As shown in the exemplary embodiment of FIG, the top of the first connection terminal 31 (e.g., in the Z direction) can contact the bottom of the first via 41 (e.g., in the Z direction). The top of the first via 41 (e.g., in the Z direction) can contact the bottom of the second connection terminal 32 (e.g., in the Z direction).

[0073] The second via 42 may be provided to penetrate the first memory semiconductor chip 21 in the Z direction. The second via 42 may be connected to each of the second connection terminal 32 and the third connection terminal 33. For example, Figure 4 As shown in the exemplary embodiment of FIG, the top of the second connection terminal 32 (e.g., in the Z direction) can contact the bottom of the second via 42 (e.g., in the Z direction). The top of the second via 42 (e.g., in the Z direction) can contact the bottom of the third connection terminal 33 (e.g., in the Z direction).

[0074] The third via 43 may be provided to penetrate the second memory semiconductor chip 22 in the Z direction. The third via 43 may be connected to each of the third connection terminal 33 and the fourth connection terminal 34. For example, Figure 4 As shown in the exemplary embodiment of FIG, the top of the third connection terminal 33 (e.g., in the Z direction) can contact the bottom of the third via 43 (e.g., in the Z direction). The top of the third via 43 (e.g., in the Z direction) can contact the bottom of the fourth connection terminal 34 (e.g., in the Z direction).

[0075] The fourth via 44 may be provided to penetrate the third memory semiconductor chip 23 in the Z direction. The fourth via 44 may be connected to each of the fourth connection terminal 34 and the fifth connection terminal 35. For example, Figure 4 As shown in the exemplary embodiment of FIG, the top of the fourth connection terminal 34 (e.g., in the Z direction) can contact the bottom of the fourth via 44 (e.g., in the Z direction). The top of the fourth via 44 (e.g., in the Z direction) can contact the bottom of the fifth connection terminal 35 (e.g., in the Z direction).

[0076] The conductive through-electrode may be provided in each of the first to fourth vias 41, 42, 43, and 44. In an exemplary embodiment, the conductive through-electrode may include at least one selected from aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr). However, exemplary embodiments of the present inventive concept are not limited thereto.

[0077] The first to fourth memory semiconductor chips 21 , 22 , 23 , 24 may be electrically connected to the buffer semiconductor chip 10 through second to fifth connection terminals 32 , 33 , 34 , 35 and second to fourth vias 42 , 43 , 44 .

[0078] The mold layer 50 may be disposed on the upper surface (e.g., in the Z direction) of the buffer semiconductor chip 10 to cover the first to fourth memory semiconductor chips 21, 22, 23, and 24. The mold layer 50 may be disposed between the buffer semiconductor chip 10 and the first memory semiconductor chip 21, between the first memory semiconductor chip 21 and the second memory semiconductor chip 22, between the second memory semiconductor chip 22 and the third memory semiconductor chip 23, and between the third memory semiconductor chip 23 and the fourth memory semiconductor chip 24.

[0079] In an exemplary embodiment, the mold layer 50 may include epoxy molding compound (EMC) or two or more silicone hybrid materials. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0080] In an exemplary embodiment, the second to fifth memory packages 132, 133, 134, 135 may have a similar configuration to the first memory package 131 described above. However, the exemplary embodiment is not limited thereto. For example, in other exemplary embodiments, at least one of the second to fifth memory packages 132, 133, 134, 135 may have a different configuration from the first memory package 131.

[0081] The fourth solder ball 164 may be disposed between each of the first to fifth memory packages 131 , 132 , 133 , 134 , 135 and the second surface 110 b of the interposer 110 .

[0082] The fourth solder balls 164 may contact the conductive sockets provided on the second surface 110b of the interposer 110. In addition, the fourth solder balls 164 may contact the first connection terminals 31 provided on each of the first to fifth memory packages 131, 132, 133, 134, 135.

[0083] In an exemplary embodiment, the fourth solder ball 164 may include at least one selected from tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), or a combination thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0084] In an exemplary embodiment, an additional molding layer may be provided between the substrate 100 and the interposer 110. For example, the additional molding layer may include epoxy molding compound EMC or two or more silicone hybrid materials. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0085] According to some exemplary embodiments, a semiconductor package can increase the memory packages installed in the semiconductor package by setting a plurality of logic semiconductor chips electrically connected and directly connected to the interposer 110 on a first surface 110a of the interposer 110 facing the substrate 100 and setting a plurality of memory packages 130 electrically connected and directly connected to the interposer 110 on a second surface 110b of the interposer 110.

[0086] Furthermore, the semiconductor package according to some exemplary embodiments may efficiently discharge heat generated from the plurality of logic semiconductor chips to the outside of the semiconductor package by providing the heat transfer units 140 and 150 on the upper surface 100 b of the substrate 100 facing the plurality of logic semiconductor chips.

[0087] In the following, reference will be made to Figure 5 and Figure 6Semiconductor packages according to some other exemplary embodiments are described. Figure 2 and Figure 3 The semiconductor package shown is different, and the description of the same elements of the previous embodiments may not be repeated.

[0088] Figure 5 is a top plan view illustrating a substrate and a heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept. Figure 6 According to an exemplary embodiment of the present invention, Figure 5 A cross-sectional view taken along line BB'.

[0089] Reference Figure 5 and Figure 6 , in the semiconductor package according to an exemplary embodiment of the present inventive concept, the first heat transfer unit 240 may extend in the X-direction to a side edge of the upper surface 200 b of the substrate 200 .

[0090] An upper surface of the first heat transfer unit 240 may be exposed on the upper surface 200 b of the substrate 200 , and a side surface of the first heat transfer unit 240 may be exposed on the side surface of the substrate 200 .

[0091] The second solder balls 262 may be disposed between the first logic semiconductor chip 121 and the second logic semiconductor chip 122 (e.g., in the X direction). The second solder balls 262 may not overlap with the first heat transfer unit 240 in the Z direction. However, exemplary embodiments of the present inventive concept are not limited thereto. The first solder balls 161 may be disposed on the lower surface 200 a of the substrate 200.

[0092] In the following, reference will be made to Figure 7 and Figure 8 Semiconductor packages according to other exemplary embodiments are described. Figure 2 and Figure 3 The semiconductor package shown is different, and the description of the same elements of the previous embodiments may not be repeated.

[0093] Figure 7 is a top plan view illustrating a substrate and a heat transfer unit of a semiconductor package according to an exemplary embodiment of the inventive concept. Figure 8 According to an exemplary embodiment of the present invention, Figure 7 A cross-sectional view taken along line CC'.

[0094] Reference Figure 7 and Figure 8In the semiconductor package according to an exemplary embodiment of the present inventive concept, the first heat transfer unit 340 may extend in the X direction to the side edge of the upper surface 300 b of the substrate 300. The second heat transfer unit 350 may be disposed on the first heat transfer unit 340 on the side edge of the upper surface 300 b of the substrate 300 (e.g., in the Z direction).

[0095] A portion of an upper surface of the first heat transfer unit 340 may be exposed on the upper surface 300 b of the substrate 300 , and a side surface of the first heat transfer unit 340 may be exposed on the side surface of the substrate 300 .

[0096] The second heat transfer unit 350 may be in contact with the first heat transfer unit 340. For example, the bottom (e.g., in the Z direction) of the second heat transfer unit 350 may be disposed on the top (e.g., in the Z direction) of the first heat transfer unit 340 located on the side edge of the substrate 300. The second heat transfer unit 350 may extend in the Z direction on the edge of the upper surface 300b of the substrate 300. For example, Figure 8 As shown in the exemplary embodiment of FIG, the second heat transfer unit 350 may extend to a height substantially the same as the height of the top surface of the interposer 110 (e.g., the distance between the top surface of the second heat transfer unit and the upper surface of the substrate 300 in the Z direction). However, exemplary embodiments of the present inventive concept are not limited thereto. The second heat transfer unit 350 may be spaced apart from the interposer 110 in the X direction.

[0097] The second solder balls 362 may be disposed between the first logic semiconductor chip 121 and the second logic semiconductor chip 122 (e.g., in the X direction). In an exemplary embodiment, the second solder balls 362 may not overlap with the first heat transfer unit 340 in the Z direction. However, exemplary embodiments of the present inventive concept are not limited thereto. The first solder balls 161 may be disposed on the lower surface 300 a of the substrate 300.

[0098] In the following, reference will be made to Figure 9 A semiconductor package according to another exemplary embodiment is described. Figure 3 The semiconductor packages shown are different, and the description of the same elements of the previously described embodiments may not be repeated.

[0099] Figure 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0100] exist Figure 9 In the exemplary embodiment of the semiconductor package shown, the third logic semiconductor chip 423 may be disposed on the second surface 110b of the interposer 110. Figure 9In the exemplary embodiment shown, the third logic semiconductor chip 423 is disposed between the second memory package 132 and the third memory package 134 (e.g., in the X direction). However, exemplary embodiments of the present inventive concept are not limited thereto, and the third logic semiconductor chip 423 may be disposed on different portions of the second surface 110 b of the interposer. Furthermore, in some exemplary embodiments, a plurality of third logic semiconductor chips 423 may be disposed on the second surface 110 b of the interposer 110 in various arrangements.

[0101] In the following, reference will be made to Figure 10 A semiconductor package according to an exemplary embodiment is described. Figure 3 The semiconductor packages shown are different, and the description of the same elements of the previously described embodiments may not be repeated.

[0102] Figure 10 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0103] Reference Figure 10 In semiconductor packages according to some other exemplary embodiments, at least a portion of the first logic semiconductor chip 121 may be disposed within a first recess R1 formed on the substrate 500. Furthermore, at least a portion of the second logic semiconductor chip 122 may be disposed within a second recess R2 formed on the substrate 500. Both the first recess R1 and the second recess R2 may be formed to be recessed into the substrate 500 from the upper surface 500 b of the substrate 500.

[0104] The first heat transfer unit 540 may be provided along at least one sidewall and bottom surface of each of the first groove R1 and the second groove R2. Figure 10 As shown in the exemplary embodiment of the present invention, the first heat transfer unit 540 may extend along each sidewall of the first groove R1 and the second groove R2 and the bottom surface of the first groove R1 and the second groove R2. The sidewalls of the first groove R1 and the second groove R2 may extend in the Z direction, and the bottom surfaces of the first groove R1 and the second groove may extend in the X direction. However, exemplary embodiments of the present inventive concept are not limited thereto. The second heat transfer unit 550 may be spaced apart from the first heat transfer unit 540 in the X direction.

[0105] The connector 545 may be provided in the base plate 500. The connector 545 may be connected between the first heat transfer unit 540 and the second heat transfer unit 550. Figure 10 In the illustrated exemplary embodiment, the connector 545 extends in the X direction between the first heat transfer unit 540 and the second heat transfer unit 550. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0106] The second solder balls 562 may be disposed between the first surface 110a of the interposer 110 and the upper surface 500b of the substrate 500. The first solder balls 161 may be disposed on the lower surface 500a of the substrate 500.

[0107] In the following, reference will be made to Figure 11 A semiconductor package according to an exemplary embodiment is described. Figure 3 The semiconductor packages shown are different, and the description of the same elements of the previously described embodiments may not be repeated.

[0108] Figure 11 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0109] Reference Figure 11 In the semiconductor package according to the exemplary embodiment of the present inventive concept, at least a portion of the first logic semiconductor chip 121 may be disposed within a first recess R1 formed on the substrate 600. Furthermore, at least a portion of the second logic semiconductor chip 122 may be disposed within a second recess R2 formed on the substrate 600. Both the first recess R1 and the second recess R2 may be formed to be recessed from the upper surface 600 b of the substrate 600 into the substrate 600.

[0110] The first heat transfer unit 640 may be disposed along at least one sidewall and bottom surface of each of the first groove R1 and the second groove R2. The first heat transfer unit 640 may also extend along the upper surface 600b of the substrate 600 in the X direction from a portion of the first heat transfer unit 640 disposed on the sidewall to a side edge of the upper surface 600b of the substrate 600.

[0111] An upper surface of the first heat transfer unit 640 may be exposed to the upper surface 600 b of the substrate 600 , and a side surface of the first heat transfer unit 640 may be exposed to the side surface of the substrate 600 .

[0112] The second solder balls 662 may be disposed between the first logic semiconductor chip 121 and the second logic semiconductor chip 122 (e.g., in the X direction). In an exemplary embodiment, the second solder balls 662 may not overlap with the first heat transfer unit 640 in the Z direction. However, exemplary embodiments of the present inventive concept are not limited thereto. The first solder balls 161 may be disposed on the lower surface 600a of the substrate 600.

[0113] In the following, reference will be made to Figure 12 A semiconductor package according to an exemplary embodiment is described. Figure 3 The semiconductor packages shown are different, and the description of the same elements of the previously described embodiments may not be repeated.

[0114] Figure 12is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0115] Reference Figure 12 In the semiconductor package according to the exemplary embodiment of the present inventive concept, at least a portion of the first logic semiconductor chip 121 may be disposed within a first recess R1 formed on the substrate 700. Furthermore, at least a portion of the second logic semiconductor chip 122 may be disposed within a second recess R2 formed on the substrate 700. Both the first recess R1 and the second recess R2 may be formed to be recessed from the upper surface 700 b of the substrate 700 into the substrate 700.

[0116] The first heat transfer unit 740 may be disposed along at least one sidewall and bottom surface of each of the first groove R1 and the second groove R2. The first heat transfer unit 740 may extend along the upper surface 700b of the substrate 700 in the X direction from a portion of the first heat transfer unit 740 disposed on the sidewall to a side edge of the upper surface 700b of the substrate 700.

[0117] The second heat transfer unit 750 may be disposed on the first heat transfer unit 740 (e.g., in the Z direction). For example, the second heat transfer unit 750 may be disposed on a side edge of the first heat transfer unit 740 and may extend in the Z direction on an edge of the upper surface 700b of the substrate 700. The second heat transfer unit 750 may be spaced apart from the interposer 110 in the X direction.

[0118] The second solder balls 762 may be disposed between the first logic semiconductor chip 121 and the second logic semiconductor chip 122 (e.g., in the X direction). In an exemplary embodiment, the second solder balls 762 may not overlap with the first heat transfer unit 740 in the Z direction. However, exemplary embodiments of the present inventive concept are not limited thereto. The first solder balls 161 may be disposed on the lower surface 700a of the substrate 700.

[0119] In the following, reference will be made to Figure 13 A semiconductor package according to an exemplary embodiment of the present invention is described. Figure 10 The semiconductor packages shown are different, and the description of the same elements of the previously described embodiments may not be repeated.

[0120] Figure 13 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0121] Reference Figure 13 In the semiconductor package according to example embodiments, the third logic semiconductor chip 823 may be disposed on the second surface 110 b of the interposer 110 .

[0122] Despite Figure 13In the exemplary embodiment shown in FIG. 1 , the third logic semiconductor chip 823 is disposed between the second memory package 132 and the third memory package 134 (e.g., in the X direction), but exemplary embodiments of the present inventive concept are not limited thereto. For example, in other exemplary embodiments, the position and number of the third logic semiconductor chips 823 disposed on the second surface 110 b of the interposer 110 may vary.

[0123] Although exemplary embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the exemplary embodiments described above, but can be manufactured in various forms without changing the technical concept or basic features of the present invention, and can be implemented in other specific forms by those skilled in the art. Therefore, it will be understood that the exemplary embodiments described above are merely exemplary and should not be construed as limiting.

Claims

1. A semiconductor package, comprising: substrate; an interposer, the interposer being disposed on the substrate, the interposer comprising a first surface facing the substrate and a second surface facing away from the substrate; a first logic semiconductor chip disposed on the first surface of the interposer, the first logic semiconductor chip being spaced apart from the substrate in a first direction perpendicular to the upper surface of the substrate; a first memory package disposed on the second surface of the interposer; a second memory package disposed on the second surface of the interposer, the second memory package being spaced apart from the first memory package in a second direction parallel to the upper surface of the substrate; and a first heat transfer unit, the first heat transfer unit being disposed on a surface of the substrate facing the first logic semiconductor chip, the first heat transfer unit including a completely exposed upper surface facing the first logic semiconductor chip, the upper surface of the first heat transfer unit overlapping with the first logic semiconductor chip in the first direction and spaced apart from the first logic semiconductor chip in the first direction.

2. The semiconductor package according to claim 1, further comprising: a second heat transfer unit, the second heat transfer unit being disposed on an edge side surface of the substrate; and A connector is provided inside the base plate, and is configured to connect the first heat transfer unit and the second heat transfer unit.

3. The semiconductor package according to claim 1, wherein The first heat transfer unit extends to a side edge of the substrate in the second direction.

4. The semiconductor package according to claim 3, further comprising a second heat transfer unit extending along the first direction on the side edge of the substrate, the second heat transfer unit being spaced apart from the interposer in the second direction, and the second heat transfer unit being in contact with the first heat transfer unit.

5. The semiconductor package according to claim 1, wherein The substrate includes a groove recessed into the substrate, and At least a portion of the first logic semiconductor chip is disposed within the groove. The semiconductor package according to claim 5 , wherein: The first heat transfer unit is disposed along at least one sidewall and a bottom surface of the groove. 7 . The semiconductor package according to claim 1 , further comprising a second logic semiconductor chip disposed on the second surface of the interposer.

8. The semiconductor package according to claim 1, wherein The first memory package includes a plurality of memory semiconductor chips stacked in the first direction.

9. The semiconductor package according to claim 8, wherein The plurality of memory semiconductor chips include vias extending in the first direction, the vias being configured to electrically connect the plurality of memory semiconductor chips to one another.

10. The semiconductor package according to claim 1, wherein The first heat transfer unit is electrically insulated from the interposer.

11. The semiconductor package according to claim 1, wherein The substrate is a printed circuit board substrate.

12. A semiconductor package, comprising: a substrate, the substrate comprising a first heat transfer unit disposed on an upper surface of the substrate, the first heat transfer unit comprising a completely exposed upper surface; an interposer, the interposer being disposed on the substrate, the interposer comprising a first surface facing the substrate and a second surface facing away from the substrate, the interposer being connected to the substrate; a logic semiconductor chip disposed on the first surface of the interposer, the logic semiconductor chip overlapping the upper surface of the first heat transfer unit in a first direction perpendicular to the upper surface of the substrate, the logic semiconductor chip being spaced apart from the upper surface of the first heat transfer unit in the first direction, and the logic semiconductor chip being connected to the interposer; and A first memory package is disposed on the second surface of the interposer, the first memory package being connected to the interposer.

13. The semiconductor package according to claim 12, further comprising a second memory package, the second memory package being disposed on the second surface of the interposer, the second memory package being spaced apart from the first memory package in a second direction parallel to the upper surface of the substrate.

14. The semiconductor package according to claim 12, wherein The first memory package includes a plurality of memory semiconductor chips stacked in the first direction.

15. The semiconductor package according to claim 12, further comprising: a second heat transfer unit, the second heat transfer unit being disposed on an edge side surface of the substrate; and A connector is provided inside the base plate, and is configured to connect the first heat transfer unit and the second heat transfer unit.

16. The semiconductor package according to claim 12, wherein The first heat transfer unit extends in a second direction parallel to the upper surface of the substrate.

17. The semiconductor package according to claim 12, wherein: The substrate includes a groove recessed into the substrate; and At least a portion of the logic semiconductor chip is disposed within the groove.

18. A semiconductor package, comprising: a substrate comprising first solder balls disposed on a lower surface of the substrate; an inner plug-in unit, the inner plug-in unit being disposed on the upper surface of the substrate, the inner plug-in unit comprising a first surface facing the substrate and a second surface facing away from the substrate; a second solder ball configured to connect the upper surface of the substrate and the first surface of the interposer; a first logic semiconductor chip disposed on the first surface of the interposer, the first logic semiconductor chip being spaced apart from the upper surface of the substrate in a first direction perpendicular to the upper surface of the substrate; a third solder ball connecting the first surface of the interposer and the first logic semiconductor chip; a first memory package disposed on the second surface of the interposer, the first memory package comprising a plurality of memory semiconductor chips stacked in the first direction; a second memory package spaced apart from the first memory package in a second direction parallel to the upper surface of the substrate; a fourth solder ball configured to connect the second surface of the interposer with each of the first memory package and the second memory package; and a first heat transfer unit disposed on the upper surface of the substrate, the first heat transfer unit including a completely exposed upper surface facing the first logic semiconductor chip, the upper surface of the first heat transfer unit overlapping with the first logic semiconductor chip in the first direction and spaced apart from the first logic semiconductor chip in the first direction.

19. The semiconductor package according to claim 18, further comprising: a second logic chip, the second logic chip being disposed on the first surface of the interposer, wherein: the second logic semiconductor chip is spaced apart from the first logic semiconductor chip in the second direction; and The second logic semiconductor chip is spaced apart from the upper surface of the substrate in the first direction.

20. The semiconductor package according to claim 18, wherein The first heat transfer unit is electrically insulated from the interposer.

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