System and method for a self-aligned trench MOSFET contact

Abstract

The present invention relates to a system and method for self-aligned trench MOSFET contacts. Embodiments provide a system and method including a semiconductor device fabricated by forming hard mask pillars on a surface of a substrate and forming sacrificial spacers on a first side and a second side of each hard mask pillar. An opening gap may be formed between adjacent sacrificial spacers. The semiconductor device may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the opening gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources into the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers within the substrate to form contact trenches, and filling the contact trenches with a conductive material to form contacts.

Description

Background Art

[0001] For trench MOSFET devices, reducing the resistance of the channel region (i.e., R ON ) allows more current to travel through the switch. Reducing the device pitch of semiconductor circuits is one way to achieve a lower R ON . One way to reduce the device pitch is to use a lithography process that positions the devices closer to each other on a substrate. For current trench MOSFET manufacturing processes, the lithography capabilities are limited to a minimum device pitch of about 200 nm or 300 nm. For example, a KrF scanner has a minimum device pitch of about 300 nm, and an ArF scanner has a minimum device pitch of about 200 nm. Reducing the device pitch below the minimum lithography capabilities requires additional techniques. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments are described with reference to the following drawings. In all the drawings, the same reference numerals are used to refer to like features and components. The features shown in the drawings are not necessarily drawn to scale. Some features of the embodiments may be enlarged in scale or shown in a somewhat schematic form, and for clarity and conciseness, some details of the elements may not be shown.

[0003] Figure 1 is a flowchart of a method of manufacturing an embodiment of a semiconductor device;

[0004] Figures 2-5 is a cross-sectional side view of an embodiment of a semiconductor device during the manufacturing method;

[0005] Figure 6 is a cross-sectional top view of an embodiment of a semiconductor device;

[0006] Figures 7-14 is a cross-sectional side view of an embodiment of a semiconductor device during the manufacturing method;

[0007] Figure 15 is a cross-sectional top view of an embodiment of a semiconductor device;

[0008] Figure 16 is a flowchart of a possible method of manufacturing a second embodiment of a semiconductor device; and

[0009] Figures 17-20 is a cross-sectional side view of a second embodiment of a semiconductor device during the manufacturing method. DETAILED DESCRIPTION

[0010] The embodiments disclosed herein include using spacers during the manufacture of semiconductor devices to reduce device pitch without changing the lithography process. Specifically, embodiments may include forming sacrificial spacers on either side of a hard mask assembly (e.g., hard mask pillars), and then removing the sacrificial spacers later in the manufacturing method to form contact trenches and contacts. These resulting contacts are aligned with gate trenches, and the device pitch is approximately half of the lithography limit. Due to the self-aligned double patterning scheme described herein, the device has a higher body / source ratio of width to smaller Si mesa. As used herein, "self-aligned" means that the contacts and electrodes are formed to be aligned with each other without performing a lithography process on each contact or electrode.

[0011] Figure 1 is a flowchart of a manufacturing method 1000 of an embodiment of a semiconductor device 100.

[0012] Figure 2 is a cross-sectional side view of an embodiment of a semiconductor device 100 during a manufacturing method. The semiconductor device 100 is fabricated on a substrate 102, which may include a variety of materials such as silicon, germanium, gallium arsenide, etc.

[0013] In an exemplary embodiment of method 1000, at stage 1020, the semiconductor device 100 includes hard mask pillars 106 that have been formed on the substrate 102. The hard mask pillars 106 may be formed by several methods, such as depositing or growing a uniform layer of hard mask material on the substrate 102, then patterning the layer, and then etching the pattern so that only certain regions of the hard mask (e.g., hard mask pillars 106) remain on the substrate 102. A lithography pattern may also be applied before the hard mask material is deposited or grown on the substrate 102 so that the hard mask material is deposited in certain regions of the pattern, while other regions (i.e., regions covered by the lithography photoresist) do not receive the hard mask material in a first location. The lithography used to etch the hard mask / hard mask pillars 106 may include KrF scanner lithography processing, ArF scanner lithography processing, etc.

[0014] After the lithography process, the hard mask pillars 106 can be thinned beyond the pattern by a controlled etching process such as chemical wash to make the thinned hard mask pillars 106 have a specific desired thickness 108. The thinning of the hard mask pillars 106 results in the hard mask pillars 106 having a thickness 108 that is less than the minimum lithography limit of the lithography processing capabilities. The minimum lithography limit depends on the wavelength of the light used to illuminate the photoresist on the semiconductor device 100 with the mask. For example, the wavelength of the KrF scanner lithography process has a minimum lithography limit for device pitch of 300 nm. The wavelength of the ArF scanner lithography process has a minimum lithography limit for device pitch of approximately 200 nm. As described below, this can also translate to other components of the semiconductor device 100 that have a thickness less than the minimum lithography limit of the lithography processing capabilities. Figure 2 The hard mask pillar 106 in

[0015] Figure 3 FIG. 6 is a cross-sectional side view of an embodiment of the semiconductor device 100 during the manufacturing method 1000. As shown in stage 1030, the semiconductor device 100 includes sacrificial spacers 110a, 110b formed around the hard mask pillar 106. The substrate 102 can be cleaned before applying the sacrificial spacers 110a, 110b such that there is no oxide between the substrate 102 and the sacrificial spacers 110a, 110b. If oxide etch chemicals are used at any time during the method 1000, the cleaning ensures that the sacrificial spacers 110a, 110b remain attached to the substrate 102. The sacrificial spacers 110a, 110b can be formed using a variety of techniques. For example, a nitride layer can be deposited uniformly as a film over the entire surface of the substrate 102. The nitride layer can then be etched downward subsequently to form the sacrificial spacers 110a and 110b.

[0016] Thus, when the nitride layer is etched, the semiconductor device 100 includes a first sacrificial spacer 110a on a first side 112a of the hard mask 106, a second sacrificial spacer 110b on a second side 112b of the hard mask 106, and an opening gap 114 outside the sacrificial spacers 110a, 110b. The first sacrificial spacer 110a can have the same size or a different size from the second sacrificial spacer 110b. The pattern of the gap 114, the first sacrificial spacer 110a, the hard mask pillar 106, the second sacrificial spacer 110b, and the gap 114 can be repeated as needed to cover the substrate 102 or an area of the substrate 102 that is designed for a specific purpose (e.g., power current).

[0017] Figure 4It shows that at stage 1040, the hard mask pillars 106 have been etched away to form additional gaps 115. The etching process is configured to remove the hard mask pillars 106 without interacting with the sacrificial spacers 110a, 110b or the substrate 102. This is one reason why the substrate 102 can be cleaned before depositing the sacrificial spacers 110a, 110b, because the substrate 102 may have a native oxide etched by the same process as the hard mask pillars 106.

[0018] In an exemplary embodiment, the first sacrificial spacer 110a includes a point 118 located between the inclined side 120 and the point side 122. The point side 122 and the inclined side 120 may be at different angles relative to the substrate 102 and / or may be curved in different ways. Thus, the gaps 114, 115 on either side of the first sacrificial spacer 110a may also be of different shapes. In some embodiments (see below Figure 18 ), the sacrificial spacers 110a, 110b may be polished to remove the point 118 so that the sacrificial spacers 110a, 110b are square, to increase the likelihood that each gap 114, 115 uniformly receives a wet etching process to form the trenches described below.

[0019] Figure 5 A cross-sectional side view of an embodiment of the semiconductor device 100 during stage 1050 of the manufacturing method 1000. The substrate 102 is etched in each of the gaps 114, 115 to form gate trenches 116. The gate trenches 116 can be etched without significantly changing the shape or size of the sacrificial spacers 110a, 110b. For example, a wet etching or dry etching process that uses a material to etch the substrate 102 without chemically interacting with the nitride of the sacrificial spacers 110a, 110b can be used to etch the gate trenches 116. The shape of the sacrificial spacers 110a, 110b (e.g., changed by polishing or etching) can also be used to adjust the shape of the gate trenches 116. For example, when the first sacrificial spacer 110a is not polished, the gate trench 116 can be deeper on the inclined side 120 of the first sacrificial spacer 110a because additional etching material can enter the substrate 102 due to the wider gap 114. In Figure 5In [the figure], the sides of the gate trench 116 are shown as vertical with a constant width 124, but other shapes and / or angles of the gate trench 116 can also be etched into the substrate 102. The width 124 can have the same dimension as the width 108 of the hard mask pillar 106 and can be, for example, less than 100 nm. There are Si mesa 130s with a width 128 between the gate trenches 116. For example, the Si mesa width 128 can be between 60 nm and 200 nm. As emphasized above, this width 128 can be less than the lithography limit that could otherwise be achieved for the semiconductor device 100. In some embodiments, the width 128 can be half of the lithography limit because the sacrificial spacers 110a, 110b are not primarily formed by a lithography process. As detailed below, the Si mesa 130 can be implanted with dopants to form channels, sources, and body regions.

[0020] Figure 6 FIG. [number] is a cross-sectional top view of an embodiment of the semiconductor device 100 at stage 1050. The top view shows the gate trenches 116 extending along the substrate 102. As described above, relative to the hard mask pillars 106, the gate trenches 116 can be formed as multiple parallel gate trenches 116 above the surface of the substrate 102. The semiconductor device 100 includes a body region 138 and a source region 140 that are designed to receive different types of doping. The body region 138 provides the positive or negative charge required to turn on the semiconductor device 100 during operation to the source region 130 and the channel (see Figure 11 )). As the Si mesa width 128 narrows in the design of the semiconductor device 100, a higher ratio of the width occupied by the body region 138 and the source region 140 may be required to avoid parasitic bipolar transistor action. This situation can be worsened if the source contact is not aligned along the Si mesa 130. The contacts disclosed herein are self-aligned to the gate trenches 116 along the body region 138 and the source region 140 to avoid parasitic bipolar transistor action.

[0021] Figure 7 FIG. [number] is a cross-sectional side view of an embodiment of the semiconductor device 100 during stage 1060 of the manufacturing method 1000. The sacrificial spacers 110a, 110b have been thinned or reduced in cross-section. Pull-back is achieved by an etching process that etches the sacrificial spacers 110a, 110b while having a minimal impact on the Si mesa 130. As shown, the result of the pull-back is that the Si mesa 130 is wider than the sacrificial spacers 110a, 110b.

[0022] Figure 8A cross-sectional side view of an embodiment of semiconductor device 100 during stage 1070 of fabrication method 1000. A layer of gate insulator or gate oxide 132 has been formed within gate trench 116 and on the exposed areas of Si mesa 130 of semiconductor device 100. For example, gate oxide 132 can be formed by growing silicon dioxide on substrate 102.

[0023] Figure 9 A cross-sectional side view of an embodiment of semiconductor device 100 during stage 1080 of fabrication method 1000. Gate trench 116 is filled with polysilicon 134 to form gate electrode 136. Polysilicon 134 can be layered and annealed over sacrificial spacers 110a, 110b.

[0024] Figure 10 A cross-sectional side view of an embodiment of semiconductor device 100 during stage 1090 of fabrication method 1000. Polysilicon 134 has been reduced such that only gate electrode 136 remains within gate trench 116. A wet etching process or a dry etching process can be used to etch polysilicon 134 without affecting sacrificial spacers 110, gate oxide 132, or Si mesa 130.

[0025] Figure 11A cross-sectional side view of an embodiment of semiconductor device 100 during stage 1100 of fabrication method 1000. Si mesa 130 is implanted with one or more dopants to form channels 140a, 140b and sources 142a, 142b in substrate 102. Dopants for channels 140a, 140b may include, for example, boron, boron ions or other similar dopants that provide positively charged holes, while dopants for sources 142a, 142b may include, for example, arsenic, arsenic ions or other similar dopants that provide negatively charged electrons to semiconductor device 100. First sacrificial spacer 110a has first channel 140a and first source 142a implanted thereunder, and second sacrificial spacer 110b has second channel 140b and second source 142b implanted thereunder. It may be possible to implant dopants directly into Si mesa 130, but dopants entering Si mesa 130 directly beneath sacrificial spacer 110a will have to pass through sacrificial spacer 110a. Thus, the implantation energy will be different for different regions of Si mesa 130, which complicates the fabrication method. Thus, channels 140a, 140b and sources 142a, 142b may be implanted at angle 144 to avoid sacrificial spacers 110a, 110b during implantation. Implant angle 144 of the dopants may result in curved dopant profiles, such as curved dopant profiles formed at the bottoms of channels 140a, 140b and sources 142a, 142b, such as 146a, 146b, 148a, 148b. Angle 144 may be between 3 degrees and 10 degrees, such as 7 degrees, to implant dopants into Si mesa 130 and avoid sacrificial spacers 110a, 110b.

[0026] Figure 12 A cross-sectional side view of an embodiment of semiconductor device 100 during stage 1110 of fabrication method 1000. Semiconductor device 100 includes insulator layer 160 formed on top of substrate 102 and surrounding sacrificial spacers 110a, 110b. Insulator layer 160 may include a variety of materials for insulating substrate 102 from a future source plate or other conductive components that may be present above insulator 160. For example, the insulator may comprise an oxide, glass or other material. Additionally, insulator 160 may be annealed, but in some examples, insulator 160 is not annealed.

[0027] Figure 13A cross-sectional side view of an embodiment of a semiconductor device 100 during stage 1120 of manufacturing method 1000. The insulator layer 160 has been etched such that the top surface 162 falls at least below the points 118 of the sacrificial spacers 110a, 110b. This enables the etching process to remove the sacrificial spacers 110a, 110b from within the insulator layer 160 to form contact trenches 164a, 164b. The contact trenches 164a, 164b are etched through the top surface 162 into the insulator layer 160 and into the source regions 142a, 142b. Additionally, as shown, the contact trenches 164a, 164b can be etched through the source regions 142a, 142b such that the contact trenches protrude into the channels 140a, 140b. In some other examples, the contact trenches 164a, 164b can be etched to different depths within the substrate 102. For example, the semiconductor device 100 can be formed such that the first contact trench extends through the first source 142a, while the second contact trench 164b is etched to only contact the second source 142b without perforating, or vice versa.

[0028] Figure 14 A cross-sectional side view of an embodiment of a semiconductor device 100 during stage 1130 of manufacturing method 1000. The contact trenches 164a, 164b have been filled with metal or other conductive material to form contacts 166a, 166b. The contacts 166a, 166b can be electrically connected and include the same conductive material as the source plate 168 that electrically connects the semiconductor device 100 to different devices or power sources.

[0029] Method 1000 ends at stage 1140, where the contacts 166a, 166b are formed and aligned to the Si mesa 130. Further processing can be performed on the semiconductor device before it is a finished product. As Figure 15 shown in the cross-sectional top view, at stage 1140, independent of the lithography process used in any previous method, the contacts 166a, 166b are self-aligned with the gate trenches 116. Thus, charging the gate electrode 136 enables current to flow through the narrow Si mesa 130, through the substrate 102 and the source plate 168, while still using a normal lithography scanner.

[0030] Figure 16Flowchart of a possible manufacturing method 2000 for a second embodiment of the semiconductor device 200. The semiconductor device 200 can be manufactured in the order indicated in the flowchart, but this is not necessary. Additionally, like the semiconductor device 100 described above, the semiconductor device 200 can be manufactured as part of a larger circuit, and the method 2000 can start at stage 2010 after additional or alternative processing is completed. The method 2000 can include several method features not shown but described above. For example, at stage 2020, a hard mask pillar 208 can be formed on the semiconductor device 200, and at stage 2030, sacrificial spacers 210a, 210b, 210c, 210d are also formed. In the method 2000, the semiconductor device 200 can include additional or alternative processing as described below.

[0031] Figure 17 Cross-sectional side view of a second embodiment of the semiconductor device 200 during stage 2033 of the manufacturing method 2000. Figure 17 Shows additional or alternative processing as described above at stage 1040 and Figure 4 before the hard mask pillar 208 described above is etched. That is, once the hard mask pillar 208 and the sacrificial spacers 210a, 210b, 210c, 210d are formed on the substrate 202, a filler material 270, such as glass or doped glass, is formed over the sacrificial spacers 210 and the hard mask pillar 208. The filler material 270 fills the gap 214 between the sacrificial spacers 210a, 210b, 210c, 210d that is not occupied by the hard mask pillar 208.

[0032] Figure 18 Cross-sectional side view of a second embodiment of the semiconductor device 200 during stage 2036 of the manufacturing method 2000. The filler material 270, the sacrificial spacers 210a, 210b, 210c, 210d, and the hard mask pillar 208 are polished so that the top surface 272 is flush with the substrate 202. This polishing makes the top surface 272 of the sacrificial spacers 210a, 210b, 210c, 210d flat, making the two sides of the sacrificial spacers uniform.

[0033] Figure 19 Cross-sectional side view of a second embodiment of the semiconductor device during stage 2040 of the manufacturing method 2000. As described above in Figure 3As shown, the hard mask 208 can be removed and / or etched with minimal impact on the sacrificial spacers 210. Additionally, the fill material 270 can also be removed and / or etched with minimal impact on the sacrificial spacers 210a, 210b, 210c, 210d. After etching the hard mask pillars 208 and the fill material 270, the semiconductor device 200 has gaps 214 on each side of the sacrificial spacers 210. The gaps 214 can thus be used to etch the gate trenches 216, as Figure 20 shown in the cross-sectional side view of. Thus, additional or alternative processing including the layered fill material 270 can be beneficial for creating a flat top surface 272, which can result in better uniformity in the depth and width of the gate trenches 216. The method 2000 can include other processing described above with respect to Figure 1 to form channels, sources, and source contacts within the semiconductor device 200. After the source contacts are filled with conductive material, the method 2000 ends 2140, and the semiconductor 200 is ready for further processing.

[0034] Example 1: Again, the present disclosure includes a method of manufacturing a semiconductor device on a substrate, the method including forming hard mask pillars on a surface of the substrate; forming sacrificial spacers on a first side and a second side of each hard mask pillar, wherein an open gap is formed between adjacent sacrificial spacers; etching the hard mask pillars to form pillar gaps; etching gate trenches into the substrate through the open gaps and the pillar gaps; forming gate electrodes within the gate trenches; implanting channels and sources into the substrate below the sacrificial spacers; forming an insulator layer around the sacrificial spacers; etching the sacrificial spacers within the substrate to form contact trenches; and filling the contact trenches with a conductive material to form contacts.

[0035] Example 2: The method according to Example 1, wherein forming the hard mask pillars includes thinning the hard mask pillars by etching.

[0036] Example 3: The method according to Example 1, including cleaning the substrate before forming the sacrificial spacers.

[0037] Example 4: The method according to Example 1, including self-aligning the contact trenches and the gate trenches.

[0038] Example 5: The method according to Example 1, including etching each sacrificial spacer before implanting the channels and the sources into the substrate.

[0039] Example 6: The method according to Example 1, including polishing each sacrificial spacer before etching the gate trenches.

[0040] Example 7: The method according to Example 1 includes forming a filler material layer within the opening gap and above the hard mask pillar; and polishing the hard mask pillar, the sacrificial spacer, and the filler material, or any combination thereof.

[0041] Example 8: The method according to Example 1, wherein implanting the channel and the source includes implanting dopants at an angle between 3 degrees and 10 degrees.

[0042] Example 9: The method according to Example 1 includes annealing the insulator layer before etching the sacrificial spacer.

[0043] Example 10: The method according to Example 1 includes etching the source after etching the sacrificial spacer, wherein the contact contacts the channel.

[0044] Example 11: The method according to Example 1, wherein forming the hard mask pillar includes KrF scanner lithography or ArF scanner lithography.

Claims

1. A semiconductor device, comprising: a silicon substrate, the silicon substrate including a surface; a gate electrode, the gate electrode being formed in a gate trench that extends from the surface into the substrate; a channel region, the channel region being adjacent to the gate electrode, the channel region including a non-uniform channel dopant distribution; a source region, the source region being adjacent to the gate electrode between the surface and the channel region, the source region including a non-uniform source dopant distribution; an insulator layer, the insulator layer being formed over the substrate; and a source contact, the source contact extending through the insulator layer, wherein the source contact includes a width less than the minimum lithography limit for the processing capabilities.

2. The semiconductor device according to claim 1, wherein the channel dopant distribution includes a curved distribution, wherein the dopant concentration directly under the source contact is lower than the dopant concentration away from the source contact.

3. The semiconductor device according to claim 1, wherein the source dopant distribution includes a curved distribution, wherein the dopant concentration directly under the source contact is lower than the dopant concentration away from the source contact.

4. The semiconductor device according to claim 1, wherein the source contact is self-aligned with the gate electrode.

5. The semiconductor device according to claim 1, including an Si mesa width less than 200 nm.

6. The semiconductor device according to claim 1, including a gate trench width less than 100 nm.

7. The semiconductor device according to claim 1, wherein the source contact extends through the source region and contacts the channel region.

8. The semiconductor device according to claim 1, including a ratio greater than two of the width of the body region to the width of the source region.

9. The semiconductor device according to claim 1, including an additional gate electrode formed in an additional gate trench positioned opposite the channel from the gate trench.

10. A method of manufacturing a semiconductor device on a substrate, comprising: forming hard mask pillars on a surface of the substrate; forming sacrificial spacers on a first side and a second side of each hard mask pillar, wherein an opening gap is formed between adjacent sacrificial spacers; etching the hard mask pillars to form pillar gaps; etching gate trenches into the substrate through the opening gaps and the pillar gaps; forming a gate electrode within the gate trenches; implanting channels and sources into the substrate under the sacrificial spacers; forming an insulator layer around the sacrificial spacers; etching the sacrificial spacers downward until different depths within the substrate are reached to form contact trenches, wherein, before etching the sacrificial spacers, the sacrificial spacers are thinned such that the sacrificial spacers have a width less than the minimum lithography limit for the processing capabilities; and filling the contact trenches with a conductive material to form contacts.

11. The method according to claim 10, wherein forming the hard mask pillars comprises: Thinning the hard mask pillars by etching.

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