Testing device, system and method

Abstract

The present application discloses a testing device, system, and method. The testing device includes: a test circuit, a power supply circuit, a detection circuit, and a processing circuit. The test circuit is connected to a chip under test and the detection circuit, the processing circuit is connected to the detection circuit, and the power supply circuit is respectively connected to the test circuit, the detection circuit, and the processing circuit; the processing circuit controls the power supply circuit to output a first voltage to the chip under test via the test circuit, and the test circuit performs a system test on the chip under test at the first voltage; the processing circuit controls the power supply circuit to output a second voltage to the chip under test via the detection circuit to replace the first voltage, the test circuit performs a system test on the chip under test at the second voltage, the chip under test performs a voltage pull-off limit test at the second voltage, and the detection circuit detects the electrical signal state of the chip under test. The present application achieves voltage hot replacement in a working state by replacing the first voltage with the second voltage, and facilitates performing a pull-off limit test while performing a system test on the chip under test.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a testing device, system and method. Background Art

[0002] Conventional testing devices used to test chips require switching between different test voltages when performing various tests, often requiring the test chip to be powered off and then on again, resulting in low test efficiency. Furthermore, a single power supply circuit is typically used to power the entire test device, and no detection circuit is provided to monitor the device's operating status. If a short circuit occurs in the test chip, causing a power supply problem, the faulty component cannot be detected in a timely manner, leading to damage to the test device. Summary of the Invention

[0003] This application at least provides a testing device, system and method.

[0004] In a first aspect, the present application provides a testing device for carrying and testing a chip to be tested, the testing device comprising:

[0005] A test circuit is used to connect to the chip to be tested and to perform system testing on the chip to be tested;

[0006] A detection circuit, connected to the test circuit, is used to detect the electrical signal state of the chip under test;

[0007] Processing circuit, connected to the detection circuit;

[0008] a power supply circuit, connected to the test circuit, the detection circuit, and the processing circuit respectively, and connected to a power supply for power supply;

[0009] Among them, the processing circuit is used to control the power supply circuit to output a first voltage to the chip to be tested through the test circuit, so that the test circuit performs a system test on the chip to be tested at the first voltage; the processing circuit is also used to control the power supply circuit to output a second voltage to the chip to be tested through the detection circuit to replace the first voltage, so that the test circuit performs a system test on the chip to be tested at the second voltage, and the chip to be tested performs a voltage deviation limit test at the second voltage, and the detection circuit detects the electrical signal state of the chip to be tested when the deviation limit test is performed.

[0010] Optionally, the electrical signal includes a detection current signal and a detection voltage signal, and the detection circuit includes:

[0011] A power chip is connected to the power supply circuit and the processing circuit respectively, and is used to convert the supply voltage of the power supply circuit into an output voltage and output it to the chip under test;

[0012] Sampling resistor, connected between the power chip and the test circuit;

[0013] The electrical detection module is connected to both ends of the sampling resistor to detect the voltage of the sampling resistor and obtain a detection voltage;

[0014] The AD conversion chip is connected to one end of the sampling resistor, and is used to detect the current of the sampling resistor, obtain the detection current, and convert the detection current into a detection current signal through AD conversion;

[0015] The AD conversion chip is further connected to one end of the electrical detection module for converting the detection voltage into a detection voltage signal;

[0016] The AD conversion chip is further connected to the processing circuit and is used to transmit the detection voltage signal and the detection current signal to the processing circuit.

[0017] Optionally, the power chip is provided with a potentiometer for adjusting the output voltage of the power chip under the control of the processing circuit.

[0018] Optionally, the processing circuit is pre-set with a current threshold range, and the processing circuit is used to compare the detection current signal with the current threshold range; in response to the detection current signal exceeding the current threshold range, the processing circuit controls the power supply circuit to stop outputting the power supply voltage to the power chip.

[0019] Optionally, the processing circuit is pre-set with a voltage threshold range, the detection current is within the current threshold range, and the processing circuit adjusts the potentiometer of the power chip in response to the detection current signal being within the current threshold range to control the output voltage of the power chip;

[0020] If the output voltage of the control power supply chip is within the voltage threshold range and is output as multiple different voltages, the processing circuit is used to detect the detection current at the multiple different voltages in real time through the AD conversion chip; or,

[0021] If the output voltage of the power supply chip is controlled to be the second voltage, the chip to be tested undergoes a voltage deviation limit test, and the processing circuit is used to detect the detection current at the second voltage in real time through the AD conversion chip. The second voltage is greater than or equal to the maximum voltage within the voltage threshold range, or the second voltage is less than or equal to the minimum voltage within the voltage threshold range.

[0022] Optionally, the power chip is pre-set with a threshold current and a cut-off voltage, and the processing circuit is pre-set with a test time;

[0023] The detection current is greater than the threshold current, the output voltage of the power chip is the cut-off voltage, and the processing circuit receives a detection voltage signal corresponding to the cut-off voltage within the test time, and then turns off the power chip.

[0024] Optionally, the power supply circuit further includes a switch, and the switch is connected to the test circuit and the processing circuit respectively;

[0025] The processing circuit is used to receive a detection voltage signal corresponding to a cut-off voltage within a test time, turn off the switch, and the power supply circuit stops outputting the power supply voltage to the test circuit.

[0026] Optionally, the power supply circuit includes a first voltage regulator and a second voltage regulator, the first voltage regulator is connected to the power supply and is used to convert high-voltage direct current into a first threshold voltage, and the second voltage regulator is respectively connected to the first voltage regulator, the power supply chip and the processing circuit and is used to convert the first threshold voltage into a second threshold voltage to supply power to the power supply chip and the processing circuit.

[0027] The second aspect of the present application provides a test system, including the test device and the host as described above, the host and the processing circuit are connected through a serial port, the host sends a test instruction to the chip to be tested through the processing circuit, and the chip to be tested is tested according to the test instruction.

[0028] The third aspect of the present application provides a testing method, comprising:

[0029] receiving a power-on instruction from the host through the processing circuit;

[0030] Perform short circuit test on the chip under test through the detection circuit;

[0031] If no short circuit is detected, power is supplied to the test circuit via the power supply circuit, and a test instruction is sent to the test circuit via the processing circuit;

[0032] Outputting a first voltage to the chip under test through the power supply circuit and the test circuit, the test circuit performing a system test on the chip under test at the first voltage in response to a test instruction;

[0033] Controlling, by the processing circuit, the power supply circuit to output a second voltage to the chip under test via the detection circuit to replace the first voltage, so that the test circuit performs a system test on the chip under test at the second voltage and performs a voltage deviation limit test on the chip under test at the second voltage;

[0034] The detection circuit is used to detect the electrical signal state of the chip under test when performing the pull-off limit test.

[0035] The beneficial effects of the present application are: different from the existing technology, the present application realizes voltage hot replacement in the working state by replacing the first voltage with the second voltage, which is convenient for performing system testing on the chip to be tested while performing pull-off limit testing on the chip to be tested, and can obtain the maximum withstand voltage and minimum working voltage of the chip to be tested.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 This is a schematic structural diagram of an embodiment of the test device of the present application;

[0039] Figure 2 It is a structural schematic diagram of another embodiment of the testing device of the present application;

[0040] Figure 3 It is a structural diagram of another embodiment of the testing device of the present application;

[0041] Figure 4 It is a structural diagram of an embodiment of the test system of the present application;

[0042] Figure 5 It is a flow chart of an embodiment of the testing method of the present application. DETAILED DESCRIPTION

[0043] To enable those skilled in the art to better understand the technical solutions of the present application, the test device, system, and method provided by the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It will be understood that the described embodiments are only a portion of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0044] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0045] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the test device of the present application. Figure 1 As shown, the test device 1 includes a test circuit 10 , a power supply circuit 20 , a detection circuit 31 and a processing circuit 40 . The test circuit 10 is connected to a chip to be tested 11 for performing a system test on the chip to be tested 11 .

[0046] The test device 1 of this embodiment can be configured in a plate-like shape, for example, a test board for installation on a test machine. The test board can be installed on an automatic test machine in a detachable manner. The test board can be used to carry the chip under test 11 and perform system testing on the chip under test 11. In other words, the test board can simulate the operation process of the chip under test 11 on an actual terminal, thereby detecting whether the chip under test 11 has defects and recording the defect information. Taking a DRAM chip as an example, when the test board is installed on an automatic test machine to perform system testing on the chip under test 11, it can detect whether the chip under test 11 has storage address damage or error problems, and then record the storage address with the problem for uploading to a server or recording on the chip under test 11. Then, when the chip under test 11 is used in an actual terminal, the actual terminal can obtain the storage address with the problem and can avoid calling the storage address with the problem, so that the chip under test 11 can run well on the actual terminal.

[0047] In addition, the test circuit 10 of the test device 1 can have a CPU that is compatible with the chip under test 11. That is, the test circuit 10 can be adjusted or replaced according to the corresponding test manufacturer and application terminal to simulate the operating environment of the final actual terminal. Of course, the test circuit 10 can also include a memory, such as ROM, to cooperate with the CPU to test the chip under test 11. Taking Huawei as an example, to test the DRAM chip of a Huawei mobile phone equipped with a Kirin CPU, the COU on the test circuit 10 of the test device 1 can be replaced with the corresponding Kirin CPU, making the test results more accurate and more compatible. The processing circuit 40 can receive instructions, signals or data from the CPU on the test circuit 10, and can be used for the test circuit 10 to record and forward the test results of the chip under test 11, or to issue test instructions to the CPU of the test circuit 10. At this time, the DRAM chip tested can be a RAM (volatile memory) that cooperates with the CPU for testing, specifically one of SDRAM or DDRAM.

[0048] On the other hand, the chip under test 11 itself may have an integrated CPU, and cooperate with the memory on the test circuit 10, such as RAM or ROM, for testing. The processing circuit 40 can receive instructions, signals, or data from the CPU on the chip under test 11, and can be used by the test circuit 10 to record and forward the test results of the chip under test 11, or to issue test instructions to the CPU of the chip under test 11.

[0049] The testing device 1 performs a system test on the chip to be tested 11, which can not only test whether there are logical problems in the chip to be tested 11, but also test the compatibility of the chip to be tested 11 with the corresponding test circuit 10. Compared with traditional physical logic testing, it can further test whether the chip to be tested 11 has better compatibility with the actual terminal, and it has low cost, strong scalability and adjustability, and can quickly adapt to different products and different manufacturers to meet the needs of different customers.

[0050] The power supply circuit 20 is connected to the test circuit 10 , the detection circuit 31 and the processing circuit 40 respectively, and outputs a power supply voltage to the test circuit 10 , the detection circuit 31 and the processing circuit 40 to supply power to the test circuit 10 , the detection circuit 31 and the processing circuit 40 .

[0051] The detection circuit 31 is connected to the test circuit 10 and the processing circuit 40 , and is configured to detect the electrical signal state of the chip under test 11 and output the electrical signal state of the chip under test 11 to the processing circuit 40 .

[0052] To enable test device 1 to perform a system test on chip 11, test circuit 10 of test device 1 is internally provided with a voltage source, which serves as a test voltage source for chip 11. Test circuit 10 outputs a first voltage to chip 11 as the test voltage for chip 11, so that test circuit 10 performs a system test on chip 11 at the first voltage.

[0053] Among them, the chip under test 11 needs to be screened before the system test is carried out to ensure that the chips under test 11 undergoing the system test are all test chips that are working properly, and to prevent the bad chips under test 11 from short-circuiting and causing damage to the test device 1. Specifically, the processing circuit 40 controls the detection circuit 31 to work, so that the power supply circuit 20 outputs a short-circuit detection voltage to the chip under test 11 through the detection circuit 31; if the chip under test 11 is working normally, the processing circuit 40 controls the power supply circuit 20 to output a power supply voltage to the test circuit 10, so that the test circuit 10 outputs a first voltage to the chip under test 11, and at the same time controls the detection circuit 31 to be turned off; if the chip under test 11 is working abnormally, that is, when a short circuit occurs, the processing circuit 40 directly controls the detection circuit 31 to be turned off.

[0054] To perform a voltage pull-out limit test on the chip under test 11, the processing circuit 40 further controls the power supply circuit 20 to output a second voltage to the chip under test 11, and gradually increases the second voltage. When the second voltage increases to be greater than the first voltage, the second voltage replaces the first voltage as the power supply for the test circuit 10, so that the test circuit 10 performs a system test on the chip under test 11 at the second voltage, and causes the chip under test 11 to perform a voltage pull-out limit test at the second voltage. The detection circuit 31 detects the electrical signal state of the chip under test 11 during the pull-out limit test.

[0055] Combine Figure 1 , see further Figure 2 , Figure 2 This is a structural diagram of another embodiment of the test device of the present application. Figure 2 As shown, the power supply circuit 20 includes a switch 21, a first voltage regulator 22, and a second voltage regulator 23. The first voltage regulator 22 is connected to the switch 21 and the second voltage regulator 23, respectively. The power supply circuit 20 is connected to the test circuit 10, the processing circuit 40, and the detection circuit 31 through the switch 21 and the second voltage regulator 23, respectively.

[0056] The detection circuit 31 includes a power chip 311, a sampling resistor 312, an electrical detection module 313, an A / D converter chip 314, an operational amplifier 315, and a low-pass filter 316. The power chip 311 is provided with a potentiometer 3111 for adjusting the output voltage of the power chip 311. Alternatively, the potentiometer 3111 can be an adjustable resistor. Alternatively, the low-pass filter 316 can be an RC low-frequency filter. Alternatively, the operational amplifier 315 can have a magnification of 50 times.

[0057] The power chip 311 is connected to the power supply circuit 20 through the second voltage regulator 23 and is also connected to the processing circuit 40. The power chip 311 is used to convert the supply voltage of the power supply circuit 20 into an output voltage and output it to the chip under test 11. The power chip 311 is used for voltage conversion and can be a voltage conversion chip, such as an LT3045 chip.

[0058] The detection circuit 31 detects electrical signals including a detection current signal and a detection voltage signal when the chip under test 11 is subjected to a pull-to-limit test.

[0059] The sampling resistor 312 is connected between the power chip 311 and the test circuit 10. The electrical detection module 313 is connected to both ends of the sampling resistor 312 and detects the voltage drop across the sampling resistor 312 to obtain a detection voltage. Optionally, the electrical detection module 313 can obtain a detection current based on the resistance of the sampling resistor 312 and the detection voltage.

[0060] The AD conversion chip 314 is connected to one end of the sampling resistor 312 through the operational amplifier 315 and the low-pass filter 316, detects the current of the sampling resistor 312, obtains the detection current, and performs AD conversion on the detection current to a detection current signal; the AD conversion chip 314 is connected to one end of the electrical detection module 313 through the low-pass filter 316, and performs AD conversion on the detection voltage to a detection voltage signal; the AD conversion chip 314 is further connected to the processing circuit 40, and transmits the detection voltage signal and the detection current signal to the processing circuit 40.

[0061] The first voltage regulator 22 is configured to convert the high-voltage direct current into a first threshold voltage. Optionally, the high-voltage direct current is 12V, and the first threshold voltage is 4.4V. The second voltage regulator 23 is configured to further convert the first threshold voltage into a second threshold voltage so that the output voltage meets the operating voltage requirements of the power chip 311 and the processing circuit 40. Optionally, the second threshold voltage is 3.3V. The power chip 311 further converts the second threshold voltage of the second voltage regulator 23 into an output voltage that meets the operating voltage requirements of the chip under test 11.

[0062] The processing circuit 40 is pre-set with a current threshold range, and the processing circuit 40 compares the detected current signal with the current threshold range.

[0063] In order to better screen the chip under test 11, it is necessary to detect whether the chip under test 11 is short-circuited. The processing circuit 40 controls the power supply circuit 20 to output a short-circuit detection voltage to the chip under test 11 via the detection circuit 31. At this time, the processing circuit 40 detects the detection current signal of the chip under test 11 via the detection circuit 31 and compares the detection current signal with the current threshold range. If the detection current signal is within the current threshold range, it indicates that the chip under test 11 is working normally. The processing circuit 40 controls the power supply chip 311 to be turned off and the switch 21 to be turned on at the same time, so that the power supply circuit 20 outputs a supply voltage to the test circuit 10. The test circuit 10 outputs a test voltage to the chip under test 11 through the voltage source, so that the test circuit 10 performs a system test on the chip under test 11 at a first voltage. If the detection current signal exceeds the current threshold range, it indicates that the chip under test 11 is working abnormally, that is, the chip under test 11 is short-circuited. The processing circuit 40 controls the power supply chip 311 to be turned off, so that the power supply circuit 20 stops outputting the short-circuit detection voltage to the chip under test 11.

[0064] The processing circuit 40 is pre-set with a voltage threshold range. When the detection current is within the current threshold range, the processing circuit 40 controls the power chip 311 to turn on, replacing the first voltage with the second voltage, so that the test circuit 10 performs a system test on the chip under test 11 at the second voltage. The processing circuit 40 compares the detection voltage signal with the voltage threshold range. In response to the detection current signal being within the current threshold range, the processing circuit 40 adjusts the potentiometer 3111 of the power chip 311 to control the output voltage of the power chip 311.

[0065] When the second voltage replaces the first voltage and the chip under test 11 is subjected to a pull-to-limit test, the processing circuit 40 adjusts the potentiometer 3111 to continuously change the output voltage of the power chip 311 within the voltage threshold range, thereby causing the power chip 311 to output multiple different voltages. The processing circuit 40 uses the AD conversion chip 314 to detect the detection current at multiple different voltages in real time to detect the operating state and operating current of the chip under test 11 at different voltages in real time. The second voltage is greater than or equal to the maximum voltage within the voltage threshold range, or the second voltage is less than or equal to the minimum voltage within the voltage threshold range.

[0066] In response to the detection current signal exceeding the current threshold range, the processing circuit 40 controls the switch 21 to close, thereby controlling the power supply circuit 20 to stop outputting the power supply voltage to the test circuit 10 and simultaneously controlling the power chip 311 to close.

[0067] Furthermore, the processing circuit 40 adjusts the potentiometer 3111 of the power chip 311 so that the output voltage of the power chip 311 exceeds the operating voltage range of the chip under test 11 , thereby obtaining the maximum withstand voltage and the minimum operating voltage of the chip under test 11 .

[0068] The current threshold range and voltage threshold range preset by the processing circuit 40 are equal to the standard operating current range and standard operating voltage range of the chip under test 11 .

[0069] The power chip 311 is pre-set with a threshold current and a cutoff voltage, and the processing circuit 40 is pre-set with a test time. Optionally, the threshold current can be 100 mA. The threshold current is related to the operating current of the chip under test 11 and is greater than the maximum operating current of the chip under test 11. Optionally, the cutoff voltage can be 0.2 V. Optionally, the test time can be 150 ms.

[0070] When a short circuit occurs in the chip under test 11 and the detection current exceeds the threshold current, the power supply chip 311, based on its pin function, reduces the output voltage to the cutoff voltage. This voltage is the cutoff voltage, and the current flowing through the sampling resistor 312 is zero. The cutoff voltage is converted into a detection voltage signal by the AD converter chip 314. When the processing circuit 40 receives the detection voltage signal corresponding to the cutoff voltage within the test time, it detects an abnormality in the detection voltage and detection current, controls the enable pin of the power supply chip 311, and shuts down the power supply chip 311. Simultaneously, the processing circuit 40 closes the switch 21, causing the power supply circuit 20 to stop outputting the supply voltage to the test circuit 10.

[0071] Combine Figure 1-2 , see further Figure 3 , Figure 31 is a schematic diagram of the structure of another embodiment of the test device of the present application. Different from the above embodiment, the test device 1 of this embodiment further includes a first PMOS transistor 37, a second PMOS transistor 50, a first detection circuit 32 and a second detection circuit 33.

[0072] The first PMOS transistor 37 is disposed between the sampling resistor 312 and the test circuit 10 for power isolation and preventing current backflow, thereby preventing the problem of the detection circuit 31 being burned out due to a short circuit of the chip under test 11 .

[0073] The second PMOS transistor 50 is disposed between the power supply circuit 20 and the test circuit 10 for power isolation and preventing current backflow, thereby preventing the power supply circuit 20 from burning out due to a short circuit of the chip under test 11 .

[0074] This embodiment takes a DRAM chip as an example. The DRAM chip includes three test voltages, namely VDD1, VDD2, and VDDQ, to test the three functions of the DRAM chip. Therefore, three detection circuits need to be set up to detect the working state of the DRAM chip under the three test voltages and the current in the standby state. In this embodiment, the detection circuit 31, the first detection circuit 32, and the second detection circuit 33 constitute the total detection circuit 30. Before the voltage hot replacement is performed, the three sub-voltage sources VDD1, VDD2, and VDDQ in the voltage source of the test circuit 10 respectively test the DRAM chip; after the voltage hot replacement is performed, the power supply circuit 20 supplies power to the chip under test 11 through the detection circuit 31, the first detection circuit 32, and the second detection circuit 33, respectively, replacing the sub-voltage sources VDD1, VDD2, and VDDQ; at the same time, the processing circuit 40 detects the working state of the chip under test 11 through the detection circuit 31, the first detection circuit 32, and the second detection circuit 33.

[0075] The structures of the first detection circuit 32 and the second detection circuit 33 are the same as those of the detection circuit 31. Specifically, the first detection circuit 32 includes a first power supply chip 321, a first sampling resistor 322, a first electrical detection module 323, a first AD conversion chip 324, a first operational amplifier 325, a first low-pass filter 326 and a third PMOS transistor 327. The first power supply chip 321 is provided with a first potentiometer 3211; the second detection circuit 33 includes a second power supply chip 331, a second sampling resistor 332, a second electrical detection module 333, a second AD conversion chip 334, a second operational amplifier 335, a second low-pass filter 336 and a fourth PMOS transistor 337. The second power supply chip 331 is provided with a second potentiometer 3311.

[0076] In this embodiment, the three functions of the chip to be tested 11 are detected by the detection circuit 31, the first detection circuit 32 and the second detection circuit 33. The processing circuit 40 adjusts the potentiometer 3111 of the detection circuit 31, the potentiometer 3211 of the first detection circuit 32 and the potentiometer 3311 of the second detection circuit 33 respectively, so that the output voltages of the detection circuit 31, the first detection circuit 32 and the second detection circuit 33 are respectively within the first voltage range, the second voltage range and the third voltage range of the chip to be tested 11.

[0077] The VDD1 range of the DRAM chip is 1.70V-1.95V, the VDD2 range is 1.06V-1.17V, and the VDDQ range is 1.06V-1.17V. That is, the voltage control ranges of the detection circuit 31, the first detection circuit 32, and the second detection circuit 33 are 1.70V-1.95V, 1.06V-1.17V, and 1.06V-1.17V, respectively. The limit voltage of the chip under test 11 is 1.06V and 1.95V.

[0078] The IDD1 of a DRAM chip ranges from 2mA to 3mA, the IDD2 ranges from 2.3mA to 5mA, and the IDDQ ranges from 0.04mA to 0.08mA. As the number of bad blocks in the chip under test 11 increases, the current of the chip under test 11 in the standby state increases accordingly. Therefore, the chips under test 11 can be graded by comparing the currents of the chips under test 11 in the standby state. The lower the current of the chip under test 11 in the standby state, the better the chip under test 11.

[0079] The processing circuit 40 may include a microprocessor (MCU), and may also include a FLASH memory and a ROM memory compatible with the microprocessor, so as to store relevant data of the test circuit 10, the power supply circuit 20 and the detection circuit 31, etc., so as to ensure the normal progress of the test process.

[0080] This application also provides a test system 4, see Figure 4 , Figure 4 1 is a schematic diagram of the structure of an embodiment of the test system of the present application. The test system 4 includes a test device 41 and a host 42. The test device 41 is the test device 1 disclosed in the above embodiment and will not be described in detail here.

[0081] The host 42 is connected to the processing circuit 40 via a serial port. The host 42 sends a test instruction to the chip under test 11 via the processing circuit 40. The chip under test 11 performs the test according to the test instruction. Optionally, the serial port includes at least one of a USB serial port and a network serial port.

[0082] Specifically, host 42 sends instructions to processing circuit 40 via the serial port. Processing circuit 40 receives and verifies the instructions. If the verification instruction is incomplete, processing circuit 40 reports an instruction error to host 42. If the verification instruction is complete, processing circuit 40 further determines the instruction type and performs the corresponding operation. Optionally, the instruction type specifically includes at least one of reading device information, upgrading the device, setting information of the chip under test 11, and a test command. The test command may include at least one of testing the chip under test 11 and powering on and off the test circuit 10.

[0083] This application also provides a testing method, see Figure 5 , Figure 5 This is a flow chart of an embodiment of the test method of this application. The specific test steps are as follows: Figure 5 shown.

[0084] S11: receiving a power-on instruction from the host through the processing circuit;

[0085] S12: Perform a short circuit test on the chip to be tested through the detection circuit;

[0086] S13: If no short circuit is detected, power is supplied to the test circuit via the power supply circuit, and a test instruction is sent to the test circuit via the processing circuit;

[0087] The host 42 is connected to the processing circuit 40 via a serial port, and the processing circuit 40 is connected to the test circuit 10 via a serial port. The host 42 sends a test instruction to the test circuit 10 via the processing circuit 40 .

[0088] S14: outputting a first voltage to the chip under test through the power supply circuit and the test circuit, and the test circuit performing a system test on the chip under test at the first voltage in response to the test instruction;

[0089] S15: controlling the power supply circuit through the processing circuit to output a second voltage to the chip under test via the detection circuit to replace the first voltage, so that the test circuit performs a system test on the chip under test at the second voltage and performs a voltage deviation limit test on the chip under test at the second voltage;

[0090] S16: Detecting the electrical signal state of the chip under test during the pull-out limit test through the detection circuit.

[0091] The electrical signal includes a detection current signal and a detection voltage signal.

[0092] The processing circuit 40 compares the detected current signal with the current threshold range. When the detected current signal exceeds the current threshold range, the processing circuit 40 determines that the circuit is abnormal, controls the power supply circuit 20 to stop working, and reports to the host 42.

[0093] When the detected current signal is within the current threshold range, the processing circuit 40 compares the detected voltage signal with the voltage threshold range. When the detected voltage signal exceeds the voltage threshold range, the processing circuit 40 adjusts the potentiometer 3111 to keep the output voltage of the power chip 311 within the voltage threshold range.

[0094] When the output voltage of the power chip 311 is adjusted to the voltage threshold range by the processing circuit 40, if the detected current signal is outside the current threshold range, the processing circuit 40 determines that the circuit is abnormal, controls the power supply circuit 20 to stop working, and reports to the host 42.

[0095] The present application realizes hot voltage replacement in the working state by replacing the first voltage with the second voltage; at the same time, the pull-off limit test is performed on the chip to be tested 11, and the maximum withstand voltage and the minimum working voltage of the chip to be tested 11 can be obtained, and the working state of the chip to be tested 11 can be detected and regulated in real time by the detection circuit 31. At the same time, the processing circuit 40 can make the output voltage of the power chip 311 be located in the first voltage range, the second voltage range and the third voltage range of the chip to be tested 11 respectively by adjusting the potentiometer 3111 to perform testing at different working voltages. In addition, by obtaining the current of the chip to be tested 11 in the standby state, the chip to be tested 11 can be graded. In addition, when a short circuit occurs in the chip to be tested 11, the processing circuit 40 controls the power supply circuit 20 to stop outputting the power supply voltage to the test circuit 10, which can realize automatic overcurrent protection and prevent the short circuit of the chip to be tested 11 from causing abnormal power supply of the power supply circuit 20, thereby damaging the test device 1.

[0096] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A testing device, characterized in that: Used to carry the chip to be tested and test the chip to be tested, including: A test circuit, connected to the chip to be tested, comprising a CPU and a memory adapted for the chip to be tested, and configured to perform a system test on the chip to be tested; A detection circuit, connected to the test circuit, for detecting the electrical signal of the chip to be tested, wherein the detection circuit includes a power chip; a processing circuit connected to the detection circuit; a power supply circuit, connected to the test circuit, the detection circuit, and the processing circuit, respectively, and connected to a power source for power supply; The power supply circuit includes a switch, a first voltage regulator, and a second voltage regulator. The first voltage regulator is connected to the power supply and is respectively connected to the switch and the second voltage regulator. The switch is respectively connected to the test circuit and the processing circuit. The second voltage regulator is respectively connected to the power supply chip and the processing circuit. In which, the processing circuit is used to control the power supply circuit to output a first voltage to the chip to be tested through the test circuit, so that the test circuit performs the system test on the chip to be tested at the first voltage; the processing circuit is also used to control the power supply circuit to output a second voltage to the chip to be tested through the detection circuit to replace the first voltage, so that the test circuit performs the system test on the chip to be tested at the second voltage, and performs a voltage pull-off limit test on the chip to be tested at the second voltage, and detects the electrical signal of the chip to be tested when the pull-off limit test is performed through the detection circuit.

2. The testing device according to claim 1, wherein: The power chip is connected to the power supply circuit and the processing circuit respectively, and is used to convert the power supply voltage of the power supply circuit into an output voltage and output it to the chip under test; The electrical signal includes a detection current signal and a detection voltage signal, and the detection circuit further includes: a sampling resistor connected between the power chip and the test circuit; an electrical detection module, connected to both ends of the sampling resistor, for detecting the voltage of the sampling resistor to obtain a detection voltage; An AD conversion chip is connected to one end of the sampling resistor, and is used to detect the current of the sampling resistor to obtain a detection current, and is used to perform AD conversion on the detection current to form the detection current signal; The AD conversion chip is further connected to one end of the electrical detection module, and is used to perform AD conversion on the detection voltage to the detection voltage signal; The AD conversion chip is further connected to the processing circuit and is used to transmit the detection voltage signal and the detection current signal to the processing circuit.

3. The testing device according to claim 2, characterized in that The power chip is provided with a potentiometer for adjusting the output voltage of the power chip under the control of the processing circuit.

4. The testing device according to claim 3, characterized in that: The processing circuit is pre-set with a current threshold range, and the processing circuit is used to compare the detection current signal with the current threshold range; in response to the detection current signal exceeding the current threshold range, the processing circuit controls the power supply circuit to stop outputting the power supply voltage to the power chip.

5. The testing device according to claim 4, characterized in that: The processing circuit is pre-set with a voltage threshold range, and in response to the detection current signal being within the current threshold range, the processing circuit further adjusts the potentiometer of the power chip to control the output voltage of the power chip; If the output voltage of the power supply chip is controlled to be within the voltage threshold range and output as a plurality of different voltages, the processing circuit is used to detect the detection current under the plurality of different voltages in real time through the AD conversion chip; or, If the output voltage controlled by the power supply chip is the second voltage, the chip under test performs the voltage deviation limit test, and the processing circuit is used to detect the detection current under the second voltage in real time through the AD conversion chip. The second voltage is greater than or equal to the maximum voltage within the voltage threshold range, or the second voltage is less than or equal to the minimum voltage within the voltage threshold range.

6. The testing device according to claim 5, characterized in that: The power chip is pre-set with a threshold current and a cut-off voltage, and the processing circuit is pre-set with a test time; The detection current is greater than the threshold current, the output voltage of the power chip is the cut-off voltage, and the processing circuit receives a detection voltage signal corresponding to the cut-off voltage within the test time, then turns off the power chip.

7. The testing device according to claim 6, characterized in that The processing circuit is configured to receive a detection voltage signal corresponding to the cut-off voltage within the test time, close the switch, and cause the power supply circuit to stop outputting the power supply voltage to the test circuit.

8. The testing device according to claim 7, characterized in that: The first voltage regulator is used to convert high-voltage direct current into a first threshold voltage, and the second voltage regulator is used to convert the first threshold voltage into a second threshold voltage to supply power to the power chip and the processing circuit.

9. A testing system, characterized in that: The test system includes the test device according to any one of claims 1 to 8 and a host, the host is connected to the processing circuit via a serial port, the host sends a test instruction to the chip to be tested through the processing circuit, and the chip to be tested is tested according to the test instruction.

10. A testing method, characterized in that: A test device according to any one of claims 1 to 8, comprising: receiving a power-on instruction from the host through the processing circuit; Perform short circuit detection on the chip to be tested through the detection circuit; If no short circuit is detected, power is supplied to the test circuit via the power supply circuit, and a test instruction is sent to the test circuit via the processing circuit; outputting a first voltage to the chip under test via the power supply circuit and the test circuit, wherein the test circuit performs a system test on the chip under test at the first voltage in response to the test instruction; Controlling, by the processing circuit, the power supply circuit to output a second voltage to the chip under test via the detection circuit to replace the first voltage, so that the test circuit performs the system test on the chip under test at the second voltage and performs the voltage pull-off limit test on the chip under test at the second voltage; The detection circuit detects the electrical signal state of the chip under test when the pull-off limit test is performed.

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