Method of forming a semiconductor device

Abstract

The present invention is titled "Method of forming a semiconductor device". In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed, and another material is formed on the sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. A source contact opening and a gate contact opening are formed together.

Description

Technical Field

[0001] The present invention generally relates to electronic devices, and more particularly, to semiconductors, semiconductor structures, and methods of forming semiconductor devices. Background Art

[0002] In the past, the semiconductor industry has utilized various methods and structures to form trench metal oxide semiconductor field effect transistors (MOSFETs). As process technology has allowed for smaller device pitches, it has become more difficult to provide reliable contacts to the MOSFETs. In some manufacturing techniques, the contacts become misaligned, which sometimes increases the Rdson of the MOSFET. A higher Rdson results in either poor performance or alternatively higher manufacturing costs. In some applications, the misalignment of some MOSFET features results in a degradation of the unclamped inductive switching (UIS) performance.

[0003] In some other manufacturing techniques, different masking and etching operations are utilized to form source contacts and gate contacts. These different operations for the two contacts result in higher manufacturing costs for the MOSFET.

[0004] Accordingly, there is a desire for a manufacturing technique that provides more reliable contacts, provides a more reliable Rdson, reduces manufacturing operations, and / or reduces manufacturing costs. Brief Description of the Drawings

[0005] Figure 1 An example of an enlarged plan view of a portion of an embodiment of a semiconductor device according to the present invention;

[0006] Figure 2 Showing according to the present invention Figure 1 An example of an enlarged cross-section of a portion of a device;

[0007] Figure 3 Showing an early stage in an example of an embodiment of a method of forming a device according to the present invention Figure 1-2 of;

[0008] Figure 4 Showing a subsequent stage in an example of an embodiment of a method of forming a device according to the present invention Figure 1-2 of;

[0009] Figure 5 Showing another subsequent stage in an example of an embodiment of a method of forming a device according to the present invention Figure 1-2 of;

[0010] Figure 6 Showing another subsequent stage in an example of an embodiment of a method of forming a device according to the present invention Figure 1-2 of;

[0011] Figure 7 Another subsequent step in an example of an embodiment of a method of forming a Figure 1-2 device according to the present invention;

[0012] Figure 8 Another subsequent step in an example of an embodiment of a method of forming a Figure 1-2 device according to the present invention; and

[0013] Figure 9 Another subsequent step in an example of an embodiment of a method of forming a Figure 1-2 device according to the present invention;

[0014] For clarity and simplicity of illustration, the elements in the figures are not necessarily drawn to scale, some elements may be exaggerated for illustrative purposes, and like reference numerals in different figures indicate like elements unless otherwise specified. In addition, to simplify the description, the description and details of well-known steps and elements may be omitted. As used herein, a current-carrying element or current-carrying electrode means an element of a device that carries the current passing through the device, such as the source or drain of a MOS transistor or the emitter or collector of a bipolar transistor or the cathode or anode of a diode, while a control element or control electrode means an element of a device that controls the current passing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Additionally, one current-carrying element may carry a current passing through the device in one direction, such as a current entering the device, while a second current-carrying element may carry a current passing through the device in the opposite direction, such as a current leaving the device. Although the device may be described herein as certain N-channel or P-channel devices or certain N-type or P-type doped regions, those of ordinary skill in the art will understand that complementary devices according to the present invention are also possible. Those of ordinary skill in the art understand that the conduction type refers to the mechanism by which conduction occurs, such as by holes or electron conduction, and thus the conduction type does not refer to the doping concentration but rather to the doping type, such as P-type or N-type. Those skilled in the art should understand that the terms "during", "simultaneously with", and "when" used herein in connection with circuit operations do not precisely mean that an action occurs immediately after the triggering action, but rather that there may be some small but reasonable delay between the reactions triggered by the initial action, such as various propagation delays. Additionally, the term "simultaneously with" means that an action occurs at least for a period of time during the duration of the triggering action. The use of the words "about" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent the value or position from being exactly the stated value or position. It is recognized in the art that a deviation of up to at least ten percent (10%) (and for some elements including semiconductor doping concentrations, up to twenty percent (20%)) is a reasonable deviation from the ideal target as exactly described. When used in connection with signal states, the term "active" means the active state of a signal, while the term "inactive" means the inactive state of a signal. The actual voltage value or logic state of a signal (such as "1" or "0") depends on whether positive logic or negative logic is being used. Thus, if positive logic is being used, a high voltage or high logic may be active, and if negative logic is being used, a low voltage or low logic may be active; while if positive logic is being used, a low voltage or low state may be inactive, and if negative logic is being used, a high voltage or high logic may be inactive. In this document, a positive logic convention is used, but those skilled in the art understand that a negative logic convention may also be used.The terms "first", "second", "third", etc. (such as when used as part of an element name) in the claims and / or the detailed description are used to distinguish between similar elements and do not necessarily describe an order in time, space, rank, or any other manner. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, and the embodiments described herein are capable of operating in an order other than that described or illustrated herein. Referring to "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present invention. Thus, the phrase "in an embodiment" that appears in different places throughout this specification does not necessarily refer to the same embodiment, but in some cases, it may refer to the same embodiment. Additionally, as will be apparent to those of ordinary skill in the art, in one or more embodiments, the specific features, structures, or characteristics may be combined in any suitable manner. For the sake of clarity in the drawings, the doped regions of the device structure are shown as having substantially straight edges and corners with precise angles. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of the doped regions are generally not straight and the corners are not precise angles.

[0015] Additionally, this specification shows a cellular design in place of a monolithic design (in the cellular design, the body region is a plurality of cellular regions), (in the monolithic design, the body region is constituted by a single region formed in an elongated pattern, typically a serpentine pattern in some embodiments). However, this specification is intended to apply to both cellular implementations and single-substrate implementations.

[0016] The embodiments to be illustrated and described below appropriately may lack any element not specifically disclosed herein and / or may be implemented in the absence of any element not specifically disclosed herein. Detailed Description

[0017] Figure 1 An example of an enlarged plan view of a portion of an embodiment of a semiconductor device 20 formed using improved manufacturing techniques is shown. In one embodiment, the device 20 may include a trench MOSFET. The device 20 includes an active portion 21 configured to conduct current between active elements within portion 21. For example, portion 21 may be configured to form a channel region that selectively allows current to flow from the source region of the trench MOSFET to the drain region. The device 20 also includes a non-active portion 22 that facilitates the formation of electrical connections to the portion of the device 20 within portion 21, but does not conduct current flowing through the device 20, although some current may flow into portion 22 to charge parasitic capacitance, etc.

[0018] In an embodiment of a trench MOSFET, device 20 includes a plurality of gate trenches 26. Each trench 26 has an active portion 33 within portion 21 and also has a length 48 such that the non-active portion 40 of each trench 26 is within portion 22. The gate electrode 25 extends into portion 22 and covers the non-active portion 40 of trench 26 but does not extend into the active portion 21. The source 24 extends into portion 21 and covers the active portion 33 of trench 26 but does not extend into the non-active portion 22. The terminal trench 28 may be formed to surround portions 21 and 22 to isolate device 20 from other devices. In some embodiments, trench 28 may have a different configuration and may be in a different position relative to trench 26. In one embodiment, trench 28 may be formed as a plurality of connection domains within which trench 26 and portions 21 and 22 are formed.

[0019] Figure 2 An enlarged cross-sectional example of a portion of device 20 along section line 2-2 as shown in Figure 1 is shown. Figure 2 The left hand portion of Figure 2 shows an example of an embodiment of the active portion 33 of trench 26 and also shows trench 28 formed within the active portion 21, and

[0020] Figure 3 The right hand portion of

[0021] shows an example of an embodiment of the non-active portion 40 of trench 26 and also shows trench 28 formed within the non-active portion 22. Figure 1)。The opening 46 can be formed to have a width 53 and can extend a depth 49 from the surface 31 into the substrate 30. Additionally, an opening 47 is formed that extends from the surface 31 into the substrate 30 where the trench 28 will be located therein. The openings 46 are separated from each other by a distance or width 54 such that a portion of the substrate 30 forms a protrusion 70 between the openings 46. One embodiment can include that the protrusion 70 can also be formed between the opening 47 and an adjacent opening 46. Optionally, the opening 47 can be formed to extend further into the substrate 30 than the depth 49. The opening 47 can be formed simultaneously or non-simultaneously with the opening 46. In one embodiment, the bottoms of the openings 46 and 47 can have a circular shape. The openings 46 and 47 can be formed by trench etching operations well known to those skilled in the art. One embodiment can include forming the openings 46 and 47 using anisotropic etching techniques, or alternatively the trenches 26 and 28.

[0022] One embodiment can include forming an optional insulator layer 50 on the surface 31 and removing portions of the layer 50 where the openings 46 and 47 will be formed. The layer 50 can be silicon dioxide formed by oxidizing the surface 31. Then, the layer 50 and the openings therein can be used as a mask for forming the openings 46 and 47.

[0023] Figure 4 An example of a subsequent stage in one embodiment of the method of forming the device 20 is shown. The widths of the openings 46 and 47 expand near the surface 31. The widths of the openings 46 and 47 are expanded to a width 55 that extends a certain depth or distance 51 from the surface 31 into the substrate 30. The depth 51 is much less than the depth 49. Expanding the widths of the openings 46 and 47 reduces the width of the protrusion 70 at the surface 31 to a width 56 that extends a depth 51 into the substrate 30. The width 56 is less than the width 54. In one embodiment, the width 56 is at least about seventy nanometers (70 nm) less than the width 54. Other embodiments can include that the width 56 can be anywhere between about seven nanometers (70 nm) to about eighty nanometers (80 nm) less than the width 54.

[0024] In one embodiment, isotropic etching can be used to expand the widths of the openings 46 and 47. During the operation of expanding the widths of the openings 46 and 47, portions of the optional layer 50 can also be removed. Then, the remaining portion of the layer 50 can be removed.

[0025] Figure 5Illustrates another subsequent stage in an embodiment of a method of forming device 20. Insulator 73 is formed along the sidewalls and bottom of openings 46 and 47. In one embodiment, insulator 73 is formed to have a thickness or width 58 along portions of openings 46 and 47 having width 53. In other embodiments, insulator 73 may also be formed along sidewalls having width 55 and along surface 31 with width 58. One embodiment may include forming insulator 73 from silicon dioxide. For example, an exposed portion of substrate 30 may be oxidized to form insulator 73.

[0026] Subsequently, shield conductor 75 may be formed in the lower portion of opening 46. Terminal conductor 74 may also be formed within the remainder of opening 47. Conductors 74 and 75 may be formed from well-known conductor materials, such as doped polysilicon or other conductor materials.

[0027] Embodiments of forming conductors 74 and 75 may include filling openings 46 and 47 with conductor material. In some embodiments, the conductor material may extend out of surface 31 of substrate 30 and extend onto or cover the surface. For such embodiments, a planarization process (such as a chemical mechanical polishing (CMP) process) may be used to remove portions of the conductor material from the surface of substrate 30 and / or from the surface of insulator 73 formed on surface 31. Then, portions of conductor 75 within opening 46 may be removed. During the process of removing portions of conductor 75, mask 44 (shown in dashed lines) may be used to protect opening 47 to leave the conductor material as conductor 74 within opening 47. Then mask 44 may be removed.

[0028] Figure 6 Illustrates another subsequent step in an example of an embodiment of a method of forming device 20. Spacer insulator 76 may be formed on conductor 75 within opening 46. Those skilled in the art will understand that insulator 76 separates or isolates conductor 75 from gate conductor 83 ( Figure 2 ), as will be further explained below.

[0029] One embodiment of forming insulator 76 may include forming insulator material within opening 46 and on conductor 75 such that the material fills at least a portion of the remainder of opening 46. Insulator material may also be formed on conductor 74. One embodiment may include forming insulator material to fill the remainder of opening 46 and extend to cover surface 31, such as forming insulator material covering insulator 73 on surface 31 ( Figure 5)。The material for the insulator 76 can be any of a variety of well-known insulator materials, such as silicon dioxide or other well-known insulator materials. Some embodiments may include removing a portion of the insulator material from the covering surface 31, for example, by planarizing the insulator material. CMP or other types of planarization procedures can be used. The removal step also removes the portion of the insulator 73 on the surface 31 of the substrate 30.

[0030] Then, a portion of the insulator material within the opening 46 can be removed to a certain distance or depth 77, such that a portion of the insulator material remains on the conductor 75 as the insulator 76. One embodiment may include forming a mask 60 (shown in dashed lines) covering the opening 47 during the step of removing the portion of the insulator, to protect the opening 47 and the trench 28. During the step of removing the insulator material to the depth 77, the portion of the insulator 73 located on the sidewalls of the opening 46 is also removed, as shown by the dashed line 68, down to the depth 77, such that a portion of the insulator 73 remains on the sidewalls of the opening 46 deeper than the distance 77, to form the insulator 78, which extends from the bottom of the opening 46 towards the surface 31 at least up to the insulator 76, and optionally adjacent to all of the insulator 76. The depth 77 is greater than the depth 51 but less than the depth 49. The method of forming the insulators 76 and 78 is well-known to those skilled in the art.

[0031] Figure 7 Another subsequent step in an example of an embodiment showing a method of forming the device 20 is shown. After forming the insulators 76 and 78, another insulator 80 is formed on the sidewalls of the opening 46, which extends from the surface 31 down to the depth 77 or alternatively extends to the insulator 78. One embodiment may include forming the insulator 80 to at least the depth 77 into the opening 46. The insulator 80 has a thickness less than the thickness 58 of the insulator 78. A portion of the insulator 80 can sometimes be referred to as a gate insulator. In one embodiment, the insulator 80 can also be formed to extend onto the surface 31 and onto the protrusion 70, which is positioned between and adjacent to the openings 46. The insulator 80 can be one or more of a variety of well-known insulator materials that can be used as a gate insulator for a transistor. In one embodiment, the insulator 80 can be silicon dioxide formed by oxidizing the silicon exposed within the opening 46 and on the surface 31. Even though the mask 60 covers the opening 47, one embodiment may include that a portion of the conductor 74 can be oxidized into the insulator 65. Then the mask 60 can be removed.

[0032] Subsequently, a gate conductor 83 can be formed in the opening 46. As will be seen further below, the conductor 83 is recessed from the surface 31 to the depth 52, such that the depth 52 from the surface 31 is greater than the depth 51. Thus, the conductor 83 extends further into the opening 46 from the depth 52.

[0033] One embodiment of a method of forming conductor 83 may include filling the remainder of opening 46 with a conductor material. The conductor material may be formed to fill opening 46 and extend to cover surface 31. A portion of the conductor material may be removed to leave the conductor material within opening 46. For example, the conductor material may be planarized by CMP or other well-known methods. In some embodiments, a portion of the material of conductor 83 may also be formed over conductor 74 within opening 47. The formation of conductor 83 will be continued hereinafter.

[0034] Doped region 85 may be formed within substrate 30 and extend at least between openings 46. Region 85 may be shaped to extend substantially parallel to surface 31. In some embodiments, region 85 may also extend laterally into opening 47 and optionally may extend through opening 47. In some embodiments, region 85 does not extend into portion 22. Region 85 is shaped to be positioned at least a depth 84 below surface 31 such that depth 84 is not less than depth 52. In one embodiment, depth 84 may be greater than depth 52.

[0035] Subsequently, the portion of protrusion 70 that is within active portion 21 and positioned between openings 46 is doped to form a doped region, and doped region 87 may have a conductivity type opposite to that of region 85. One embodiment may include region 87 having N-type conductivity and region 85 having P-type conductivity. In one embodiment, region 85 may be formed in a portion of substrate 30 having N-type conductivity. Doped region 87 extends a depth 59 from surface 31 such that depth 59 is greater than depth 51. Region 87 extends downward along the sidewalls of opening 46 having width 55 within protrusion 70 to the sidewalls having width 53 such that a portion of doped region 87 is adjacent to insulator 80, which is located on the sidewalls of the portion of opening 46 having width 53. In some embodiments, depth 59 is greater than depth 52 such that a portion of region 87 abuts a portion of insulator 80 that abuts conductor 83. In one embodiment, depth 84 is greater than depth 59 such that region 87 does not extend as far as depth 84 of region 85. During the formation of region 87, the portion of protrusion 70 adjacent to opening 47 is masked with another mask 61 (dashed lines) similar to mask 60 such that doped region 87 does not extend to be adjacent to insulator 73 within opening 47.

[0036] Returning to conductor 83, the portion of the conductor material within opening 46 can be removed down to depth 52 to leave conductor 83 within each opening 46. The material for conductor 83 can be any well-known conductor material that can be used to form the gate conductor of a MOSFET. For example, the material for conductor 83 can be doped polysilicon, or silicide, or self-aligned silicide (salacided) or other well-known conductor materials. Those skilled in the art will understand that in other embodiments, the order of forming regions 83, 87, and 85 can be different.

[0037] Mask 61 can be removed.

[0038] Figure 8 Another subsequent step in an example of an embodiment showing a method of forming device 20 is shown. An insulator 92 is formed to cover conductor 83 and protrusion 70. In one embodiment, an insulator 92 is formed to cover all trenches 26. One embodiment can include forming an insulator 92 that covers any one of all active portions 21 and non-active portions 22 and the surface 31 therebetween. An embodiment of insulator 92 can have a configuration that covers all surfaces 31. One embodiment can include insulator 92 extending sufficiently into opening 46 to contact conductor 83.

[0039] A stop layer 94 is formed on insulator 92. One embodiment of stop layer 94 covers at least all trenches 26 and protrusion 70. In one embodiment, a stop layer 94 is formed to cover all of insulator 92. An opening is formed that covers stop layer 94 and at least trenches 26 and protrusion 70.

[0040] A mask 99 is applied and patterned. Mask 99 has a mask opening 97 that covers a portion of the length of protrusion 70 within active portion 21 but not within non-active portion 22. Mask 99 also has an opening 98 that covers a portion of conductor 83 within non-active portion 22 but does not cover the portion of conductor 83 within active portion 21. Opening 97 has a width that is the length of opening 97 extending substantially parallel to length 48 ( Figure 1 ) but the length of opening 97 is less than the width of portion 21. An embodiment of opening 97 has a width that is the same as the width 56 of the narrower portion of protrusion 70 ( Figure 4)Substantially the same width. However, in other embodiments, the widths may be different. Substantially simultaneously, the opening 98 is formed by passing through an opening in a portion of the non-active portion 22 and covering a portion of the conductor 83. The length of the opening 98 is substantially parallel to the length 48 but less than the width of the portion 22. The openings 97 and 98 are formed in the openings by removing the underlying portions of the openings, where the removal operation substantially stops when reaching the layer 94. For example, the openings may be etched by an etchant that substantially does not etch the material of the layer 94. One embodiment may include that the layer 94 may be silicon nitride and the openings may be silicon dioxide. One embodiment may include etching the openings using an etchant that is preferential to silicon dioxide compared to silicon nitride. In one embodiment, the openings may be etched using a fluorine-based etchant that substantially does not affect the material layer 94. Since the removal substantially stops after reaching the layer 94, the removal operation is substantially independent of the thickness of the openings.

[0041] Subsequently, the exposed portions of the layer 94 within the openings 97 and 98 (as shown by the dashed portions of the layer 94) are removed to expose the underlying portion of the insulator 92. In one embodiment, the operation of removing the exposed portions of the layer 94 substantially stops when reaching the insulator 92. For example, the layer 94 may be etched by an etchant that substantially does not etch the material of the insulator 92. One embodiment may include that the layer 94 may be phosphosilicate glass (PSG) or silicon dioxide or other materials that are not etched by the etching of the layer 94. In one embodiment, the operation of removing the layer 94 is preferential to silicon nitride compared to silicon and silicon dioxide, so the removal substantially does not affect the materials of the layers 96 or 92. One embodiment may include that the layer 94 may be etched using an etchant that substantially does not affect the material of the insulator 92.

[0042] Figure 9 Another subsequent step in an example of an embodiment showing a method of forming the device 20 is shown. The opening 97 extends through the insulator 92 and through the insulator 80 to at least expose the protrusion 70 (as shown by the dashed line indicating the top of the protrusion 70), or alternatively at least expose the region 87. Substantially simultaneously, the opening 98 also extends through the insulator 92 to at least expose the conductor 83. In one embodiment, the insulator 92 is etched through the openings 97 and 98 using an etchant that etches silicon dioxide faster than silicon or silicon nitride to remove the materials of the insulators 92 and 80, and substantially does not affect the materials of the protrusion 70 and the conductor 83.

[0043] Then, each opening 97 extends through the corresponding protrusion 70 and region 87 to at least expose the doped region 85. One embodiment of the removal operation is preferential to silicon over silicon dioxide or silicon nitride. Thus, if the opening 97 is slightly offset from the middle of the protrusion 70, the removal substantially does not affect the material of the insulator 92, so the removal does cause the opening 97 to extend laterally to expose the conductor 83. Thus, because region 87 has silicon dioxide on its sidewalls, the subsequently formed electrode 24 cannot contact the conductor 83. Additionally, the portion of the opening 97 that passes through region 87 is substantially self-aligned with the trench 33. For example, the portions of the opening 97 can be substantially equidistant from each trench 33 on opposite sides of the opening 97. Thus, the source portion of the contact region 87 is self-aligned with the trench 33. Although the lower portion of the opening 97 is narrower than the upper portion of the opening 97, in some embodiments, the two portions can have the same width.

[0044] Substantially simultaneously, each opening 98 can extend into the material of the corresponding conductor 83. In the case where the conductor 83 is a self-aligned silicide or silicide material, the opening 98 will only slightly extend into the conductor 83. In the case where the conductor 83 is doped polysilicon that is not a silicide or self-aligned silicide material, the opening 98 can extend into the material of the conductor 83, as shown by the dashed lines. In some embodiments, the opening 97 that passes through region 87 can be referred to as a source contact opening, and the opening 98 that exposes the conductor 83 can be referred to as a gate contact opening.

[0045] Forming both openings 97 and 98 using the same removal operation saves the manufacturing operations of previously forming a source contact opening (such as opening 97) using one set of operations and forming a gate contact opening (such as opening 98) using a separate set of operations. Thus, the current method saves costs.

[0046] Referring back Figure 1-2 , a mask can be applied and patterned with a mask opening that covers at least the opening 97 and a separate mask opening that covers at least the opening 98. The mask opening can extend to additionally expose a portion of the opening adjacent to the openings 97 and 98. Then, a conductor material is applied to fill the opening 97 and form a source 24 within the opening 97, and electrically contact the doped region 87 and the doped region 85. The conductor material in portion 21 can extend to cover the surface 31 between all the openings 97 of the trenches 26. The conductor material also forms a gate electrode 25 in the opening 98. The conductor material in portion 22 also extends to cover the surface 31 between all the openings 98 of the trenches 26.

[0047] The conductor material can be any well-known conductor material. One embodiment can include the conductor material being a multi-layer metal including a titanium and titanium nitride (TiN) barrier layer.

[0048] Based on all of the foregoing, those skilled in the art should understand that examples of embodiments of a method of forming a semiconductor device may include:

[0049] Providing a substrate (e.g., substrate 30) having a first surface (e.g., a top surface), the substrate being a semiconductor substrate having a first conductivity type (e.g., N-type);

[0050] Forming a plurality of gate trench openings (e.g., openings 46 - 47) having a first width (e.g., width 53), the plurality of gate trench openings extending a first distance (e.g., distance 49) into the substrate, wherein each gate trench opening (e.g., the opening of trench 33) is in an active region (e.g., region 21) of the semiconductor device and has a length (e.g., length 48) such that, for example, portion 40 extends from the active region into a non-active region (e.g., region 22) of the semiconductor device.

[0051] Forming a terminal trench opening (e.g., opening 47 of trench 28) having a first width extending into the substrate, wherein the terminal trench opening surrounds the plurality of gate trench openings and wherein the plurality of gate trench openings leave a protrusion of the substrate having a second width (e.g., width 54), the protrusion being between each gate trench opening and also along the outer edge of the terminal trench opening;

[0052] Expanding the first width to a third width (e.g., width 55), wherein the third width extends a second distance (e.g., distance 51) into the substrate, the second distance being less than the first distance, thereby reducing the second width of the protrusion to a fourth width (e.g., width 56), wherein the fourth width extends substantially the second distance into the substrate;

[0053] Forming a first insulator (e.g., insulator 78) having a first thickness along at least a first portion of the sidewalls of the plurality of gate trench openings, the plurality of gate trench openings having the first width, wherein the first insulator extends a third distance from the bottom of the plurality of gate trench openings toward the first surface;

[0054] Forming a second insulator, such as insulator 80, having a second thickness along another portion of the sidewall, wherein the second insulator extends from the third distance toward the first surface;

[0055] Forming a gate conductor, such as conductor 83, in the plurality of gate trench openings and adjacent to the second insulator;

[0056] Forming a third insulator, such as insulator 92, covering the gate conductor and the protrusion;

[0057] Forming an etch stop layer, such as layer 94, on the third insulator;

[0058] Form a fourth insulator (e.g., insulator 96) covering the etch stop layer, wherein the material of the etch stop layer is not affected by the operation of removing the material of the fourth insulator;

[0059] Etch portions of the fourth insulator covering the protrusions to form a first opening through the fourth insulator, and etch portions of the fourth insulator covering the gate conductors in the non-active regions of the plurality of gate trench openings to form a second opening through the fourth insulator, wherein the etching substantially stops on the etch stop layer;

[0060] Extend the first opening and the second opening through the etch stop layer;

[0061] Etch the exposed portion of the third insulator through the first opening and into the protrusion and through the second opening to expose the gate conductors;

[0062] Form a source covering the protrusions and the plurality of gate trench openings in the active region, and extend through the first opening to form an electrical connection with the protrusion; and

[0063] Form a gate electrode covering the plurality of gate trench openings in the non-active region, and extend through the second opening to form an electrical connection with the gate conductors.

[0064] One embodiment of the method may further include forming an etch stop layer from a material that is not etched by an etchant that can etch the material of the fourth insulator.

[0065] Another embodiment may include forming the etch stop layer from silicon nitride.

[0066] One embodiment may further include doping portions of the protrusion to form a first doped region having a first conductivity type within the protrusion and adjacent to the second insulator on the sidewalls.

[0067] Embodiments of the method may further include forming a first doped region having a second conductivity type in the substrate adjacent to the second insulator and under the protrusion, wherein the first doped region extends laterally between each of the plurality of gate trench openings.

[0068] In one embodiment, the method may include doping portions of the protrusion to form a second doped region having a first conductivity type covering the first doped region.

[0069] One embodiment may further include etching through the protrusion to at least expose the first doped region.

[0070] Another embodiment may include forming the gate conductors from doped polysilicon.

[0071] Embodiments of the method may further include self-aligning siliciding at least a portion of the gate conductors after etching the exposed portion of the third insulator.

[0072] The method may also have an embodiment that may include forming a shielding conductor within and adjacent to the first insulator in the plurality of gate trench openings after the step of forming the first insulator.

[0073] One embodiment may include forming a spacer insulator that covers the shielding conductor and is positioned between the shielding conductor and the gate conductor.

[0074] Those skilled in the art will also understand that another example of an embodiment of a method of forming a semiconductor device may include:

[0075] providing a substrate having a first surface, the substrate being a semiconductor substrate of a first conductivity type;

[0076] forming a plurality of gate trench openings having a first width (e.g., width 53), the plurality of gate trench openings extending a first distance (e.g., distance 49) into the substrate, wherein each gate trench opening is located in an active region (e.g., region 21) of the semiconductor device and has a length (e.g., length 48) extending from the active region to a non-active region (e.g., region 22) of the semiconductor device, wherein the plurality of gate trench openings leave a protrusion of the substrate having a second width (e.g., width 54), the protrusion being between each gate trench opening;

[0077] extending the first width to a third width (e.g., width 55), wherein the third width extends a second distance (e.g., distance 51) into the substrate, the second distance being less than the first distance, thereby reducing the second width of the protrusion to a fourth width (e.g., width 56), wherein the fourth width extends substantially the second distance into the substrate;

[0078] forming a gate insulator (e.g., insulator 80) having a first thickness along at least a first portion of the sidewalls of the plurality of gate trench openings;

[0079] forming a gate conductor (e.g., conductor 83) within the plurality of gate trench openings and adjacent to the first portion of the gate insulator, the first portion being positioned along the first width of the plurality of gate trench openings;

[0080] forming a first insulator, such as insulator 92, that covers the gate conductor and the protrusion;

[0081] forming a stop layer, such as layer 94, on the first insulator;

[0082] forming a second insulator (e.g., insulator 96) that covers the stop layer, wherein the material of the stop layer is not affected by an operation of removing the material of the second insulator;

[0083] Remove a portion of the second insulator that covers the protruding portion to form a first opening through the second insulator, and substantially simultaneously remove a portion of the gate conductor in the non-active region of the second insulator that covers the plurality of gate trench openings to form a second opening through the second insulator, wherein the removal stops substantially on the stop layer;

[0084] Extend the first opening and the second opening through the stop layer;

[0085] Extend the first opening and the second opening through the exposed portion of the first insulator, including extending the first opening into the protruding portion and extending the second opening to expose the gate conductor; and

[0086] Form a first electrode in the active region that covers the protruding portion and the plurality of gate trench openings, wherein the first conductor extends through the first opening to form an electrical connection with the underlying portion of the protruding portion, and form a gate electrode in the non-active region that covers the plurality of gate trench openings and extends through the second opening to form an electrical connection with the gate conductor.

[0087] The method may also have an embodiment that may include forming a mask positioned between the active region and the non-active region that covers the plurality of gate trench openings, wherein the first opening is exposed in a first mask opening of the mask and the second opening is exposed in a second mask opening of the mask, and subsequently applying a conductor material to form the first electrode and the gate electrode.

[0088] One embodiment may also include forming a first doped region of a second conductivity type within the substrate and adjacent to the gate insulator, wherein the first doped region extends between each of the gate trench openings.

[0089] In one embodiment, the method may include extending the first opening into the protruding portion, which includes extending the first opening to at least contact the first doped region.

[0090] Another embodiment may include doping a portion of the protruding portion with a first conductivity type to form a source region of the semiconductor device.

[0091] Those skilled in the art should also understand that examples of embodiments of a method of forming a semiconductor device may include:

[0092] Providing a semiconductor substrate having a first surface;

[0093] Form a plurality of gate trench openings having a first width (e.g., width 53), the plurality of gate trench openings extending a first distance into the semiconductor substrate, and leaving a protrusion (e.g., protrusion 70) of the semiconductor substrate having a second width between the plurality of gate trench openings, wherein each gate trench opening has a length along the first surface (e.g., link 48) that extends from the active region of the semiconductor device into the non-active region of the semiconductor device;

[0094] Expand the first width of each gate trench opening to a third width (e.g., width 55) to obtain at least a second distance from the first surface, wherein the second distance is less than the first distance, thereby leaving each gate trench opening with the first width along the remainder of the first distance, wherein expanding the first width reduces the second width of the protrusion to a fourth width (e.g., width 56) to obtain at least the second distance;

[0095] Form a gate conductor in each of the plurality of gate trench openings;

[0096] Form a first insulator, such as insulator 92 and / or 80, having the fourth width on the sidewalls of the protrusion;

[0097] Form a stop layer, such as layer 94, covering the first insulator;

[0098] Form a second insulator, such as insulator 96, covering the stop layer;

[0099] Form a first opening through the second insulator that covers a portion of the protrusion in the active region, and substantially simultaneously form a second opening through the second insulator that covers a portion of the gate conductor in the non-active region, wherein the first opening and the second opening substantially stop on the stop layer;

[0100] Extending the first opening and the second opening through the first insulator includes extending the first opening into the protrusion; and

[0101] Form a first electrode in the active region covering the protrusion and the plurality of gate trench openings, wherein the first electrode extends through the first opening to form an electrical connection with the protrusion, and form a gate electrode in the non-active region covering the plurality of gate trench openings and extending through the second opening to form an electrical connection with the gate conductor.

[0102] An embodiment of the method may further include forming a gate conductor, including forming the gate conductor and each gate trench opening, wherein the gate conductor extends from within the active region into the non-active region.

[0103] The method may have an embodiment that may further include forming a stop layer, which includes forming the stop layer from a material that is not etched by an etchant that can etch the second insulator.

[0104] Another embodiment may include doping a portion of the protrusion to form a first doped region in the protrusion, wherein the doping is performed before the step of forming the first insulator.

[0105] In view of all of the above, a novel device and method are clearly disclosed. Among other features, a semiconductor device is included that forms protrusions positioned between gate trenches, wherein a portion of the protrusion near the surface has a narrower width than the underlying portion of the protrusion. The narrower portion of the protrusion has sidewalls having a material on the sidewalls that is substantially not etched by an etchant that etches the material of the protrusion. This results in self-alignment between the source contact and the active trench portion 33. Such a method of forming a semiconductor device improves the reliability of the source connection and provides the device with a more reliable Rdson and improved UIS performance.

[0106] In addition, forming the source contact opening and the gate contact opening substantially simultaneously reduces the manufacturing cost of the semiconductor device.

[0107] Although the subject matter of this specification has been described by specific preferred embodiments and exemplary embodiments, the foregoing drawings and description of this specification merely depict typical and non-limiting examples of the embodiments of the subject matter, and thus do not regard the foregoing drawings and description as limiting its scope. Many alternatives and variations will be obvious to those skilled in the art. As those skilled in the art will understand, different steps may be used to form the semiconductor device, provided that the step forms a material along the sidewalls of the protrusion that is substantially not etched by removing the protrusion, and provided that the source contact opening and the gate contact opening are formed by substantially simultaneous operations.

[0108] The subject matter of a particular MOSFET structure has been described, but the method is directly applicable to other transistor structures, including BiCMOS, metal semiconductor FET (MESFET), HFET, other transistor structures, and diodes.

[0109] As reflected in the claims below, aspects of the present invention may have fewer features than all of the features of a single embodiment disclosed above. Accordingly, the claims set forth below are hereby expressly incorporated into the description of the drawings, and each claim itself represents a separate embodiment of the present invention. In addition, although some embodiments described herein include some features included in other embodiments but do not include other features included therein, those skilled in the art should understand that combinations of features of different embodiments are intended to be within the scope of the present invention and are intended to form different embodiments.

Claims

1. A method of forming a semiconductor device, comprising: Providing a substrate having a first surface, the substrate being a semiconductor substrate of a first conductivity type; Forming a plurality of gate trench openings having a first width, the gate trench openings extending a first distance into the substrate, wherein each gate trench opening is located in an active region of the semiconductor device and has a length extending from the active region to a non-active region of the semiconductor device; Forming a terminal trench opening having the first width, the terminal trench opening extending into the substrate, wherein the terminal trench opening surrounds the plurality of gate trench openings, and wherein the plurality of gate trench openings leave a protrusion of the substrate having a second width, the protrusion being between each gate trench opening and also along an outer edge of the terminal trench opening; Expanding the first width to a third width, wherein the third width extends a second distance into the substrate, the second distance being less than the first distance, thereby reducing the second width of the protrusion to a fourth width, wherein the fourth width extends substantially the second distance into the substrate; Forming a first insulator having a first thickness along at least a first portion of sidewalls of the plurality of gate trench openings having the first width, wherein the first insulator extends a third distance from a bottom of the plurality of gate trench openings toward the first surface; Forming a second insulator having a second thickness along another portion of the sidewalls, wherein the second insulator extends from the third distance toward the first surface; Forming a gate conductor in the plurality of gate trench openings and adjacent to the second insulator; Forming a third insulator covering the gate conductor and the protrusion; Forming an etch stop layer on the third insulator; Forming a fourth insulator covering the etch stop layer, wherein a material of the etch stop layer is not affected by an operation of removing a material of the fourth insulator; Etching a portion of the fourth insulator covering the protrusion to form a first opening through the fourth insulator, and etching a portion of the fourth insulator covering the gate conductor in the non-active region of the plurality of gate trench openings to form a second opening through the fourth insulator, wherein the etching substantially stops on the etch stop layer; Extending the first opening and the second opening through the etch stop layer; Etching an exposed portion of the third insulator through the first opening and into the protrusion and through the second opening to expose the gate conductor; Forming a source in the active region covering the protrusion and the plurality of gate trench openings and extending through the first opening to form an electrical connection with the protrusion; And Forming a gate electrode in the non-active region covering the plurality of gate trench openings and extending through the second opening to form an electrical connection with the gate conductor.

2. The method according to claim 1, wherein forming the etch stop layer comprises: Forming the etch stop layer from silicon nitride.

3. The method according to claim 1 further comprises: A first doped region of a second conductivity type is formed in the substrate adjacent to the second insulator and under the protrusion, wherein the first doped region extends laterally between each of the plurality of gate trench openings, and A portion of the protrusion is doped to form a second doped region of the first conductivity type covering the first doped region.

4. The method according to claim 3, wherein etching the exposed portion of the third insulator through the first opening and into the protrusion comprises: Etch through the protrusion to at least expose the first doped region.

5. A method of forming a semiconductor device, comprising: Providing a substrate having a first surface, the substrate being a semiconductor substrate of a first conductivity type; Forming a plurality of gate trench openings having a first width, the plurality of gate trench openings extending a first distance into the substrate, wherein each gate trench opening is located in an active region of the semiconductor device and has a length extending from the active region to a non-active region of the semiconductor device, wherein the plurality of gate trench openings leave a protrusion of the substrate having a second width, the protrusion being between each gate trench opening; Expanding the first width to a third width, wherein the third width extends a second distance into the substrate, the second distance being less than the first distance, thereby reducing the second width of the protrusion to a fourth width, wherein the fourth width substantially extends the second distance into the substrate; Forming a gate insulator having a first thickness along at least a first portion of the sidewalls of the plurality of gate trench openings; Forming a gate conductor in the plurality of gate trench openings and adjacent to a first portion of the gate insulator positioned along the first width of the plurality of gate trench openings; Forming a first insulator covering the gate conductor and the protrusion; Forming a stop layer on the first insulator; Forming a second insulator covering the stop layer, wherein the material of the stop layer is not affected by an operation of removing the material of the second insulator, Removing a portion of the second insulator covering the protrusion to form a first opening through the second insulator, and substantially simultaneously removing a portion of the second insulator covering the gate conductor in the non-active region of the plurality of gate trench openings to form a second opening through the second insulator, wherein the removal substantially stops on the stop layer; Extending the first opening and the second opening through the stop layer; Extending the first opening and the second opening through an exposed portion of the first insulator, including extending the first opening into the protrusion and extending the second opening to expose the gate conductor; And Forming a first electrode covering the protrusion and the plurality of gate trench openings in the active region, wherein the first electrode extends through the first opening to form an electrical connection with a lower portion of the protrusion, and forming a gate electrode covering the plurality of gate trench openings in the non-active region and extending through the second opening to form an electrical connection with the gate conductor.

6. The method according to claim 5 further comprises: Form a first doped region of a second conductivity type within the substrate and adjacent to the gate insulator, wherein the first doped region extends between each gate trench opening, and Extend the first opening to at least contact the first doped region.

7. The method according to claim 5 further comprises: Dope a portion of the protrusion with a first conductivity type to form a source region of the semiconductor device.

8. A method of forming a semiconductor device, comprising: Providing a semiconductor substrate having a first surface; Forming a plurality of gate trench openings having a first width, the plurality of gate trench openings extending a first distance into the semiconductor substrate, and leaving a protrusion of the semiconductor substrate having a second width between the plurality of gate trench openings, wherein each gate trench opening has a length along the first surface extending from the active region of the semiconductor device to the non-active region of the semiconductor device; Expanding the first width of each gate trench opening to a third width for at least a second distance from the first surface, wherein the second distance is less than the first distance, thereby leaving each gate trench opening with the first width along the remaining portion of the first distance, wherein expanding the first width reduces the second width of the protrusion to a fourth width for at least the second distance; Forming a gate conductor in each of the plurality of gate trench openings; Forming a first insulator on the sidewalls of the protrusion, the first insulator having the fourth width; Forming a stop layer covering the first insulator; Forming a second insulator covering the stop layer; Forming a first opening through the second insulator covering a portion of the protrusion in the active region, and substantially simultaneously forming a second opening through the second insulator covering a portion of the gate conductor in the non-active region, wherein the first opening and the second opening substantially stop on the stop layer; Extending the first opening and the second opening through the first insulator, including extending the first opening into the protrusion; And Forming a first electrode covering the protrusion and the plurality of gate trench openings in the active region, wherein the first electrode extends through the first opening to form an electrical connection with the protrusion, and forming a gate electrode covering the plurality of gate trench openings in the non-active region and extending through the second opening to form an electrical connection with the gate conductor.

9. The method according to claim 8, wherein forming the gate conductor comprises: Form the gate conductor and each gate trench opening, wherein the gate conductor extends from within the active region into the non-active region.

10. The method according to claim 8 further comprises: Dope a portion of the protrusion to form a first doped region in the protrusion, wherein the doping is performed before the step of forming the first insulator.

Images