Vertical Field-Effect Transistor Device and Method of Manufacturing the Same

Abstract

The present invention provides a vertical field effect transistor (VFET) device and a method for manufacturing the same. The method for manufacturing a VFET device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed on the substrate, and a doped layer formed on the substrate between the fin structures, the doped layer including a bottom source / drain (S / D) region; forming a shallow trench under the top surface of the substrate and through the doped layer and the substrate between the fin structures to isolate the fin structures from each other; filling the shallow trench and the space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above the height of the top surface of the doped layer except in the shallow trench such that a shallow trench isolation (STI) structure having a top surface at or above the height of the top surface of the doped layer is formed in the shallow trench; forming gate structures on the fin structures respectively; and forming top S / D regions on the fin structures.

Description

Technical Field

[0001] Devices and methods consistent with exemplary embodiments of the inventive concept relate to the structure of a vertical field effect transistor (VFET) and a method of manufacturing the same. Background Art

[0002] A VFET is produced or manufactured by forming a vertical fin for a current flow channel on a semiconductor substrate, forming a bottom source / drain (S / D) region and a top S / D region under and above the vertical fin, respectively, and forming a gate structure on sidewalls of the vertical fin. Thus, different from the lateral current flow in the prior art planar FET or finFET, current flows in a direction perpendicular to the semiconductor substrate in the VFET.

[0003] Since VFET devices formed from VFETs are known to have various advantages, including a high density structure superior to planar FET or finFET devices, more improved structures and methods of manufacturing VFET devices are sought. Summary of the Invention

[0004] Various embodiments of the inventive concept may provide an improved method of manufacturing a VFET device and a VFET device manufactured thereby.

[0005] According to an aspect of an exemplary embodiment, a method of manufacturing a VFET device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed on the substrate, and a doped layer formed on the substrate between the fin structures, the doped layer including a bottom source / drain (S / D) region; forming a shallow trench under a top surface of the substrate and through the doped layer and the substrate between the fin structures to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a height of a top surface of the doped layer except in the shallow trench such that a shallow trench isolation (STI) structure having a top surface at or above a height of the top surface of the doped layer is formed in the shallow trench; forming a gate structure on the fin structures, respectively; and forming a top S / D region on the fin structures.

[0006] According to one aspect of an exemplary embodiment, a method for manufacturing a VFET device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed on the substrate, and a doped layer formed on the substrate between the fin structures, the doped layer including a bottom source / drain (S / D) region; forming a shallow trench under the top surface of the substrate and through the doped layer and the substrate between the fin structures to isolate the fin structures from each other; filling a space between the fin structures including the shallow trench with an insulating material; etching the insulating material such that the insulating material filled between the fin structures and above the shallow trench is etched later than the insulating material filled in other positions to form an STI structure in the shallow trench; forming gate structures on the fin structures respectively; and forming a top S / D region on the fin structures.

[0007] According to one aspect of an exemplary embodiment, a VFET device may include: a substrate; a doped layer formed on the substrate by doping with impurities, the doped layer including a bottom source / drain (S / D) region; a plurality of fin structures formed vertically on the substrate above the doped layer; a top S / D region formed on the fin structures; and an STI structure filling a shallow trench formed under the top surface of the substrate and through the doped layer and the substrate between the fin structures, wherein a top surface of the STI structure is at or above a height of a top surface of the doped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0009] Figures 1A to 1I A cross-sectional side view of a method for manufacturing a VFET device structure according to an embodiment is shown;

[0010] Figures 2A to 2L A cross-sectional side view of a method for manufacturing a VFET device according to an embodiment is shown; and

[0011] Figures 3A to 3L A cross-sectional side view of a method for manufacturing a VFET device according to an embodiment is shown; DETAILED DESCRIPTION

[0012] Various embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. These embodiments are merely exemplary and may be embodied in many different forms and should not be construed as limiting the inventive concept. Rather, these embodiments are provided only so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity; thus, the drawings are not necessarily drawn to scale and some features may be exaggerated to show details of particular components or elements. Accordingly, the specific structural details and functional details disclosed herein are not to be construed as limiting, but merely as a representative basis for teaching those skilled in the art to variously employ the embodiments in methods and structures.

[0013] It is not excluded that the embodiments provided herein are associated with one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the inventive concept. For example, even if what is described in a particular embodiment is not described in a different embodiment, it may be understood to be relevant or combinable with the different embodiment, unless otherwise mentioned in its description.

[0014] For the purposes of the description hereinafter, the terms “upper”, “lower”, “top”, “bottom”, “left” and “right” and their derivatives may relate to the disclosed structures based on context as oriented in the drawings. The same reference numerals in different drawings may refer to the same structural components or their elements.

[0015] It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it may be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly connected to” or “directly coupled to” another element or layer, no intervening elements or layers are present.

[0016] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of” when following a list of elements modify the entire list of elements and not individual elements of the list. Thus, for example, both “at least one of A, B or C” and “A, B and / or C” mean A, B, C or any combination thereof. Expressions such as “at least one of” when following a list of elements modify the entire list of elements and not individual elements of the list.

[0017] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. It will also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly so defined.

[0018] Figures 1A to 1I A cross-sectional side view of a method of manufacturing a VFET device structure according to an embodiment is shown.

[0019] Figure 1A An intermediate VFET device structure 100 is shown, in which a substrate 101 is provided and a plurality of fin structures 102-1 to 102-4 are vertically formed on the substrate 101. Each of the fin structures 102-1 to 102-4 may include a fin 102F and a mask 102M formed on the fin 102F. However, depending on the choice of manufacturing process, the mask 102M may not be included in each of the fin structures 102-1 to 102-4. For the design purpose of forming a VFET device from the intermediate VFET device structure 100, the fin structures 102-1 and 102-2 are spaced apart from the fin structures 102-3 and 102-4 such that the VFETs formed around the fin structures 102-1 and 102-2 are isolated from the VFETs formed around the fin structures 102-3 and 102-4. Isolation of the VFETs will be performed by forming an insulating structure such as a shallow trench isolation (STI) structure between the fin structures 102-1 and 102-2 and the fin structures 102-3 and 102-4, which will be described later.

[0020] In Figure 1A the substrate 101 and the fin 102F may be formed of a semiconductor material such as silicon (Si), germanium (Ge), or a compound thereof (SiGe). The mask 102F formed on the fin 102M may include a dielectric material such as silicon nitride (SiN) for patterning the fin 102F on the substrate 101. In addition, the intermediate VFET structure 100 includes a doped layer 103, which is formed by epitaxially growing a semiconductor layer on the substrate 101 and doping impurities therein. The material forming the doped layer 103 may be similar to the material forming the substrate 101. When the intermediate VFET device structure 100 is completed, the impurities doped in the doped layer 103 may be boron or a combination thereof to form a p-type VFET, or may be phosphorus, arsenic, indium, or a combination thereof to form an n-type VFET. The doped layer 103 is provided to form the bottom source / drain (S / D) regions of the VFETs of the intermediate VFET device structure 100.

[0021] Figure 1BShows that the bottom spacer 104 is deposited on the top surface of the doped layer 103 between the fin structures 102-1 to 102-4 to insulate the doped layer 103 from adjacent elements such as gate structures to be discussed later. The bottom spacer 104 may include a low-k dielectric material such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), silicon oxynitride (SiON), silicon boron carbon nitride (SiBCN), silicon oxycarbonitride (SiOCN), or a combination thereof, but is not limited thereto. The bottom spacer 104 can be formed on the doped layer 103 by at least one of methods such as chemical vapor deposition (CVD), plasma-enhanced CVD (PEVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), anisotropic deposition, etc., but is not limited thereto.

[0022] Figure 1C Shows that the shallow trench 105 is etched from the bottom spacer 104 and the doped layer 103 into the substrate 101 to provide space for STI to be processed later. The method used for etching in this process can be dry etching, but is not limited thereto.

[0023] Figure 1D Shows that, before forming the STI, the outer surfaces of the fin structures 102-1 to 102-4, the top surface of the bottom spacer 104 between the fin structures 102-1 to 102-4, and the surface of the shallow trench 105 are lined or deposited with a dielectric layer 106 including a material such as SiN by a method such as ALD but not limited thereto to prevent damage from subsequent STI processes using oxide materials, such as oxidation of these elements.

[0024] Figure 1E Shows that the STI dielectric 107 as an insulating material is deposited on the dielectric layer 106 covering the outer surfaces of the fin structures 102-1 to 102-4, the top surface of the bottom spacer 104 between the fin structures 102-1 to 102-4, and the surface of the shallow trench 105 by a method such as CVD or floating vapor CVD but not limited thereto to completely fill the space between the fin structures 102-1 to 102-4 and the shallow trench 105. The STI dielectric 107 formed by this deposition process can be formed of a dielectric oxide material (such as SiO, silicon dioxide (SiO2), silicon oxynitride (SiO x N y ) or a combination thereof, but is not limited thereto).

[0025] Figure 1FIllustrated is that the STI dielectric 107 is planarized (or polished) by a method such as, but not limited to, chemical mechanical planarization (CMP), such that the top surface of the planarized STI dielectric 107 is coplanar with the top surfaces of the fin structures 102-1 to 102-4, and the dielectric layer 106 lined on the top surfaces of the fin structures 102-1 to 102-4 is exposed.

[0026] Figure 1G Illustrated is that the planarized STI dielectric 107 is etched by dry etching or wet etching, but not limited to, to expose the fin structures 102-1 to 102-4 lined with the dielectric layer 106 thereon and form the STI structure 107-1. Here, even after etching the planarized STI dielectric 107, the dielectric layer 106 remains on the outer surfaces of the fin structures 102-1 to 102-4, the top surface of the bottom spacer 104, the side surfaces of the bottom spacer 104, and the portions of the surfaces forming the shallow trenches 105 on the side surfaces of the doped layer 103, because the dielectric layer 106 is formed of a material (such as SiN) having an etching selectivity with respect to the material forming the STI dielectric 107 (such as SiO or SiO2).

[0027] Meanwhile, referring to 1G, although the STI dielectric 107 disposed between the fin structures 102-1 to 102-4 is completely removed by the etching to form a gate structure on the fin structures 102-1 to 102-4 later, the STI dielectric 107 at the position above the shallow trench 105 can be recessed excessively below the height of the top surface of the doped layer 103. Therefore, the STI structure 107-1 formed by etching in the Figure 1G process has a top surface below the height of the top surface of the doped layer 103.

[0028] Figure 1H Illustrated is that, after stripping the dielectric layer 106 (not shown) from the outer surfaces of the fin structures 102-1 to 102-4, the top surface of the bottom spacer 104, the side surfaces of the bottom spacer 104, and the portions of the surfaces forming the shallow trenches 105 on the side surfaces of the doped layer 103, on it and on Figure 1GOn the top surface of the STI structure 107-1 formed by an etching process in the process, a gate structure 108 is deposited. The deposition of the gate structure 108 can be performed by a method such as, but not limited to, ALD. The gate structure 108 may include: a conductor layer 108-1 formed of a metal or a metal compound, such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof, but not limited to this; and a high-k layer 108-2 formed of a metal oxide material or a metal silicate, such as an oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof, but not limited to this.

[0029] Figure 1I It shows the etching by a method such as, but not limited to, dry etching in Figure 1H the process of depositing the gate structure 108 to expose the top surfaces of the fin structures 102-1 to 102-4, the top surface of the bottom spacer 104 between the fin structures 102-1 to 102-4, and the top surface of the STI structure 107-1 disposed in the shallow trench 105, thereby forming a VFET device structure.

[0030] Here, it should be noted that since the STI dielectric 107 is overly recessed at the shallow trench 105 in Figure 1G the process, when the gate structure 108 is formed and etched in Figure 1H and Figure 1I the process, the residue 108-3 of the gate structure 108 may remain at the portions of the side surfaces of the bottom spacer 104 and the side surfaces of the doped layer 103 that form the shallow trench 105. Since this residue 108-3 of the gate structure 108 contacts or is disposed very close to the doped layer 103, a short circuit may occur between the residue 108-3 of the gate structure 108 and a part of the bottom S / D region formed at the side surface of the doped layer 103, which may increase unnecessary capacitance, thereby reducing the AC performance of the VFET device formed by the VFET device structure 100 and adversely affecting the productivity of the VFET device.

[0031] Therefore, more improved methods for manufacturing the VFET device structure are considered below.

[0032] Figures 2A to 2L A cross-sectional side view showing a method for manufacturing a VFET device according to an embodiment is shown.

[0033] In the process performed in the present embodiment as Figures 2A to 2F shown, the process is the same as that in Figures 1A to 1Fis the same as or similar to the process performed in the previous embodiments shown. Accordingly, although a repetitive description of the process is omitted, the intermediate VFET device structure 200 according to the present embodiment includes a substrate 201, a plurality of fin structures 202-1 to 202-4 each including a fin 202F and a mask 202M, a doping layer 203, a bottom spacer 204, a shallow trench 205, a dielectric layer 206, and an STI dielectric 207 as an insulating material.

[0034] Figure 2G It is shown that, as in Figure 1F in the process of Figure 2F after planarizing the STI dielectric 207, in the planarized STI dielectric 207, preferably but not necessarily directly beneath its top surface, at a position overlapping with the shallow trench 205, a recessed delay structure 210 is inserted. The recessed delay structure 210 may be formed of a material (such as SiN but not limited thereto) having an etching selectivity with respect to the STI dielectric layer 207 formed of a dielectric oxide material. The width WR of the recessed delay structure 210 may be the same as or slightly smaller than the width WS of the shallow trench 205. However, the inventive concept is not limited thereto. Accordingly, the recessed delay structure 210 may be capable of delaying the etching of the planarized STI dielectric 207 at a position above the shallow trench 205 as will be described below with reference to Figure 2H is described.

[0035] Referring to Figure 2G , the recessed delay structure 210 is shown to be inserted in the STI dielectric 207 after depositing and planarizing the STI dielectric 207. However, the inventive concept is not limited thereto, because according to an embodiment, the recessed delay structure 210 may be inserted in the STI dielectric 207 before planarizing the STI dielectric 207. For example, after patterning Figure 2E the STI dielectric 207 shown to ensure an area where the recessed delay structure 210 is to be inserted, the STI dielectric 207 is dry-etched to form a recess therein, and the recessed delay structure 210 is deposited before planarizing the STI dielectric 207 including the recessed delay structure 210 by CMP.

[0036] Figure 2HIt shows that the planarized STI dielectric 207 is etched by dry etching or wet etching but not limited thereto, to expose the fin structures 202-1 to 202-4 of the underlying dielectric layer 206 and form the STI structure 207-1. Through this etching process, the planarized STI dielectric 207 filled between the fin structures 202-1 to 202-4 is completely removed above the height of the top surface of the doped layer 203, specifically above the height of the top surface of the bottom spacer 204, except at the positions of the shallow trenches 205, so as to form a gate structure on the fin structures 202-1 to 202-4 later.

[0037] It should be noted here that, due to the recess delay structure 210 inserted in the STI dielectric 207 in the Figure 2G process, compared with other parts of the STI dielectric 207, the part of the STI dielectric 207 at or near the position where the recess delay structure 210 is inserted above the shallow trench 205 can be etched later, thus preventing the excessive indentation of the STI dielectric 207 at the position above the shallow trench 205 that may occur in the Figure 1G etching process. Alternatively, the STI structure 207-1 formed by etching in this process may have a protrusion 211 protruding above the height of the top surface of the bottom spacer 204 at the shallow trench 205 between the fin structures 202-1 and 202-2 and the fin structures 202-3 and 202-4. The protrusion 211 of the STI structure 207-1 may be trapezoidal in shape above the height of the top surface of the bottom spacer 204, but not limited thereto. Here, the top surface and side surfaces of the protrusion 211 may be above the height of the top surface of the bottom spacer 204 and below the height of the top surface of the fin 202F.

[0038] From Figure 2H the process, it is further noted that although Figure 2G shows that the recess delay structure 210 is inserted directly below the top surface of the planarized STI dielectric 207 in the planarized STI dielectric 207, the recess delay structure 210 may be inserted at a certain distance below the top surface of the planarized STI dielectric 207, as long as the recess delay structure 210 can delay the etching of the planarized STI dielectric 207 such that the protrusion 211 can be formed at the shallow trench 205 between the fin structures 202-1 and 202-2 and the fin structures 202-3 and 202-4 above the height of the top surface of the bottom spacer 204.

[0039] Figure 2HIt is further shown that even after etching and planarizing the STI dielectric 207, the dielectric layer 206 remains on the outer surfaces of the fin structures 202-1 to 202-4 and on the top surface of the bottom spacer 204 between the fin structures 202-1 to 202-4 because the dielectric layer 206 is formed of a material (such as SiN) that has an etching selectivity with respect to the material forming the STI dielectric 207 (such as SiO or SiO2). However, the STI structure 207-1 formed by the etching process of Figure 2H specifically its protrusion 211, has no dielectric layer 206 thereon.

[0040] Figure 2I It is shown that after stripping the dielectric layer 206 (not shown) from the outer surfaces of the fin structures 202-1 to 202-4 and from the top surface of the bottom spacer 204 between the fin structures 202-1 to 202-4, the gate structure 208 is deposited thereon and on the protrusion 211 of the STI structure 207-1. Here, as described with reference to Figure 1H the deposition of the gate structure 208 can be performed by a method such as but not limited to ALD, and the gate structure 208 can include: a conductor layer 208-1 formed of a metal or a metal compound, such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof, but not limited thereto; and a high-κ layer 208-2 formed of a metal oxide material or a metal silicate, such as an oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof, but not limited thereto.

[0041] Figure 2J It is shown that the gate structure 208 deposited in the process of Figure 2I is etched by a method such as but not limited to dry etching to expose the top surfaces of the fin structures 202-1 to 202-4, the top surface of the bottom spacer 204 between the fin structures 202-1 to 202-4, and the protrusion 211 of the STI structure 207-1, thereby forming a VFET device structure corresponding to the VFET device structure shown in Figure 1I Here, it should be noted that different from the processes of

[0042] when in Figure 1H and Figure 1I the process of Figure 2I and Figure 2JWhen forming and etching the gate structure 208 in the process, residues of the gate structure 208 do not remain on the side surfaces of the bottom spacer 204 and at the portions of the side surfaces of the doped layer 203 where the shallow trench 205 is formed. This is because the recess delay structure 210 is inserted into the STI dielectric 207 to delay the etching of the STI dielectric 207 at the position of the shallow trench 205, thereby forming the STI structure 207-1 having the protrusion 211 to prevent such residues of the gate structure 208 from being formed. Therefore, a short circuit does not occur between the residues of the gate structure 208 and a part of the bottom S / D region formed at the side surface of the doped layer 203 as in the Figure 2H process. Therefore, the method of manufacturing the VFET device structure according to the present embodiment can prevent an unnecessary increase in capacitance (which reduces the AC performance of the VFET device formed by the intermediate VFET device structure 100) and a decrease in the productivity of the VFET device. Figure 1I process.

[0043] It should also be noted that, in order to be consistent with the inventive concept, different processes other than the Figures 2G to 2J etching process using the delay recess structure 210 can be used, as long as the etching of the STI dielectric 207 at the position above the shallow trench 205 can be delayed to prevent residues of the gate structure 208 from remaining on the side surfaces of the bottom spacer 204 and at the portions of the side surfaces of the doped layer 203 where the shallow trench 205 is formed. In addition, although the delayed etching according to the present embodiment produces the STI structure 207-1 having the protrusion 211 above the heights of the top surfaces of the doped layer 203 and the bottom spacer 204 to prevent residues of the gate structure 208 from being formed in the shallow trench 205, the inventive concept is not limited thereto. According to an embodiment, the delayed etching can be controlled such that the top surface of the STI structure 207-1 is formed not below the heights of the top surface of the doped layer 203 or the top surface of the bottom spacer 204, as long as the delayed etching can prevent residues of the gate structure 208 from being formed in the shallow trench 205 as Figure 1G shown.

[0044] Figure 2K and 2L show that, in Figure 2I and Figure 2JAfter the fin structures 202-1 to 202-4 on which the gate structure 208 is deposited and etched are provided, the VFET device structure is planarized and / or etched again to remove at least the mask 202M from the fin structures 202-1 to 202-4, and an interlayer dielectric (ILD) layer 212, a top spacer 213, and a top S / D region 214 are further deposited and formed, and a contact liner 215 and a contact structure 216 are further formed on the top S / D region 214, thereby forming a desired VFET device. Here, the ILD layer 212 formed of a material including nitride, oxide, or a combination thereof but not limited thereto may be deposited between the fin structures 202-1 to 202-4. The top spacer 213 formed of a material similar to or different from that of the bottom spacer 204 may be deposited on the gate structure 208 to electrically isolate the gate structure 208 from the top S / D region 214. The top S / D region 214 may also be formed by epitaxially growing a semiconductor layer on the fin structures 202-1 to 202-4 from which the mask 202M has been removed and doping impurities therein.

[0045] Figures 3A to 3L A cross-sectional side view showing a method of manufacturing a VFET device according to an embodiment is shown.

[0046] As described in detail below, the process performed in this embodiment is different from that in Figures 2A to 2L the previous embodiment shown in that the process of forming the bottom spacer on the doped layer is performed after forming and etching the STI dielectric in the intermediate VFET device structure, while in the previous embodiment, the process of forming the bottom spacer on the doped layer is performed after forming and etching the STI dielectric in the intermediate VFET device structure.

[0047] Figure 3A An intermediate VFET device structure 300 is shown, in which a substrate 301 is provided and a plurality of fin structures 302-1 to 302-4 are vertically formed on the substrate 301. Each of the fin structures 302-1 to 302-4 may include a fin 302F and a mask 302M formed on the fin 302F. However, depending on the choice of manufacturing process, the mask 302M may not be included in each of the fin structures 302-1 to 302-4. For the design purpose of forming a VFET device from the intermediate VFET device structure 300, the fin structures 302-1 and 302-2 are spaced apart from the fin structures 302-3 and 302-4 such that the VFETs formed around the fin structures 302-1 and 302-2 are isolated from the VFETs formed around the fin structures 302-3 and 302-4.

[0048] Figure 3BShows the outer surfaces of the fin structures 302-1 to 302-4 and the top surface of the doped layer 303 between the fin structures 302-1 to 302-4, and a dielectric layer 306 including a material such as SiN is lined or deposited by a method such as ALD but not limited thereto to prevent damage such as oxidation of these elements from a subsequent STI process using an oxide material.

[0049] Figure 3C Shows that the shallow trench 305 is etched from the doped layer 303 lined with the dielectric layer 306 into the substrate 301 to provide space for the STI to be processed later. The method used for etching in this process can be dry etching but is not limited thereto.

[0050] Figure 3D Shows that on the dielectric layer 306 covering the outer surfaces of the fin structures 302-1 to 302-4 and the top surface of the doped layer 303 between the fin structures 302-1 to 302-4 and in the shallow trench 305, an STI dielectric 307 as an insulating material is deposited by a method such as CVD or floating vapor CVD but not limited thereto to completely fill the space between the fin structures 302-1 to 302-4 and the shallow trench 305. The STI dielectric 307 formed by this deposition process can be formed of a material (such as SiO or SiO2 but not limited thereto) having an etching selectivity with respect to the dielectric layer 306.

[0051] Figure 3E Shows that the STI dielectric 307 is planarized (or polished) by a method such as CMP but not limited thereto, such that the top surface of the planarized STI dielectric 307 is coplanar with the top surfaces of the fin structures 302-1 to 302-4, and the dielectric layer 306 padded on the top surfaces of the fin structures 302-1 to 302-4 is exposed.

[0052] Figure 3F Shows that after Figure 3F the STI dielectric 307 is planarized in the process, a recessed delay structure 310 is inserted in the STI dielectric 307, preferably but not necessarily directly under the top surface of the STI dielectric 307 at a position overlapping the shallow trench 305. The recessed delay structure 310 can be formed of a material (such as SiN but not limited thereto) having an etching selectivity with respect to the STI dielectric 307 formed of a dielectric oxide material. The width WR of the recessed delay structure 310 can be the same as or slightly smaller than the width WS of the shallow trench 305. However, the inventive concept is not limited thereto. Thus, the recessed delay structure 310 can be as will be described below with reference to Figure 3Getching of the STI dielectric 307 that can delay planarization at a position above the shallow trench 305 is described.

[0053] Referring Figure 3F , the recess delay structure 310 is shown inserted into the STI dielectric 307 after deposition and planarization of the STI dielectric 307. However, the inventive concept is not limited thereto, because according to an embodiment, the recess delay structure 310 can be inserted into the STI dielectric 307 before planarization of the STI dielectric 307.

[0054] Figure 3G It is shown that the planarized STI dielectric 307 is etched by dry etching or wet etching but not limited thereto to expose the fin structures 302-1 to 302-4 on which the dielectric layer 306 is mounted and to form the STI structure 307-1. Through this etching process, the planarized STI dielectric 307 filled between the fin structures 302-1 to 302-4 except at the position of the shallow trench 305 above the height of the top surface of the doped layer 303 is completely removed so as to form a gate structure on the fin structures 302-1 to 302-4 later.

[0055] It should be noted here that, due to the recess delay structure 310 inserted into the STI dielectric 307 in the Figure 3F process, compared with other parts of the STI dielectric 307, the part of the STI dielectric 307 at or near the position where the recess delay structure 310 is inserted above the shallow trench 305 can be etched later, thereby preventing the excessive recess of the STI dielectric 307 at the position above the shallow trench 305 that may occur in the Figure 3G etching process. Alternatively, the STI structure 307-1 formed by etching in this process can have a protrusion 311 protruding above the height of the top surface of the doped layer 303 at the shallow trench 305 between the fin structures 302-1 and 302-2 and the fin structures 302-3 and 302-4. The protrusion 311 of the STI structure 307-1 can be trapezoidal in shape above the height of the top surface of the doped layer 303 but not limited thereto. Here, the top surface and the side surface of the protrusion 311 can be above the height of the top surface of the doped layer 303 and below the height of the top surface of the fin 302F.

[0056] From Figure 3G the process it is further noted that although Figure 3Fshows the insertion of a recessed delay structure 310 in the planarized STI dielectric 307 directly beneath the top surface of the planarized STI dielectric 307. However, the recessed delay structure 310 can be inserted at a distance beneath the top surface of the planarized STI dielectric 307 as long as the recessed delay structure 310 can delay the etching of the planarized STI dielectric 307 such that the protrusions 311 can be formed at the shallow trench 305 between the fin structures 302-1 and 302-2 and the fin structures 302-3 and 302-4 above the height of the top surface of the doped layer 303.

[0057] Figure 3G Further shown is that even after etching the planarized STI dielectric 307, the dielectric layer 306 remains on the outer surfaces of the fin structures 302-1 to 302-4 and the top surface of the doped layer 303 between the fin structures 302-1 to 302-4 because the dielectric layer 306 is formed of a material (such as SiN) having an etching selectivity relative to the material forming the STI dielectric 307 (such as SiO or SiO2). However, the STI structure 307-1 formed by Figure 3G the etching process, specifically its protrusions 311, does not have the dielectric layer 306 thereon.

[0058] Figure 3H shows that after stripping the dielectric layer 306 (not shown) from the outer surfaces of the fin structures 302-1 to 302-4 and the top surface of the doped layer 303 between the fin structures 302-1 to 302-4, a bottom spacer 304 is deposited on the top surface of the doped layer 303 between the fin structures 302-1 to 302-4 and on the protrusions 311 of the STI structure 307-1 to isolate the doped layer 303 from adjacent elements such as a gate structure to be discussed later. The bottom spacer 304 can include a low-k dielectric material such as SiO, SiN, SiON, SiCN, SiON, SiBCN, SiOCN, or a combination thereof, but is not limited thereto. The bottom spacer 304 can be formed on the doped layer 304 between the fin structures 302-1 to 302-4 and on the protrusions 311 by at least one of methods such as CVD, PEVD, PVD, ALD, PEALD, anisotropic deposition, etc., but is not limited thereto. It should be noted here that due to the protrusions 311, the bottom spacer 304 conformally deposited on the protrusions 311 presents a corresponding protrusion shape as Figure 3H shown.

[0059] Figure 3I shows the deposition of the gate structure 308 on the outer surfaces of the fin structures 302-1 to 302-4 and the top surface of the bottom spacer 304. Here, as referred to Figure 2IAs shown, the deposition of the gate structure 308 can be performed by a method such as, but not limited to, ALD, and the gate structure 308 can include: a conductor layer 308-1 formed of a metal or a metal compound, such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof, but not limited thereto; and a high-κ layer 308-2 formed of a metal oxide material or a metal silicate, such as an oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof, but not limited thereto.

[0060] Figure 3J It is shown that the gate structure 308 deposited in the process of Figure 3I is etched by a method such as, but not limited to, dry etching, so as to expose the top surfaces of the fin structures 302-1 to 302-4 and the top surface of the bottom spacer 304, thereby forming a VFET device structure corresponding to the Figure 2J shown VFET device structure.

[0061] Here, it should be noted that, different from the process of Figure 1H and Figure 1I , when the gate structure 308 is formed and etched in the process of Figure 3I and Figure 3J , residues of the gate structure 308 do not remain at the portions of the side surfaces of the bottom spacer 304 and the doped layer 303 where the shallow trench 305 is formed. This is because the recess delay structure 310 is inserted into the STI dielectric 307 to delay the etching of the STI dielectric 307 at the position of the shallow trench 305 in the process of Figure 3G , thereby forming an STI structure 307-1 having protrusions 311 to prevent the formation of such residues of the gate structure 308. Therefore, a short circuit between the residues of the gate structure 308 and the bottom S / D region formed at the side surface of the doped layer 303 does not occur as in the process of Figure 1I . Therefore, the method for manufacturing a VFET device structure according to the present embodiment can also prevent an increase in unnecessary capacitance (which reduces the AC performance of the VFET device formed by the intermediate VFET device structure 100) and a decrease in the productivity of the VFET device. In addition, compared with the method described with reference to Figures 2A to 2L , the method for manufacturing a VFET device structure according to the present embodiment can also prevent the loss of the bottom spacer 304.

[0062] It should also be noted that, consistent with the inventive concept, in addition to Figure 3F and Figure 3GUsing a process different from the etching process of the delay recess structure 310, as long as it can delay the etching of the STI dielectric 307 at a position above the shallow trench 305 to prevent residues of the gate structure 308 from remaining on the side surfaces of the bottom spacer 304 and the side surfaces of the doped layer 203 at the portions forming the shallow trench 305. In addition, although the delayed etching according to the present embodiment produces the STI structure 307-1 having the protrusion 311 above the height of the top surfaces of the doped layer 303 and the bottom spacer 304 to prevent residues of the gate structure 308 from being formed in the shallow trench 305, the inventive concept is not limited thereto. According to an embodiment, the delayed etching can be controlled such that the top surface of the STI structure 307-1 is formed not below the height of the top surface of the doped layer 303, as long as the delayed etching can prevent residues of the gate structure 308 from being formed in the shallow trench 305 as Figure 1G shown.

[0063] Figure 3K And Figure 3L shows that, after the fin structures 302-1 to 302-4 on which the gate structure 308 is deposited and etched in Figure 3I and Figure 3J are provided, the VFET device structure is flattened and / or etched again to remove at least the mask 302M from the fin structures 302-1 to 302-4, and the ILD layer 312, the top spacer 313, and the top S / D region 314 are further deposited or formed, and the contact liner 315 and the contact structure 316 are further formed on the top S / D region 314, thereby forming the desired VFET device. Here, the ILD layer 312 formed of a material including nitride, oxide, or a combination thereof but not limited thereto can be deposited between the fin structures 302-1 to 302-4. The top spacer 313 formed of a material similar to or different from the material of the bottom spacer 304 can be deposited on the gate structure 308 to electrically isolate the gate structure 308 from the top S / D region 314. The top S / D region 314 can also be formed by epitaxially growing a semiconductor layer on the fin structures 302-1 to 302-4 from which the mask 302M has been removed and doping impurities therein.

[0064] The foregoing is an illustration of exemplary embodiments and will not be construed as a limitation thereof. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the above embodiments without substantially departing from the inventive concept.

[0065] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 862,839, filed on Jun. 18, 2019, and U.S. Patent Application No. 16 / 846,813, filed on Apr. 13, 2020, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A method for manufacturing a vertical field effect transistor device, the method comprising: Providing an intermediate vertical field effect transistor structure, the intermediate vertical field effect transistor structure comprising a substrate, a plurality of fin structures formed on the substrate, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source / drain region, a bottom surface of the fin structures and a bottom surface of the doped layer being in the same plane; Forming a shallow trench through the doped layer and the substrate under a top surface of the substrate and between the fin structures to isolate the fin structures from each other; Filling the shallow trench and a space between the fin structures with an insulating material; Etching the insulating material filled between the fin structures above a height of a top surface of the doped layer except in the shallow trench, such that a shallow trench isolation structure having a top surface at or above the height of the top surface of the doped layer is formed in the shallow trench; Forming gate structures on the fin structures respectively; And Forming top source / drain regions on the fin structures, wherein the etching of the insulating material is performed such that the insulating material at a position above the shallow trench is etched later than the insulating material at a position between the shallow trench and the fin structures.

2. The method according to claim 1, wherein the shallow trench isolation structure has a protrusion protruding above the height of the top surface of the doped layer.

3. The method according to claim 1, further comprising inserting a recess delay structure into the insulating material at a position above the shallow trench before etching the insulating material.

4. The method according to claim 3, wherein the recess delay structure is inserted into the insulating material at a height same as a height of a top surface of the fin structures.

5. The method according to claim 3, wherein the insulating material and the material forming the recess delay structure have an etching selectivity with respect to each other.

6. The method according to claim 5, wherein the insulating material is formed of a dielectric oxide material.

7. The method according to claim 5, wherein the recess delay structure is formed of a material comprising silicon nitride.

8. The method according to claim 1, wherein the intermediate vertical field effect transistor structure further comprises bottom spacers formed on the doped layer between the fin structures, and wherein the shallow trench is formed through the bottom spacers, the doped layer and the substrate between the fin structures.

9. The method according to claim 8, wherein the shallow trench isolation structure is formed in the shallow trench such that the top surface of the shallow trench isolation structure is at or above a height of a top surface of the bottom spacers.

10. The method according to claim 1, further comprising forming bottom spacers on the doped layer between the fin structures and on the top surface of the shallow trench isolation structure after etching the insulating material.

11. The method according to claim 10, wherein a top surface of the bottom spacer on the top surface of the shallow trench isolation structure is higher than a top surface of the bottom spacer on the doped layer.

12. A method for manufacturing a vertical field effect transistor device, the method comprising: providing an intermediate vertical field effect transistor structure including a substrate, a plurality of fin structures formed on the substrate, and a doped layer formed on the substrate between the fin structures, the doped layer including bottom source / drain regions; forming shallow trenches under a top surface of the substrate and through the doped layer and the substrate between the fin structures to isolate the fin structures from each other; filling a space between the fin structures including the shallow trenches with an insulating material; etching the insulating material such that the insulating material filled between the fin structures and above the shallow trenches is etched later than the insulating material filled in positions between the shallow trenches and the fin structures to form a shallow trench isolation structure in the shallow trenches; forming gate structures on the fin structures respectively; and forming top source / drain regions on the fin structures.

13. The method according to claim 12, wherein the shallow trench isolation structure has a protrusion protruding above a height of the top surface of the doped layer.

14. A vertical field effect transistor device, comprising: a substrate; a doped layer formed on the substrate by doping impurities, the doped layer including bottom source / drain regions; a plurality of fin structures formed vertically on the substrate above the doped layer; top source / drain regions formed on the fin structures; a shallow trench isolation structure filling the shallow trenches, the shallow trenches being formed under the top surface of the substrate and through the doped layer and the substrate between the fin structures; and bottom spacers formed on the top surface of the shallow trench isolation structure and the doped layer, wherein a top surface of the shallow trench isolation structure is at or above a height of the top surface of the doped layer, wherein a bottom surface of the fin structures and a bottom surface of the doped layer are in the same plane.

15. The vertical field effect transistor device according to claim 14, wherein the shallow trench isolation structure has a protrusion protruding above the height of the top surface of the doped layer.

16. The vertical field effect transistor device according to claim 15, wherein the protrusion of the shallow trench isolation structure has a trapezoidal shape above the height of the top surface of the doped layer.

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