Semiconductor device and method for manufacturing the same

Abstract

The present disclosure is related to a semiconductor device and a method for manufacturing the same. In the present disclosure, the semiconductor device includes a packaging component, the packaging component including: a plurality of integrated circuit dies; an encapsulation body located around the plurality of integrated circuit dies; a redistribution structure located on the encapsulation body and the plurality of integrated circuit dies, the redistribution structure being electrically coupled to the plurality of integrated circuit dies; a plurality of sockets located on the redistribution structure, the plurality of sockets being electrically coupled to the redistribution structure; and a support ring located on the redistribution structure and surrounding the plurality of sockets, the support ring being disposed along the outermost edge of the redistribution structure, the support ring at least partially overlapping the redistribution structure in a lateral direction.

Description

Technical Field

[0001] The disclosed embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor technology continues to evolve, integrated circuit dies are becoming smaller and smaller. In addition, more and more functions are being integrated into the integrated circuit die. As a result, the number of input / output (I / O) pads required for the integrated circuit die increases, while the area available for the I / O pads decreases. The density of the I / O pads increases rapidly over time, increasing the difficulty of packaging the integrated circuit die.

[0003] In some packaging techniques, the integrated circuit die is singulated from the wafer before being packaged. An advantageous feature of such packaging techniques is that a fan-out type package can be formed, which enables the input / output pads on the die to be redistributed over a larger area. Thus, the number of input / output pads on the surface of the die can be increased. Summary of the invention

[0004] The disclosed embodiment provides a semiconductor device including a packaging component, wherein the packaging component includes: a plurality of integrated circuit dies; an encapsulation body located around the plurality of integrated circuit dies; a redistribution structure located above the encapsulation body and the plurality of integrated circuit dies, the redistribution structure being electrically coupled to the plurality of integrated circuit dies; a plurality of sockets located above the redistribution structure, the plurality of sockets being electrically coupled to the redistribution structure; and a support ring located above the redistribution structure and surrounding the plurality of sockets, the support ring being arranged along the outermost edge of the redistribution structure, the support ring at least partially overlapping with the redistribution structure in a laterally direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0007] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12and Fig.13 Various views illustrate intermediate steps during a process for forming a package assembly in accordance with some embodiments.

[0008] Fig.14 and Fig.15 Various views are shown of a process for securing a package assembly between a thermal module and a mechanical support in accordance with some embodiments.

[0009] Fig.16 A cross-sectional view illustrating module installation in a system wafer assembly according to some embodiments.

[0010] Fig.17 A cross-sectional view of a system wafer assembly according to some other embodiments is shown.

[0011] Fig.18 A cross-sectional view of a system wafer assembly according to some other embodiments is shown.

[0012] Fig.19 A cross-sectional view of a system wafer assembly according to some other embodiments is shown.

[0013] Fig. 20 A top view of a package assembly is shown in accordance with some embodiments.

[0014] [Explanation of Symbols]

[0015] 50: Integrated circuit die

[0016] 50A: System-on-Chip (SoC) die

[0017] 50B: Input / output (I / O) interface die

[0018] 52: Semiconductor substrate

[0019] 62, 144: Pad

[0020] 64: Passivation film

[0021] 66: Die connector

[0022] 68, 110, 114, 118, 122, 126, 130, 134: Dielectric layer

[0023] 100: Packaging components

[0024] 101, 101A, 101B: Computing sites

[0025] 102, 102A: Connection site

[0026] 103: Carrier substrate

[0027] 104: Adhesive layer

[0028] 106: Encapsulation

[0029] 108: Rewiring Structure

[0030] 108A: Fine feature part

[0031] 108B: Thick feature part

[0032] 112, 116, 120, 124, 128, 132: Metallized pattern

[0033] 136: Under Bump Metal (UBM)

[0034] 138: Strip

[0035] 139: Support ring

[0036] 140, 402: Conductive connectors

[0037] 142: Socket

[0038] 143: Connectors

[0039] 146: Bottom filler

[0040] 148, 204, 302: Bolt holes

[0041] 200: Thermal module

[0042] 202: Bolt

[0043] 206: Fasteners

[0044] 208: Thermal Interface Material (TIM)

[0045] 300: Mechanical support

[0046] 304: Opening

[0047] 400: Module

[0048] AA, BB: transverse line

[0049] D1: inner diameter

[0050] D2: outer diameter

[0051] D3: Overall diameter / diameter

[0052] T1: First thickness

[0053] T2: Second thickness

[0054] T3: The third thickness

[0055] T4: Fourth thickness

[0056] T5: Thickness

[0057] W1, W2, W3, W4: Width DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0059] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0060] According to some embodiments, a system wafer assembly is formed by clamping a package structure between a thermal module and a mechanical support. A support ring is fitted around the perimeter of the package structure before the package structure is removed from the carrier substrate. The support ring provides mechanical support for the package structure, thereby reducing warpage of the system wafer assembly after the carrier substrate is removed. Reducing the warpage of the system wafer assembly helps to increase the uniformity of the pressure applied to the thermal module. Therefore, the thermal dissipation of the assembly can be improved.

[0061] Figure 1A cross-sectional view of an integrated circuit die 50 is shown in accordance with some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), an application-specific die (e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA)), etc.), the like, or a combination thereof.

[0062] The integrated circuit die 50 may be formed in a wafer that may include different device areas that are singulated in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 may be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as a multi-layered substrate or a gradient substrate. The semiconductor substrate 52 has an active surface sometimes referred to as a front side (e.g., Figure 1 The upward-facing surface in the image) and the inactive surface sometimes called the back side (e.g. Figure 1 A plurality of devices may be formed at the surface of the front side of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure is located on the semiconductor substrate 52, and the devices are interconnected to form an integrated circuit. The interconnect structure may be formed by, for example, forming a plurality of metallization patterns located in a plurality of dielectric layers on the semiconductor substrate 52. The plurality of metallization patterns include a plurality of metal lines and a plurality of through holes formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure is electrically coupled to the device of the semiconductor substrate 52.

[0063] The integrated circuit die 50 also includes a plurality of pads 62 (e.g., aluminum pads) for external connections. The pads 62 are located on an active surface of the integrated circuit die 50, such as in and / or on an interconnect structure. The integrated circuit die 50 has one or more passivation films 64 on it (e.g., on portions of the interconnect structure and pads 62). A plurality of openings extend through the passivation film 64 to the pads 62. A plurality of die connectors 66 (e.g., conductive pillars (e.g., formed of a metal such as copper)) extend through the openings in the passivation film 64 and are physically and electrically coupled to corresponding pads 62 in the pads 62. The die connectors 66 can be formed, for example, by plating. The die connectors 66 electrically couple corresponding integrated circuits of the integrated circuit die 50.

[0064] Optionally, a plurality of solder areas (e.g., solder balls or solder bumps) may be provided on the pads 62. The solder balls may be used to perform a chip probe (CP) test on the integrated circuit die 50. The CP test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 that is a known good die and undergoes subsequent processing will be packaged, and the die that fails the CP test will not be packaged. After the test, the solder area may be removed in a subsequent processing step.

[0065] The dielectric layer 68 may or may not be located on the active surface of the integrated circuit die 50, such as on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally encapsulates the die connector 66, and the dielectric layer 68 laterally contacts the integrated circuit die 50. Initially, the dielectric layer 68 may bury the die connector 66 so that the topmost surface of the dielectric layer 68 is located above the topmost surface of the die connector 66. In some embodiments where a solder area is disposed on the die connector 66, the dielectric layer 68 may also bury the solder area. Alternatively, the solder area may be removed before forming the dielectric layer 68.

[0066] The dielectric layer 68 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; a similar material; or a combination thereof. The dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the die connector 66 is exposed through the dielectric layer 68 during the formation of the integrated circuit die 50. In some embodiments, the die connector 66 remains buried and is exposed during a subsequent process for packaging the integrated circuit die 50. Any solder area that may be present on the die connector 66 may be removed when the die connector 66 is exposed.

[0067] In some embodiments, the integrated circuit die 50 is a stacked device including a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device, such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, or a similar device including a plurality of memory dies. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates 52 may have (or may not have) an interconnect structure.

[0068] Figures 2 to 13 Various views are shown of intermediate steps during a process for forming package assembly 100 in accordance with some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 9 , Fig.10 , Fig.11 and Fig.13 is a cross-sectional view, and Figure 8 and Fig.12is a top view. The package component 100 is a reconstructed wafer having multiple packaging areas, wherein one or more of the multiple integrated circuit dies 50 are packaged in each of the packaging areas. The packaging area includes multiple computing sites 101 and multiple connection sites 102. Each of the computing sites 101 may have, for example, logic functions, memory functions, etc., and the package component 100 may be a single computing device including the computing site 101 and the connection site 102, such as a system-on-wafer (SoW) device. For example, the package component 100 may be an artificial intelligence (AI) accelerator, and each computing site 101 may be a neural network node of the AI ​​accelerator. Each of the connection sites 102 may have, for example, multiple external connectors, and the computing site 101 of the package component 100 may be connected to multiple external systems through the connection site 102. Exemplary systems of the package assembly 100 include AI servers, high-performance computing (HPC) systems, high-power computing devices, cloud computing systems, edge computing systems, etc. The figure shows two computing sites 101 (e.g., computing site 101A and computing site 101B) and one connection site 102 (e.g., connection site 102A), but it should be understood that the package assembly 100 may include many computing sites 101 and many connection sites 102, and the computing and connection sites may be arranged in various ways. Figure 8 and Fig.12 An exemplary layout of package assembly 100 is shown and discussed. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 9 , Fig.10 , Fig.11 and Fig.13 Only a portion of the package assembly 100 is shown, for example Figure 8 and Fig.12 The part represented by the cross-section line AA in .

[0069] exist Figure 2In the embodiment of the present invention, a carrier substrate 103 is provided, and an adhesive layer 104 is formed on the carrier substrate 103. The carrier substrate 103 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 103 may be a wafer so that a plurality of packages can be formed simultaneously on the carrier substrate 103. The adhesive layer 104 may be removed from the overlying structure to be formed in a subsequent step together with the carrier substrate 103. In some embodiments, the adhesive layer 104 is any suitable adhesive, epoxy resin, die attach film (DAF), etc., and the adhesive layer 104 is applied on the surface of the carrier substrate 103. In some embodiments, the adhesive layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the adhesive layer 104 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to ultraviolet (UV) light.

[0070] A plurality of integrated circuit dies 50 are then bonded to the adhesive layer 104. A desired type and number of integrated circuit dies 50 are bonded in each of the computing sites 101A and 101B and the connection site 102A. In some embodiments, a first type of integrated circuit die, such as a SoC die 50A, is bonded in each computing site 101A and 101B, and a second type of integrated circuit die, such as an input / output interface (I / O interface) die 50B, is bonded in the connection site 102A. Although a single integrated circuit die 50 is shown in each site, it should be understood that multiple integrated circuit dies may be bonded adjacent to each other in some or all sites. When multiple integrated circuit dies are bonded in each computing site 101A and 101B, the multiple integrated circuit dies may have the same technology node or different technology nodes. For example, the integrated circuit die 50 may include a die formed at a 10nm technology node, a die formed at a 7nm technology node, similar dies, or a combination thereof.

[0071] exist Figure 3In the embodiment of the present invention, an encapsulant 106 is formed on and around various components. After being formed, the encapsulant 106 encapsulates the integrated circuit die 50. The encapsulant 106 may be a molding compound, an epoxy resin, etc., and may be applied by compression molding, transfer molding, etc. The encapsulant 106 may be applied in a liquid or semi-liquid form and then cured. In some embodiments, the encapsulant 106 is formed on the carrier substrate 103 so that the integrated circuit die 50 is buried or covered, and then a planarization process is performed on the encapsulant 106 to expose the die connector 66 of the integrated circuit die 50. After the planarization process, the topmost surface of the encapsulant 106, the topmost surface of the die connector 66, and the topmost surface of the dielectric layer 68 are coplanar. The planarization process may be, for example, chemical-mechanical polishing (CMP).

[0072] exist Figures 4 to 6 In the embodiment, a redistribution structure 108 having a fine-featured portion 108A and a coarse-featured portion 108B is formed on the encapsulation body 106 and the integrated circuit die 50 (see Figure 6 ). The rewiring structure 108 includes multiple metallization patterns, multiple dielectric layers and multiple under-bump metallurgy (UBM). The metallization pattern may also be referred to as a rewiring layer or a rewiring. The rewiring structure 108 is shown as an example having six layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the rewiring structure 108. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated. The fine feature portion 108A and the thick feature portion 108B of the rewiring structure 108 include metallization patterns and dielectric layers of different sizes.

[0073] exist Figure 4, a fine feature portion 108A of the redistribution structure 108 is formed. The fine feature portion 108A of the redistribution structure 108 includes: dielectric layers 110, 114, 118, and 122; and metallization patterns 112, 116, and 120. In some embodiments, the dielectric layers 114, 118, and 122 are formed of the same dielectric material and are formed to the same thickness. Similarly, in some embodiments, the plurality of conductive features of the metallization patterns 112, 116, and 120 are formed of the same conductive material and are formed to the same thickness. Specifically, the dielectric layers 114, 118, and 122 have a small first thickness T1, such as a first thickness T1 in the range of about 3 μm to about 15 μm, and the conductive features of the metallization patterns 112, 116, and 120 have a small second thickness T2, such as a second thickness T2 in the range of about 0.5 μm to about 6 μm.

[0074] As an example of forming a fine feature portion 108A of the rewiring structure 108, a dielectric layer 110 is deposited on the encapsulation 106, the dielectric layer 68, and the die connector 66. In some embodiments, the dielectric layer 110 is formed of a photosensitive material (e.g., PBO, polyimide, BCB, etc.) that can be patterned using a photolithographic mask. The dielectric layer 110 can be formed by spin coating, lamination, CVD, a similar process, or a combination thereof. The dielectric layer 110 is then patterned. The patterning forms a plurality of openings that expose portions of the die connector 66. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 110 to light when the dielectric layer 110 is a photosensitive material or by etching using, for example, anisotropic etching. If the dielectric layer 110 is a photosensitive material, the dielectric layer 110 can be developed after exposure.

[0075] Then, a metallization pattern 112 is formed. The metallization pattern 112 has a plurality of conductor portions (also referred to as conductive lines or traces) and a plurality of through-hole portions (also referred to as vias), the conductor portions being located on and extending along the main surface of the dielectric layer 110, and the through-hole portions extending through the dielectric layer 110 to physically and electrically couple the die connectors 66 of the integrated circuit die 50. As an example of forming the metallization pattern 112, a seed layer is formed on the dielectric layer 110 and in a plurality of openings extending through the dielectric layer 110. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located on the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). Then, a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 112. The patterning forms a plurality of openings through the photoresist to expose the seed layer. Then a conductive material is formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating) or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the seed layer of the underlying portion forms the metallization pattern 112. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing process or a stripping process such as using oxygen plasma. Once the photoresist is removed, an acceptable etching process (e.g., by wet etching or dry etching) is used to remove the exposed portion of the seed layer.

[0076] A dielectric layer 114 is then deposited on the metallization pattern 112 and the dielectric layer 110. The dielectric layer 114 may be formed in a manner similar to the dielectric layer 110 and from a material similar to the dielectric layer 110. A metallization pattern 116 is then formed. The metallization pattern 116 has a plurality of conductive line portions and a plurality of via portions, wherein the conductive line portions are located on and extend along the main surface of the dielectric layer 114, and the via portions extend through the dielectric layer 114 to physically and electrically couple the metallization pattern 112. The metallization pattern 116 may be formed in a manner similar to the metallization pattern 112 and from a material similar to the metallization pattern 112.

[0077] A dielectric layer 118 is then deposited on the metallization pattern 116 and the dielectric layer 114. The dielectric layer 118 may be formed in a manner similar to the dielectric layer 110 and from a material similar to the dielectric layer 110. A metallization pattern 120 is then formed. The metallization pattern 120 has a plurality of conductive line portions and a plurality of via portions, wherein the conductive line portions are located on and extend along the main surface of the dielectric layer 118, and the via portions extend through the dielectric layer 118 to physically and electrically couple the metallization pattern 116. The metallization pattern 120 may be formed in a manner similar to the metallization pattern 112 and from a material similar to the metallization pattern 112.

[0078] A dielectric layer 122 is deposited over the metallization pattern 120 and the dielectric layer 118. The dielectric layer 122 may be formed in a similar manner and from similar materials as the dielectric layer 110.

[0079] exist Figure 5 , a thick feature portion 108B of the redistribution structure 108 is formed. The thick feature portion 108B of the redistribution structure 108 includes: dielectric layers 126, 130 and 134; and metallization patterns 124, 128 and 132. In some embodiments, the dielectric layers 126, 130 and 134 are formed of the same dielectric material and are formed to the same thickness. Similarly, in some embodiments, the plurality of conductive features of the metallization patterns 124, 128 and 132 are formed of the same conductive material and are formed to the same thickness. Specifically, the dielectric layers 126, 130 and 134 have a large third thickness T3, such as a third thickness T3 in the range of about 10 μm to about 80 μm, and the conductive features of the metallization patterns 124, 128 and 132 have a large fourth thickness T4, such as a fourth thickness T4 in the range of about 3 μm to about 50 μm. The third thickness T3 is greater than the first thickness T1 (see Figure 4 ), and the fourth thickness T4 is greater than the second thickness T2 (see Figure 4 ).

[0080] As an example of forming the thick feature portion 108B of the rewiring structure 108, a metallization pattern 124 is formed. The metallization pattern 124 has a plurality of wire portions and a plurality of through-hole portions, the wire portions being located on the main surface of the dielectric layer 122 and extending along the main surface of the dielectric layer 122, and the through-hole portions extending through the dielectric layer 122 to physically couple and electrically couple the metallization pattern 120. As an example of forming the metallization pattern 124, a seed layer is formed on the dielectric layer 122 and in a plurality of openings extending through the dielectric layer 122. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located on the titanium layer. The seed layer may be formed using, for example, PVD. Then, a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist may be formed by spin coating, etc. and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 124. The patterning forms a plurality of openings through the photoresist to expose the seed layer. Then a conductive material is formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating) or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the seed layer of the underlying portion can form a metallization pattern 124. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by, for example, an acceptable ashing process or a stripping process using oxygen plasma or the like. Once the photoresist is removed, an acceptable etching process (e.g., by wet etching or dry etching) is used, for example, to remove the exposed portion of the seed layer.

[0081] A dielectric layer 126 is then deposited on the metallization pattern 124 and the dielectric layer 122. In some embodiments, the dielectric layer 126 is formed of a photosensitive material (e.g., PBO, polyimide, BCB, etc.) that can be patterned using a photolithography mask. The dielectric layer 126 can be formed by spin coating, lamination, CVD, a similar process, or a combination thereof. A metallization pattern 128 is then formed. The metallization pattern 128 has a plurality of conductive line portions and a plurality of via portions, the conductive line portions being located on and extending along the main surface of the dielectric layer 126, and the via portions extending through the dielectric layer 126 to physically and electrically couple the metallization pattern 124. The metallization pattern 128 can be formed in a manner similar to the metallization pattern 124 and by a material similar to the metallization pattern 124.

[0082] A dielectric layer 130 is then deposited on the metallization pattern 128 and the dielectric layer 126. The dielectric layer 130 may be formed in a similar manner and from a similar material as the dielectric layer 126. A metallization pattern 132 is then formed. The metallization pattern 132 has a plurality of conductive line portions and a plurality of via portions, wherein the conductive line portions are located on and extend along the main surface of the dielectric layer 130, and the via portions extend through the dielectric layer 130 to physically and electrically couple the metallization pattern 128. The metallization pattern 132 may be formed in a similar manner and from a similar material as the metallization pattern 124.

[0083] A dielectric layer 134 is deposited over the metallization pattern 132 and the dielectric layer 130. The dielectric layer 134 may be formed in a similar manner and from similar materials as the dielectric layer 126.

[0084] exist Figure 6 In the embodiment of the present invention, a plurality of under bump metal (UBM) 136 are formed to externally connect the rewiring structure 108. The under bump metal 136 has a plurality of bump portions and a plurality of via portions, wherein the bump portions are located on and extend along the main surface of the dielectric layer 134, and the via portions extend through the dielectric layer 134 to physically and electrically couple the metallization pattern 132. Therefore, the under bump metal 136 is electrically coupled to the integrated circuit die 50. The under bump metal 136 can be formed in a similar manner and from a similar material as the metallization pattern 132. In some embodiments, the under bump metal 136 has a different size from the metallization patterns 112, 116, 120, 124, 128, and 132.

[0085] exist Figure 7 In the embodiment, the support ring 139 is attached to the redistribution structure 108 . Figure 8 is a top view of the package assembly 100 after the support ring 139 is attached, and Figure 7 right Figure 8 108. The support ring 139 extends around the perimeter of the package component 100, for example, along the outermost edge of the redistribution structure 108. As discussed further below, the package component 100 can have several possible shapes in a top view. The support ring 139 has the same top view shape as the package component 100. In this embodiment, the package component 100 and the support ring 139 have an untruncated circular shape. It should be understood that the package component 100 and the support ring 139 can have other shapes, such as a regular polygonal shape or an irregular polygonal shape.

[0086] The support ring 139 is secured to the rewiring structure 108 by an adhesive and optionally by mechanical fasteners. The support ring 139 is bonded to the rewiring structure 108 using an adhesive, such as any suitable glue, epoxy, etc. The adhesive may be dispensed on the support ring 139 or the rewiring structure 108 before the support ring 139 is placed on the perimeter of the rewiring structure 108, and the adhesive may be cured before further processing. In some embodiments, the support ring 139 is also mechanically fastened to the rewiring structure 108 using, for example, bolts and fasteners (discussed further below).

[0087] The support ring 139 is formed of a material having high rigidity, such as a metal (e.g., steel, titanium, cobalt, etc.). The support ring 139 has a greater rigidity than other components of the package assembly 100. In other words, the Young's modulus of the support ring 139 may be greater than the Young's modulus of the redistribution structure 108, the encapsulation body 106, and the integrated circuit die 50. For example, the Young's modulus of the support ring 139 may be in a range of about 10 GPa to about 1000 GPa. In contrast, the Young's modulus of the redistribution structure 108 may be in a range of about 1 GPa to about 12 GPa, the Young's modulus of the encapsulation body 106 may be in a range of about 10 GPa to about 30 GPa, and the Young's modulus of the integrated circuit die 50 may be in a range of about 100 GPa to about 200 GPa. Since the support ring 139 has high rigidity, the support ring 139 provides mechanical support for the package assembly 100 during a subsequent carrier substrate debonding process (discussed further below).

[0088] The support ring 139 has an inner width and an outer width. In the illustrated embodiment, the support ring 139 is an annular shape having an inner diameter D1 and an outer diameter D2. For example, the inner diameter D1 may be in the range of about 280 mm to about 299.5 mm, and the outer diameter D2 may be in the range of about 300.5 mm to about 320.5 mm. The support ring 139 has a thickness T5 and a width W1, wherein the thickness T5 may be in the range of about 0.5 mm to about 20 mm, and the width W1 may be in the range of about 0.5 mm to about 20 mm. The thickness T5 and the width W1 of the support ring 139 together determine the amount of mechanical support provided by the support ring 139 to the package component 100, wherein a larger width W1 and / or thickness T5 provides greater mechanical support. However, a large width W1 also causes the support ring 139 to occupy more lateral area, thereby reducing the amount of space available for the under-bump metal 136. A moderate width W1 (e.g., a width W1 in the range of about 5 mm to about 7 mm) can provide sufficient mechanical support for the package component 100 without excessively reducing the amount of space available for the under bump metallurgy 136. Similarly, a large thickness T5 causes the support ring 139 to occupy more vertical area, thereby increasing the height of the package component 100. A moderate thickness T5 (e.g., a thickness T5 of about 2 mm) can provide sufficient mechanical support for the package component 100 without excessively increasing the bulk of the package component 100.

[0089] In the illustrated embodiment, the support ring 139 at least partially overlaps the rewiring structure 108 in the lateral direction and extends beyond the edge of the rewiring structure 108. In other words, the outermost edge of the support ring 139 can extend beyond the outermost edge of the rewiring structure 108. For example, the rewiring structure 108 has an overall diameter D3 (or more generally, an overall width), which can be in the range of about 250 mm to about 300 mm. The diameter D3 can be smaller than the outer diameter D2 but larger than the inner diameter D1. The portion of the support ring 139 that overlaps the rewiring structure 108 has a width W2, and the portion of the support ring 139 that extends beyond the edge of the rewiring structure 108 has a width W3. For example, the width W2 can be in the range of about 0.5 mm to about 10 mm, and the width W3 can be in the range of about 0.5 mm to about 10 mm. The width W3 is smaller than the width W2. In some embodiments, the width W3 is less than about half of the width W2. For example, the ratio of width W3 to width W2 may be in a range of about 1:10 to about 9:10, such as less than about 1:2. In another embodiment (shown below), support ring 139 is laterally confined within the edge of redistribution structure 108 .

[0090] exist Fig. 9In the embodiment of the present invention, carrier substrate peeling is performed to separate (or "peel off") the carrier substrate 103 from the encapsulation body 106 and the integrated circuit die 50. In some embodiments, the peeling includes removing the carrier substrate 103 and the adhesive layer 104 by, for example, a grinding process or a planarization process (e.g., CMP). In some embodiments, the peeling includes projecting light (e.g., laser light or UV light) to the adhesive layer 104 so that the adhesive layer 104 decomposes under the heat of the light and the carrier substrate 103 can be removed. After removal, the backside surface of the integrated circuit die 50 is exposed, and the backside surface of the encapsulation body 106 is flush with the backside surface of the integrated circuit die 50. The structure is then placed on a tape 138. Peeling the carrier substrate 103 from the package assembly 100 may cause the wafer to warp. The mechanical support provided by the support ring 139 allows the support ring 139 to apply a force to the package assembly 100 in a direction opposite to the direction of the wafer warping. As such, the support ring 139 helps reduce the amount of wafer warpage caused by carrier substrate peeling. In experiments, the support ring 139 helped reduce wafer warpage by up to 30%.

[0091] exist Fig.10 In the embodiment of the present invention, a plurality of conductive connectors 140 are formed on the under bump metal 136. The conductive connectors 140 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connectors 140 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar materials, or combinations thereof. In some embodiments, the conductive connectors 140 are formed by forming a solder or solder paste layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. at the beginning. Once the solder layer has been formed on the structure, reflow may be performed to shape the material into the desired bump shape.

[0092] exist Fig.11In the embodiment of the present invention, a plurality of sockets 142 and a plurality of connectors 143 are attached to the rewiring structure 108. The sockets 142 and connectors 143 are interfaces for externally connecting the package component 100. The sockets 142 and connectors 143 include a plurality of pads 144 (e.g., aluminum pads) for external connection. The sockets 142 and connectors 143 are mounted to the under bump metal 136 using a conductive connector 140. After forming a support ring 139, the sockets 142 and connectors 143 are attached to the rewiring structure 108, and the sockets 142 and connectors 143 are arranged inside the support ring 139 so that the support ring 139 surrounds the sockets 142 and connectors 143. Since the support ring 139 helps to reduce the warping of the rewiring structure 108, the heights of the sockets 142 and connectors 143 can be more uniform. Therefore, the quality of the plurality of joints formed between the under bump metal 136 and the sockets 142 and connectors 143 can be improved. In the illustrated embodiment, the socket 142 is attached at the computing sites 101A and 101B, and the connector 143 is attached at the connection site 102A. An underfill 146 is formed to fill the gap between the socket 142 and the connector 143 and the redistribution structure 108. The underfill 146 may be formed by a capillary flow process after the socket 142 and the connector 143 are attached, or may be formed by a suitable deposition method before the socket 142 and the connector 143 are attached.

[0093] Socket 142 is an electrical and physical interface for a plurality of modules (discussed further below) that may be installed at computing sites 101A and 101B after manufacturing package assembly 100. For example, a user of package assembly 100 may install modules in socket 142 to form a complete functional system at computing sites 101A and 101B. The type of module selected for installation depends on the type of functional system desired at computing sites 101A and 101B. Examples of modules that may be installed in socket 142 include memory modules, voltage regulator modules, power supply modules, integrated passive device (IPD) modules, and the like. Socket 142 may include different components that may include different materials, such as a chassis and a plurality of contact pins. Although socket 142 is formed of a plurality of different materials, socket 142 generally has an average stiffness that may be quantified by the Young's modulus of socket 142. The socket 142 has a high average stiffness, for example, having a Young's modulus that may range from about 10 GPa to about 30 GPa. As discussed further below, subsequently formed overlying features have a lower average stiffness than the socket 142 .

[0094] The connector 143 is the electrical and physical interface of the package assembly 100 to multiple external systems. For example, when the package assembly 100 is installed as a component of a larger external system (such as a data center), the connector 143 can be used to couple the package assembly 100 to the external system. Examples of the connector 143 include multiple receptors of a ribbon cable, a flexible printed circuit, etc.

[0095] The socket 142 and the connector 143 may be attached to the redistribution structure 108 in various layouts. Fig.11 The layout shown in is an example. Fig.12 1 is a top view of the package assembly 100. Each socket 142 directly overlies the SoC die 50A of the corresponding computing site 101A or 101B and is electrically coupled to the SoC die 50A. Connectors 143 are arranged around the periphery of the package assembly 100, thereby increasing the area available for the sockets 142. The connection site 102A may include one or more connectors 143. In the embodiment shown, the connectors 143 are offset laterally relative to the input / output interface die 50B. In another embodiment, the connectors 143 directly overlie the input / output interface die 50B.

[0096] exist Fig.13 In the embodiment of the present invention, a plurality of bolt holes 148 are formed through the package assembly 100. The bolt holes 148 may be formed by a drilling process (e.g., laser drilling, mechanical drilling, etc.). The bolt holes 148 may be formed by drilling the outline of the bolt holes 148 using a drilling process and then removing the material separated by the outline. In some embodiments, some of the bolt holes 148 are formed through the support ring 139. Specifically, the bolt holes 148 around the perimeter of the package assembly 100 may be formed through the support ring 139.

[0097] Fig.14 and Fig.15Various views of a process for securing a package assembly 100 between a thermal module 200 and a mechanical support 300 are shown according to some embodiments. The thermal module 200 may be a heat sink, a heat spreader, a cold plate, etc. The mechanical support 300 is a rigid support that may be formed of a material having high rigidity, such as a metal (e.g., steel, titanium, cobalt, etc.). The mechanical support 300 physically engages portions of the socket 142 to secure the socket 142 when the module is installed or removed. By clamping the package assembly 100 between the thermal module 200 and the mechanical support 300, warping of the package assembly 100 (e.g., warping caused by carrier substrate peeling) may be reduced. Fig.14 is a three-dimensional view showing one quarter of the package assembly 100, thermal module 200, and mechanical support 300 during assembly according to some embodiments. Fig.14 Some details are omitted. Fig.15 is a cross-sectional view showing some parts of the package assembly 100, the thermal module 200 and the mechanical support 300 after assembly, and combined with Fig.14 right Fig.15 To elaborate. Fig.15 is along Fig.14 The reference cross-section line BB in is shown.

[0098] The package assembly 100 is removed from the strip 138 and fastened between the thermal module 200 and the mechanical support 300 using a plurality of bolts 202. The bolts 202 are threaded through the bolt holes 148 of the package assembly 100, through the corresponding plurality of bolt holes 204 in the thermal module 200, and through the corresponding plurality of bolt holes 302 in the mechanical support 300. Fasteners 206 are screwed onto the bolts 202 and tightened to clamp the package assembly 100 between the thermal module 200 and the mechanical support 300. The fasteners 206 can be, for example, nuts that are screwed onto the bolts 202. The fasteners 206 are attached to the bolts 202 at both sides of the resulting system wafer assembly, for example, at the side with the thermal module 200 (sometimes referred to as the back side) and at the side with the mechanical support 300 (sometimes referred to as the front side). In some embodiments, the bolts 202 and fasteners 206 also mechanically fasten the support ring 139 to the redistribution structure 108. After the mechanical supporter 300 is fixed, the mechanical supporter 300 is disposed laterally inside the support ring 139 so that the support ring 139 surrounds the mechanical supporter 300 in the laterally direction.

[0099] Before fastening the various components together, a thermal interface material (TIM) 208 is dispensed on the back side of the package assembly 100 (see Fig.15) to physically and thermally couple the thermal module 200 to the integrated circuit die 50. During fastening, the fastener 206 is tightened, thereby increasing the mechanical force applied to the package assembly 100 by the thermal module 200 and the mechanical support 300. The fastener 206 is tightened until the thermal module 200 applies a desired amount of pressure to the thermal interface material 208. For example, the tightening of the fastener 206 can be performed using a torque ranging from about 0.01 N·m to about 3.5 N·m.

[0100] As described above, the support ring 139 helps reduce warpage of the package assembly 100 (e.g., warpage caused by carrier substrate peeling), and also helps increase the uniformity of the height of the socket 142 and the connector 143. In this way, when the mechanical force is applied using the fastener 206, the uniformity of the pressure distribution across the thermal interface material 208 at the computing sites 101A and 101B can be improved. The thermal resistance of the thermal interface material 208 depends on the pressure applied to the thermal interface material 208, wherein a greater pressure results in a lower thermal resistance. However, if the pressure applied exceeds a sufficient amount, the thermal resistance of the thermal interface material 208 may not be further reduced. By tightening the fastener 206 beyond a point where no further reduction in thermal resistance can be achieved, and by increasing the uniformity of the pressure distribution across the thermal interface material 208, the thermal resistance of substantially all areas of the thermal interface material 208 can be minimized within the limits of the material of the thermal interface material 208.

[0101] To facilitate the installation of the module, the mechanical bracket 300 has a plurality of openings 304 that expose portions of the socket 142. Multiple edge regions of the mechanical bracket 300 (e.g., multiple edge regions of the outermost perimeter and multiple edge regions of the openings 304) are physically engaged and overlapped with multiple edge regions of the socket 142. In some embodiments, the mechanical bracket 300 only engages some edge regions of the socket 142.

[0102] Fig.16 A cross-sectional view of the resulting system wafer assembly is shown after a plurality of modules 400 are installed in the sockets 142 . Fig.16 is along Fig.14 101A and 101B. As described above, module 400 may be a memory module, a voltage regulator module, a power supply module, an integrated passive device (IPD) module, etc. Module 400 includes a plurality of conductive connectors 402 that are inserted into corresponding receiving members to physically and electrically couple contact pins of socket 142. Module 400 is thus secured in socket 142 to form a complete functional system at computing sites 101A and 101B. After installation, module 400 is disposed in opening 304 of mechanical bracket 300.

[0103] Fig.17 A cross-sectional view of a system wafer assembly according to some other embodiments is shown. Fig.17 is along Fig.14 In this embodiment, the support ring 139 is confined within the edge of the redistribution structure 108 in the lateral direction. In other words, the support ring 139 completely overlaps the redistribution structure 108 in the lateral direction and does not extend beyond the edge of the redistribution structure 108 in the lateral direction.

[0104] Fig.18 A cross-sectional view of a system wafer assembly according to some other embodiments is shown. Fig.18 is along Fig.14 BB in FIG. 1 . In this embodiment, the support ring 139 does not have a constant width W1, but rather has a varying width W1. The width W1 continuously decreases in a direction extending away from the main surface of the redistribution structure 108 (e.g., in a direction extending from the package assembly 100 to the mechanical support 300). The width W1 can decrease in a linear manner (as shown) or in a nonlinear manner (not shown).

[0105] Fig.19 A cross-sectional view of a system wafer assembly according to some other embodiments is shown. Fig.19 is along Fig.14 BB in FIG. 1 is used to illustrate the width W1 of the support ring 139. In this embodiment, the support ring 139 does not have a constant width W1, but has a variable width W1. The width W1 decreases in a step manner in a direction extending away from the main surface of the redistribution structure 108 (for example, in a direction extending from the package component 100 to the mechanical support 300). Each step in the reduction process has a width W4, and the width W4 can be in the range of about 0.1 mm to about 1 mm.

[0106] Fig. 20 A top view of a package assembly 100 according to some other embodiments is shown. As described above, the package assembly 100 and the support ring 139 can have several possible shapes in the top view. In this embodiment, the package assembly 100 and the support ring 139 have a truncated circular shape. Using a truncated circular shape can help reduce the overall space occupied by the resulting system wafer assembly, thereby increasing the amount of system wafer assembly that can be included in the internal system.

[0107] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein can be used in combination with a test method that includes intermediate verification of known good dies to improve yield and reduce costs.

[0108] Embodiments may achieve various advantages. Attaching support ring 139 to package assembly 100 may reduce warping of package assembly 100. Thus, the height of socket 142 and connector 143 may be more uniform, thereby improving the quality of the joint formed between under bump metal 136 and socket 142 and connector 143. In addition, when package assembly 100 is clamped between thermal module 200 and mechanical support 300, the uniformity of pressure distribution across thermal interface material 208 at computing stations 101A and 101B may be improved. Thus, heat dissipation of the assembly may be improved. Finally, support ring 139 provides some protection for the edges of package assembly 100, thereby reducing the risk of damaging the package assembly when the package assembly is manipulated.

[0109] In an embodiment, a semiconductor device includes a packaging component, the packaging component including: a plurality of integrated circuit dies; an encapsulation body located around the plurality of integrated circuit dies; a redistribution structure located above the encapsulation body and the plurality of integrated circuit dies, the redistribution structure being electrically coupled to the plurality of integrated circuit dies; a plurality of sockets located above the redistribution structure, the plurality of sockets being electrically coupled to the redistribution structure; and a support ring located above the redistribution structure and surrounding the plurality of sockets, the support ring being arranged along the outermost edge of the redistribution structure, the support ring at least partially overlapping with the redistribution structure in a laterally direction.

[0110] In some embodiments of the device, the support ring has a first portion and a second portion, the first portion overlapping the rewiring structure in a lateral direction, and the second portion extending beyond the outermost edge of the rewiring structure. In some embodiments of the device, the support ring is confined to the outermost edge of the rewiring structure in a lateral direction. In some embodiments of the device, the support ring has a constant width. In some embodiments of the device, the support ring has a width that decreases in a direction extending away from a major surface of the rewiring structure. In some embodiments of the device, the width of the support ring decreases in a linear manner. In some embodiments of the device, the width of the support ring decreases in a step manner. In some embodiments of the device, the support ring has an untruncated circular shape. In some embodiments of the device, the support ring has a truncated circular shape. In some embodiments, the device further includes: a mechanical support physically coupled to the plurality of sockets, the support ring laterally surrounding the mechanical support. In some embodiments, the device also includes: a thermal module, physically and thermally coupled to the enclosure and the plurality of integrated circuit dies; a plurality of first bolts, extending through the mechanical support, the redistribution structure, the enclosure and the thermal module; and a plurality of second bolts, extending through the support ring, the redistribution structure, the enclosure and the thermal module.

[0111] In an embodiment, a method for manufacturing a semiconductor device includes: placing a plurality of integrated circuit dies on a carrier substrate; encapsulating the plurality of integrated circuit dies with an encapsulation body; forming a rewiring structure over the encapsulation body and the plurality of integrated circuit dies, the rewiring structure having a first diameter; bonding a support ring to the rewiring structure, the support ring having an inner diameter and an outer diameter, the inner diameter being smaller than the first diameter and the outer diameter being larger than the inner diameter; after attaching the support ring to the rewiring structure, peeling the carrier substrate from the plurality of integrated circuit dies and the encapsulation body; and attaching a plurality of sockets to the rewiring structure, the plurality of sockets being surrounded by the support ring.

[0112] In some embodiments, the method further comprises: drilling a plurality of first bolt holes through the support ring, the rewiring structure, and the enclosure; and screwing the support ring to the rewiring structure using a plurality of first bolts extending through the plurality of first bolt holes. In some embodiments, the method further comprises: drilling a plurality of second bolt holes extending through the rewiring structure and the enclosure; screwing the mechanical bracket to the plurality of sockets using a plurality of second bolts extending through the plurality of second bolt holes. In some embodiments, the method further comprises: screwing a thermal module to the plurality of integrated circuit dies and the enclosure using the plurality of second bolts. In some embodiments of the method, the outer diameter is greater than the first diameter. In some embodiments of the method, the outer diameter is equal to the first diameter.

[0113] In an embodiment, a method for manufacturing a semiconductor device includes: assembling the package assembly between the thermal module and the mechanical support using a plurality of bolts extending through the thermal module, the package assembly and the mechanical support, wherein the package assembly includes: a plurality of integrated circuit dies; an encapsulation body located around the plurality of integrated circuit dies; a redistribution structure located above the encapsulation body and the plurality of integrated circuit dies, the redistribution structure being electrically coupled to the plurality of integrated circuit dies; a plurality of sockets located above the redistribution structure, the plurality of sockets being electrically coupled to the redistribution structure; a plurality of external connectors located above the redistribution structure, the plurality of external connectors being electrically coupled to the redistribution structure; and a support ring located above the redistribution structure and surrounding the plurality of sockets and the plurality of external connectors, the support ring being arranged along the outermost edge of the redistribution structure, the support ring at least partially overlapping the redistribution structure in a lateral direction; and tightening a plurality of fasteners on the plurality of bolts to increase the force applied to the package assembly by the thermal module and the mechanical support.

[0114] In some embodiments, the method further comprises: inserting a plurality of modules into the plurality of sockets. In some embodiments, the method further comprises: connecting the plurality of external connectors to an external system.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: Package components, including: a plurality of integrated circuit dies; an encapsulation body disposed around the plurality of integrated circuit dies; a redistribution structure located above the encapsulation body and the plurality of integrated circuit dies, the redistribution structure being electrically coupled to the plurality of integrated circuit dies; a plurality of sockets located on the rewiring structure, the plurality of sockets being electrically coupled to the rewiring structure; and A support ring is located on the rewiring structure and surrounds the plurality of sockets. The support ring is arranged along the outermost edge of the rewiring structure and at least partially overlaps with the rewiring structure in a lateral direction. 2 . The device of claim 1 , wherein the support ring has a first portion and a second portion, the first portion overlapping the redistribution structure in a lateral direction, the second portion extending beyond the outermost edge of the redistribution structure.

3. The apparatus of claim 1, wherein the support ring is defined laterally within the outermost edge of the redistribution structure. The device of claim 1 , wherein the support ring has a constant width. 5 . The device of claim 1 , wherein the support ring has a width that decreases in a direction extending away from a major surface of the redistribution structure. The device of claim 5 , wherein the width of the support ring decreases in a linear manner.

7. The device of claim 5, wherein the width of the support ring decreases in a step-wise manner.

8. The device of claim 1, wherein the support ring has an untruncated circular shape.

9. The device of claim 1, wherein the support ring has a truncated circular shape.

10. The apparatus according to claim 1, further comprising: A mechanical support is physically coupled to the plurality of sockets, and the support ring laterally surrounds the mechanical support.

11. The apparatus according to claim 10, further comprising: a thermal module physically and thermally coupled to the encapsulation and the plurality of integrated circuit dies; a plurality of first bolts extending through the mechanical bracket, the redistribution structure, the enclosure, and the thermal module; as well as A plurality of second bolts extend through the support ring, the redistribution structure, the enclosure and the thermal module.

12. A method for manufacturing a semiconductor device, comprising: placing a plurality of integrated circuit dies on a carrier substrate; encapsulating the plurality of integrated circuit dies using an encapsulation body; forming a redistribution structure over the encapsulation and the plurality of integrated circuit dies, the redistribution structure having a first diameter; bonding a support ring to the rewiring structure, the support ring having an inner diameter and an outer diameter, the inner diameter being smaller than the first diameter and the outer diameter being larger than the inner diameter; After attaching the support ring to the redistribution structure, peeling the carrier substrate from the plurality of integrated circuit dies and the encapsulation; and A plurality of sockets are attached to the rewiring structure, the plurality of sockets being surrounded by the support ring.

13. The method according to claim 12, further comprising: drilling a plurality of first bolt holes through the support ring, the redistribution structure, and the enclosure; as well as The support ring is bolted to the rewiring structure using a plurality of first bolts extending through the plurality of first bolt holes.

14. The method according to claim 13, further comprising: drilling a plurality of second bolt holes extending through the redistribution structure and the enclosure; as well as The mechanical bracket is bolted to the plurality of sockets using a plurality of second bolts extending through the plurality of second bolt holes.

15. The method according to claim 14, further comprising: A thermal module is bolted to the plurality of integrated circuit dies and the encapsulation using the plurality of second bolts.

16. The method of claim 12, wherein the outer diameter is greater than the first diameter.

17. The method of claim 12, wherein the outer diameter is equal to the first diameter.

18. A method for manufacturing a semiconductor device, comprising: Assembling the package assembly between the thermal module and the mechanical bracket using a plurality of bolts extending through the thermal module, the package assembly, and the mechanical bracket, wherein the package assembly comprises: a plurality of integrated circuit dies; an encapsulation body disposed around the plurality of integrated circuit dies; a redistribution structure located above the encapsulation body and the plurality of integrated circuit dies, the redistribution structure being electrically coupled to the plurality of integrated circuit dies; a plurality of sockets located on the rewiring structure, the plurality of sockets being electrically coupled to the rewiring structure; a plurality of external connectors located on the rewiring structure, the plurality of external connectors being electrically coupled to the rewiring structure; and a support ring, located on the rewiring structure and surrounding the plurality of sockets and the plurality of external connectors, the support ring being disposed along the outermost edge of the rewiring structure, and the support ring at least partially overlapping the rewiring structure in a lateral direction; and A plurality of fasteners are tightened onto the plurality of bolts to increase the force applied to the packaging assembly by the thermal module and the mechanical bracket.

19. The method according to claim 18, further comprising: A plurality of modules are inserted into the plurality of sockets.

20. The method of claim 18, further comprising: The plurality of external connections are connected to an external system.

21. The method of claim 18, wherein the support ring has a first portion and a second portion, the first portion laterally overlapping the redistribution structure, the second portion extending beyond the outermost edge of the redistribution structure.

22. The method of claim 18, wherein the support ring is defined laterally within the outermost edge of the redistribution structure.

23. The method of claim 18, wherein the support ring has a constant width. 24 . The method of claim 18 , wherein the support ring has a width that decreases in a linear manner in a direction extending away from a major surface of the redistribution structure. 25 . The method according to claim 18 , wherein the support ring has a width that decreases in a stepwise manner in a direction extending away from a main surface of the redistribution structure.

26. The method of claim 18, wherein the support ring has an untruncated circular shape.

27. The method of claim 18, wherein the support ring has a truncated circular shape.

28. The method of claim 18, wherein the plurality of bolts comprises: a plurality of first bolts extending through the mechanical bracket, the redistribution structure, the enclosure, and the thermal module; as well as A plurality of second bolts extend through the support ring, the redistribution structure, the enclosure and the thermal module.

29. A method of manufacturing a semiconductor device, comprising: encapsulating a plurality of integrated circuit dies using an encapsulation body; forming a redistribution structure over the encapsulation and the plurality of integrated circuit dies, the redistribution structure having a plurality of redistribution conductors connected to the plurality of integrated circuit dies; attaching a support ring to and around the periphery of the redistribution structure, the support ring having the same top-down shape as the redistribution structure, the support ring having a Young's modulus greater than that of the redistribution structure, the encapsulation body, and the plurality of integrated circuit dies; as well as A plurality of sockets are attached to the rewiring structure, the plurality of sockets being surrounded by the support ring.

30. The method of claim 29, wherein fitting the support ring to and around the perimeter of the redistribution structure comprises: drilling a plurality of bolt holes through the support ring, the redistribution structure, and the enclosure; as well as The support ring is bolted to the rewiring structure using a plurality of bolts extending through the plurality of bolt holes.

31. The method of claim 29, wherein the redistribution structure has a first diameter, and the support ring has an inner diameter and an outer diameter, wherein the inner diameter is smaller than the first diameter and the outer diameter is larger than the first diameter.

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