Display device and manufacturing method thereof

Abstract

A display device and a method for manufacturing the same are provided. The display device includes: a substrate including a display area and a first non-display area outside the display area, wherein a thin film transistor and a display device electrically connected to the thin film transistor are arranged in the display area; a through-portion vertically penetrating the substrate; a second non-display area between the through-portion and the display area; and an encapsulation layer on the display device and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially. The first and second inorganic encapsulation layers extend from the through-portion and directly contact each other in the second non-display area, and the first inorganic encapsulation layer directly contacts another underlying inorganic layer in the second non-display area.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0072418, filed on June 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of one or more embodiments relate to a display device and a method of manufacturing the same. Background Art

[0003] Recently, physical buttons and the like have been removed from the front of a display device, and the display area for displaying an image has been expanded. In addition, a display device has been introduced in which a separate component (such as a camera, etc.) for extending the functionality of the display device is placed in the display area to increase the display area. In order to place a separate component such as a camera in the display area, a groove or a through-portion in which the separate component can be positioned is formed in the display area. However, the groove or through-portion formed in the display area becomes a new permeable path through which external moisture and the like can penetrate into the display area. Summary of the Invention

[0004] According to aspects of one or more embodiments, there are provided a display device in which penetration of external moisture or the like through a through portion in a display area is prevented or substantially prevented, and a method of manufacturing the display device.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0006] According to one or more embodiments, a display device includes: a substrate including a display area and a first non-display area outside the display area, in which a plurality of thin film transistors and a plurality of display devices electrically connected to the plurality of thin film transistors are arranged; a through portion penetrating the substrate in a vertical direction; a second non-display area between the through portion and the display area; and an encapsulation layer on the plurality of display devices and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer extend to the through portion and are in direct contact with each other in the second non-display area, and the first inorganic encapsulation layer is in direct contact with another inorganic layer below the first inorganic encapsulation layer in the second non-display area.

[0007] The first inorganic encapsulation layer may directly contact an upper surface of the substrate in the second non-display area.

[0008] The substrate may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer sequentially stacked, and the first inorganic encapsulation layer may directly contact the second barrier layer in the second non-display area.

[0009] The display device may also include: a first inorganic insulating layer between the semiconductor layer and the gate electrode of each of the multiple thin film transistors; and a second inorganic insulating layer between the gate electrode and the source electrode of each of the multiple thin film transistors and between the gate electrode and the drain electrode of each of the multiple thin film transistors, and another inorganic layer directly contacting the first inorganic encapsulation layer in the second non-display area may include the first inorganic insulating layer or the second inorganic insulating layer.

[0010] The display device may further include a planarization layer between the plurality of thin film transistors and the plurality of display devices, and the planarization layer may extend to a portion of the second non-display area.

[0011] Each of the plurality of display devices may include a pixel electrode on a planarization layer, a counter electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the counter electrode, and at least some layers of the intermediate layer and the counter electrode may extend outside the planarization layer.

[0012] In the second non-display area, a first internal dam around the through portion may be disposed on the planarization layer, and the organic encapsulation layer may be outside an area partitioned by the first internal dam.

[0013] The display device may further include a pixel defining layer on the planarization layer and covering edges of the pixel electrodes of the plurality of display devices, and the first internal dam may include the same material as the pixel defining layer.

[0014] The display device may further include a second internal dam surrounding the through portion in the second non-display area at a position spaced apart from the first internal dam, the second internal dam being on the planarization layer.

[0015] In the second non-display area, a plurality of data lines may be arranged on the second inorganic insulating layer, the planarization layer may cover the plurality of data lines, and the first internal dam may overlap at least some of the plurality of data lines.

[0016] According to one or more embodiments, a display device includes a display area, a first non-display area around the display area, and a second non-display area at least a portion of which is surrounded by the display area. A method for manufacturing the display device includes: in the display area, forming a plurality of thin film transistors on a substrate, a planarization layer covering the plurality of thin film transistors, and a plurality of pixel electrodes on the planarization layer and electrically connected to the plurality of thin film transistors; forming a metal layer in the second non-display area; forming an intermediate layer and a counter electrode on the plurality of pixel electrodes; removing the metal layer from the substrate; sequentially forming a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer on the counter electrode; and forming a through portion penetrating the substrate in part of the second non-display area, wherein at least some layers in the intermediate layer and the counter electrode are extended from the display area to the second non-display area and formed on the metal layer, and at least some layers in the intermediate layer and the counter electrode formed on the metal layer are separated from the substrate by removing the metal layer.

[0017] The metal layer may be formed in parallel with the plurality of pixel electrodes.

[0018] Each of the plurality of thin film transistors may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and a metal layer may be formed in parallel with the semiconductor layer, in parallel with the gate electrode, or in parallel with the source and drain electrodes.

[0019] The first inorganic encapsulation layer and the second inorganic encapsulation layer can be in direct contact with each other in the area where the metal layer is removed from them, and the first inorganic encapsulation layer can be in direct contact with another inorganic layer arranged below the first inorganic encapsulation layer in the area where the metal layer is removed from it, and a through portion can be formed by penetrating the substrate, the first inorganic encapsulation layer, the second inorganic encapsulation layer and the other inorganic layer.

[0020] The first inorganic insulating layer and the second inorganic insulating layer can extend to part of the second non-display area, the first inorganic insulating layer is between the semiconductor layer and the gate electrode of each of the multiple thin film transistors, the second inorganic insulating layer is between the gate electrode and the source electrode of each of the multiple thin film transistors and between the gate electrode and the drain electrode of each of the multiple thin film transistors, and a metal layer can be formed on the first inorganic insulating layer or the second inorganic insulating layer.

[0021] The substrate may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer sequentially stacked, and the first inorganic encapsulating layer may be in direct contact with the second barrier layer in a region from which the metal layer is removed.

[0022] The manufacturing method may further include forming a pixel defining layer on the planarization layer covering edges of a plurality of pixel electrodes, wherein the planarization layer may extend to a portion of the second non-display area to be spaced a distance from the metal layer, and in the second non-display area, a first internal dam comprising the same material as the pixel defining layer may be formed on the planarization layer.

[0023] The first inner dam may surround the through portion, and the organic encapsulation layer may be located outside a region partitioned by the first inner dam.

[0024] At least one of the intermediate layers may contact another inorganic layer disposed under the first inorganic encapsulation layer in a gap between the metal layer and the planarization layer.

[0025] In the second non-display area, a plurality of data lines covered by the planarization layer may be formed, and the first internal dam may be formed to overlap at least some of the plurality of data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of the disclosed embodiments will become more apparent through the following description of some example embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 is a schematic plan view of a display device according to an example embodiment;

[0028] Figure 2 It is along Figure 1 The line I-I' and the line II-II' are intercepted Figure 1 A schematic cross-sectional view of a display device;

[0029] Figure 3 yes Figure 1 An enlarged plan view of area "A" of the display device;

[0030] Figure 4 According to an example embodiment Figure 3 A schematic plan view of a through portion of

[0031] Figure 5 It is along Figure 4 The line III-III' is intercepted Figure 4 A schematic cross-sectional view of a through portion of

[0032] Figure 6 According to another exemplary embodiment, Figure 4 A schematic cross-sectional view of the through portion taken along line III-III';

[0033] Figure 7 According to another exemplary embodiment, Figure 4 A schematic cross-sectional view of the through portion taken along line III-III'; and

[0034] Figures 8 to 11 is a schematic cross-sectional view of a manufacturing process of a display device according to example embodiments. DETAILED DESCRIPTION

[0035] Reference will now be made in more detail to some embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following description will only describe the embodiments with reference to the accompanying drawings to explain various aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. When a statement such as "at least one (of which)..." follows a column of elements, the statement modifies the entire column of elements without modifying the individual elements in the column.

[0036] It will be understood that when a component such as a layer, film, region, or plate is referred to as being “on” another component, it can be directly on the other component or one or more intervening components may be present.

[0037] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings may be arbitrarily shown for the convenience of explanation, the embodiments are not limited thereto.

[0038] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order from the described order.

[0039] The present disclosure will now be described more fully with reference to the accompanying drawings, in which some example embodiments of the invention are shown and in which like reference numerals refer to like elements.

[0040] It will be understood that although terms such as “first” and “second” may be used herein to describe various components, these components are not limited by these terms, and the terms are used to distinguish one component from another.

[0041] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] It will also be understood that the term “comprise” and / or variations thereof used herein specify the presence of stated features or components, but does not preclude the presence or addition of one or more other features or components.

[0043] In the embodiments described herein, when a layer, region, or component is connected to another layer, region, or component, the multiple layers, regions, or components may be directly connected to one another, and the multiple layers, regions, or components may also be indirectly connected to one another with another layer, region, or component therebetween.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments of the inventive concepts belong. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0045] Figure 1 is a schematic plan view of a display device according to an example embodiment, and Figure 2 It is along Figure 1 The line I-I' and the line II-II' are intercepted Figure 1 Schematic cross-sectional view of a display device.

[0046] Reference Figure 1 and Figure 2 The display device 10 includes a display area DA that displays an image; a first non-display area PA1 surrounding the display area DA; and a second non-display area PA2, at least a portion or some portions of which are surrounded by the display area DA. The substrate 100 includes the display area DA, the first non-display area PA1, and the second non-display area PA2.

[0047] The display device is in the display area DA, and the first non-display area PA1 may include a pad area, etc., where any one of various electronic devices, printed circuit boards, etc. is electrically connected.

[0048] In the display area DA, in addition to the display device, a thin film transistor 210 electrically connected to the display device may be further provided. Figure 2 In the embodiment, the organic light emitting device 300 is provided in the display area DA as a display device. The electrical connection of the organic light emitting device 300 to the thin film transistor 210 can be interpreted as the pixel electrode 310 of the organic light emitting device 300 being electrically connected to the thin film transistor 210.

[0049] At least a portion or some portions of the second non-display area PA2 are surrounded by the display area DA, and are disposed between the display area DA and the at least one through portion H. Figure 1The second non-display area PA2 is shown to be within the display area DA and thus completely surrounded by the display area DA, but one or more embodiments are not limited thereto. For example, a portion of the second non-display area PA2 may contact the first non-display area PA1.

[0050] The through portion H may be a space for a separate component for one or more functions of the display device 10, or a space for a separate component that can add a new function to the display device 10. For example, any one of a sensor, a light source, a camera module, etc. may be provided in the through portion H. In an embodiment, there may be at least two through portions H.

[0051] Since the through-portion H is a region through which the substrate 100 and the layers stacked on the substrate 100 are vertically penetrated, external moisture or oxygen may penetrate into the display device 10 through the inner vertical side surface of the display device 10 exposed through the through-portion H. However, according to an embodiment, the second non-display area PA2 may include a moat area MA surrounding the through-portion H, and thus, moisture penetration may be effectively prevented or substantially prevented. Figure 4 The moat area MA will be described in more detail and reference will first be made to Figure 2 The structure of the display device 10 according to the embodiment is described.

[0052] The substrate 100 may include any of a variety of materials. When the display device 10 is a bottom-emitting type in which an image is generated toward the substrate 100, the substrate 100 includes a transparent material. However, when the display device 10 is a top-emitting type in which an image is generated in a direction away from the substrate 100, the substrate 100 may not include a transparent material. In this case, the substrate 100 may include a metal. When the substrate 100 includes a metal, the substrate 100 may include any of iron (Fe), chromium (Cr), manganese (Mn), nickel (Ni), titanium (Ti), molybdenum (Mo), stainless steel (SUS), Invar, Inconel, Kovar, and the like.

[0053] For example, the substrate 100 may have a multi-layer structure in which a first base layer 101 , a first barrier layer 102 , a second base layer 103 , and a second barrier layer 104 are sequentially stacked.

[0054] In an embodiment, the first base layer 101 and the second base layer 103 may each include a transparent glass material, which mainly includes, for example, SiO2. However, the first base layer 101 and the second base layer 103 are not limited thereto and may each include a transparent plastic material. The plastic material may be polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide (PI), polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0055] The thicknesses of the first base layer 101 and the second base layer 103 may be the same or different. For example, each of the first base layer 101 and the second base layer 103 may include PI and may have a thickness between about 3 μm and about 20 μm.

[0056] The first barrier layer 102 and the second barrier layer 104 are layers that prevent or substantially prevent external impurities from penetrating into the display device 10 through the substrate 100, and both may include a material such as silicon nitride (SiN x ) and / or silicon oxide (SiO x ). For example, the first barrier layer 102 may be any one of a layer including an amorphous silicon layer and a silicon oxide layer to improve adhesion between adjacent layers, and the second barrier layer 104 may be a silicon oxide layer. In an embodiment, each of the first barrier layer 102 and the second barrier layer 104 may have a thickness of about With The thickness is between , but the embodiment is not limited thereto.

[0057] In an embodiment, a buffer layer may be further formed on the substrate 100. The buffer layer may block impurities or moisture from penetrating through the substrate 100. For example, the buffer layer may include a material such as SiO x 、SiN x 、Silicon oxynitride (SiO x N y ), an inorganic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO2) or titanium nitride (TiN), or an organic material such as PI, polyester or acrylic, and may have a stacked structure including any of the foregoing materials. In some embodiments, the second barrier layer 104 of the substrate 100 may be part of a buffer layer having a multi-layer structure.

[0058] The thin film transistor 210 is disposed in the display area DA of the substrate 100 , and a display device electrically connected to the thin film transistor 210 is disposed in the display area DA of the substrate 100 in addition to the thin film transistor 210 . Figure 2 An organic light-emitting device 300 is shown as a display device. A thin film transistor (not shown) may be provided in the first non-display area PA1 of the substrate 100. The thin film transistor provided in the first non-display area PA1 may be part of a circuit unit for controlling an electrical signal transmitted to, for example, the display area DA.

[0059] The thin film transistor 210 includes a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217. The semiconductor layer includes amorphous silicon, polycrystalline silicon, or an organic semiconductor material. When a buffer layer is disposed on the substrate 100, the semiconductor layer 211 may be on the buffer layer.

[0060] The gate electrode 213 is provided above the semiconductor layer 211, and in response to a signal transmitted to the gate electrode 213, the source electrode 215 and the drain electrode 217 are electrically connected to each other. In an embodiment, the gate electrode 213 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer structure or a multi-layer structure. In this case, in order to ensure insulation between the semiconductor layer 211 and the gate electrode 213, a first inorganic insulating layer 120 may be provided between the semiconductor layer 211 and the gate electrode 213. The first inorganic insulating layer 120 may include a material such as SiO x 、SiN x or SiO x N y The first inorganic insulating layer 120 may be formed in the display area DA, the first non-display area PA1, and the second non-display area PA2.

[0061] The second inorganic insulating layer 130 may be provided on the gate electrode 213 and may include an inorganic layer such as SiO x 、SiN x or SiO x N y The second inorganic insulating layer 130 may be formed in the display area DA, the first non-display area PA1, and the second non-display area PA2.

[0062] The source electrode 215 and the drain electrode 217 are provided on the second inorganic insulating layer 130. The source electrode 215 and the drain electrode 217 are electrically connected to the semiconductor layer 211 through contact holes formed in the second inorganic insulating layer 130 and the first inorganic insulating layer 120, respectively. In an embodiment, considering conductivity, etc., the source electrode 215 and the drain electrode 217 may each include at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu, and may have a single-layer structure or a multi-layer structure.

[0063] In order to protect the thin film transistor 210 having the above structure, a protective layer (not shown) covering the thin film transistor 210 may be provided. The protective layer may include, for example, an inorganic material such as SiO x 、SiNx or SiO x N y The protective layer may comprise one or more layers.

[0064] The planarization layer 140 may be provided on the thin film transistor 210. Figure 2 , for example, when the organic light emitting device 300 may be provided at a level higher than that of the thin film transistor 210, the planarization layer 140 may cover the thin film transistor 210 and may planarize unevenness caused by the thin film transistor 210. The planarization layer 140 may include, for example, an organic insulating material such as acrylic, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). Figure 2 The planarization layer 140 is shown as a single layer; however, the planarization layer 140 may be a multi-layer layer. The display device 10 according to the embodiment may include both the protective layer and the planarization layer 140 , or may include only the planarization layer 140 .

[0065] The organic light emitting device 300 is disposed on the planarization layer 140 in the display area DA, and includes a pixel electrode 310 , an opposing electrode 330 , and an intermediate layer 320 disposed between the pixel electrode 310 and the opposing electrode 330 and including an emission layer.

[0066] An opening exposing at least one of the source electrode 215 and the drain electrode 217 of the thin film transistor 210 is formed in the planarization layer 140, and on the planarization layer 140, there is a pixel electrode 310 that contacts any one of the source electrode 215 and the drain electrode 217 through the opening and is electrically connected to the thin film transistor 210.

[0067] The pixel electrode 310 may include a transparent (or semi-transparent) electrode or a reflective electrode. When the pixel electrode 310 includes a transparent (or semi-transparent) electrode, the pixel electrode 310 may include, for example, ITO, IZO, ZnO, In2O3, IGO, or AZO. When the pixel electrode 310 includes a reflective electrode, the pixel electrode 310 may include a reflective layer comprising any one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a combination thereof, and a layer comprising ITO, IZO, ZnO, In2O3, IGO, or AZO. However, the embodiment is not limited thereto, and the pixel electrode 310 may include any one of various materials and may have any one of various structures such as a single-layer structure and a multilayer structure.

[0068] The pixel defining layer 150 may be disposed on the planarization layer 140. Since the pixel defining layer 150 has an opening corresponding to each sub-pixel (ie, an opening exposing at least the central portion of the pixel electrode 310), the pixel defining layer 150 defines the pixel. Figure 2, the pixel defining layer 150 prevents or substantially prevents arcing, etc., from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel defining layer 150 may include, for example, an organic insulating material such as PI or HMDSO.

[0069] The intermediate layer 320 of the organic light-emitting device 300 includes an emission layer. The emission layer may include a polymer organic material or a low molecular weight organic material that emits light of a certain color. In addition, the intermediate layer 320 may include at least one functional layer among a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL). Such a functional layer may include an organic material. Some of the layers forming the intermediate layer 320 (e.g., (multiple) functional layers) may be formed integrally across multiple organic light-emitting devices 300.

[0070] The counter electrode 330 may cover the display area DA. In an embodiment, the counter electrode 330 may be integrally formed for a plurality of organic light-emitting devices 300 and may correspond to the pixel electrode 310. The counter electrode 330 may include a transparent (or translucent) electrode or a reflective electrode. In an embodiment, when the counter electrode 330 includes a transparent (or translucent) electrode, the counter electrode 330 may include a layer containing a metal having a small work function (i.e., any one of Li, Ca, lithium fluoride (LiF) / Ca, LiF / Al, Al, Ag, Mg, and combinations thereof) and a transparent (translucent) conductive layer including ITO, IZO, ZnO, In2O3, etc. When the counter electrode 330 includes a reflective electrode, the counter electrode 330 may include a layer containing any one of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and combinations thereof. However, the structure and material of the counter electrode 330 are not limited thereto and may be changed.

[0071] Meanwhile, in order for the display device 10 to display an image, an electrical signal (e.g., a preset electrical signal) is applied to the counter electrode 330. To this end, a voltage line 420 is aligned in the first non-display area PA1 to transmit the electrical signal (e.g., a preset electrical signal) to the counter electrode 330. The voltage line 420 may be a common power supply voltage line.

[0072] When various conductive layers are formed in the display area DA, the voltage line 420 and the conductive layers may be formed of the same material in parallel (eg, simultaneously). Figure 2The voltage line 420 is shown disposed on the second inorganic insulating layer 130 in the first non-display area PA1, similarly to the source electrode 215 and the drain electrode 217 of the thin film transistor 210 disposed on the second inorganic insulating layer 130 in the display area DA. In an embodiment, when the source electrode 215 and the drain electrode 217 of the thin film transistor 210 are formed on the second inorganic insulating layer 130 in the display area DA, the voltage line 420 is formed on the second inorganic insulating layer 130 in the first non-display area PA1 from the same material as the source electrode 215 and the drain electrode 217 in parallel (e.g., simultaneously). Therefore, the voltage line 420 may have the same structure as the source electrode 215 and the drain electrode 217. However, the embodiment is not limited thereto and may be implemented in various forms, such as in the example in which, when the gate electrode 213 is formed, the voltage line 420 is formed on the first inorganic insulating layer 120 in parallel (e.g., simultaneously) with the gate electrode 213 of the same material.

[0073] The counter electrode 330 may directly contact the voltage line 420, or Figure 2 , the counter electrode 330 may be electrically connected to the voltage line 420 through the protective conductive layer 421. The protective conductive layer 421 may be provided on the planarization layer 140 and may extend onto the voltage line 420, thereby being electrically connected to the voltage line 420. Therefore, the counter electrode 330 may contact the protective conductive layer 421 in the first non-display area PA1, and the protective conductive layer 421 may also contact the voltage line 420 in the first non-display area PA1.

[0074] like Figure 2 As shown in , the protective conductive layer 421 is provided on the planarization layer 140, and therefore, the protective conductive layer 421 may be formed in parallel (e.g., simultaneously) from the same material as the components located on the planarization layer 140 in the display area DA. In an embodiment, when the pixel electrode 310 is formed on the planarization layer 140 in the display area DA, the protective conductive layer 421 may be formed in parallel (e.g., simultaneously) from the same material as the pixel electrode 310 on the planarization layer 140 in the first non-display area PA1. Therefore, the protective conductive layer 421 may have the same structure as the pixel electrode 310. As shown in FIG. Figure 2 As shown in FIG, the protective conductive layer 421 may cover the portion of the voltage line 420 that is not covered by the planarization layer 140 and is exposed. Therefore, during the formation of the first confinement dam 610 or the second confinement dam 620, damage to the portion of the voltage line 420 exposed outside the planarization layer 140 may be prevented or substantially prevented.

[0075] like Figure 2As shown in FIG, to prevent or substantially prevent impurities such as external oxygen or moisture from penetrating into the display area DA through the planarization layer 140, the planarization layer 140 may have an opening 140b in the first non-display area PA1. The opening 140b may surround the display area DA. In embodiments, when the protective conductive layer 421 is formed, the protective conductive layer 421 may fill the opening 140b. Thus, impurities that have penetrated the planarization layer 140 in the first non-display area PA1 can be effectively prevented or substantially prevented from penetrating into the planarization layer 140 in the display area DA.

[0076] A capping layer 160 that improves the efficiency of light generated from the organic light-emitting device 300 may be located on the counter electrode 330. The capping layer 160 may cover the counter electrode 330 and may extend outside the counter electrode 330 to contact the protective conductive layer 421 disposed below the counter electrode 330. Since the counter electrode 330 covers the display area DA and extends beyond the display area DA, the capping layer 160 may also cover the display area DA and extend to the first non-display area PA1 outside the display area DA. The capping layer 160 includes an organic material.

[0077] As described above, the capping layer 160 improves the efficiency of light generated from the organic light emitting device 300. For example, the capping layer 160 can improve the efficiency of light extraction to the outside. The improvement in efficiency caused by the use of the capping layer 160 can be uniformly achieved in the display area DA. In an embodiment, the capping layer 160 has an upper surface corresponding to the curve of the upper surface of the layer below the capping layer 160. That is, as Figure 2 As shown in , at a portion of the capping layer 160 disposed above the opposing electrode 330 , an upper surface of the capping layer 160 may have a shape corresponding to a curve of the upper surface of the opposing electrode 330 .

[0078] The encapsulation layer 500 is disposed above the capping layer 160. The encapsulation layer 500 protects the organic light emitting device 300 from external moisture, oxygen, etc. To this end, the encapsulation layer 500 extends to the first non-display area PA1 outside the display area DA. The encapsulation layer 500 may have a multi-layer structure. In an embodiment, as shown in FIG. Figure 2 As shown in , the encapsulation layer 500 may include a first inorganic encapsulation layer 510 , an organic encapsulation layer 520 , and a second inorganic encapsulation layer 530 .

[0079] The first inorganic encapsulating layer 510 may cover the capping layer 160 and may include SiO x 、SiN x 、SiO x N y wait.

[0080] Since the first inorganic encapsulation layer 510 is formed along the structure below it, Figure 2As shown in FIG, the upper surface of the first inorganic encapsulation layer 510 may be uneven. The organic encapsulation layer 520 may cover the first inorganic encapsulation layer 510 and have a sufficient thickness, so that the upper surface of the organic encapsulation layer 520 can be substantially flat throughout the display area DA. In embodiments, the organic encapsulation layer 520 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, an acrylic resin (e.g., poly(methyl methacrylate), polyacrylic acid, etc.), or any combination thereof.

[0081] The second inorganic encapsulating layer 530 covers the organic encapsulating layer 520 and may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc. The second inorganic encapsulating layer 530 may extend to the outside of the organic encapsulating layer 520 and may contact the first inorganic encapsulating layer 510, thereby preventing the organic encapsulating layer 520 from being exposed to the outside.

[0082] In embodiments, since the encapsulation layer 500 includes the first inorganic encapsulation layer 510, the organic encapsulation layer 520, and the second inorganic encapsulation layer 530, although cracks occur in the encapsulation layer 500, such cracks do not develop between the first inorganic encapsulation layer 510 and the organic encapsulation layer 520 or between the organic encapsulation layer 520 and the second inorganic encapsulation layer 530 due to the multi-layer structure of the encapsulation layer 500. Therefore, the formation of a path through which external moisture, oxygen, etc. penetrate into the display area DA can be prevented or reduced.

[0083] While the encapsulation layer 500 is being formed, the structure below the encapsulation layer 500 may be damaged. For example, the first inorganic encapsulation layer 510 may be formed by using chemical vapor deposition, and when the first inorganic encapsulation layer 510 is formed by using chemical vapor deposition, the layer directly below the first inorganic encapsulation layer 510 may be damaged. Therefore, when the first inorganic encapsulation layer 510 is formed directly on the capping layer 160, the capping layer 160 that improves the efficiency of light generated from the organic light-emitting device 300 may be damaged, and thus, the light efficiency of the display device 10 may be reduced. Therefore, according to an embodiment, a protective layer 170 may be provided between the capping layer 160 and the encapsulation layer 500 to prevent or substantially prevent the capping layer 160 from being damaged during the formation of the encapsulation layer 500. In an embodiment, the protective layer 170 may include LiF.

[0084] As described above, the cover layer 160 may extend to the display area DA and the first non-display area PA1 outside the display area DA. Therefore, the protective layer 170 may extend to the outside of the cover layer 160 and prevent or substantially prevent the cover layer 160 from directly contacting the encapsulation layer 500. In this case, the protective layer 170 covers the end portion 160a of the cover layer 160, and thus the end portion 170a of the protective layer 170 is disposed on the planarization layer 140. In an embodiment, as shown in FIG. Figure 2 As shown in FIG, the end portion 170 a of the protection layer 170 directly contacts the protection conductive layer 421 on the planarization layer 140 .

[0085] Therefore, since the first inorganic encapsulation layer 510, which is the lowermost layer of the encapsulation layer 500, does not contact the capping layer 160 including an organic material but contacts the protective layer 170 including an inorganic material such as LiF, the adhesion between the encapsulation layer 500 and the layers below it can be maintained large. Therefore, when the display device 10 is manufactured or used after manufacturing, it is possible to effectively prevent or reduce the encapsulation layer 500 from peeling off from the lower layer.

[0086] When forming the encapsulation layer 500, and in more detail, when forming the organic encapsulation layer 520, the material used to form the organic encapsulation layer 520 is confined within a region (eg, a predetermined region). Figure 2 As shown in FIG, the first limiting dam 610 may be provided in the first non-display area PA1. Figure 2 As shown in FIG, the first inorganic insulating layer 120, the second inorganic insulating layer 130, and the planarization layer 140 may be provided not only in the display area DA of the substrate 100 but also in the first non-display area PA1. The first confinement dam 610 is provided in the first non-display area PA1 to be separated from the planarization layer 140.

[0087] In an embodiment, the first confinement dam 610 may have a multi-layer structure. That is, the first confinement dam 610 may include a first layer 611 and a second layer 613 in a direction away from a portion close to the substrate 100. In an embodiment, the first layer 611 and the planarization layer 140 in the first non-display area PA1 may be formed in parallel (e.g., simultaneously) from the same material as the planarization layer 140 formed in the display area DA, and the second layer 613 and the pixel defining layer 150 in the first non-display area PA1 may be formed in parallel (e.g., simultaneously) from the same material as the pixel defining layer 150 formed in the display area DA.

[0088] like Figure 2 As shown in , in addition to the first limiting dam 610, the second limiting dam 620 may be between the first limiting dam 610 and the end 140a of the planarization layer 140. The second limiting dam 620 may be on a portion of the protective conductive layer 421 on the voltage line 420. In an embodiment, the second limiting dam 620 is separated from the planarization layer 140 and is disposed in the first non-display area PA1. In an embodiment, the second limiting dam 620 may have a multi-layer structure like the first limiting dam 610 and may include a smaller number of layers than the first limiting dam 610, and therefore, the height of the second limiting dam 620 from the substrate 100 is less than the height of the first limiting dam 610 from the substrate 100. In an embodiment, as Figure 2 As shown in FIG, the second confinement dam 620 and the second layer 613 of the first confinement dam 610 are formed of the same material in parallel (eg, simultaneously).

[0089] Therefore, the position of the organic encapsulation layer 520 is limited by the second limiting dam 620, and thus, the second limiting dam 620 can prevent or substantially prevent the material for forming the organic encapsulation layer 520 from overflowing toward the outside of the second limiting dam 620 during the formation of the organic encapsulation layer 520. Even if the material for forming the organic encapsulation layer 520 partially overflows toward the outside of the second limiting dam 620, the position of the organic encapsulation layer 520 is limited by the first limiting dam 610, and thus, the material for forming the organic encapsulation layer 520 may not move in a direction toward the edge 100a of the substrate 100. In an embodiment, as Figure 2 As shown in FIG, the first and second inorganic encapsulating layers 510 and 530 formed by using chemical vapor deposition cover the first and second confinement dams 610 and 620 and are formed to the outside of the first confinement dam 610 .

[0090] like Figure 2 As shown in FIG, the crack prevention portion 630 is provided in the first non-display area PA1. The crack prevention portion 630 may extend along at least some portions of the edge 100a of the substrate 100. For example, the crack prevention portion 630 may have a shape that surrounds or extends once around the display area DA. In some embodiments, the crack prevention portion 630 may be discontinuous. The crack prevention portion 630 may prevent or substantially prevent cracks from extending into the display area DA, the cracks being generated in the first inorganic insulating layer 120 and the second inorganic insulating layer 130 including an inorganic material due to impact, etc., when cutting a motherboard during the manufacture of the display device 10 or when using the display device 10.

[0091] The crack prevention portion 630 may have any of a variety of shapes, and in an embodiment, as shown in FIG. Figure 2 As shown in FIG, the crack prevention portion 630 and some components formed in the display area DA may be formed of the same material in parallel (eg, simultaneously), and the crack prevention portion 630 may also have a multi-layer structure.

[0092] Figure 2 The crack prevention portion 630 is shown to have a multi-layer structure including a lower layer 630' and an upper layer 630" disposed on the lower layer 630'. In more detail, Figure 2In the embodiment, the crack prevention portion 630 includes a lower layer 630' and an upper layer 630", wherein the lower layer 630' includes the same material as the first inorganic insulating layer 120, and the upper layer 630" includes the same material as the second inorganic insulating layer 130 disposed on the first inorganic insulating layer 120. In the embodiment, when the buffer layer is formed on the substrate 100, the crack prevention portion 630 may include a layer including the same material as the buffer layer. In the embodiment, as Figure 2 As shown in FIG, there may be a plurality of crack prevention portions 630 separated from each other.

[0093] The crack prevention portion 630 may be formed when the first inorganic insulating layer 120 and the second inorganic insulating layer 130 are partially removed. Figure 2 As shown in , a groove from which the first and second inorganic insulating layers 120 and 130 are removed is formed in at least one side of the crack prevention portion 630, and the crack prevention portion 630 may include remaining portions of the first and second inorganic insulating layers 120 and 130 adjacent to the groove.

[0094] like Figure 2 As shown in FIG, the crack prevention portion 630 may be covered by a cover layer 650. In an embodiment, for example, when the planarization layer 140 is formed in the display area DA, the cover layer 650 and the planarization layer 140 may be formed in parallel (e.g., simultaneously) from the same material. That is, the cover layer 650 may include a layer including an organic material that covers the crack prevention portion 630 including an inorganic material. The cover layer 650 may cover the ends of the first inorganic insulating layer 120 and / or the second inorganic insulating layer 130 along the edge 100a of the substrate 100, and may also cover the crack prevention portion 630.

[0095] Figure 3 yes Figure 1 an enlarged plan view of area "A"; Figure 4 According to an example embodiment Figure 3 a schematic plan view of a through portion of the Figure 5 is along the Figure 4 Schematic cross-sectional view taken along line III-III'. Figure 6 and Figure 7 According to other example embodiments Figure 4 A cross-sectional view of the through portion taken along line III-III'.

[0096] Figure 3 The through portion H and the surroundings of the through portion H are schematically shown. Figure 3, the organic light emitting device 300 electrically connected to the data line DL is arranged in the display area DA around the through-portion H, and the second non-display area PA2 may be defined as an area between the through-portion H and the display area DA and not displaying an image.

[0097] The data lines DL extend in the first direction and are electrically connected to the data driver 1100. In an example, the data driver 1100 is a chip on panel (COP) type and may be disposed in the first non-display area ( Figure 1 The display device is provided in the PA1 of the first non-display area or on a flexible printed circuit board (FPCB) (not shown) electrically connected to terminals provided in the first non-display area.

[0098] Due to the through-hole H provided in the display area DA, some of the data lines DL extending in the first direction may not be straight in the first direction. In this case, some of the data lines DL bypass the through-hole H, and the data lines DL bypassing the through-hole H are provided around the through-hole H in the second non-display area PA2.

[0099] Although not in Figure 3 , but the scan lines may extend in the second direction crossing the data lines DL, and some of the scan lines may bypass the through-portion H in the region where the through-portion H is formed. As another example, the display device ( Figure 1 10) includes two scan drivers arranged on both sides of the display area DA, and thus can prevent the scan line from bypassing the through-portion H. For example, the scan line electrically connected to the organic light emitting device 300 on the left side of the through-portion H and the scan line electrically connected to the organic light emitting device 300 on the right side of the through-portion H can be connected to different scan drivers.

[0100] Referring to FIG. 1 , which shows the through portion H in more detail Figure 4 and Figure 5 , a moat area MA surrounding the through portion H may be located around the through portion H vertically penetrating the substrate 100. The moat area MA is within the second non-display area PA2.

[0101] In the second non-display area PA2 , some of the data lines DL may be arranged. For example, in the second non-display area PA2 , the data lines DL are above the second inorganic insulating layer 130 and may be covered by the planarization layer 140 .

[0102] The first internal dam 710 may be disposed on the planarization layer 140 in the second non-display area PA2, and a second internal dam 720 may be further disposed separate from the first internal dam 710. The second internal dam 720 may be between the first internal dam 710 and the through portion H and on the planarization layer 140.

[0103] In an embodiment, the first inner dam 710 and the second inner dam 720 may be formed before forming a pixel defining layer ( Figure 2 150) are formed in parallel (eg, simultaneously) from the same material and may respectively surround the through portion H. The first inner dam 710 and the second inner dam 720 may perform the same as the first limiting dam ( Figure 2 610) and the second limiting dam ( Figure 2 620). Therefore, the first inner dam 710 and the second inner dam 720 can prevent or substantially prevent the material used to form the organic encapsulation layer 520 from flowing toward the through portion H during the formation of the organic encapsulation layer 520. Therefore, the organic encapsulation layer 520 can be outside the area surrounded by the first inner dam 710. The second inner dam 720 can block the flow of the material used to form the organic encapsulation layer 520 for a second time. The first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 can extend toward the through portion H beyond the second inner dam 720.

[0104] The first and second internal dams 710 and 720 may overlap some of the data lines DL arranged in the second non-display area PA2 , and thus, the area of ​​the second non-display area PA2 may be reduced.

[0105] In the second non-display area PA2, the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 are in direct contact with each other, and the first inorganic encapsulation layer 510 is in direct contact with another inorganic layer therebelow. More specifically, the moat area MA surrounding the through portion H may be located in the second non-display area PA2. In an embodiment, in the moat area MA, there may be a layer comprising only inorganic materials. In the moat area MA, the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 are in direct contact with each other, and the first inorganic encapsulation layer 510 is in direct contact with another inorganic layer therebelow. For example, when the first inorganic insulating layer 120 and the second inorganic insulating layer 130 are formed to extend to the moat area MA, the first inorganic encapsulation layer 510 may be in direct contact with the second inorganic insulating layer 130.

[0106] In another embodiment, Figure 6 As shown in FIG, the first inorganic insulating layer 120 may extend to the moat area MA, and the second inorganic insulating layer 130 may be covered by the planarization layer 140 in the second non-display area PA2. In this case, the first inorganic encapsulating layer 510 may directly contact the first inorganic insulating layer 120 in the moat area MA.

[0107] In another embodiment, Figure 7As shown in FIG, both the first inorganic insulating layer 120 and the second inorganic insulating layer 130 may not extend to the moat area MA and may be covered by the planarization layer 140 in the second non-display area PA2. In this case, the first inorganic encapsulation layer 510 may directly contact the upper surface of the substrate 100 in the moat area MA. In an embodiment, the first inorganic encapsulation layer 510 may directly contact the second barrier layer ( Figure 2 104). In an embodiment, when a buffer layer is further formed on the substrate 100, the first inorganic encapsulation layer 510 may directly contact the buffer layer in the moat area MA.

[0108] Therefore, it is possible to effectively prevent external moisture and the like from passing through the display device ( Figure 1 The side profile exposed by the through portion H of 10) penetrates into the display area.

[0109] According to the prior art, grooves can be formed in the depth direction of the substrate 100 to surround the through portion H and to be separated from each other, and the intermediate layer 320 can become discontinuous due to the grooves to prevent moisture from penetrating through the through portion H. However, in order to improve the anti-penetration, a large number of grooves must be formed, and thus the area of ​​the second non-display area PA2 increases. For example, when 20 grooves are formed around the through portion H, the length of the area where the grooves are located is about 300 μm, but when the display device ( Figure 1 When the moat area MA is included in the embodiment 10), the length of the moat area MA can be less than or equal to 100 μm. The length of the region where the conventional groove is located and the length of the moat area MA according to the present disclosure both represent the lengths measured in the radial direction of a circle with the through portion H at its center. That is, according to one or more embodiments of the present disclosure, the moat area MA can achieve excellent anti-permeability and reduce the area of ​​the second non-display area PA2.

[0110] In addition, since the first inorganic encapsulation layer 510 directly contacts another inorganic layer thereunder in the moat area MA, it is possible to effectively prevent the first inorganic encapsulation layer 510 from being damaged during the manufacture of the display device ( Figure 1 10) or an encapsulation layer caused when using the display device after manufacturing ( Figure 2 500) peeling.

[0111] Figures 8 to 11 yes Figure 1 A schematic cross-sectional view of a manufacturing process of a display device, and showing the steps along Figure 1 Line I-I' and Figure 4 A cross section taken along line III-III'.

[0112] Reference Figure 8A thin film transistor 210 and a planarization layer 140 covering the thin film transistor 210 are formed over the substrate 100. For example, the thin film transistor 210 may be in the display area DA, and the planarization layer 140 may extend to a portion of the second non-display area PA2.

[0113] The thin film transistor 210 may include a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217. A first inorganic insulating layer 120 including an inorganic material may be formed between the semiconductor layer 211 and the gate electrode 213. The first inorganic insulating layer 120 may be formed in the display area DA, the first non-display area ( Figure 1 In addition, the second inorganic insulating layer 130 formed between the gate electrode 213 and the source electrode 215 and between the gate electrode 213 and the drain electrode 217 includes an inorganic material, and the second inorganic insulating layer 130 may extend to the first non-display area ( Figure 1 PA1) and a second non-display area PA2.

[0114] An opening exposing the drain electrode 217 is formed in the planarization layer 140, and a pixel electrode 310 is formed on the planarization layer 140. The pixel electrode 310 may be formed by forming a metal material for forming the pixel electrode 310 on the substrate 100 and then patterning the metal material. The pixel electrode 310 may contact the drain electrode 217 through the opening.

[0115] When forming the pixel electrode 310, a metal layer M may also be formed in the second non-display area PA2. In an embodiment, the metal layer M may include the same material as the pixel electrode 310. The metal layer M may be formed in a central portion of the second non-display area PA2 and may be spaced a certain distance from an end portion of the planarization layer 140 extending to the second non-display area PA2.

[0116] In an embodiment, the metal layer M may be formed simultaneously with the formation of the thin film transistor 210. For example, the metal layer M may be formed in parallel (e.g., simultaneously) with the gate electrode 213 or with the source electrode 215 and the drain electrode 217. In an embodiment, the metal layer M may be formed in parallel (e.g., simultaneously) with the semiconductor layer 211.

[0117] When the metal layer M is formed in parallel (for example, simultaneously) with the semiconductor layer 211, the metal layer M can be formed directly on the substrate 100, and when the metal layer M is formed in parallel (for example, simultaneously) with the gate electrode 213, the metal layer M can be formed on the substrate 100 or the first inorganic insulating layer 120, and when the metal layer M is formed in parallel (for example, simultaneously) with the source electrode 215 and the drain electrode 217, the metal layer M can be formed on the substrate 100, the first inorganic insulating layer 120 or the second inorganic insulating layer 130.

[0118] Then, if Figure 9 As shown in FIG, a pixel defining layer 150 is formed on the pixel electrode 310. The pixel defining layer 150 may cover the edge of the pixel electrode 310 and may include an opening that exposes the central portion of the pixel electrode 310. During the formation of the pixel defining layer 150, a first internal dam 710 may be formed in the second non-display area PA2. In an embodiment, a second internal dam 720 may be formed together with the first internal dam 710. The first internal dam 710 and the second internal dam 720 may be disposed on the planarization layer 140 in the second non-display area PA2.

[0119] The organic light-emitting device 300 is formed by stacking an intermediate layer 320 and a counter electrode 330 on the pixel electrode 310 exposed through the opening of the pixel defining layer 150. In an embodiment, at least some layers included in the intermediate layer 320 may be integrally formed in the display area DA and the entire second non-display area PA2. In an embodiment, the counter electrode 330, the capping layer 160, and the protective layer 170 may also be integrally formed in the display area DA and the entire second non-display area PA2, and the capping layer 160 and the protective layer 170 may be formed on the counter electrode 330. Therefore, the intermediate layer 320 or some layers included in the intermediate layer 320, the counter electrode 330, the capping layer 160, and the protective layer 170 may be sequentially stacked on the metal layer M in the second non-display area PA2.

[0120] Then, if Figure 10 and Figure 11 As shown in FIG, after removing the metal layer M from the substrate 100 and then forming the encapsulation layer 500 over the substrate 100, a through portion H penetrating the substrate 100 and the like is formed in a central portion of the second non-display area PA2.

[0121] In an embodiment, the metal layer M may be removed by irradiating the laser light L in the depth direction of the substrate 100. When the metal layer M is removed from the substrate 100 by heating the metal layer M due to the irradiation of the laser light L, the intermediate layer 320 stacked on the metal layer M or some layers included in the intermediate layer 320, the counter electrode 330, the capping layer 160, and the protective layer 170 may be separated from the substrate 100 together with the metal layer M. Therefore, the organic film and the like included in the intermediate layer 320 may not be continuously formed from the display area DA to the through portion H.

[0122] The metal layer M and the planarization layer 140 may be formed to be separated from each other, and some layers included in the intermediate layer 320 may contact the inorganic layer directly below the metal layer M in the gap between the metal layer M and the planarization layer 140. Therefore, because some layers included in the intermediate layer 320 and the like have steps due to the metal layer M and stress may concentrate on the steps, only the region corresponding to the metal layer M may be easily separated during the removal of the metal layer M. Therefore, during the removal of the metal layer M, some of the intermediate layer 320 may be prevented or substantially prevented from being peeled off from the side surfaces of the planarization layer 140 or the second inner dam 720 along the side surfaces of the planarization layer 140 or the second inner dam 720.

[0123] After the metal layer M is removed, a first inorganic encapsulating layer 510 , an organic encapsulating layer 520 , and a second inorganic encapsulating layer 530 are sequentially formed, and a through portion H is formed in the second non-display area PA2 .

[0124] The first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 are formed in the display area DA and the second non-display area PA2. In contrast, the organic encapsulation layer 520 is formed to a limited extent due to the first internal dam 710 and the second internal dam 720. Therefore, in the second non-display area PA2, the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 are in direct contact with each other on the outer portion of the planarization layer 140.

[0125] The through portion H is formed by vertically penetrating the substrate 100 and the first and second inorganic insulating layers 120 and 130, the first and second inorganic encapsulating layers 510 and 530 stacked on the substrate 100. Therefore, the moat area MA may be defined as an area excluding the through portion H from an area where the metal layer M is removed in the second non-display area PA2.

[0126] Due to the removal of the metal layer M, the first inorganic encapsulation layer 510 can directly contact another inorganic layer thereunder in the moat area MA. For example, the first inorganic encapsulation layer 510 can directly contact the second inorganic insulating layer 130, and thus, moisture or the like can be effectively prevented from penetrating into the display area DA from the side profile of the through-portion H. Therefore, compared with the comparative example in which a groove is formed around the through-portion H in the depth direction of the substrate 100 to prevent moisture penetration, the display device ( Figure 1 The manufacturing process of 10) can be simplified.

[0127] Figure 11 It is shown that the first inorganic encapsulation layer 510 directly contacts the second inorganic insulation layer 130 in the moat area MA, but one or more embodiments are not limited thereto, and as Figure 6 and Figure 7 As shown in FIG, the first inorganic encapsulation layer 510 may directly contact the first inorganic insulating layer 120 or the substrate 100 in the moat area MA by disposing the region where the first inorganic insulating layer 120 and the second inorganic insulating layer 130 are formed.

[0128] According to one or more disclosed embodiments, in a display device, by making a through portion (in which a separate component such as a camera is provided) directly contact the first inorganic layer and the second inorganic layer of the encapsulation layer in an area surrounding the through portion, and by making the first inorganic layer directly contact another inorganic layer thereunder, the non-display area can be reduced and penetration of external moisture or the like through the through portion can be prevented or substantially prevented. However, the scope of the disclosure is not limited to these aspects or effects.

[0129] It will be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A display device, comprising: A substrate including a display area and a first non-display area outside the display area, wherein a plurality of thin film transistors and a plurality of display devices electrically connected to the plurality of thin film transistors are arranged in the display area; a through portion penetrating the substrate in a vertical direction; a second non-display area between the through portion and the display area; as well as an encapsulation layer on the plurality of display devices and comprising a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer extend to the through portion and directly contact each other in the second non-display area, and the first inorganic encapsulation layer directly contacts another inorganic layer below the first inorganic encapsulation layer in the second non-display area, and The entire portion where the first inorganic encapsulating layer and the another inorganic layer contact each other is continuous and flat.

2. The display device according to claim 1, wherein The first inorganic encapsulation layer directly contacts an upper surface of the substrate in the second non-display area.

3. The display device according to claim 2, wherein The substrate includes a first base layer, a first barrier layer, a second base layer, and a second barrier layer sequentially stacked, and The first inorganic encapsulating layer directly contacts the second barrier layer in the second non-display area.

4. The display device according to claim 1, further comprising: a first inorganic insulating layer between the semiconductor layer and the gate electrode of each of the plurality of thin film transistors; and a second inorganic insulating layer between the gate electrode and the source electrode of each of the plurality of thin film transistors and between the gate electrode and the drain electrode of each of the plurality of thin film transistors, The other inorganic layer directly contacting the first inorganic encapsulation layer in the second non-display area includes the first inorganic insulating layer or the second inorganic insulating layer.

5. The display device according to claim 4, further comprising a planarization layer between the plurality of thin film transistors and the plurality of display devices. in, The planarization layer extends to a portion of the second non-display area. The display device according to claim 5 , wherein: Each of the plurality of display devices includes: a pixel electrode on the planarization layer; a counter electrode on the pixel electrode; and an intermediate layer between the pixel electrode and the counter electrode, and At least some of the intermediate layers and the counter electrode extend outside the planarization layer.

7. The display device according to claim 5, wherein In the second non-display area, a first inner dam around the through portion is disposed on the planarization layer, and The organic encapsulation layer is located outside the region partitioned by the first inner dam.

8. The display device according to claim 7, further comprising a pixel defining layer on the planarization layer and covering edges of the pixel electrodes of the plurality of display devices. in, The first inner dam includes the same material as the pixel defining layer. 9 . The display device according to claim 7 , further comprising a second internal dam surrounding the through portion in the second non-display area at a position spaced apart from the first internal dam, the second internal dam being on the planarization layer.

10. The display device according to claim 7 further comprises a plurality of data lines, the plurality of data lines are in the second non-display area and arranged on the second inorganic insulating layer, the planarization layer covers the plurality of data lines, and the first internal dam overlaps with at least some of the plurality of data lines.

11. A method for manufacturing a display device, the display device comprising a display area, a first non-display area surrounding the display area, and a second non-display area at least partially surrounded by the display area, the method comprising: In the display area, a plurality of thin film transistors are formed on a substrate, a planarization layer covers the plurality of thin film transistors, and a plurality of pixel electrodes are on the planarization layer and electrically connected to the plurality of thin film transistors; forming a metal layer in the second non-display area; forming an intermediate layer and a counter electrode on the plurality of pixel electrodes; removing the metal layer from the substrate; sequentially forming a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer on the counter electrode; as well as forming a through portion penetrating the substrate in a central portion of the second non-display area, wherein at least some of the layers in the intermediate layer and the counter electrode extend from the display area to the second non-display area and are formed on the metal layer, and the at least some of the layers in the intermediate layer and the counter electrode formed on the metal layer are separated from the substrate by removing the metal layer.

12. The manufacturing method according to claim 11, wherein: The metal layer is formed in parallel with the plurality of pixel electrodes.

13. The manufacturing method according to claim 11, wherein: Each of the plurality of thin film transistors includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and The metal layer is formed in parallel with the semiconductor layer, the metal layer is formed in parallel with the gate electrode, or the metal layer is formed in parallel with the source electrode and the drain electrode.

14. The manufacturing method according to claim 11, wherein: the first inorganic encapsulating layer and the second inorganic encapsulating layer are in direct contact with each other in a region from which the metal layer is removed, the first inorganic encapsulating layer directly contacts another inorganic layer arranged below the first inorganic encapsulating layer in the region from which the metal layer is removed, The through portion is formed by penetrating the substrate, the first inorganic encapsulating layer, the second inorganic encapsulating layer, and the another inorganic layer.

15. The manufacturing method according to claim 14, wherein: A first inorganic insulating layer and a second inorganic insulating layer extend to a portion of the second non-display area, the first inorganic insulating layer being between the semiconductor layer and the gate electrode of each of the plurality of thin film transistors, the second inorganic insulating layer being between the gate electrode and the source electrode of each of the plurality of thin film transistors, and between the gate electrode and the drain electrode of each of the plurality of thin film transistors, and The metal layer is formed on the first inorganic insulating layer or the second inorganic insulating layer.

16. The manufacturing method according to claim 14, wherein: The substrate includes a first base layer, a first barrier layer, a second base layer, and a second barrier layer sequentially stacked, and The first inorganic encapsulating layer directly contacts the second barrier layer in the region from which the metal layer is removed.

17. The manufacturing method according to claim 14, further comprising forming a pixel defining layer on the planarization layer to cover edges of the plurality of pixel electrodes, in, The planarization layer extends to a portion of the second non-display area to be spaced a distance from the metal layer, and In the second non-display area, a first inner dam including the same material as the pixel defining layer is formed on the planarization layer.

18. The manufacturing method according to claim 17, wherein: The first internal dam surrounds the through portion, and The organic encapsulation layer is located outside the region partitioned by the first inner dam. 19 . The manufacturing method of claim 18 , further comprising forming a plurality of data lines in the second non-display area and covered by the planarization layer, and forming the first internal dam to overlap at least some of the plurality of data lines.

20. The manufacturing method according to claim 17, wherein: At least one of the intermediate layers contacts another inorganic layer disposed under the first inorganic encapsulating layer in a gap between the metal layer and the planarization layer.

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