Semiconductor device with buried gate structure and method for manufacturing the same

Abstract

Disclosed are a semiconductor device for improving gate induced drain leakage and a method for manufacturing the same. The semiconductor device comprises: a substrate; a first doped region and a second doped region, which are formed to be separated from each other by a trench in the substrate; a first gate dielectric layer above the trench; a lower gate above the first gate dielectric layer; an upper gate above the lower gate and having a width smaller than the lower gate; and a second gate dielectric layer between the upper gate and the first gate dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0071525, filed on Jun. 17, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments relate to a semiconductor device, and more particularly, to a semiconductor device having a buried gate structure and a method for manufacturing the same. Background Art

[0004] Generally, metal gate electrodes can be applied to high-performance transistors. In particular, buried gate type transistors require control of threshold voltage for high-performance operation. In addition, gate induced drain leakage (GIDL) characteristics greatly affect the performance of buried gate type transistors. Summary of the invention

[0005] Exemplary embodiments of the present invention are directed to a semiconductor device including a novel transistor structure that reduces gate induced drain leakage (GIDL) and a method of manufacturing the same.

[0006] According to an embodiment of the present invention, a semiconductor device may include: a substrate; a first doped region and a second doped region, the two being formed to be separated from each other by a groove in the substrate; a first gate dielectric layer above the groove; a lower gate above the first gate dielectric layer; an upper gate above the lower gate and having a width smaller than the lower gate; and a second gate dielectric layer between the upper gate and the first gate dielectric layer.

[0007] According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include: forming a trench in a substrate; forming a first gate dielectric layer above the trench; forming a lower gate above the first gate dielectric layer; forming a second gate dielectric layer covering the first gate dielectric layer; and forming an upper gate above the second gate dielectric layer and the lower gate.

[0008] These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

[0010] Figure 2A is shown along Figure 1 The cross-sectional view of the semiconductor device taken along line AA' is shown.

[0011] Figure 2B is shown along Figure 1 The cross-sectional view of the semiconductor device is taken along line BB'.

[0012] Figure 3 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0013] FIG. 4A to FIG. 4J is a cross-sectional view illustrating a method of forming a semiconductor device according to an embodiment of the present invention.

[0014] Figure 5 is a cross-sectional view illustrating damage of a gate dielectric layer due to fluorine according to a comparative example.

[0015] FIG. 6A to FIG. 6D is a cross-sectional view illustrating another method for forming a semiconductor device.

[0016] FIG. 7A to FIG. 7D is a cross-sectional view illustrating still another method for forming a semiconductor device.

[0017] FIG. 8A to FIG. 8D is a cross-sectional view illustrating still another method for forming a semiconductor device.

[0018] Fig. 9 is a cross-sectional view showing a memory cell. DETAILED DESCRIPTION

[0019] The exemplary embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams as ideal schematic views of the present invention. Therefore, the structure of the drawings may be modified according to manufacturing techniques and / or tolerances. Embodiments of the present invention are not limited to the specific structures shown in the drawings, but may include any changes in the structure that may be produced according to the manufacturing process. Therefore, the shapes of the regions and regions shown in the drawings are intended to illustrate the specific structures of the regions of the elements, and are not intended to limit the scope of the present invention.

[0020] In the following, in the present embodiment, the threshold voltage Vt depends on the flat band voltage VFB. The flat band voltage VFB depends on the work function. The work function can be designed by various methods. For example, the work function can be adjusted by the material of the gate electrode, the material between the gate electrode and the channel, etc. By increasing or decreasing the work function, the flat band voltage can be shifted. A high work function can shift the flat band voltage in a positive direction, while a low work function can shift the flat band voltage in a negative direction. As described above, the threshold voltage can be adjusted by shifting the flat band voltage. In an embodiment, the threshold voltage can be adjusted by shifting the flat band voltage even if the channel concentration is reduced or the channel doping is ignored. In particular, the flat band voltage can be reduced by a low work function material or a dipole, thereby improving gate induced drain leakage (GIDL).

[0021] In the following, in the present embodiment, a buried gate structure may be located in a trench. The buried gate structure may include a gate dielectric layer and a gate electrode. The gate dielectric layer may cover the surface of the trench, and the gate electrode may partially fill the trench on the gate dielectric layer. Therefore, the gate electrode may be referred to as a "buried gate electrode". The gate electrode may include a lower buried portion LB and an upper buried portion UB. The lower buried portion LB may fill the lower portion of the trench, and the upper buried portion UB may fill the upper portion of the trench on the lower buried portion LB. In this way, the gate electrode may be a dual gate electrode having an upper buried portion UB located on the lower buried portion LB. The lower buried portion LB may overlap with the channel, and the upper buried portion UB may overlap with the first doped region and the second doped region (i.e., the source / drain region).

[0022] Figure 1 is a plan view showing a semiconductor device 100 according to an embodiment of the present invention. Figure 2A It is shown along Figure 1 The cross-sectional view of the semiconductor device 100 is taken along line AA′. Figure 2B It is shown along Figure 1 The cross-sectional view of the semiconductor device 100 is taken along line BB′.

[0023] refer to Figures 1 to 2B , the semiconductor device 100 may include a buried gate structure 100G, a first doping region 113, and a second doping region 114. An isolation layer 102 and an active region 104 may be formed in a substrate 101. The first doping region 113 and the second doping region 114 may be formed in the active region 104. A trench 105 may be formed to pass through the active region 104 and the isolation layer 102. The buried gate structure 100G may be formed in the trench 105. A channel CH may be formed between the first doping region 113 and the second doping region 114 next to the buried gate structure 100G. The channel CH may be defined along the contour of the trench 105. The semiconductor device 100 may be a part of a memory cell. For example, the semiconductor device 100 may be a cell transistor of a DRAM.

[0024] The semiconductor device 100 may include: a substrate 101; a first doping region 113 and a second doping region 114 formed to be spaced apart from each other by a trench 105 in the substrate 101; a first gate dielectric layer 106L conformally formed in the trench 105 to cover the bottom and sidewall surfaces of the trench 105; a lower buried portion LB formed on the first gate dielectric layer 106L to fill the lower portion of the trench 105 not filled by the first gate dielectric layer 106L; an upper buried portion UB having a width smaller than the lower buried portion LB and may be formed on the lower buried portion LB; and a second gate dielectric layer 106U formed between the upper buried portion UB and the first gate dielectric layer 106L. The first gate dielectric layer 106L may include an extension portion 106E, and the second gate dielectric layer 106U may be located between the upper buried portion UB and the extension portion 106E of the first gate dielectric layer 106L. The second gate dielectric layer 106U may be conformally formed on the first gate dielectric layer 106L and may extend to cover the entire range of the sidewall surface of the trench 105 not covered by the lower buried portion LB. The upper buried portion UB may be formed on the second gate dielectric layer 106U to fill the open space remaining in the trench 105, but the upper buried portion UB may have a top surface located lower than the top surface of the substrate 101. The top surfaces of the first gate dielectric layer 106L and the second gate dielectric layer 106U may be at the same level as the top surface of the substrate 101. The space of the trench 105 not filled by the upper buried portion UB may be filled by the capping layer 112.

[0025] The semiconductor device 100 may be formed on a substrate 101. The substrate 101 may be any material suitable for semiconductor processes. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of a silicon-containing material. The substrate 101 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 101 may include another semiconductor material, such as germanium. The substrate 101 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0026] An isolation layer 102 and an active region 104 may be formed in a substrate 101. The active region 104 may be defined by the isolation layer 102. The isolation layer 102 may be a shallow trench isolation (STI) region formed by trench etching. The isolation layer 102 may be formed by filling a shallow trench (e.g., isolation trench 103) with a dielectric material. The isolation layer 102 may include silicon oxide, silicon nitride, or a combination thereof.

[0027] The trench 105 is a space in which the buried gate structure 100G may be formed. The trench 105 may also be referred to as a “gate trench”. The trench 105 may be formed in the substrate 101. Figure 1 , the trench 105 may have a line shape extending in any direction. The trench 105 may have a line shape crossing the active region 104 and the isolation layer 102. The trench 105 may have a shallower depth than the isolation trench 103. Figures 1 to 2B As shown in the embodiment of FIG. 1 , the bottom of the groove 105 may be flat, however, in some embodiments, the bottom of the groove 105 may be curved. In some embodiments, the lower portion of the groove 105 may have a curvature.

[0028] The first doping region 113 and the second doping region 114 may be formed in the active region 104. The first doping region 113 and the second doping region 114 are regions doped with conductive dopants. For example, the conductive dopant may include at least one of phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first doping region 113 and the second doping region 114 may be doped with dopants of the same conductivity type. The first doping region 113 and the second doping region 114 may be doped with the same conductive dopant. The first doping region 113 and the second doping region 114 may be located in the active region 104 on both sides of the trench 105. The bottom surfaces of the first doping region 113 and the second doping region 114 may be located at a predetermined depth from the top surface of the active region 104. The first doping region 113 and the second doping region 114 may contact the sidewall surface of the trench 105. The bottom surfaces of the first doping region 113 and the second doping region 114 may be higher than the bottom surface of the trench 105. The first doping region 113 may be referred to as a “first source / drain region”, and the second doping region 114 may be referred to as a “second source / drain region”.

[0029] The trench 105 may include a first trench T1 and a second trench T2. The first trench T1 may be formed in the active region 104. The second trench T2 may be formed in the isolation layer 102. The trench 105 may have a shape extending continuously from the first trench T1 to the second trench T2. In the trench 105, the bottom surface of the first trench T1 and the bottom surface of the second trench T2 may be located at different levels. For example, the bottom surface of the first trench T1 may be located at a higher level than the bottom surface of the second trench T2. When the isolation layer 102 is recessed, a height difference between the first groove T1 and the second groove T2 may be formed. Therefore, the second trench T2 may include a recessed region R, the bottom surface of which is lower than the bottom surface of the first trench T1. Due to the step height between the bottom surfaces of the first trench T1 and the second trench T2, a fin region 104F may be formed in the active region 104. Therefore, the active region 104 may include a fin region 104F.

[0030] As described above, the fin region 104F may be formed below the first trench T1, and the sidewall surface of the fin region 104F is exposed by the recessed isolation layer 102F. The fin region 104F is a region in which a portion of the channel CH may be formed. The fin region 104F is referred to as a "saddle fin". The fin region 104F may increase the channel width and improve electrical characteristics.

[0031] In some embodiments, the fin region 104F may be omitted.

[0032] The buried gate structure 100G may be embedded in the trench 105. The buried gate structure 100G may be disposed in the active region 104 between the first doping region 113 and the second doping region 114, and extend into the isolation layer 102. In the buried gate structure 100G, a bottom surface of a portion disposed in the active region 104 and a bottom surface of a portion disposed in the isolation layer 102 may be located at different heights. When the fin region 104F is omitted, a bottom surface of a portion disposed in the active region 104 and a bottom surface of a portion disposed in the isolation layer 102 may be located at the same height.

[0033] The buried gate structure 100G may include a first gate dielectric layer 106L, a lower buried portion LB, an upper buried portion UB, a second gate dielectric layer 106U, and a capping layer 112 .

[0034] The first gate dielectric layer 106L may be conformally formed on the bottom surface and the sidewall surface of the trench 105. The first gate dielectric layer 106L may include silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The high-k material may include a material having a higher dielectric constant than silicon oxide. For example, the high-k material may include any suitable material with a dielectric constant higher than 3.9. In some embodiments, the high-k material may include any suitable material with a dielectric constant higher than 10. In some embodiments, the high-k material may include any suitable material with a dielectric constant ranging from 10 to 30. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other high-k materials may also be selectively used as the high-k material. The first gate dielectric layer 106L may include a metal oxide. The first gate dielectric layer 106L may have a shape surrounding a bottom surface and sidewall surfaces of the lower buried portion LB. The first gate dielectric layer 106L may be located between the channel CH and the lower buried portion LB.

[0035] The first gate dielectric layer 106L may include an extension portion 106E, and the extension portion 106E may contact the first doping region 113 and the second doping region 114 .

[0036] The top surface of the lower buried portion LB may be located at a level lower than the top surface of the active area 104. The lower buried portion LB may fill the lower portion of the trench 105. The lower buried portion LB may be a low resistance material for reducing the gate film resistance. The lower buried portion LB may be a metal-based material. The lower buried portion LB may include a metal, a metal nitride, or a combination thereof. The lower buried portion LB may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof. The lower buried portion LB may be formed only of titanium nitride. In addition, the lower buried portion LB may be formed by a stack of titanium nitride (TiN) and tungsten (W) (i.e., TiN / W).

[0037] In some embodiments, the lower buried portion LB may have a high work function. A high work function refers to a work function higher than the mid-bandgap work function of silicon. A low work function refers to a work function lower than the mid-bandgap work function of silicon. Specifically, the high work function may be higher than 4.5 eV, and the low work function may be lower than 4.5 eV. The lower buried portion LB may include P-type polysilicon.

[0038] In some embodiments, the lower buried portion LB may have an increased high work function. The lower buried portion LB may include metal silicon nitride. The metal silicon nitride may be a metal nitride doped with silicon. The lower buried portion LB may include a metal silicon nitride having an adjusted silicon atomic percentage. For example, the lower buried portion LB may include tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function and contain silicon to further improve its work function. Silicon titanium nitride may have an adjusted silicon atomic percentage, thereby having an increased high work function. In order to have an increased high work function, the atomic percentage (at%) of silicon in silicon titanium nitride may be equal to or less than 21at%. As a comparative example, in order to have a low work function, the atomic percentage (at%) of silicon in silicon titanium nitride may be equal to or greater than 30at%.

[0039] The upper buried portion UB may be formed on the lower buried portion LB, and a top surface of the upper buried portion UB may be located at a lower level than a top surface of the active region 104. The upper buried portion UB may partially fill an upper portion of the trench 105. The upper buried portion UB and the lower buried portion LB may be made of the same material or different materials.

[0040] The upper buried portion UB may be a low resistance material for reducing the gate film resistance. The upper buried portion UB may be a metal-based material. The upper buried portion UB may include a metal, a metal nitride, or a combination thereof. The upper buried portion UB may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof. The upper buried portion UB may be formed only of titanium nitride. In addition, the upper buried portion UB may be formed by a stack of titanium nitride (TiN) and tungsten (W) (i.e., TiN / W). In some embodiments, each of the lower buried portion LB and the upper buried portion UB may be formed only of titanium nitride. In addition, each of the lower buried portion LB and the upper buried portion UB may be formed by a stack of titanium nitride (TiN) and tungsten (W) (i.e., TiN / W). The width of the upper buried portion UB may be less than the width of the lower buried portion LB, so the volume occupied by the lower buried portion LB in the trench 105 may be larger. The lower buried portion LB and the upper buried portion UB may have the same height or different heights.

[0041] In some embodiments, the upper buried portion UB may have a low work function. The upper buried portion UB may include N-type polysilicon. In some embodiments, the lower buried portion LB may be P-type polysilicon, and the upper buried portion UB may be N-type polysilicon. In some embodiments, the lower buried portion LB may be formed of a stack of titanium nitride and tungsten (TiN / W), and the upper buried portion UB may be N-type polysilicon.

[0042] The capping layer 112 may be used to protect the upper buried portion UB. The capping layer 112 may fill the upper portion of the trench 105 above the upper buried portion UB. The top surface of the capping layer 112 may be located at the same level as the top surfaces of the first doping region 113 and the second doping region 114. For example, the capping layer 112 may include a dielectric material. In some embodiments, the capping layer 112 may include silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the capping layer 112 may include a combination of silicon nitride and silicon oxide. In some embodiments, the capping layer 112 may include a silicon nitride liner and a spin-on dielectric (SOD) material.

[0043] The second gate dielectric layer 106U may be formed between the extension portion 106E of the first gate dielectric layer 106L and the upper buried portion UB. The first gate dielectric layer 106L and the second gate dielectric layer 106U may be made of the same material. The second gate dielectric layer 106U may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The first gate dielectric layer 106L and the second gate dielectric layer 106U may have the same thickness. In some embodiments, the thickness of the second gate dielectric layer 106U may be less than the thickness of the first gate dielectric layer 106L. The bottom of the second gate dielectric layer 106U may contact the lower buried portion LB. More specifically, as Figure 2A As shown in the embodiment of FIG. 1 , the bottom of the second gate dielectric layer 106U may contact the top surface of the edge of the lower buried portion LB that is not covered by the upper buried portion UB.

[0044] The extension portion 106E of the first gate dielectric layer 106L and the second gate dielectric layer 106U may form a dual gate dielectric structure 107. The dual gate dielectric structure 107 may have a greater thickness than the first gate dielectric layer 106L. The dual gate dielectric structure 107 may be located between the upper buried portion UB and the first doped region 113 and the second doped region 114. The total thickness of the first gate dielectric layer 106L and the second gate dielectric layer 106U may be greater than the thickness of the first gate dielectric layer 106L.

[0045] The trench 105 may include a bottom surface 105B, a lower sidewall surface 105L, and an upper sidewall surface 105U. The bottom surface 105B and the lower sidewall surface 105L of the trench 105 may be covered by a single gate dielectric structure of a first gate dielectric layer 106L. The upper sidewall surface 105U of the trench 105 may be covered by a dual gate dielectric structure 107 (i.e., an extension portion 106E of the first gate dielectric layer 106L and the second gate dielectric layer 106U).

[0046] As described above, in some embodiments, GIDL can be improved by the dual gate dielectric structure 107. In addition, in some embodiments, GIDL can be improved by the upper buried portion UB having a low work function. In some preferred embodiments, GIDL can be improved by both the dual gate dielectric structure 107 and by selecting the material of the upper buried portion UB to have a low work function.

[0047] Figure 3 2 is a cross-sectional view showing a semiconductor device 200 according to an embodiment of the present invention. In addition to the configuration of the buried gate structure 200G, Figure 3 The configuration of the semiconductor device 200 shown in FIG. 2 may be similar to that of Figure 2AThe configuration of the semiconductor device 100 shown in FIG.

[0048] refer to Figure 3 , the semiconductor device 200 may include a buried gate structure 200G, a first doping region 113, and a second doping region 114. An isolation layer 102 and an active region 104 may be formed in the substrate 101. The first doping region 113 and the second doping region 113 may be formed in the active region 104. A trench 105 passing through the active region 104 and the isolation layer 102 may be formed. The buried gate structure 200G may be embedded in the trench 105. A channel CH may be formed between the first doping region 113 and the second doping region 114 next to the buried gate structure 200G. The channel CH may be defined along the outline of the trench 105. The semiconductor device 200 may be a part of a memory cell. For example, the semiconductor device 200 may be a cell transistor of a DRAM.

[0049] The buried gate structure 200G may be embedded in the trench 105. The buried gate structure 200G may extend into the isolation layer 102 while being disposed in the active region 104 between the first doping region 113 and the second doping region 114. The fin region 104F may be located in the active region 104 below the buried gate structure 200G.

[0050] The buried gate structure 200G may include a first gate dielectric layer 106L, a lower buried portion LB, an upper buried portion UB, a second gate dielectric layer 106U, and a capping layer 112. The lower buried portion LB may include a first barrier layer 108 and a first gate electrode 109, and the upper buried portion UB may include a second barrier layer 110 and a second gate electrode 111.

[0051] The first gate dielectric layer 106L may be conformally formed on the bottom surface and the sidewall surface of the trench 105. The first gate dielectric layer 106L may include silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The high-k material may include a material having a higher dielectric constant than silicon oxide. For example, the high-k material may include any suitable material with a dielectric constant higher than 3.9. In some embodiments, the high-k material may include any suitable material with a dielectric constant higher than 10. In some embodiments, the high-k material may include any suitable material with a dielectric constant ranging from 10 to 30. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other well-known high-k materials may also be selectively used as the high-k material. The first gate dielectric layer 106L may include a metal oxide. The first gate dielectric layer 106L may have a shape surrounding a bottom surface and sidewall surfaces of the lower buried portion LB. The first gate dielectric layer 106L may be located between the channel CH and the lower buried portion LB.

[0052] The first gate dielectric layer 106L may include an extension portion 106E, and the extension portion 106E may contact the first doping region 113 and the second doping region 114 .

[0053] The first barrier layer 108 may be conformally formed on the first gate dielectric layer 106L. The first gate electrode 109 may be formed on the first barrier layer 108 to fill the space of the trench that is not filled by the first barrier layer 108 and the first gate dielectric layer 106L. The top surfaces of the first barrier layer 108 and the first gate electrode 109 may be located at a level lower than the top surface of the active region 104. The top surfaces of the first barrier layer 108 and the first gate electrode 109 may be located at the same level. The top surfaces of the first barrier layer 108 and the first gate electrode 109 may be located at the same level as the bottom surfaces of the first doping region 113 and the second doping region 114. The first barrier layer 108 and the first gate electrode 109 may fill the lower portion of the trench 105. The first barrier layer 108 and the first gate electrode 109 may preferably be made of different low-resistance materials. In some embodiments, the first barrier layer 108 and the first gate electrode 109 may be made of different metal-based materials.

[0054] In some embodiments, the first barrier layer 108 may include a metal nitride. The first barrier layer 108 may be formed of tantalum nitride (TaN) or titanium nitride (TiN). In some embodiments, the first barrier layer 108 may have a high work function. A high work function refers to a work function higher than the mid-bandgap work function of silicon. A low work function refers to a work function lower than the mid-bandgap work function of silicon. Specifically, a high work function may be higher than 4.5 eV, and a low work function may be lower than 4.5 eV.

[0055] The first barrier layer 108 may have an increased high work function. For example, the first barrier layer 108 may include metal silicon nitride. The metal silicon nitride may be a metal nitride doped with silicon. The first barrier layer 108 may be a metal silicon nitride with an adjusted silicon atomic percentage. For example, the first barrier layer 108 may be tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function and contain silicon to further increase its work function. Titanium silicon nitride may have an adjusted silicon atomic percentage, thereby having an increased high work function. In order to have an increased high work function, the atomic percentage (at%) of silicon in the titanium silicon nitride may be equal to or less than 21 at%. As a comparative example, in order to have a low work function, the atomic percentage (at%) of silicon in the titanium silicon nitride may be equal to or greater than 30 at%.

[0056] The first gate electrode 109 may include a metal or a metal nitride. The first gate electrode 109 may include tungsten or titanium nitride. When tungsten is used as the first gate electrode 109, the first gate dielectric layer 106L may be damaged by the process of forming the first gate electrode 109. For example, tungsten hexafluoride (WF6) gas may be used to deposit the tungsten layer, and the first gate dielectric layer 106L may be corroded by fluorine. In order to prevent fluorine from corroding the first gate dielectric layer 106L, the present invention adopts a first barrier layer 108, which may be formed between the first gate 109 and the first gate dielectric layer 106L. For example, in a preferred embodiment, the first gate electrode 109 may be formed of tungsten (W), and the first barrier layer 108 may be formed of titanium nitride (TiN) resistant to fluorine corrosion. The lower buried portion LB may include a stack of TiN / W.

[0057] The second barrier layer 110 may be formed on the first gate electrode 109. The second barrier layer 110 may be formed between the first gate electrode 109 and the second gate electrode 111. The first barrier layer 108 and the second barrier layer 110 may be made of the same or different materials. The second barrier layer 110 may include a metal nitride. The second barrier layer 110 may be formed of tantalum nitride (TaN) or titanium nitride (TiN). As described below, the second barrier layer 110 may be formed by a deposition process such as physical vapor deposition or by a plasma treatment such as plasma nitridation.

[0058] The second gate electrode 111 may be formed on the second barrier layer 110. A top surface of the second gate electrode 111 may be located at a level lower than a top surface of the active region 104. The second barrier layer 110 and the second gate electrode 111 may partially fill an upper portion of the trench 105. The second gate electrode 111 may include a low work function material. The second gate electrode 111 may include polysilicon having a low work function, for example, polysilicon doped with N-type impurities.

[0059] The capping layer 112 may be used to protect the second gate electrode 111. The capping layer 112 may fill the upper portion of the trench 105 above the second gate electrode 111. For example, the capping layer 112 may include a dielectric material. In some embodiments, the capping layer 112 may include silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the capping layer 112 may include a combination of silicon nitride and silicon oxide. The capping layer 112 may include a silicon nitride liner and a spin-on dielectric (SOD) material.

[0060] The second gate dielectric layer 106U may be formed between the extension portion 106E of the first gate dielectric layer 106L and the second gate electrode 111. The first gate dielectric layer 106L and the second gate dielectric layer 106U may be made of the same material. The second gate dielectric layer 106U may include silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The first gate dielectric layer 106L and the second gate dielectric layer 106U may have the same thickness. In some embodiments, the thickness of the second gate dielectric layer 106U may be less than the thickness of the first gate dielectric layer 106L. The bottom of the second gate dielectric layer 106U may contact the first barrier layer 108 and the second barrier layer 110. Specifically, the bottom surface of the second gate dielectric layer 106U may contact the top surface of the edge of the first barrier layer 108. The side surface of the bottom of the second gate dielectric layer 106U may contact the surface of the edge of the second barrier layer 110.

[0061] The extension portion 106E of the first gate dielectric layer 106L and the second gate dielectric layer 106U may form a double gate dielectric structure 107. The double gate dielectric structure 107 may have a greater thickness than the first gate dielectric layer 106L. The double gate dielectric structure 107 may be located between the second gate electrode 111 and the first doped region 113 and the second doped region 114.

[0062] The trench 105 may include a bottom surface 105B, a lower sidewall surface 105L, and an upper sidewall surface 105U. The bottom surface 105B and the lower sidewall surface 105L of the trench 105 may be covered by a single gate dielectric structure of a first gate dielectric layer 106L. The upper sidewall surface 105U of the trench 105 may be covered by a dual gate dielectric structure 107 (i.e., an extension portion 106E of the first gate dielectric layer 106L and the second gate dielectric layer 106U).

[0063] As described above, in some embodiments, GIDL can be improved by the dual gate dielectric structure 107. In addition, in some embodiments, GIDL can be improved by the second gate electrode 111 having a low work function. In some preferred embodiments, GIDL can be improved by both the dual gate dielectric structure 107 and by selecting the material of the second gate electrode 111 to have a low work function.

[0064] FIG. 4A to FIG. 4J is a cross-sectional view illustrating a method of forming a semiconductor device according to an embodiment of the present invention. FIG. 4A to FIG. 4J Shown is the method for forming Figure 3 The method of the semiconductor device 200 shown in FIG.

[0065] like Figure 4A As shown, an isolation layer 12 can be formed in the substrate 11. The active area 14 is defined by the isolation layer 12. The isolation layer 12 can be formed by a shallow trench isolation (STI) process. For example, an isolation trench 13 can be formed by etching the substrate 11. The isolation trench 13 is filled with a dielectric material, and thus the isolation layer 12 can be formed. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. The isolation trench 13 may be filled with a dielectric material by a chemical vapor deposition (CVD) process or another deposition process. In addition, a planarization process such as chemical mechanical polishing (CMP) may be additionally performed.

[0066] Then, a plurality of trenches 15 may be formed in the substrate 11. Each trench 15 may have a linear shape passing through the active region 14 and the isolation layer 12. The trenches 15 may be formed by an etching process to the substrate 11 using a hard mask layer 16 as an etching mask. The hard mask layer 16 may be formed on the substrate 11 and have a linear opening. The hard mask layer 16 may be formed of a material having an etching selectivity to the substrate 11. The hard mask layer 16 may be a silicon oxide, such as tetraethyl orthosilicate (TEOS). The trenches 15 may be formed to be shallower than the isolation trenches 13. The trenches 15 may be deep enough to form a large average cross-sectional area of ​​a gate electrode to be formed subsequently. In this way, the resistance of the gate electrode may be reduced. In some embodiments, the bottom edge of the trench 15 may have a curvature.

[0067] Subsequently, the fin region 14F may be formed. The fin region 14F may be formed by selectively recessing the isolation layer 12 below each trench 15. The structure of the fin region 14F may refer to Figure 2B The fin region 104F.

[0068] refer to Figure 4B , a first gate dielectric layer 17 may be formed on the surface of each trench 15. Before the first gate dielectric layer 17 may be formed, the inner surface of each trench 15 damaged by the etching process may be restored. For example, a sacrificial oxide may be formed by a thermal oxidation process and then the sacrificial oxide may be removed.

[0069] For example, the first gate dielectric layer 17 may be formed by a thermal oxidation process. The first gate dielectric layer 17 may include silicon oxide.

[0070] In some embodiments, the first gate dielectric layer 17 may be formed by a deposition process such as a CVD process or an atomic layer deposition (ALD) process. The first gate dielectric layer 17 that may be formed by a deposition process may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other well-known high-k materials may also be selectively used as the high-k material. The first gate dielectric layer 17 may include a material having a high oxygen atom density.

[0071] The first barrier material 18A may be formed on the first gate dielectric layer 17 and the hard mask layer 16. The first barrier material 18A may be conformally formed on the surface of the first gate dielectric layer 17. The first barrier material 18A may include a metal-based material. The first barrier material 18A may include a metal nitride. The first barrier material 18A may include titanium nitride or tantalum nitride. The first barrier material 18A may be formed by an ALD or CVD process.

[0072] The first conductive layer 19A may be formed on the first barrier material 18A. The first conductive layer 19A may be formed on the first barrier material 18A to fill each trench 15. The first conductive layer 19A includes a low-resistance metal material. The first conductive layer 19A may include tungsten. The first conductive layer 19A may be formed by a CVD or ALD process.

[0073] like Figure 4CAs shown, a first barrier layer 18 and a first gate electrode 19 may be formed inside each trench 15. In order to form the first barrier layer 18 and the first gate electrode 19, a recess process may be performed. The recess process may be performed by a dry etching process (e.g., an etch-back process). The first barrier layer 18 may be formed by performing an etch-back process on the first barrier material 18A. The first gate electrode 19 may be formed by performing an etch-back process on the first conductive layer 19A. In some embodiments, a planarization process may be performed in advance to expose the top surface of the hard mask layer 16, and then an etch-back process of the recess process may be performed. The top surfaces of the first barrier layer 18 and the first gate electrode 19 may be located at the same level.

[0074] Top surfaces of the first barrier layer 18 and the first gate electrode 19 may be recessed to a level lower than a top surface of the active region 14. The first barrier layer 18 and the first gate electrode 19 may be abbreviated as a 'lower buried portion LB'.

[0075] After forming the first barrier layer 18 and the first gate electrode 19 , the surface of the first gate dielectric layer 17 may be partially exposed.

[0076] like Figure 4D As shown, a second gate dielectric layer 20A may be formed on the first barrier layer 18 and the first gate electrode 19. The second gate dielectric layer 20A may be conformally formed. For example, the second gate dielectric layer 20A may be formed by ALD or CVD. The second gate dielectric layer 20A may be made of the same or different material as the first gate dielectric layer 17. The first gate dielectric layer 17 and the second gate dielectric layer 20A may have the same thickness. In some embodiments, the second gate dielectric layer 20A may have a smaller or larger thickness than the first gate dielectric layer 17.

[0077] For example, the second gate dielectric layer 20A may be formed by a CVD or ALD process. The second gate dielectric layer 20A may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include a hafnium oxide, a hafnium silicon oxide, a hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k material may include a lanthanum oxide, a lanthanum aluminum oxide, a zirconium oxide, a zirconium silicon oxide, a zirconium silicon oxynitride, an aluminum oxide, or a combination thereof. Other well-known high-k materials may also be selectively used as the high-k material. The second gate dielectric layer 20A may include a material having a low oxygen atom density. The second gate dielectric layer 20A may include a material having a lower oxygen atom density than the first gate dielectric layer 17.

[0078] like Figure 4EAs shown, an etching process may be performed on the second gate dielectric layer 20A. For example, an etch-back process may be performed on the second gate dielectric layer 20A, and the second gate dielectric layer 20 having a spacer shape may be retained by the etch-back process. The second gate dielectric layer 20 may cover the top surface of the first barrier layer 18 and expose the top surface of the first gate electrode 19. The second gate dielectric layer 20 may cover the exposed portion of the first gate dielectric layer 17 on the first barrier layer 18. The second gate dielectric layer 20 may extend to cover the sidewall surface of the hard mask layer 16. The second gate dielectric layer 20 may not cover the top surface of the hard mask layer 16. In some embodiments, a portion of the second gate dielectric layer 20 may cover the top surface of the hard mask layer 16.

[0079] Through the above series of processes, a double gate dielectric layer 21 including a first gate dielectric layer 17 and a second gate dielectric layer 20 may be formed. The double gate dielectric layer 21 may cover the surface of each trench 15. The first gate dielectric layer 17 of the double gate dielectric layer 21 may completely cover the surface of each trench 15, and the second gate dielectric layer 20 thereof may partially cover the first gate dielectric layer 17.

[0080] The sidewall surface of each trench 15 may be divided into a lower sidewall surface 15L and an upper sidewall surface 15U, and the height of the lower sidewall surface 15L may be less than the height of the upper sidewall surface 15U. The lower sidewall surface 15L may be a portion extending from the bottom surface of each trench 15, and the upper sidewall surface 15U may be a portion extending from the lower sidewall surface 15L. The first gate dielectric layer 17 may cover the bottom surface 15B, the lower sidewall surface 15L, and the upper sidewall surface 15U of each trench 15, and the second gate dielectric layer 20 may cover the sidewall surface 15U of the trench 15 on the first gate dielectric layer 17. A portion of the first gate dielectric layer 17 may be located between the second gate dielectric layer 20 and the upper sidewall 15U of each trench 15. The first gate dielectric layer 17 may be located between the first barrier layer 18 and the lower sidewall 15L of each trench 15.

[0081] As described above, bottom surface 15B and lower sidewall surface 15L of trench 15 may be covered by a single structure of first gate dielectric layer 17 , and upper sidewall surface 15U of trench 15 may be covered by a dual structure of first gate dielectric layer 17 and second gate dielectric layer 20 .

[0082] like Figure 4FAs shown, a second barrier layer 22 may be formed on the top surface of the first gate electrode 19. The first barrier layer 18 and the second barrier layer 22 may be formed of the same material or different materials. The second barrier layer 22 may include a metal-based material. The second barrier layer 22 may include a metal nitride. The second barrier layer 22 may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof. The second barrier layer 22 may be formed non-conformally. The non-conformal second barrier layer 22 may be formed by physical vapor deposition (PVD). For example, according to PVD, the second barrier layer 22 may cover the top surface of the first gate electrode 19 without covering a portion of the second gate dielectric layer 20.

[0083] When the second barrier layer 22 is deposited, first to third dummy materials 22A, 22B, and 22C may be formed. The first to third dummy materials 22A, 22B, and 22C may be made of the same material as the second barrier layer 22. The first dummy material 22A may cover the top surface of the hard mask layer 16, the second dummy material 22B may extend from the first dummy material 22A and cover the sidewall surface of the first hard mask layer 16, and the third dummy material 22C may extend from the second dummy material 22B and cover a portion of the top of the second gate dielectric layer 20.

[0084] As described above, the first to third dummy materials 22A, 22B, and 22C may be formed when the second barrier layer 22 is deposited. The second barrier layer 22 may be a covering portion covering the top surface of the lower buried portion LB, and the first to third dummy materials 22A, 22B, and 22C may be dummy portions partially covering the second gate dielectric layer 20. The second barrier layer 22 and the first to third dummy materials 22A, 22B, and 22C may be non-conformally deposited without contacting each other.

[0085] The second barrier layer 22 may include titanium nitride deposited by PVD (ie, PVD TiN). The second barrier layer 22 may be used to prevent interdiffusion or interaction between the first gate electrode 19 and a subsequent second gate electrode. The first to third dummy materials 22A, 22B, and 22C may be removed in a subsequent process.

[0086] like Figure 4GAs shown, a second conductive layer 23A may be formed on the second barrier layer 22 and the second gate dielectric layer 20. The second conductive layer 23A may be formed on the second gate dielectric layer 20 and may fill each trench 15. The second conductive layer 23A may include a material having a low work function. The second conductive layer 23A may include polysilicon having a low work function, for example, polysilicon doped with N-type impurities. The second conductive layer 23A may be formed by CVD or ALD. In some embodiments, the first gate electrode 19 and the second conductive layer 23A may be made of different materials. In some embodiments, the first gate electrode 19 and the second conductive layer 23A may be made of the same material. The second conductive layer 23A may be formed of a low resistance material to reduce the gate film resistance.

[0087] like Figure 4H As shown, a second gate electrode 23 may be formed in each trench 15. In order to form the second gate electrode 23, a recess process may be performed. The recess process may be performed by a dry etching process (e.g., an etch-back process). The second gate electrode 23 may be formed by performing an etch-back process on the second conductive layer 23A. In some embodiments, a planarization process may be performed in advance to expose the hard mask layer 16, and then an etch-back process of the recess process may be performed. The top surface of the second gate electrode 23 may be recessed to a level lower than the top surface of the active region 14.

[0088] When an etch-back process is performed on the second conductive layer 23A, the first to third dummy materials 22A, 22B, and 22C may serve to protect the second gate dielectric layer 20. In other words, when an etch-back process of the second conductive layer 23A is performed, the second gate dielectric layer 20 may be protected from damage.

[0089] The third dummy layer 22C may not remain on the contact surface between the second gate electrode 23 and the second gate dielectric layer 20. To this end, the height of the second gate electrode 23 may be adjusted.

[0090] In addition, when the etch-back process is performed on the second conductive layer 23A, the second gate dielectric layer 20 may be exposed, and the first gate dielectric layer 17 may not be exposed. As a result, the etch-back process performed on the second conductive layer 23A may prevent the first gate dielectric layer 17 from being damaged. The second gate dielectric layer 20 may serve as a protective layer to prevent etching damage to the first gate dielectric layer 17. When the etch-back process is performed on the second conductive layer 23A, a portion of the second gate dielectric layer 20 may be damaged. However, since the first gate dielectric layer 17 is retained without damage, the GIDL may be improved.

[0091] The second barrier layer 22 and the second gate electrode 23 may be referred to as an upper buried portion UB. Thus, a double buried gate structure including a lower buried portion LB and an upper buried portion UB may be formed. The lower buried portion LB may include a first gate electrode 19 having a low resistance, and the upper buried portion UB may include a second gate electrode 23 having a low work function. The gate resistance of the double buried gate structure may be reduced due to the first gate electrode 19, and GIDL may be improved due to the second gate electrode 23. The second barrier layer 22 may prevent mutual diffusion and interaction between the first gate electrode 19 and the second gate electrode 23. Since the second barrier layer 22 is not present on the sidewall of the second gate electrode 23, GIDL may be further improved due to the second gate electrode 23.

[0092] like Fig. 4I As shown, the first to third dummy layers 22A, 22B and 22C may be removed. The first to third dummy layers 22A, 22B and 22C may be removed, for example, by a wet etching process. At this time, the hard mask layer 16, the second gate dielectric layer 20 and the second gate electrode 23 may not be lost. Since the first to third dummy layers 22A, 22B and 22C are removed, the surface of the second gate dielectric layer 20 may be exposed.

[0093] In some embodiments, the first to third dummy layers 22A, 22B, and 22C may not remain when the process of forming the second gate electrode 23 is completed. In other words, all of the first to third dummy layers 22A, 22B, and 22C may be removed when the etch-back process performed on the second conductive layer 23A is completed.

[0094] like Figure 4J As shown, a capping layer 24 may be formed on the second gate electrode 23 and the second gate dielectric layer 20. The capping layer 24 includes a dielectric material. The capping layer 24 may include silicon nitride. Subsequently, the capping layer 24 may be planarized so that the top surface of the hard mask layer 16 is exposed. The capping layer 24 may have an oxide-nitride-oxide (ONO) structure.

[0095] Through the above series of processes, a buried gate structure can be formed. The buried gate structure includes a first gate dielectric layer 17, a first barrier layer 18, a first gate electrode 19, a second gate dielectric layer 20, a second barrier layer 22, a second gate electrode 23 and a capping layer 24. The top surface of the second gate electrode 23 is located at a level lower than the top surface of the active region 14. Since the top surface of the second gate electrode 23 is recessed to a low level, the physical distance between the second gate electrode 23 and the peripheral conductive material (e.g., contact plug) can be fully ensured.

[0096] After forming the capping layer 24, a doping process of impurities is performed by implantation or other doping techniques. Thus, a first doping region 25 and a second doping region 26 are formed in the substrate 11. The first doping region 25 and the second doping region 26 may have a depth that overlaps with the second gate electrode 23 and the second gate dielectric layer 20 in a horizontal direction. The second gate dielectric layer 20 may overlap with the first doping region 25 and the second doping region 26 in a horizontal direction. The first barrier layer 18 and the first gate electrode 19 may not overlap with the first doping region 25 and the second doping region 26 in a horizontal direction. The lowest portion of the second gate dielectric layer 20 may be at the same level as the lowest portion of the first doping region 25 and the second doping region 26.

[0097] When the first doping region 25 and the second doping region 26 are formed, a channel 27 may be defined along the surface of each trench 15. The length of the channel 27 may be defined by the lower buried portion LB.

[0098] The first gate dielectric layer 17 may be located between the lower buried portion LB and the channel 27, and the first gate dielectric layer 17 and the second gate dielectric layer 20 may be located between the upper buried portion UB and the first doping region 25 and the second doping region 26. Specifically, a single gate dielectric structure formed by the first gate dielectric layer 17 may be located between the lower buried portion LB and the channel 27, and a dual gate dielectric structure 21 formed by the first gate dielectric layer 17 and the second gate dielectric layer 20 may be located between the second gate electrode 23 and the first doping region 25 and the second doping region 26. The dual gate dielectric structure 21 may have a greater thickness than the single gate dielectric structure.

[0099] Figure 5 is a cross-sectional view illustrating damage of a gate dielectric layer due to fluorine according to a comparative example.

[0100] Figure 5 An example is shown in which the second gate dielectric layer 20 is omitted, and when the etch-back process is performed on the second conductive layer 23A, the surface of the first gate dielectric layer 17 may be subjected to corrosion 20'. Here, the corrosion 20' of the first gate dielectric layer 17 may include a case where the surface of the first gate dielectric layer 17 is damaged or a portion thereof is lost.

[0101] Thus, when erosion 20 ′ of the first gate dielectric layer 17 occurs, the GIDL may increase.

[0102] Since the second gate dielectric layer 20 may be formed according to the present embodiment, the first gate dielectric layer 17 may be prevented from being damaged, and thus GIDL may be improved.

[0103] FIG. 6A to FIG. 6D is a cross-sectional view illustrating another method for forming a semiconductor device. FIG. 6A to FIG. 6D The method shown can be similar to 4A to Figure 4J The method shown.

[0104] pass FIG. 4A to FIG. 4E According to the method shown, a second gate dielectric layer 20 covering the exposed portion of the first gate dielectric layer 17 may be formed on the lower buried portion LB.

[0105] Then, if Fig. 6A As shown, a plasma treatment 31 that can form the second gate dielectric layer 20 can be performed on the substrate 11. The plasma treatment 31 can be performed in an atmosphere of a nitrogen-containing gas or an oxygen-containing gas. The plasma treatment 31 can include plasma nitridation or plasma oxidation.

[0106] The top surface of the lower buried portion LB may be modified by plasma treatment 31. For example, the top surface of the lower buried portion LB may be nitrided by plasma nitridation. The second barrier layer 19N may be formed by such plasma nitridation. The second barrier layer 19N may be a portion where the top surface of the first gate electrode 19 is nitrided. The second barrier layer 19N may be a nitride of the first gate electrode 19. When the first gate electrode 19 includes tungsten, the second barrier layer 19N may be tungsten nitride.

[0107] In some embodiments, the surface of the second gate dielectric layer 20 may be modified during the plasma treatment 31. For example, the surface of the second gate dielectric layer 20 may be nitrided (refer to reference numeral '20N').

[0108] As described above, the second barrier layer 19N may be selectively formed only on the top surface of the lower buried portion LB.

[0109] like Figure 6B As shown, a second conductive layer 23A may be formed on the second barrier layer 19N and the second gate dielectric layer 20. The second conductive layer 23A may be formed on the second gate dielectric layer 20 to fill each trench 15. The second conductive layer 23A includes a material with a low work function. The second conductive layer 23A may include polysilicon with a low work function, for example, polysilicon doped with N-type impurities. The second conductive layer 23A may be formed by CVD or ALD. The first gate electrode 19 and the second conductive layer 23A may be made of different materials. In some embodiments, the first gate electrode 19 and the second conductive layer 23A may be made of the same material. The second conductive layer 23A may be formed of a low resistance material to reduce the gate film resistance.

[0110] like Figure 6CAs shown, a second gate electrode 23 may be formed in each trench 15. In order to form the second gate electrode 23, a recess process may be performed. The recess process may be performed by a dry etching process (e.g., an etch-back process). The second gate electrode 23 may be formed by performing an etch-back process on the second conductive layer 23A. In some embodiments, a planarization process may be performed in advance to expose the hard mask layer 16, and then an etch-back process of the recess process may be performed. The top surface of the second gate electrode 23 may be recessed to a level lower than the top surface of the active region 14.

[0111] When the etch-back process is performed on the second conductive layer 23A, the second gate dielectric layer 20 may be exposed, and the first gate dielectric layer 17 may not be exposed. As a result, the etch-back process performed on the second conductive layer 23A may prevent the first gate dielectric layer 17 from being damaged. The second gate dielectric layer 20 may serve as a protective layer to prevent etching damage to the first gate dielectric layer 17. When the etch-back process is performed on the second conductive layer 23A, a portion of the second gate dielectric layer 20 may be damaged. However, since the first gate dielectric layer 17 is retained without damage, the GIDL may be improved.

[0112] The second barrier layer 19N and the second gate electrode 23 may be referred to as an upper buried portion UB. Thus, a double buried gate structure including a lower buried portion LB and an upper buried portion UB may be formed. The lower buried portion LB may include a first gate electrode 19 having a low resistance, and the upper buried portion UB may include a second gate electrode 23 having a low work function. The gate resistance of the double buried gate structure may be reduced due to the first gate electrode 19, and GIDL may be improved due to the second gate electrode 23. The second barrier layer 19N may prevent mutual diffusion and interaction between the first gate electrode 19 and the second gate electrode 23. Since the second barrier layer 19N is not present on the sidewall of the second gate electrode 23, GIDL may be further improved due to the second gate electrode 23.

[0113] like Fig.6D As shown, a capping layer 24 may be formed on the second gate electrode 23 and the second gate dielectric layer 20. The capping layer 24 includes a dielectric material. The capping layer 24 may include silicon nitride. Subsequently, the capping layer 24 may be planarized so that the top surface of the hard mask layer 16 is exposed. The capping layer 24 may have an ONO structure.

[0114] After the capping layer 24 may be formed, a doping process of impurities may be performed by implantation or other doping techniques. Thus, a first doping region 25 and a second doping region 26 may be formed in the substrate 11.

[0115] FIG. 7A to FIG. 7D is a cross-sectional view illustrating still another method for forming a semiconductor device. Figures 7A to 7DThe method shown can be similar to 4A to Figure 4J The method shown.

[0116] pass FIG. 4A to FIG. 4E According to the method shown, the second gate dielectric layer 20 covering the exposed portion of the first gate dielectric layer 17 can be formed.

[0117] Then, if Fig. 7A As shown, a sacrificial material 41 may be formed to cover the second gate dielectric layer 20. The sacrificial material 41 may be formed on the entire surface of the substrate 11 while covering the second gate dielectric layer 20 and the second barrier material 22. The sacrificial material 41 may include a dipole inductive material. The dipole inductive material may reduce the work function value of the subsequent upper buried portion.

[0118] The sacrificial material 41 may be formed by ALD or CVD. The sacrificial material 41 may include lanthanum atoms as a dipole sensing material. The sacrificial material 41 may include a lanthanum layer, a lanthanum oxide (La2O3), or a monolayer of lanthanum oxide. In some embodiments, the dipole sensing material may also include yttrium, germanium, lutetium, or strontium in addition to lanthanum. The sacrificial material 41 may include yttrium oxide (Y2O3), germanium oxide (GeO2), lutetium oxide (Lu2O3), or strontium oxide (SrO). The thickness of the sacrificial material 41 may be 20 angstroms or less. The thickness of the sacrificial material 41 may be 1 angstrom to 20 angstroms.

[0119] like Figure 7B As shown, a thermal annealing process 42 may be performed. The thermal annealing process 42 may include a rapid thermal annealing (RTA) process. The sacrificial material 41 may be exposed to the thermal annealing process 42. When the thermal annealing process 42 is performed, the dipole sensing material may diffuse from the sacrificial material 41. The diffused dipole sensing material may be locally located in the second gate dielectric layer 20. The diffused dipole sensing material may be located at the interface between the first gate dielectric layer 17 and the second gate dielectric layer 20. Therefore, a dipole sensing portion 43 may be locally formed in the second gate dielectric layer 20. The dipole sensing portion 43 may include the diffused dipole sensing material. For example, the dipole sensing portion 43 may contain lanthanum atoms. The second gate dielectric layer 20 and the first gate dielectric layer 17 may be silicon oxide, and the dipole sensing portion 43 may be silicon oxide diffused with lanthanum. The dipole sensing portion 43 may be lanthanum silicate.

[0120] In some embodiments, the dipole sensing material may be diffused into the top surface of the first gate electrode 19 by the thermal annealing process 42 .

[0121] like Figure 7CAs shown, the sacrificial material 41 may be removed. For example, the sacrificial material 41 may be removed by a wet etching process. By applying the wet etching process to the sacrificial material 41 as described above, the sacrificial material 41 may be selectively removed without damaging the second gate dielectric layer 20.

[0122] Next, you can go to 4F to Fig. 4I The second barrier layer 22 and the second gate electrode 23 are formed by the method shown in FIG. Fig.7D As shown in , a second barrier layer 22 may be formed on the first gate electrode 19, and a second gate electrode 23 may be formed on the second barrier layer 22. A sidewall surface of the second gate electrode 23 may contact the second gate dielectric layer 20. The second gate dielectric layer 20 may be located between the second gate electrode 23 and the first gate dielectric layer 17, and the second gate dielectric layer 20 may include a dipole induction portion 43.

[0123] Afterwards, you can Figure 4J The method shown is used to form the capping layer 24 , the first doping region 25 and the second doping region 26 .

[0124] The generation mechanism of the dipole will be described as follows. The oxygen atom density in the dipole induction portion 43 may be lower than the oxygen atom density of the first gate dielectric layer 17 and the oxygen atom density of the second gate dielectric layer 20. Due to the difference between the oxygen atom densities, the oxygen atoms of the first gate dielectric layer 17 and the second gate dielectric layer 20 diffuse into the dipole induction portion 43. Through the diffusion of oxygen atoms, the first gate dielectric layer 17 and the second gate dielectric layer 20 are positively charged, while the dipole induction portion 43 is negatively charged. In this way, a dipole is induced at the interface between the positively charged first gate dielectric layer 17 and the second gate dielectric layer 20 and the negatively charged dipole induction portion 43. When the dipole is induced, the energy band of the second gate electrode 23 increases, and thus the work function of the second gate electrode 23 decreases. As a result, GIDL may be suppressed due to the reduction in the work function of the second gate electrode 23. The dipole induction portion 43 may not overlap with the channel 27. When the dipole inductive portion 43 and the channel 27 overlap each other, it is difficult to adjust the threshold voltage due to the induction of the low work function.

[0125] FIG. 8A to FIG. 8D is a cross-sectional view illustrating still another method for forming a semiconductor device. FIG. 8A to FIG. 8D The method shown can be similar to 4A to Figure 4J In addition, FIG. 8A to FIG. 8D The method shown can be similar to 7A to Fig.7D The method shown.

[0126] pass FIG. 4A to FIG. 4E According to the method shown, the second gate dielectric layer 20 covering the exposed portion of the first gate dielectric layer 17 can be formed.

[0127] Then, if Fig. 8A As shown, a sacrificial liner 51 and a sacrificial material 41 may be formed to cover the second gate dielectric layer 20. The sacrificial liner 51 and the sacrificial material 41 may be formed on the entire surface of the substrate 11 while covering the second gate dielectric layer 20 and the second barrier layer 22. The sacrificial liner 51 may include a metal nitride. The sacrificial liner 51 may include titanium nitride. The sacrificial material 41 may include a dipole induction material. The dipole induction material may reduce the work function value of the subsequent upper buried portion.

[0128] The sacrificial liner 51 and the sacrificial material 41 may be formed by ALD or CVD. The sacrificial material 41 may contain lanthanum atoms as a dipole sensing material. The sacrificial material 41 may include a lanthanum layer, a lanthanum oxide (La2O3), or a monolayer of lanthanum oxide. In some embodiments, the dipole sensing material may include yttrium, germanium, lutetium, or strontium other than lanthanum. The sacrificial material 41 may include yttrium oxide (Y2O3), germanium oxide (GeO2), lutetium oxide (Lu2O3), or strontium oxide (SrO). The thickness of the sacrificial material 41 may be 20 angstroms or less. The thickness of the sacrificial material 41 may be 1 angstrom to 20 angstroms.

[0129] like Figure 8B As shown, a thermal annealing process 42 may be performed. The thermal annealing process 42 may include a rapid thermal annealing (RTA) process. The sacrificial material 41 may be exposed to the thermal annealing process 42. When the thermal annealing process 42 is performed, the dipole sensing material may diffuse from the sacrificial material 41. The diffused dipole sensing material may be locally located in the second gate dielectric layer 20. The diffused dipole sensing material may be located at an interface between the sacrificial liner 51 and the second gate dielectric layer 20. Therefore, a dipole sensing portion 43' may be locally formed in the second gate dielectric layer 20. The dipole sensing portion 43' may include a diffused dipole sensing material. The dipole sensing portion 43' may include lanthanum atoms. The second gate dielectric layer 20 and the first gate dielectric layer 17 may be silicon oxide, and the dipole sensing portion 43' may be silicon oxide diffused with lanthanum. The dipole sensing portion 43' may be lanthanum silicate.

[0130] In some embodiments, the dipole sensing material may be diffused into the top surface of the first gate electrode 19 by the thermal annealing process 42 .

[0131] like Figure 8C As shown, the sacrificial material 41 and the sacrificial liner 51 can be removed. For example, the sacrificial material 41 and the sacrificial liner 51 can be removed by a wet etching process. By applying the wet etching process to the sacrificial material 41 and the sacrificial liner 51 as described above, the sacrificial material 41 and the sacrificial liner 51 can be selectively removed without damaging the second gate dielectric layer 20.

[0132] Next, you can FIG. 4F to FIG. 4I The second barrier layer 22 and the second gate electrode 23 are formed by the method shown in FIG. Fig.8D As shown in , a second barrier layer 22 may be formed on the first gate electrode 19, and a second gate electrode 23 may be formed on the second barrier layer 22. A sidewall surface of the second gate electrode 23 may contact the second gate dielectric layer 20. The second gate dielectric layer 20 may be located between the second gate electrode 23 and the first gate dielectric layer 17, and the second gate dielectric layer 20 may include a dipole induction portion 43'. The dipole induction portion 43' may directly contact the sidewall surface of the second gate electrode 23.

[0133] Afterwards, you can Figure 4J The method shown forms a capping layer 24 , a first doping region 25 , and a second doping region 26 .

[0134] Fig. 9 is a cross-sectional view showing the memory cell 100M.

[0135] refer to Fig. 9 , the memory cell 100M may include a cell transistor, a bit line BL, and a capacitor CAP. The cell transistor may include Figure 3 The semiconductor device 200 of FIG. 200B may include a buried gate structure 200G, a channel region CH, a first doping region 113, and a second doping region 114. The first doping region 113 may be electrically connected to the bit line BL. The second doping region 114 may be electrically connected to the capacitor CAP.

[0136] In the memory cell 100M, the buried gate structure 200G may be referred to as a buried word line structure BWL. The buried word line structure BWL may be embedded in the trench 105. The buried word line structure BWL may include a first gate dielectric layer 106L, a second gate dielectric layer 106U, a first barrier layer 108, a first gate electrode 109, a second barrier layer 110, a second gate electrode 111, and a capping layer 112. The first gate dielectric layer 106L may include an extension portion 106E, and the extension portion 106E may contact the first doped region 113 and the second doped region 114. The second gate dielectric layer 106U may be formed between the second gate electrode 111 and the extension portion 106E. A dual gate dielectric structure 107 may be formed between the second gate electrode 111 and the first doped region 113 and the second doped region 114.

[0137] Except for the buried gate structure 200G, the buried word line structure BWL may be replaced with any one of the buried gate structures according to the above-described embodiments.

[0138] The capacitor CAP may include a storage node, a dielectric layer and a plate node. The storage node may have a cylindrical shape or a columnar shape. The dielectric layer may be formed on the surface of the storage node. The dielectric layer may include at least one selected from the group including zirconium oxide, aluminum oxide and hafnium oxide. For example, the dielectric layer may have a ZAZ (ZrO2 / Al2O3 / ZrO2) structure in which a first zirconium oxide, aluminum oxide and a second zirconium oxide are stacked. The plate node may be formed on the dielectric layer. The storage node and the plate node may include a metal-containing material.

[0139] The memory cell 100M may be a part of a dynamic random access memory (DRAM) device. When the memory cell 100M is applied to the DRAM device, the refresh characteristics of the DRAM device may be improved. Furthermore, leakage may be prevented, thereby improving retention time.

[0140] According to various embodiments of the present invention, a semiconductor device having a dual gate dielectric structure may be formed, thereby preventing damage to a gate dielectric layer of the dual gate dielectric structure in subsequent processes and reducing GIDL.

[0141] Furthermore, according to various embodiments of the present invention, a semiconductor memory device having a gate electrode with a low work function may be formed, thereby further reducing GIDL.

[0142] Furthermore, according to various embodiments of the present invention, a semiconductor memory device including a dipole may be formed, thereby further reducing GIDL.

[0143] Although the present invention has been described for specific embodiments, it should be noted that these embodiments are not intended to limit the scope of the present invention. In addition, it should be noted that those skilled in the art can implement the present invention in various ways by substitution, change and modification without departing from the scope of the present invention defined by the appended claims.

Claims

1. A semiconductor device, comprising: substrate; a first doped region and a second doped region formed to be separated from each other by a trench in the substrate; a first gate dielectric layer over the trench; a lower gate, on the first gate dielectric layer; an upper gate, above the lower gate; a second gate dielectric layer, covering all sidewall surfaces of the first gate dielectric layer that are not covered by the lower gate; as well as A dipole inducing material is contained in the second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are formed of the same dielectric material, The dipole sensing material is located at the interface between the first gate dielectric layer and the second gate dielectric layer. Wherein, a double gate dielectric layer including the first gate dielectric layer and the second gate dielectric layer is located between the upper gate and the first doped region and the second doped region.

2. The semiconductor device according to claim 1, wherein A total thickness of the first gate dielectric layer and the second gate dielectric layer is greater than a thickness of the first gate dielectric layer.

3. The semiconductor device according to claim 1, wherein The lower gate and the upper gate include the same conductive material.

4. The semiconductor device according to claim 1, wherein: The upper gate includes a conductive material with a low work function, and the lower gate includes a conductive material with a low resistance.

5. The semiconductor device according to claim 1, wherein Each of the lower gate and the upper gate includes titanium nitride.

6. The semiconductor device according to claim 1, wherein The lower gate includes a stack of titanium nitride and tungsten, and the upper gate includes N-type polysilicon. 7 . The semiconductor device according to claim 1 , further comprising a barrier layer between the lower gate and the upper gate.

8. The semiconductor device according to claim 7, wherein: The blocking layer includes a nitride that nitridates a top surface of the lower gate. 9 . The semiconductor device according to claim 1 , further comprising a fin region under the lower gate, wherein a top surface and sidewall surfaces of the fin region are covered by the first gate dielectric layer.

10. The semiconductor device according to claim 1, wherein The dipole inducing material includes a material that reduces a work function value of the upper gate.

11. The semiconductor device according to claim 1, wherein The dipole sensing material includes lanthanum.

12. The semiconductor device according to claim 1, wherein The first gate dielectric layer includes silicon oxide.

13. The semiconductor device according to claim 1, wherein The first gate dielectric layer includes a first silicon oxide, the second gate dielectric layer includes a second silicon oxide, and the silicon oxide containing the dipole inducing material is located at an interface between the first silicon oxide and the second silicon oxide.

14. The semiconductor device according to claim 1, wherein Each of the first gate dielectric layer and the second gate dielectric layer includes silicon oxide, and the dipole inducing material includes lanthanum-containing silicon oxide.

15. The semiconductor device according to claim 1, further comprising: a bit line coupled to the first doped region; and A capacitor is coupled to the second doped region.

16. A method for manufacturing a semiconductor device, comprising: forming a trench in a substrate; forming a first gate dielectric layer over the trench; forming a lower gate on the first gate dielectric layer; forming a second gate dielectric layer, wherein the second gate dielectric layer covers all sidewall surfaces of the first gate dielectric layer that are not covered by the lower gate; implanting a dipole inducing material into the second gate dielectric layer; as well as forming an upper gate on the second gate dielectric layer and the lower gate, wherein the first gate dielectric layer and the second gate dielectric layer are formed of the same dielectric material, The dipole sensing material is located at the interface between the first gate dielectric layer and the second gate dielectric layer. The double gate dielectric layer including the first gate dielectric layer and the second gate dielectric layer is located between the upper gate and the first doped region and the second doped region.

17. The method according to claim 16, wherein: The step of forming the second gate dielectric layer comprises: forming a dielectric material over the first gate dielectric layer and the lower gate; and The dielectric material is etched to remain as spacers overlying the first gate dielectric layer.

18. The method according to claim 16, wherein: The first gate dielectric layer and the second gate dielectric layer include silicon oxide, silicon nitride, high-k material, or a combination thereof.

19. The method according to claim 16, wherein: The step of forming the lower gate includes: forming a first barrier material on the first gate dielectric layer; forming a first conductive material filling the trench on the first barrier material; and The first conductive material and the first barrier material are recessed to form a first gate electrode and a first barrier layer.

20. The method according to claim 16, wherein: The step of forming the upper gate comprises: selectively forming a second blocking layer on the lower gate; forming a second conductive material filling the trench on the second barrier layer; and The second conductive material is recessed to form a second gate electrode.

21. The method according to claim 20, wherein: The step of selectively forming the second barrier layer on the lower gate includes: depositing a barrier material, the barrier material including a covering portion covering a top surface of the lower gate and a dummy portion partially covering the second gate dielectric layer, The barrier material is non-conformally deposited such that the covering portion and the dummy portion do not contact each other.

22. The method according to claim 21, wherein: The step of selectively forming the second barrier layer on the lower gate is performed by physical vapor deposition (PVD).

23. The method according to claim 20, wherein the step of selectively forming the second barrier layer on the lower gate comprises: Plasma treatment is selectively performed on a top surface of the lower gate.

24. The method according to claim 23, wherein: The plasma treatment includes plasma nitridation.

25. The method of claim 16, wherein: The step of injecting the dipole inducing material into the second gate dielectric layer comprises: forming a sacrificial material including the dipole inducing material to cover the second gate dielectric layer and the lower gate; performing an annealing process to diffuse the dipole sensing material into the second gate dielectric layer; and The sacrificial material is removed.

26. The method according to claim 25, further comprising: Before forming the sacrificial material, a sacrificial liner is formed to cover the second gate dielectric layer and the lower gate.

27. The method according to claim 26, wherein: The sacrificial liner includes a metal nitride.

28. The method of claim 16, wherein: The dipole sensing material is located at an interface between the upper gate and the second gate dielectric layer.

29. The method of claim 16, wherein: The dipole sensing material is located at an interface between the second gate dielectric layer and the first gate dielectric layer.

30. The method of claim 16, wherein: The dipole inducing material includes a material that reduces a work function value of the upper gate.

31. The method of claim 16, wherein: The dipole sensing material includes lanthanum.

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