Power management circuit and power management method

Abstract

Power management circuits and methods of operation are described. A power management circuit includes a power input to receive power from a power source, a controller, a finite state machine circuit in communication with the controller, and a first voltage regulator in communication with the controller and the power input and having a first output connected to a first capacitor to store power and to first circuitry. The controller is configured to periodically enable the first voltage regulator to supply current to charge the first capacitor. The finite state machine circuit is configured to interact with the controller to control a duration of a first time period of a cycle in which the first voltage regulator supplies current to charge the first capacitor and a duration of a second time period of the cycle in which the first voltage regulator does not supply current to not charge the first capacitor and the first circuitry can receive current from the first capacitor.

Description

TECHNICAL FIELD

[0001] This specification relates to power management and in particular to power management circuitry and methods of operation that can provide low power modes of operation for electronic devices, apparatuses and equipment. BACKGROUND

[0002] Electronic devices require a source of electrical power to operate. Mains electrical power sources typically provide an unlimited supply of electrical power. However, electronic devices that cannot readily use mains electrical power sources, such as portable or mobile electronic devices, can alternatively or additionally have their own local source of electrical power, such as one or more batteries.

[0003] However, such local power sources can typically only provide a limited amount of electrical power and so can limit the time for which the electrical device can operate. This can be exacerbated in cases where the electrical device requires a relatively large amount of electrical power, for example to drive an antenna or an amplifier, and / or in cases where the electrical device is relatively small and so can only accept a small size battery.

[0004] Power consumption of the electrical device can be managed by simply turning the electrical device completely off when not required and on when required. However, in some cases it can be preferable to maintain at least some functionality of the electrical device, for example to maintain state information and / or the ability to interact with other electrical devices and / or to be able to return to a fully operable state more quickly. Thus, some electrical devices can have the ability to switch between a fully on or awake mode of operation and a sleep or quiescent mode of operation in which only some parts of the electrical device can need to consume electrical power.

[0005] To help manage power consumption, low power modules have been designed, such as low quiescent current bandgap regulators, low power hysteretic regulators or low power linear regulators.

[0006] However, it would be beneficial if even lower levels of power consumption could be achieved. SUMMARY

[0007] According to a first aspect of the disclosure, there is provided a power management circuit comprising: a power input for receiving power from a power source; a controller; a finite state machine circuit in communication with the controller; and a first voltage regulator in communication with the controller and the power input to receive power and having a first output connectable to a first capacitor for storing power and connectable to first circuitry, wherein the controller is configured to periodically enable the first voltage regulator to supply current to charge the first capacitor, and wherein the finite state machine circuit is configured to interact with the controller to control a duration of a first time period of a cycle in which the first voltage regulator supplies current to charge the first capacitor and to control a duration of a second time period of the cycle in which the first voltage regulator does not supply current to charge the first capacitor and the first circuitry can receive current from the first capacitor.

[0008] In one or more embodiments, the power management circuit can additionally comprise a second voltage regulator in communication with the controller and the power input to receive power and having a second output connectable to a second capacitor for storing power and connectable to second circuitry, wherein the controller is configured to periodically enable the second voltage regulator to supply current to charge the second capacitor, and wherein the finite state machine circuit is configured to interact with the controller to control a duration of a first time period of a cycle in which the second voltage regulator supplies current to charge the second capacitor and to control a duration of a second time period of the cycle in which the second voltage regulator does not supply current to charge the second capacitor and the second circuitry can receive current from the second capacitor.

[0009] In one or more embodiments, the first capacitor can store power and can be arranged to supply power to supply analog electrical components, and the second capacitor can store power and be arranged to supply power to supply digital electrical components.

[0010] In one or more embodiments, the power management circuit can additionally include a reference voltage circuit in communication with the controller and the power input to receive power and having a third output connectable to a reference voltage capacitor for storing power, wherein the controller can be additionally configured to periodically enable the reference voltage circuit to supply current to charge the reference voltage capacitor, and wherein the finite state machine circuit is configured to interact with the controller to control a duration of a first time period of the cycle in which the reference voltage circuit supplies current to charge the reference voltage capacitor and to control a duration of a second time period of the cycle in which the reference voltage circuit does not supply current to not charge the reference voltage capacitor.

[0011] In one or more embodiments, the power management circuit can additionally include a low frequency oscillator in communication with the controller and the finite state machine circuit, and wherein the finite state machine circuit is configured to control the duration of the first time period based on a number of cycles of the low frequency oscillator.

[0012] In one or more embodiments, the finite state machine circuit can include a first programmable register, and wherein a value set in the first programmable register is used to determine the duration of the first time period.

[0013] In one or more embodiments, the finite state machine circuit can be additionally configured to control the duration of the second time period based on a number of cycles of the low frequency oscillator.

[0014] In one or more embodiments, the finite state machine circuit can include a second programmable register, and wherein a value set in the second programmable register is used to set the duration of the second time period.

[0015] In one or more embodiments, the power management circuit can additionally include a first voltage monitor in communication with the first output and the finite state machine circuit, wherein the first voltage monitor is configured to output a first indication of a voltage of the first capacitor, and wherein the finite state machine circuit is additionally configured to control the duration of the second time period based on the first indication of the voltage of the first capacitor.

[0016] In one or more embodiments, the power management circuit can additionally comprise a second voltage monitor in communication with the second output and the finite state machine, and wherein the second voltage monitor is configured to output a second indication of a voltage of the second capacitor, and wherein the finite state machine circuit is additionally configured to control a duration of the second time period based on the second indication of the voltage of the second capacitor.

[0017] The finite state machine circuit can be additionally configured to control a duration of the second time period based on the first indication indicating that the voltage of the first capacitor has dropped below a threshold level or the second indication indicating that the voltage of the second capacitor has dropped below a threshold level.

[0018] According to a second aspect of the disclosure, there is provided a package comprising a semiconductor integrated circuit, wherein the semiconductor integrated circuit is configured to provide the power management circuit of the first aspect.

[0019] According to a third aspect of the disclosure, there is provided an electronic device comprising the power management circuit of the first aspect or the package of the second aspect. The electronic device can additionally comprise a power source connected to the power input, a first capacitor connected to the first output, and first circuitry connected to the first output. The electronic device can additionally comprise a second capacitor connected to the second output and second circuitry connected to the second output. The first circuitry can be analog circuitry and / or the second circuitry can be digital circuitry.

[0020] The electronic device can be a battery powered device, a mobile device, a smart watch, or a near field communication, NFC, device, such as a secure NFC device.

[0021] According to a fourth aspect of the disclosure, there is provided a method of managing power consumption, the method comprising: controlling a voltage regulator to periodically supply current to charge a capacitor; and using a finite state machine to control a duration of a first time period of the voltage regulator of a certain period supplying current to charge the capacitor and a duration of a second time period of the voltage regulator of the period not supplying current to not charge the capacitor and the capacitor discharging to supply current to circuitry.

[0022] The features of the first aspect can also be or result in corresponding features of the fourth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0023] Embodiments of the present application will now be described in detail by way of example only, with reference to the drawings, in which:

[0024] Figure 1 a schematic block diagram of an example electronic device is shown;

[0025] Figure 2 a schematic block diagram of power management circuitry that can be used Figure 1 in the electronic device shown is shown;

[0026] Figure 3 a timing diagram showing Figure 1 operation of the power management circuitry shown;

[0027] Figure 4 a flow diagram showing Figure 2 a first method of operation of the circuitry shown;

[0028] Figure 5 a finite state machine diagram showing Figure 2 a first example of a finite state machine that can be used Figure 4 in the circuitry and the method shown;

[0029] Figure 6 a finite state machine diagram showing Figure 2 a second example of a finite state machine that can be used Figure 4 in the circuitry and the method shown;

[0030] Figure 7 a flow diagram showing Figure 2 a second method of operation of the circuitry shown;

[0031] Figure 8 a finite state machine diagram showing Figure 2 a third example of a finite state machine that can be used Figure 7 in the circuitry and the method shown; and

[0032] Figure 9 a finite state machine diagram showing Figure 2 a second example of a finite state machine that can be used Figure 7 in the circuitry and the method shown;

[0033] Unless otherwise indicated, like items in different drawings share the same reference number. DETAILED DESCRIPTION

[0034] Reference is made to Figure 1, showing a schematic block diagram of an electronic device 100. The electronic device can take a variety of forms. For example, the electronic device can be an NFC device having a standby mode of operation. In particular, the device 100 can be a secure NFC device that spends most of its time in a low power mode and enters a high power mode only during NFC transactions such as payment or ticketing. In other embodiments, the electronic device can be a battery powered electronic device. Other embodiments of the device can provide a mobile electronic device. Another embodiment of the electronic device can be a watch, and in particular a smart watch or the like.

[0035] As shown in Figure 1 , the electronic device 100 has a power source or power supply 102. The power supply 102 can take the form of one or more batteries. The electronic device 100 can include primary electronic circuitry 104 that provides most of the operational functions of the electronic device 100. As shown in Figure 1 , the primary circuitry 104 derives power from the power supply 102. For example, the primary circuitry 104 can include analog circuitry and / or digital circuitry and can include various integrated circuits. The primary circuitry 104 includes all of those components of the electronic device that do not need to receive power during the lower power mode of operation of the electronic device 100, such as the sleep mode.

[0036] The electronic device 100 can also include power management circuitry 106 that can also be connected to the power supply 102. The power management circuitry 106 is connected to one or more analog electronic components or circuits 108 that should be supplied with power during the lower power mode of operation of the electronic device 100. Similarly, the power management circuitry 106 can also be connected to one or more digital electronic components or circuits 110 that should also be supplied with power during the low power mode of operation of the electronic device 100. The power management circuitry 106 is also connected to one or more capacitors 112 that can be charged through the power management circuitry 106, which are used to store power and supply power to the analog components 108 and / or the digital components 110.

[0037] As shown in Figure 1 , the analog electronic components 108 and digital electronic components 110 that are supplied with power during the low power mode of operation of the device 100 can be provided as an integral power supply for the power management circuitry 106, for example, as part of the same integrated circuit. However, in other embodiments, some or all of the analog components or circuitry 108 or some or all of the circuitry 110 can be provided separately to the power management circuitry 106, for example as a separate integrated circuit.

[0038] Similarly, in other embodiments, Figure 1 One or more storage capacitors 112 also shown can be provided as part of power management circuitry 106.

[0039] To avoid significant power consumption, electronic device 100 can switch between a higher power mode (e.g., a fully operational mode) and a lower power mode (e.g., a sleep mode or standby mode) to reduce power consumption from power source 102. However, even in a standby mode or sleep mode of electronic device 100, some of the electronic devices can need to consume power to operate, for example, to switch the electronic device from a standby operational mode back to a wake operational mode. Power management circuitry 106 can help reduce power consumption of electronic device 100 during a low power operational mode.

[0040] Referring to Figure 2 , a schematic block diagram of power management circuitry 200 is shown, which generally corresponds to Figure 1 power management circuitry 106, analog components 108, and digital components 110 of

[0041] Power management circuitry 200 includes a power connection 202 that can be connected to power source 102. Power connection 202 supplies power to multiple components of power management circuit 200, as shown by the power lines in bold in Figure 2 Power management circuit 200 includes a controller 204 that has multiple inputs 206 for receiving signals from other components of the circuitry, and also has multiple outputs 208 for supplying signals to other components of the circuitry. Controller 204 also has an input 210 for receiving an external wake event signal. In general, controller 204 can be provided by analog circuitry and is configured to manage a power-up sequence of the power management circuitry upon receiving a wake event signal. Controller 204 is also configured to multiplex enable signals used during analog control (power-up period) with enable signals from a finite state machine once the finite state machine is enabled and ready to control the power management circuitry.

[0042] Power management circuitry 200 additionally includes a voltage reference circuit 212 that can receive power from the power source and generate and output a reference voltage signal to a first capacitor 216 that can be charged to a reference voltage level V ref. Voltage reference circuit 212 receives a voltage reference enable signal at input 218 from controller 204, which can be asserted and de-asserted to switch the output state of voltage reference circuit 212.

[0043] The power management circuit 200 also includes a bias current circuit 220 configured to output bias currents to a plurality of other components of the circuitry. The bias current circuit 220 provides a current reference used by various analog circuits of the power management circuit 200 as its output. The bias current circuit 220 has an input 222 arranged to receive a bias current enable signal from the controller 204, which can be asserted and de-asserted to switch the output of the bias current circuit 220.

[0044] The power management circuitry 200 also includes a first low power voltage regulator circuit 230 and a second low power voltage regulator circuit 240. The first voltage regulator 230 receives the output of the bias current circuit 220 as an input, and also has a power supply input. The first voltage regulator circuit 230 is arranged to output a regulated voltage level on an analog voltage output line 232 to the analog components. The analog voltage output line 232 is also connected to an analog voltage monitor 234, and also to any low power analog component 236 corresponding generally to the analog components 108. The analog voltage output line 232 is also connected to a second capacitor 238, which can be charged to an analog voltage reference level V ana. The analog power regulator 230 also has an input 239 arranged to receive an analog voltage low power regulation enable signal from the controller 204, which can be asserted and de-asserted to switch the output of the regulator 230.

[0045] The second power regulator 240 is arranged to receive the outputs of the voltage reference circuit 212 and the bias current circuit 220 as inputs. The second regulator 240 is connected to a power supply, and outputs a regulated digital voltage on a second output line 242. A digital voltage monitor 244 is connected to the digital voltage output line 242, and digital electronic components (corresponding to 110 in Figure 1 The third capacitor 248 is also connected to the digital voltage output line 242, and can be charged to a reference digital voltage level V dig. The digital voltage regulator 240 also has an input 249 arranged to receive a digital voltage regulator enable signal from the controller 204, which can be asserted and de-asserted to switch the output of the digital voltage regulator 240.

[0046] Figure 2 The first storage capacitor 216, the second storage capacitor 238, and the third storage capacitor 248 of the power management circuit 200 generally correspond to one or more storage capacitors 112 as shown in Figure 1 ​

[0047] The analog voltage monitor 234 has an output 235 indicating whether the analog voltage level is acceptable or not acceptable. Similarly, the digital voltage monitor 244 has an output 245 indicating whether the digital voltage level is acceptable or not acceptable.

[0048] The power management circuitry 200 also includes a finite state machine 250. The finite state machine 250 can be implemented as digital circuitry. The finite state machine 250 receives as a power input the digital voltage from the digital voltage regulator 240. The finite state machine circuit 250 includes four outputs 252 supplying various signals as inputs to the analog controller 204, described in more detail below. In some embodiments, the finite state machine circuitry 250 can also receive the analog voltage level state indication from the output 235 and the digital voltage level state indication from the output 245.

[0049] The power management circuitry 200 also includes a low frequency oscillator 260 having an input 262 arranged to receive the reference current output of the bias current circuit 220, the output 264 of the low frequency oscillator 260 being supplied as an input to the finite state machine circuit 250. The low frequency oscillator 260 has a further input 266 arranged to receive a low frequency oscillator enable signal from the controller 204 and which can be asserted and de-asserted to switch the output of the low frequency oscillator.

[0050] In one embodiment, in addition to the storage capacitors 216, 238 and 248, Figure 2 All of the components shown in FIG. 2 can be provided as a single semiconductor integrated circuit as indicated by the dashed line 280. Thus, the components of the analog circuitry receiving power in the lower power mode 236 and the components of the digital circuitry receiving power in the lower power mode 246 are also provided as part of the same integrated circuit.

[0051] In other embodiments, one or more of the storage capacitors 216, 238 and 248 can also be provided as part of the integrated circuit with the power management circuitry 200.

[0052] As described in greater detail below, the finite state machine 250 is used to manage the cycle of power management performed by the power management circuitry 200. A first voltage-based mode of operation and a second timing-based mode of operation will be described below. The low frequency oscillator 260 provides a timing signal that defines a timing unit used by the system. The controller 204 manages the circuitry upon receipt of a wake-up event to initiate a low power mode of operation of the power management circuitry and the multiplexing between wake-up events of the low power mode and finite state machine control signals.

[0053] Before describing the operation of the power management circuitry 200 in detail, reference will be made to Figure 3 The principles of the method of operation of the power circuitry will be described. The first portion 302 of the timing diagram shows the level of the regulator enable signal as a function of time. The second portion 304 of the timing diagram 300 shows the level of the output voltage of the regulator as a function of time. The third portion 306 shows the current drawn by the load connected to the output of the voltage regulator as a function of time. As Figure 3 shown, the load applied to the voltage regulator draws a substantially constant current. As will be appreciated by those of ordinary skill in the art, Figure 3 The discussion applies equally to the behavior of the analog voltage regulator 230 as well as the digital voltage regulator 240.

[0054] As can be seen, the regulator enable signal has a period of duration T. During an initial or first portion of the period, the regulator enable signal is high for a time Ton, and then during a subsequent second portion of the period, the regulator enable signal is low for a time Toff, and the duration of the period T is Ton + Toff. Thus, when the voltage regulator enable signal output by the controller 204 for the analog voltage regulator 230 or the digital voltage regulator 240 is high, then the current output by the voltage regulator is used to charge the respective capacitor attached to the power output line 232, 242.

[0055] Thus, as Figure 3 shown, during the time Ton, the level of the voltage of the capacitor attached to the output line increases. When the voltage regulator enable signal is de-asserted, then during the time Toff, the voltage of the storage capacitor decreases as the power source is connected to the electrical components that are stored on the storage capacitor, e.g., the analog components 236 connected to the analog voltage storage capacitor 238 or the digital components 246 connected to the digital voltage storage capacitor 248, are consumed. Thus, by controlling the portion T of the cycle in which the storage capacitor is charged, the overall power consumption can be reduced by a factor of Ton as compared to a mode of operation in which the storage capacitor is continuously charged.

[0056] The duration Ton can be programmed through registers of the finite state machine 250 and is defined by a number of low frequency oscillator clock cycles as read by the finite state machine 250 from the output of the local low frequency oscillator 260. The duration of Toff can be set using two different methods. In a first, timing based method, the duration of Toff can also be programmed through registers in the finite state machine 250 and again defined by a number of low frequency oscillator clock cycles. In an alternative mode of operation, the duration of Toff can be set by monitoring the voltage of the storage capacitor using the analog voltage monitor circuit 234 and the digital voltage monitor circuit 244, respectively.

[0057] By managing the proportion of the period T in which supply current is used to charge the storage capacitor, significant power consumption savings can be achieved. The power consumption savings can be expressed using the following formula:

[0058]

[0059] where:

[0060] : is the total current consumption in low power mode;

[0061] : is the load current of the analog circuit 236 and digital circuit 246;

[0062] : is the static current of modules that are always on during the voltage mode or timing mode;

[0063] : is the static current of modules that are always on during the voltage mode or timing mode;

[0064] : is the duration of the on timing duration of modules that are cycled during the voltage mode or timing mode; and

[0065] : is the duration of the voltage mode period or timing mode period. Thus, the overall power consumption can be reduced by a factor of Ton / T. In the case where the analog circuit 236 and / or digital circuit 246 consume power even in the sleep state of the electronic device, then using the voltage monitor mode of operation will save even more current compared to a purely timing based mode of operation.

[0066] Referring to

[0067] , a process flow diagram is shown that illustrates Figure 4 Figure 2 ​A purely timing-based method of operation of the power management circuitry is shown. The power management circuitry 200 uses a combination of linear power management and a finite state machine to reduce power consumption by managing the portion of a certain cycle in which the storage capacitors are charged. Figure 5 A graphical representation of a finite state machine 500 as implemented by the finite state machine circuitry 250 is shown. As will be appreciated by those of ordinary skill in the art, a finite state machine can be represented by states with associated actions and transitions between states with associated transition conditions. As Figure 5 As shown, the finite state machine 500 has a first on state 502 and a second off state 504. In Figure 3 The finite state machine can transition from the on state 502 to the off state 504 by transition 506 under the condition that the duration of the on period Ton expires. Similarly, the finite state machine 500 can transition between the off state 504 and the on state 502 by transition 508 under the transition condition that the duration of the off period Toff expires. Figure 3 The finite state machine can transition from the on state 502 to the off state 504 by transition 506 under the condition that the duration of the on period Ton expires. Similarly, the finite state machine 500 can transition between the off state 504 and the on state 502 by transition 508 under the transition condition that the duration of the off period Toff expires.

[0068] Also as Figure 5 As shown, during the on state 502, the finite state machine sets the logic state of the digital voltage regulator 240 to on and also sets the logic state of the analog voltage regulator 230 to on. A corresponding regulator enable signal is output by the finite state machine circuitry 250 to the controller 204, which supplies a corresponding control signal to the analog voltage regulator 230 through signal 239 and to the digital voltage regulator 240 through signal 249. Thus, at the beginning of the Ton period, the digital voltage regulator enable signal and the analog voltage regulator enable signal are set to high and the analog voltage regulator and the digital voltage regulator output current to charge the analog voltage storage capacitor 238 and the digital voltage storage capacitor 248, respectively. Thus, at 402, during the on period Ton, the voltage regulators operate to charge the storage capacitors. During the period Ton, the finite state machine circuitry 250 receives the low frequency oscillator signal on line 264 and counts the number of low frequency oscillator clock cycles and compares the count of low frequency oscillator clock cycles to a value stored in a register. When the number of low frequency oscillator clock cycles reaches the register value, the period Ton is determined to be expired and thus, at 404, the time period Ton is determined to be expired. Thus, the finite state machine 500 transitions to the off state 504.

[0069] In state 504, the digital voltage regulator state and the analog voltage regulator state are set to off, and a corresponding signal is output by the finite state machine circuitry 250 to the controller 204 that de-asserts the enable signals to the analog voltage regulator 230 and the digital voltage regulator 240, which stop operating at 406 and suspend outputting current to charge the respective storage capacitors. Thus, at 406, no current is supplied to the storage capacitors by the voltage regulator circuit. The finite state machine begins another count of the number of low frequency oscillator clock periods and compares the count to another value set in a register to determine when the Toff period has expired. During the time Toff, low power analog components 236 and / or digital components 246 that require power can receive power by discharging the analog storage capacitor 238 or the digital storage capacitor 248, respectively.

[0070] The finite state machine 250 continues to count the low frequency oscillator clock periods until it determines at 408 that the time period Toff has expired. Upon expiration of Toff, the finite state machine transitions from the off state 504 to the on state 502, in which the logic levels of the digital voltage regulator and the analog voltage regulator are set to high, and a corresponding regulator enable signal is output to the controller 204, which can then assert the enable signals to cause the analog voltage regulator and the digital voltage regulator to resume supplying current to the storage capacitors for the duration Ton. Thus, the operation of the circuit repeats with the finite state machine periodically turning on the voltage regulators to charge the storage capacitors and then turning off the voltage regulators.

[0071] Figure 6 Another finite state machine 510 is shown that is similar to the finite state machine that can also be implemented by the finite state machine circuitry 250. The finite state machine 510 generally operates in a similar manner to the finite state machine 500 and again has an on state 512 and an off state 514, with transitions from the on state to the off state 516 and from the off state to the on state 518. Similarly, a purely timing based mode of operation is provided in which the number of low frequency oscillator clock signals are counted and a register value is compared to determine the duration of the time periods Ton and Toff. However, in the finite state machine 510, in the off state, the finite state machine also changes the state of the voltage reference enable signal from high to low and outputs a corresponding control signal to the analog controller 204.

[0072] Accordingly, during the off, non-charging state, the analog control circuit 204 also disconnects the voltage reference circuit 212 to suspend charging of the reference voltage storage capacitor 216. Accordingly, and like the charging cycles for the analog and digital voltage storage capacitors, the power management circuit can also cause a charging cycle for the reference voltage storage capacitor 216. Accordingly, because of the purely timing-based approach for controlling the charging cycles, the analog and digital voltage monitor circuits 234 and 244 can be omitted.

[0073] Figure 7 A flowchart is shown that illustrates the voltage detection operating mode of the power management circuitry 200. Similar to the purely timing-based operating approach, a finite state machine is used to manage the proportion of the timing cycles in which the storage capacitors are charged and not charged by the voltage regulator circuit.

[0074] Figure 8 A graphical representation of a finite state machine 520 implemented by the finite state machine circuit 250 is shown. Similar to the previously described finite state machines, the finite state machine 520 has an on state 522 and an off state 524. The finite state machine can transition between the on, charging state and the off, non-charging state 524 by transition 526. The finite state machine 520 can also transition between the off, non-charging state 524 and the on, charging state 522 by transition 528. Similar to the finite state machines 500 and 510, the transition condition from the on, charging state to the off, non-charging state is the number of low frequency oscillator clock cycles that elapse since a value stored in a register of the finite state machine. However, unlike the previous examples, the transition condition from the off, non-charging state to the on, charging state is a determination that the voltage level of the analog voltage storage capacitor 238 or the digital voltage storage capacitor 248 has fallen below a certain threshold.

[0075] Returning to Figure 7In the on, charging state 522, at 702 the analog controller 204 asserts the control signal to enable the analog voltage regulator 230 and the digital voltage regulator 240 to output current to charge the analog voltage storage capacitor 238 and the digital voltage storage capacitor 248, respectively. At 702, the regulators continue to output current for a duration of a time period Ton. When the finite state machine determines that the time period Ton has expired based on a count of the number of local frequency oscillator clock cycles compared to a value stored in a register at 704, then the finite state machine transitions from the on, charging state 522 to the off, non-charging state 524 corresponding to step 706 of the method 700. At 706, the logic values of the digital voltage regulator enable signal and the analog voltage regulator enable signal are set to low and the corresponding signals output by the finite state machine circuitry 250 to the controller 204 disable the analog voltage regulator 230 and the digital voltage regulator 240 to cease charging the capacitors.

[0076] The analog voltage monitor circuit 234 and the digital voltage monitor circuit 244 monitor the level of voltage on the analog voltage storage capacitor 238 and the digital voltage storage capacitor 248, respectively. If the analog voltage monitor circuit 234 or the digital voltage monitor circuit 244 determines that the measured storage voltage level drops below a threshold, then the output signal on the line 235 or 245 changes state and is received by the finite state machine circuitry 250.

[0077] Accordingly, if at 708 it is determined that the analog voltage level or the digital voltage level has dropped below the threshold, then the finite state machine transitions from the off, non-charging state 524 to the on, charging state 522. Again, at 702 the finite state machine sets the analog voltage regulator enable signal and the digital voltage regulator enable signal to high and outputs signals to the analog controller 204 to enable the analog voltage regulator 230 and the digital voltage regulator 240, which begin to supply current to recharge the analog voltage storage capacitor 238 and the digital voltage storage capacitor 248 again.

[0078] Accordingly, the power management circuitry operates to charge the storage capacitors for a time period Ton set by the register value in the finite state machine. However, the duration of the time period Toff is adaptive and determined by the voltage level of the storage capacitors. Accordingly, in the event that any of the storage capacitors discharge more quickly, then Toff can be shorter, while in the event that the storage capacitors do not discharge as quickly, then Toff can have a longer duration because the analog circuit 236 or the digital circuit 246 is consuming less.

[0079] Figure 9A graphical representation of another finite state machine 530 similar to finite state machine 520 is shown. Again, finite state machine 530 has an on state 532, an off state 534, and a transition 536 from the on state to the off state with a transition condition of a number of clock cycles meeting a stored register value. Similarly, a transition from the off, non-charging state 534 to the on, charging state 532 has a transition condition of any stored capacitor voltage falling below a threshold value through transition 538.

[0080] Similar to Figure 6 As with finite state machine 510, finite state machine 530 also provides for a reference voltage cycle by turning off the reference voltage 212 during the off, non-charging state 534 to suspend charging of the reference voltage capacitor 216.

[0081] Thus, the circuitry and methods described herein are able to reduce power consumption in a low power mode of operation by enabling and disabling a low power module in a cyclical manner based on either a voltage mode of operation or a timing mode of operation. There is significant flexibility in the system. The duration of Ton can be programmed by a register in both the voltage mode of operation and the timing mode of operation. Also, Toff can be programmed by a register in the timing mode of operation. The entire circuitry is easy to implement as it can be provided as an additional digital solution. In some embodiments, the components of the power management circuitry 200 can be implemented as a single integrated circuit.

[0082] The circuitry and methods of operation can be particularly applicable to NFC devices in a standby mode of operation. Other areas of application include any battery operated electronic device, mobile electronic devices, and personal electronic devices where low power consumption is of particular relevance, such as smart watches and the like.

[0083] In this specification, example embodiments have been presented with respect to a selected group of details. However, it will be understood by one of ordinary skill in the art that many other example embodiments can be practiced including different selected groups of details. The following claims are intended to cover all possible example embodiments.

[0084] Unless a specific order is required, any instruction and / or flowchart step can be executed in any order. Also, one of ordinary skill in the art will recognize that, while one example set of instructions / method has been discussed, the material in this specification can also be combined in a variety of ways to produce other examples and should be understood to be within the context of the detailed description provided.

[0085] While the disclosure has been presented in terms of embodiments, it will be appreciated that other embodiments can be employed without departing from the scope of the disclosure. For example, although the disclosure has been described with respect to a particular order of steps, it will be appreciated that the steps can be performed in any order. Furthermore, the steps can be performed by different parties, or by the same party. Furthermore, the steps can be performed by different parties, or by the same party.

Claims

1. A power management circuit, characterized by, comprises: a power input for receiving power from a power source; a controller; a finite state machine circuit in communication with the controller; and a first voltage regulator in communication with the controller and the power input to receive power and having a first output connectable to a first capacitor for storing power and connectable to first circuitry, wherein the controller is configured to periodically enable the first voltage regulator to supply current to charge the first capacitor, and wherein the finite state machine circuit is configured to interact with the controller to control a duration of a first time period of a cycle in which the first voltage regulator supplies current to charge the first capacitor, and to control a duration of a second time period of the cycle in which the first voltage regulator does not supply current to charge the first capacitor and the first circuitry can receive current from the first capacitor.

2. The power management circuit of claim 1, wherein, and further comprising: a second voltage regulator in communication with the controller and the power input to receive power and having a second output connectable to a second capacitor for storing power and connectable to second circuitry, wherein the controller is configured to periodically enable the second voltage regulator to supply current to charge the second capacitor, and wherein the finite state machine circuit is configured to interact with the controller to control a duration of a first time period of a cycle in which the second voltage regulator supplies current to charge the second capacitor, and to control a duration of a second time period of the cycle in which the second voltage regulator does not supply current to charge the second capacitor and the second circuitry can receive current from the second capacitor.

3. The power management circuit of claim 2, wherein, the first capacitor stores power and is arranged to supply power to supply analog electrical components, and wherein the second capacitor stores power and is arranged to supply power to supply digital electrical components.

4. The power management circuit of any one of claims 1 to 3, wherein, and further comprising: a reference voltage circuit in communication with the controller and the power input to receive power and having a third output connectable to a reference voltage capacitor for storing power, wherein the controller is configured to periodically enable the reference voltage circuit to supply current to charge the reference voltage capacitor, and wherein the finite state machine circuit is configured to interact with the controller to control a duration of a first time period of a cycle in which the reference voltage circuit supplies current to charge the reference voltage capacitor, and to control a duration of a second time period of the cycle in which the reference voltage circuit does not supply current to charge the reference voltage capacitor.

5. The power management circuit of any one of claims 1 to 3, wherein, and further comprising a low frequency oscillator in communication with the controller and the finite state machine circuit, and wherein the finite state machine circuit is configured to control the duration of the first time period based on a number of cycles of the low frequency oscillator.

6. The power management circuit of claim 5, wherein, The finite state machine circuit comprises a first programmable register, and wherein a value set in the first programmable register is used to determine the duration of the first time period.

7. The power management circuit of claim 5, wherein, The finite state machine circuit is further configured to control the duration of the second time period based on a number of cycles of the low frequency oscillator.

8. A package including a semiconductor integrated circuit, characterized by comprising: The semiconductor integrated circuit is configured to provide a power management circuit according to any one of claims 1 to 7.

9. An electronic device, comprising: comprises a power management circuit according to any one of claims 1 to 7 or a package according to claim 8, a power source connected to the power input, a first capacitor connected to the first output, and first circuitry connected to the first output.

10. A method of managing power consumption based on the power management circuit of claim 1, characterized by, The method comprises: controlling a voltage regulator to periodically supply current to charge a capacitor; and using a finite state machine to control a duration of a first time period of a cycle of the voltage regulator supplying current to charge the capacitor, and a duration of a second time period of the cycle of the voltage regulator not supplying current to not charge the capacitor and the capacitor discharging to supply current to circuitry.

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