Transistor, transistor array, memory cell array each including a capacitor and a transistor extending in a vertical direction, and method of forming a transistor array

Abstract

A transistor is disclosed that includes semiconductor material that is substantially L-shaped or substantially mirrored L-shaped in at least one straight vertical cross-section thereby having a stem extending in the vertical direction and a base extending horizontally from a lateral side of the stem above the base of the stem. The semiconductor material of the stem includes an upper source / drain region and a channel region therebelow. The transistor includes at least one of (a) and (b), wherein (a): the semiconductor material of the stem includes a lower source / drain region below the channel region, and (b): the semiconductor material of the base includes a lower source / drain region. A gate is operably laterally adjacent to the channel region of the stem. Other embodiments are disclosed that include memory cell arrays that individually include capacitors and transistors extending in the vertical direction. Methods are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to transistors, transistor arrays, memory cell arrays each including a capacitor and a transistor extending in a vertical direction. Background Art

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written or read using digit lines (which may also be referred to as bit lines, data lines, sense lines, or data / sense lines) and word lines (which may also be referred to as access lines). Digit lines conductively interconnect memory cells along columns of the array, and word lines conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and word lines.

[0003] Memory cells can be volatile or non-volatile. Non-volatile memory cells can store data for long periods of time, including when the computer is turned off. Volatile memory consumes and therefore needs to be refreshed / rewritten, in many cases, multiple times per second. Regardless, the memory cells are configured to save or store memory in at least two different selectable states. In a binary system, the states are considered to be either "0" or "1." In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

[0004] Capacitors are a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be electrostatically stored in this material. Depending on the composition of the insulator material, the stored electric field will be volatile or non-volatile. For example, a capacitor insulator material that only contains SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states and thereby can include programmable materials for capacitors and / or memory cells. The polarization state of the ferroelectric material can be changed by applying a suitable programming voltage and maintained (at least for a period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from each other and can ideally be used to write (i.e., store) and read the memory state without reversing the polarization state until it is desired to reverse this polarization state. In some memories with ferroelectric capacitors, the action of less expected reading of the memory state can reverse the polarization. Therefore, after determining the polarization state, a rewrite of the memory cell is performed to place the memory cell in a pre-read state immediately after it is determined. Regardless, memory cells incorporating ferroelectric capacitors are ideally nonvolatile due to the bi-stable nature of the ferroelectric material that forms part of the capacitor.Other programmable materials can be used as capacitor insulators to render the capacitor nonvolatile.

[0005] Field effect transistors are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductor channel region between them. A conductive gate is adjacent to the channel region and is separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures (e.g., reversibly programmable charge storage regions) as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator may be programmable, for example, ferroelectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagrammatic perspective view of a substrate configuration including a memory cell array according to an embodiment of the present invention.

[0007] Figure 2 yes Figure 1 Diagrammatic front view of the structure and through Figure 1 Line 2-2 in Get.

[0008] Figure 3 yes Figure 1 A cross-sectional view of a portion of the structure and through Figure 1 Line 3-3 in Get.

[0009] Figure 4 is a diagrammatic front view of a substrate configuration including a memory cell array according to an embodiment of the present invention.

[0010] Figure 5 is a diagrammatic front view of a substrate configuration including a memory cell array according to an embodiment of the present invention.

[0011] Figure 6 According to an embodiment of the present invention, in the process Figure 2 Schematic front view of a portion of a substrate construction before substrate construction.

[0012] Figure 7 yes Figure 6 Perspective view of the construction.

[0013] Figure 8 It is in the Figure 6 The processing steps shown below are Figure 6 Constructed view.

[0014] Fig. 9 It is in the Figure 8 The processing steps shown below are Figure 8 Constructed view.

[0015] Fig.10 It is in the Fig. 9 The processing steps shown below are Fig. 9 Constructed view.

[0016] Fig.11 It is in the Fig.10 The processing steps shown below are Fig.10 Constructed view.

[0017] Fig.12 yes Fig.11 Perspective view of the construction.

[0018] Fig.13 It is in the Fig.12 The processing steps shown below are Fig.12 Constructed view.

[0019] Fig.14 According to an embodiment of the present invention, in the process Figure 2 Schematic front view of a portion of a substrate construction before substrate construction.

[0020] Fig.15 It is in the Fig.14 The processing steps shown below are Fig.14 Constructed view.

[0021] Fig.16 It is in the Fig.15 The processing steps shown below are Fig.15 Constructed view.

[0022] Fig.17 It is in the Fig.16 The processing steps shown below are Fig.16 Constructed view.

[0023] Fig.18 It is in the Fig.17 The processing steps shown below are Fig.17 Constructed view.

[0024] Fig.19 It is in the Fig.18 The processing steps shown below are Fig.18 Constructed view. DETAILED DESCRIPTION

[0025] Embodiments of the present invention include transistors, transistor arrays, memory cell arrays each including a capacitor and a transistor extending in a vertical direction, and methods of forming a transistor array. Figures 1 to 3 Describing example embodiments, Figures 1 to 3An example fragment of a substrate construction 8 is shown that includes an array or array region 10 that has been fabricated relative to a base substrate 11. The substrate 11 may include any one or more of a conductive / conductor / conductive (i.e., electrically conductive herein), a semiconductive / semiconductor / semiconductive, and an insulating / insulator / insulating (i.e., electrically insulating herein) material. Various materials are above the base substrate 11. The materials may be Figures 1 to 3 The depicted material may be adjacent to, vertically inwardly or vertically outwardly of the material depicted. For example, other partially or fully manufactured components of the integrated circuit may be provided somewhere above, around or within the base substrate 11. Control and / or other peripheral circuitry for operating components within the memory array may also be manufactured and may be completely or partially or may not be completely or partially within the memory array or sub-array. In addition, multiple sub-arrays may also be manufactured and operated independently, in conjunction, or in other ways relative to each other. As used in this document, a "sub-array" may also be considered an array. For the sake of greater brevity of certain operational components, Figure 1 The base substrate 11 is not shown and Figure 1 and 3 Surrounding dielectric isolation material is not shown. Array 10 includes memory cells 85 that individually include capacitor 75 and transistor 25 extending in a vertical direction. In one embodiment, transistor 25 is vertical or within 10° of vertical.

[0026] In one embodiment and as shown, transistors 25 each include at least one straight vertical cross-section (e.g., Figure 2 ) is a semiconductor material 12 (e.g., variously doped silicon) that is generally L-shaped or generally mirrored L-shaped in cross-section as shown in FIG. In one such embodiment and as shown, transistors 25 may be viewed as being arranged as individual pairs of laterally adjacent transistors, e.g., in Figure 2, the two transistors 25 on the left are one pair and the two transistors 25 on the right are another pair. One individual (e.g., bulk thereof) of the semiconductor material 12 within each pair of laterally adjacent transistors (e.g., the transistor 25 illustrated on the left in each pair) is generally L-shaped in at least one straight vertical cross-section. The other individual semiconductor material 12 within each pair of laterally adjacent transistors 25 (e.g., each of the transistors 25 illustrated on the right in each pair) is generally a mirror image L-shaped in at least one straight vertical cross-section. In one embodiment and as shown, the pairs of laterally adjacent transistors 25 are laterally separated from each other further than the individual transistors 25 within each pair of laterally adjacent transistors are laterally separated from each other. For example and by way of example only, the transistors 25 within each pair of such transistors are shown as being laterally separated by 14U and the left pair of transistors 25 is shown as being laterally separated by 18U from the right pair of transistors 25. "U" is used for convenience to designate a single "unit" of length, where the numerical prefix preceding it indicates the number of such units in the vertical and horizontal directions of the depicted example. The figures are drawn to scale according to "U". An example unit "U" is 1 nanometer. Thus, in some embodiments, 14U may be 14 nanometers and 18U may be 18 nanometers.

[0027] The substantially L-shaped or substantially mirrored L-shaped semiconductor material 12 has a vertically extending stem 14 with lateral sides 15 and a bottom 16. The semiconductor material 12 also has a base 17 extending horizontally from the stem lateral sides 15 above the stem bottom 16. The semiconductor material 12 of the stem 14 includes an upper source / drain region 18 and a channel region 20 thereunder. The transistor 25 includes at least one of (a) and (b), wherein (a): the semiconductor material of the stem includes a lower source / drain region below the channel region, and (b): the semiconductor material of the base includes a lower source / drain region. Figure 1 and 2 Example embodiments are shown that include (a), and in one such embodiment, as shown, only (a) of (a) and (b), specifically, wherein the semiconductor material 12 of the rods 14 includes a lower source / drain region 22 below the channel region 20.

[0028] exist Figure 4 An alternative example embodiment configuration 8a including transistor 25a is shown in FIG. 8 . Like numerals from the above-described embodiments have been used as necessary, with the use of the suffix "a" to indicate some configuration differences. Transistor 25a includes (b), and in one such embodiment, as shown, only (b) of (a) and (b), specifically, wherein the semiconductor material 12 of substrate 17 includes lower source / drain regions 22a and channel region 20a. Figure 5Another alternative example construction 8b of transistor 25b is shown. Like numerals from the above embodiments have been used as necessary, with the suffix "b" being used to indicate some construction differences. Figure 5 An example embodiment is shown in which the lower source / drain region 22b includes both (a) and (b), specifically, in which the rods 14 and the semiconductor material 12 of the base 17 include the lower source / drain region 22b.

[0029] The gate 24 (e.g., a metal material and / or a conductively doped semiconductor material) is operably laterally adjacent to the channel region 20 of the rod 14, for example, with a gate insulator 26 (e.g., comprising, essentially consisting of, or consisting of silicon dioxide, silicon nitride and / or ferroelectric material) between the channel region 20 / 20a and the gate 24.

[0030] For simplicity, the upper and lower source / drain regions are shown in the figure using stippling. Each of the source / drain regions 18 / 22 / 22a / 22b includes a conductivity-increasing dopant in at least a portion thereof, the portion having a maximum concentration of such conductivity-increasing dopant in the corresponding source / drain region (e.g., having at least 10 19 Atom / cm 3 The channel regions 20 / 20a may use a conductivity type that may be opposite to that of the dopants in the source / drain regions and, for example, may be at a level not greater than 10 Å. 16 Atom / cm 3 The maximum concentration of conductivity increasing dopants in the channel region is appropriately doped. When a suitable voltage is applied to the gate 24, a conductive channel can be formed in the channel region 20 / 20a so that current can flow between the upper and lower source / drain regions.

[0031] The array 10 includes rows 28 of word lines 30 (e.g., metallic material and / or conductive doped semiconductor material) and columns 32 of digit lines 34 (e.g., metallic material and / or conductive doped semiconductor material). As used herein, "rows" and "columns" refer to a series of word lines and a series of digit lines, respectively, and the longitudinal direction along which individual memory cells 85 are received within the array 10. Rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns intersect relative to each other at 90° or at one or more other angles. Individual gates 24 are individual portions of individual word lines 30. In one embodiment, pairs of laterally adjacent word lines (e.g., the two left illustrated word lines 30 are one pair and the two right illustrated word lines 30 are another pair) are laterally separated from each other farther (e.g., 30U) than individual word lines 30 within each pair of laterally adjacent word lines 30 are laterally separated from each other (e.g., 14U).

[0032] The digit lines 34 of individual columns 32 are below (in one embodiment, directly below) the channel regions 20 / 20a of the transistors 25 / 25a / 25b of the individual memory cells 85 within the array 10 and interconnect the transistors 25 / 25a / 25b in the columns 32. The channel regions 20 / 20a can be considered to individually have a pair of opposing lateral sides 36. In individual rows 28, the word lines 30 are above the digit lines 34. The word lines 30 extend laterally across one of the pair of laterally opposing sides 36 of the transistor channel regions 20 / 20a and are operatively laterally adjacent to the one of the pair of laterally opposing sides 36 of the transistor channel regions 20 / 20a and interconnect the transistors 25 / 25a / 25b in the row. In one embodiment and as shown, the other of the pair of laterally opposing sides 36 of the transistor channel regions 20 / 20a in the row 28 is not operatively laterally adjacent to the word lines 30 in the row 28 and is not operatively laterally adjacent to any other of the word lines 30.

[0033] The capacitors 75 of individual memory cells 85 within the array 10 individually include a first capacitor electrode 40 (e.g., a metallic material and / or a conductively doped semiconductor material) electrically coupled to (in one embodiment, directly electrically coupled to) an upper source / drain region 18 of one of the transistors 25 / 25a / 25b and extending vertically upward from the upper source / drain region 18. The first capacitor electrode 40 has laterally opposing sides 35. In one embodiment and as shown, the first capacitor electrode 40 directly abuts against an uppermost surface 42 of the upper source / drain region 18, and in one such embodiment directly abuts against less than all of the upper source / drain region uppermost surface 42, and in one embodiment, as shown, directly abuts against less than half of all of the upper source / drain region uppermost surface 42. In one embodiment, more than half of a lowermost surface 43 of the first capacitor electrode 40 directly abuts against the upper source / drain region uppermost surface 42.

[0034] The capacitors 75 each include a vertically extending capacitor insulator 46 (e.g., including, consisting essentially of, or consisting of silicon dioxide, silicon nitride, and / or ferroelectric material) that includes a pair of laterally opposing sides 47, 49. One of the laterally opposing sides 47, 49 is operably adjacent to (in one embodiment, directly abutting) the lateral side 35 of the first capacitor electrode 40. In one such example, at least a majority (in one embodiment, all) of one laterally opposing side of the capacitor insulator and the lateral side 35 of the first capacitor electrode 40 are each linearly straight (e.g., and vertical) in a horizontal cross-section from top to bottom where they are directly abutting each other (e.g., as shown in FIG. 1 ). Figure 1 is obvious in the figure).

[0035] The capacitors 75 individually include a second capacitor electrode 50 extending in a vertical direction, the second capacitor electrode 50 extending in the vertical direction including a pair of laterally opposing sides 51, 53. One of the laterally opposing sides 51, 53 of the second capacitor electrode 50 is operably adjacent to (in one embodiment, directly against) the other laterally opposing side 47 or 49 of the capacitor insulator 46. In one embodiment and as shown, the second capacitor electrodes 50 within the array 10 are longitudinally spaced elongated lines 52 extending horizontally along a line 55 of capacitors 75, wherein individual ones of the second capacitor electrode lines 52 are shared by capacitors 75 longitudinally along the line 55 of capacitors 75. Example dielectric material 77 ( Figure 2 ; For example, silicon dioxide and / or silicon nitride) surrounds other components, such as shown. For greater clarity of other materials and components, Figure 1 and 3 The dielectric material 77 is not shown.

[0036] In one embodiment, second capacitor electrode line 52 is individually wider than individual word lines 30, and in one such embodiment, more than two times wider than individual word lines 30, in one such embodiment, at least five times wider, and in one such embodiment, no more than five times wider (e.g., five times, shown as 20U vs. 4U). In one embodiment, second capacitor electrode line 52 is individually wider than individual digit lines 34, and in one such embodiment, less than two times wider than individual digit lines 34 (e.g., 20U vs. 12U).

[0037] In one embodiment, the word lines 30 are parallel with respect to each other, and the second capacitor electrode lines 52 are parallel with respect to each other and with respect to the word lines 30. In one embodiment, the digit lines 34 are parallel with respect to each other, and the second capacitor electrode lines 52 are parallel with respect to each other and are not parallel with respect to the digit lines 34. In one embodiment, the first capacitor electrodes 40 each extend longitudinally along their respective second capacitor electrode lines 52 by a horizontal distance (e.g., 24U) that is greater than the horizontal distance (e.g., 8U) of the space along the line 55 of the capacitor 75 between the longitudinally adjacent first capacitor electrodes 40. In one embodiment, the respective pairs of laterally adjacent word lines 30 have at least a portion thereof directly below the respective second capacitor electrode lines 52.

[0038] In one embodiment and as shown, memory cells 85 within a layer of memory cells have translational symmetry, where individual ones of memory cells 85 are 1T-1C (i.e., memory cells having only one transistor and only one capacitor and no other / additional operable electronic components [e.g., no other selection devices, etc.]) and occupy approximately 1.0667F 2 , where "F" is the memory cell pitch taken horizontally, laterally, and orthogonally through the individual second capacitor electrode lines 52, capacitor insulators 46, and first capacitor electrodes 40. In one such embodiment, the horizontal area is defined by a 1F×1.0667F rectangle 95 ( Figure 2 ). For example and by way of example only, this rectangle may be 32U×30U, as shown. Also and by way of example only, in Figure 2 , 4 Example vertical and horizontal dimensions of semiconductor material 12, gate insulator 26, word lines 30, spaces between word lines 30, and spaces between such word lines and pairs of transistors 25 / 25a / 25b are shown in FIG. 5. Furthermore, by way of example only and in one embodiment, in FIG. Figure 1 Example digital line widths (e.g., 12U) and spaces between them (e.g., 20U) are shown in FIG. In an ideal embodiment, (several) alternative sizes and spacings can certainly be combined to occupy about 1.0667F. 2 The horizontal area individual memory cells use.

[0039] Embodiments of the present invention include methods of forming a transistor array, and then refer to Figures 6 to 13 Describe the method, Figures 6 to 13 Show relative to Figures 1 to 3 The same numbers and materials have been used for the previous construction.

[0040] refer to Figure 6 and 7, template lines 60 have been formed laterally spaced, vertically protruding, and longitudinally elongated above substrate 11. Template lines 60 may be partially or fully sacrificial, or may be non-sacrificial. If non-sacrificial, template lines 60 desirably comprise an insulator material (e.g., silicon dioxide). Construction 8 may be viewed as including voids 61 laterally interposed between laterally adjacent template lines 60.

[0041] refer to Figure 8 , semiconductor material 12 has been formed along the sidewalls of template lines 60 and over substrate 11, the semiconductor material 12 being laterally interposed between template lines 60 to incompletely fill voids 61. Semiconductor material 12 may be etched back or polished after deposition to reduce its thickness above horizontal surfaces compared to vertical surfaces. In any case, after semiconductor material 12 is formed, insulator material 26 has been formed along the sidewalls of semiconductor material 12 and over semiconductor material 12, the insulator material 26 being laterally interposed between template lines 60 to incompletely fill the remaining volume of voids 61 laterally interposed between laterally adjacent template lines 60.

[0042] refer to Fig. 9 , after forming insulator material 26, conductive material 87 has been formed along the sidewalls of insulator material 26 and over substrate 11, the conductive material 87 being laterally interposed in voids 61 between template lines 60. In one embodiment and as shown, after forming insulator material 26, conductive material 87 is formed to not completely fill the remaining volume of voids 61 laterally interposed between template lines 60.

[0043] refer to Fig. 9 and 10 , removed as Fig. 9 10 to form two word lines 30 therefrom between laterally adjacent template lines 60. In a desired embodiment, the lateral middle portion 65 of the conductive material 87 is removed by a maskless anisotropic etch (i.e., maskless at least within the array 10). Example doping for the upper source / drain regions 18, channel regions 20, and lower source / drain regions 22 may occur at, before, and / or after this point in processing as shown.

[0044] By this, Fig.11 and 12 Subsequent processing is shown, for example, in one embodiment, word line 30 has been used as a mask when anisotropically etching through insulator material 26 and semiconductor material 12 .

[0045] refer to Fig.13, semiconductor material 12 has been patterned (e.g., by photolithographic patterning and etching) to form blocks of semiconductor material 12 spaced longitudinally along individual word lines 30. Example blocks 12 are generally L-shaped or generally mirrored L-shaped in at least one straight vertical cross-section, thereby having rods 14 ( Figure 2 ) and a substrate 17 extending horizontally from a lateral side 15 of the rod 14 above the bottom 16 of the rod 14. The semiconductor material 12 of the rod 14 ultimately includes a source / drain region 18 on the forehead of an individual transistor 25 and a channel region 20 thereunder. Such a transistor 25 includes at least one of (a) and (b), wherein (a): the semiconductor material of the rod includes a lower source / drain region below the channel region of the individual transistor, and (b): the semiconductor material of the substrate includes a lower source / drain region ( Fig.13 Not shown in, but in Figure 4 and 5 ). An individual word line 30 is operatively laterally adjacent to the channel region 20 of an individual transistor 25 and interconnects the transistors 25 along the individual word line 30 .

[0046] refer to Figures 14 to 19 An example method is shown and described by which capacitor 75 may be formed. Again, the same numbers as in the above embodiments have been used for the previous construction and materials.

[0047] refer to Fig.14 , already on substrate 11( Fig.14 A material 66 is formed over the second capacitor electrode line 52 (not shown). A trench 67 corresponding to the longitudinal profile and shape of the second capacitor electrode line 52 has been formed in the material 66, and the trench 67 has been filled with a suitable conductive material as shown to thus form the line 52. This may occur, for example, by depositing such conductive material and flattening such conductive material at least back to the vertically outermost surface of the material 66. The material 66 may be completely sacrificial, and therefore, may include any of conductive, semiconductive, and insulator materials. One example is silicon dioxide. The conductive material of the second capacitor electrode line 52 and the substrate material below the material 66 are not shown, but may be, for example, as shown in FIG. Fig.13 It is presented as shown in the video.

[0048] refer to Fig.15 , material 66 (not shown) has been selectively removed relative to the depicted conductive material of second capacitor electrode line 52 .

[0049] refer to Fig.16 , capacitor insulator 46 is deposited and etched back (eg, by anisotropic etching without a mask at least in array region 10).

[0050] refer to Fig.17, conductive material 89 has been deposited along the sidewalls of capacitor insulator 46. This conductive material has subsequently been etched back, for example, by an anisotropic spacer etch of material 46 within array region 10 (e.g., by an anisotropic etch without a mask at least within array region 10) to substantially remove it from above the horizontal surfaces.

[0051] refer to Fig.18 , masking material 71 has been deposited and patterned into lines 72.

[0052] refer to Fig.19 , line 72 (not shown) has been used as a mask when anisotropically etching conductive material 89 to form first capacitor electrode 40 as shown, for example, to produce Figure 1 The upper part of the structure shown in Fig.19 Line 72 (not shown) has been removed.

[0053] Any of the attributes or aspects shown and / or described herein with respect to the structural embodiments may be used in the method embodiments and vice versa. The pitch multiplication principle may be used in the method aspects of the invention (e.g., a feature may be formed along the sidewall of another feature to have a lateral thickness that is less than the lateral thickness of the other feature regardless of how the other feature is formed).

[0054] In this document, unless otherwise indicated, "vertically", "higher", "up", "lower", "top", "top", "bottom", "above", "below", "down", "below", "upward", and "downward" are generally relative to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees) and may be relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "completely horizontal" is a direction along the surface of the main substrate (i.e., not angled thereto), and may be relative to the direction in which the substrate is handled during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally relative to directions that are perpendicular to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "elevationally-extending / extend(ing)elevationally" refers to a direction that is inclined at least 45° from completely horizontal. Furthermore, with respect to field effect transistors, "extend(ing) elevationally / elevationally-extending" and "extend(ing) horizontally / horizontally-extending" refer to the orientation of the transistor's channel length along which current flows between source / drain regions in operation. For bipolar junction transistors, "extend(ing) elevationally / elevationally-extending" and "extend(ing) horizontally / horizontally-extending" refer to the orientation of the base length along which current flows between emitter and collector in operation.

[0055] Furthermore, "directly above" and "directly below" require at least some lateral overlap (i.e., horizontally) of the two regions / materials / components relative to each other. Furthermore, the use of "above" without a preceding "directly" only requires that some portion of the region / material / component above another region / material / component is vertically outward from the other region / material / component (i.e., regardless of whether there is any lateral overlap of the two regions / materials / components). Similarly, the use of "below" without a preceding "directly" only requires that some portion of the region / material / component below another region / material / component is vertically inward from the other region / material / component (i.e., regardless of whether there is any lateral overlap of the two regions / materials / components).

[0056] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying it. In addition, unless otherwise stated, each material may be formed using any suitable or yet to be developed technology, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0057] In addition, "thickness" itself (without directional adjectives before) is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of the adjacent material or adjacent region of different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, the thickness refers to the average thickness, unless otherwise indicated, and due to the variable thickness, this material or region will have a certain minimum thickness and a certain maximum thickness. As used herein, "different compositions" only require that the parts of the two materials or regions that can directly abut against each other are chemically and / or physically different, for example, provided that such materials or regions are heterogeneous. If the two materials or regions are not directly against each other, then "different compositions" only require that the parts of the two materials or regions that are closest to each other are chemically and / or physically different, provided that such materials or regions are heterogeneous. In this document, when the materials, regions or structures are in at least some physical contact contact relative to each other, the materials, regions or structures are "directly against" each other. In contrast, the words “above,” “on,” “adjacent,” “along,” and “against” without the word “directly” in front of them encompass “directly against” as well as configurations in which intervening material(s), region(s), or structure(s) do not result in physical touching contact of the materials, regions, or structures relative to each other.

[0058] As used herein, regions, materials, and components are "electrically coupled" relative to one another if, in normal operation, electrical current can flow continuously from one of the regions, materials, and components to the other and primarily through the movement of subatomic positive and / or negative charges (when sufficient subatomic positive and / or negative charges are generated). Another electronic component may be between and electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0059] Additionally, a "metal material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any conductive metal compound.

[0060] in conclusion

[0061] In some embodiments, a memory cell array individually includes a capacitor and a transistor extending in a vertical direction, wherein the array includes rows of word lines and columns of digit lines, including individual ones of the columns, the individual ones including the digit lines below the channel regions of the vertically extending transistors of the individual memory cells within the array and interconnecting the transistors in the columns. The channel regions individually include a pair of opposing lateral sides. Individual ones of the rows include word lines above the digit lines. The word lines extend laterally across one of the pair of laterally opposing sides of the transistor channel regions and are operably laterally adjacent to the one of the pair of laterally opposing sides of the transistor channel regions and interconnect the transistors in the row. The other one of the pair of laterally opposing sides of the transistor channel regions in the row is not operably laterally adjacent to the word line in the row and is not operably laterally adjacent to any other of the word lines. The capacitors of the individual memory cells within the array individually include a first capacitor electrode, the first capacitor electrode being electrically coupled to an upper source / drain region of one of the transistors and extending vertically upward from the upper source / drain region. A capacitor insulator extending in a vertical direction includes a pair of laterally opposing sides, one of which is operably adjacent to a lateral side of a first capacitor electrode. A second capacitor electrode extending in a vertical direction includes a pair of laterally opposing sides, one of which is operably adjacent to another laterally opposing side of the capacitor insulator. The second capacitor electrodes within the array are longitudinally spaced elongated lines extending horizontally along a line of capacitors. Individuals of the second capacitor electrode lines are shared by capacitors longitudinally along the line of capacitors.

[0062] In some embodiments, an array of memory cells individually includes capacitors and vertically extending transistors, wherein the array includes rows of word lines and columns of digit lines, including individual ones of the columns, the individual ones including digit lines below the channel regions of the vertically extending transistors of the individual memory cells within the array and interconnecting the transistors in the row. The channel regions individually include a pair of opposing lateral sides. Individual ones of the rows include word lines above the digit lines. The word lines extend laterally across one of the pair of laterally opposing sides of the transistor channel regions and are operably laterally adjacent to the one of the pair of laterally opposing sides of the transistor channel regions and interconnecting the transistors in the row. The other one of the pair of laterally opposing sides of the transistor channel regions in the row is not operably laterally adjacent to the word line in the row and is not operably laterally adjacent to any other of the word lines. The capacitors of the individual memory cells within the array individually include a first capacitor electrode, the first capacitor electrode directly abutting against the uppermost surface of the upper source / drain region of one of the transistors and extending vertically upward from the uppermost surface. The first capacitor electrode directly abuts against less than all of the uppermost surface of the upper source / drain region. The capacitor insulator extending in the vertical direction includes a pair of laterally opposite sides, one of which is operably adjacent to the lateral side of the first capacitor electrode. The second capacitor electrode extending in the vertical direction includes a pair of laterally opposite sides, one of which is operably adjacent to the other laterally opposite side of the capacitor insulator.

[0063] In some embodiments, a memory cell array includes capacitors and vertically extending transistors, wherein the array includes rows of word lines and columns of digit lines, including individual ones of the columns, the individual ones including digit lines below the channel regions of the vertically extending transistors of the individual memory cells in the array and interconnecting the transistors in the columns. Individual ones of the rows include word lines above the digit lines. The word lines extend laterally across the lateral sides of the transistor channel regions and are operably laterally adjacent to the lateral sides of the transistor channel regions and interconnecting the transistors in the rows. The capacitors of the individual memory cells in the array each include a first capacitor electrode, the first capacitor electrode being electrically coupled to the upper source / drain region of one of the transistors and extending vertically upward from the upper source / drain region. The capacitor insulator extending vertically includes a pair of laterally opposite sides, one of the pair of laterally opposite sides being operably adjacent to the lateral side of the first capacitor electrode. The second capacitor electrode extending vertically includes a pair of laterally opposite sides. One of the laterally opposite sides of the second capacitor electrode is operably adjacent to the other laterally opposite side of the capacitor insulator. The second capacitor electrodes within the array are longitudinally spaced elongated lines extending horizontally along the line of capacitors. Individual ones of the second capacitor electrode lines are shared by capacitors longitudinally along the line of capacitors. Individual pairs of laterally adjacent word lines have at least portions thereof directly below individual second capacitor electrode lines.

[0064] In some embodiments, a transistor includes a semiconductor material that is substantially L-shaped or substantially mirrored L-shaped in at least one straight vertical cross-section, thereby having a stem extending vertically and a base extending horizontally from a lateral side of the stem above the bottom of the stem. The semiconductor material of the stem includes an upper source / drain region and a channel region therebelow. The transistor includes at least one of (a) and (b), wherein (a): the semiconductor material of the stem includes a lower source / drain region below the channel region, and (b): the semiconductor material of the base includes a lower source / drain region. The gate is operably laterally adjacent to the channel region of the stem.

[0065] In some embodiments, a method of forming a transistor array includes: forming laterally spaced, vertically protruding, and longitudinally elongated template lines above a substrate. Forming semiconductor material along the sidewalls of the template lines and above the substrate, the semiconductor material laterally interposed between the template lines to incompletely fill the gaps laterally between the laterally adjacent template lines. After forming the semiconductor material, forming an insulator material along the sidewalls of the semiconductor material and above the semiconductor material, the insulator material laterally interposed between the template lines to incompletely fill the remaining volume of the gaps laterally between the laterally adjacent template lines. After forming the insulator material, forming a conductive material along the sidewalls of the insulator material and above the insulator material, the conductive material laterally interposed between the template lines in the gaps laterally between the laterally adjacent template lines. Removing a laterally intermediate portion of the conductive material to form two word lines therefrom between the laterally adjacent template lines. Patterning the semiconductor material to form a block of semiconductor material spaced longitudinally along individual ones of the word lines. The block is substantially L-shaped or substantially mirrored L-shaped in at least one straight vertical cross-section, thereby having a rod extending vertically and a base extending horizontally from a lateral side of the rod above the bottom of the rod. The semiconductor material of the rod ultimately includes the upper source / drain region of the individual transistor and the channel region thereunder. The transistor includes at least one of (a) and (b), wherein (a): the semiconductor material of the rod includes the lower source / drain region below the channel region of the individual transistor, and (b): the semiconductor material of the substrate includes the lower source / drain region of the individual transistor. Individual word lines are operatively laterally adjacent to the channel region of the individual transistor and interconnect the transistors along the individual word lines.

Claims

1. A memory cell array, each comprising a capacitor and a transistor extending in a vertical direction, the array comprising rows of word lines and columns of digit lines, comprising: Individual ones of the columns include digit lines underlying channel regions of vertically extending transistors of individual memory cells within the array and interconnecting the transistors in the columns, the channel regions individually including a pair of opposing lateral sides; individual ones of the rows include a word line above the digit line, the word line extending laterally across and operably laterally adjacent to one of the pair of laterally opposing sides of the transistor channel region and interconnecting the transistors in the row, the other one of the pair of laterally opposing sides of the transistor channel region in the row not being operably laterally adjacent to the word line in the row and not being operably laterally adjacent to any other of the word lines; and The capacitors of the individual memory cells within the array individually include: a first capacitor electrode electrically coupled to an upper source / drain region of one of the transistors and extending vertically upward from the upper source / drain region; a vertically extending capacitor insulator including a pair of laterally opposing sides, one of the laterally opposing sides of the capacitor insulator being operably adjacent to a lateral side of the first capacitor electrode; and a second capacitor electrode extending vertically and including a pair of laterally opposing sides, one of the laterally opposing sides of the second capacitor electrode being operably adjacent to the other laterally opposing side of the capacitor insulator, the second capacitor electrodes within the array being longitudinally spaced elongated lines extending horizontally along the line of capacitors, individual ones of the second capacitor electrode lines being shared by capacitors longitudinally along the line of capacitors.

2. The array of claim 1 , wherein the one laterally opposing side of the capacitor insulator directly abuts the lateral side of the first capacitor electrode, and at least a majority of the one laterally opposing side of the capacitor insulator and the lateral side of the first capacitor electrode are each linearly straight in a horizontal cross-section from top to bottom where they directly abut each other.

3. The array of claim 2 wherein all of the one laterally opposing side of the capacitor insulator and the lateral side of the first capacitor electrode are each linearly straight side-by-side in horizontal cross-section from top to bottom where they abut directly against each other.

4. The array of claim 1, wherein the first capacitor electrode directly abuts an uppermost surface of the upper source / drain region, the first capacitor electrode directly abutting less than all of the uppermost surface of the upper source / drain region.

5. The array of claim 1 wherein the first capacitor electrodes individually extend longitudinally along their respective second capacitor electrode lines a horizontal distance that is greater than the horizontal distance of the spaces along the lines of capacitors between the longitudinally adjacent first capacitor electrodes.

6. The array of claim 1 wherein the word lines are parallel with respect to each other and the second capacitor electrode lines are parallel with respect to each other and with respect to the word lines.

7. The array of claim 1, wherein the digit lines are parallel with respect to each other, and the second capacitor electrode lines are parallel with respect to each other and not parallel with respect to the digit lines.

8. The array of claim 1 wherein the memory cells within a layer of the memory cells have translational symmetry wherein individual ones of the memory cells are 1T-1C and occupy 1.0667F 2 wherein "F" is the memory cell pitch obtained horizontally, laterally, and orthogonally through the respective second capacitor electrode lines, the capacitor insulator, and the first capacitor electrode.

9. The array of claim 8, wherein the horizontal region is bounded horizontally by a 1F x 1.0667F rectangle.

10. The array of claim 1 wherein respective pairs of the laterally adjacent word lines have at least portions thereof directly beneath the respective second capacitor electrode lines.

11. The array of claim 10 wherein the pairs of the laterally adjacent word lines are laterally separated from one another further than the individual ones of the word lines within each pair of the laterally adjacent word lines are laterally separated from one another.

12. The array of claim 1 wherein the second capacitor electrode lines are individually wider than the individual word lines.

13. The array of claim 12, wherein the second capacitor electrode lines are individually more than two times wider than the individual word lines.

14. The array of claim 13 wherein the second capacitor electrode lines are individually at least five times wider than the individual word lines.

15. The array of claim 13 wherein the second capacitor electrodes are individually no more than five times wider than the individual word lines.

16. The array of claim 1 wherein the second capacitor electrode lines are individually wider than the individual digit lines.

17. The array of claim 16 wherein the second capacitor electrode lines are individually less than two times wider than the individual digit lines.

18. The array of claim 1 wherein the capacitor insulator is ferroelectric.

19. The array of claim 1, wherein each of the transistors comprises: a semiconductor material which is L-shaped or mirrored L-shaped in at least one straight vertical cross-section, thereby having a stem extending vertically and a base extending horizontally from a lateral side of the stem above a base of the stem, the semiconductor material of the stem including individual ones of the upper source / drain regions and individual ones of the channel regions below the individual upper source / drain regions; At least one of (a) and (b), wherein (a): the semiconductor material of the rods includes a lower source / drain region below the channel region; and (b): The semiconductor material of the substrate includes a lower source / drain region; and Gates are operatively located laterally adjacent to the channel region of the stem, individual ones of the gates being individual parts of individual ones of the word lines.

20. An array according to claim 19, comprising individual pairs of laterally adjacent transistors, one individual of the semiconductor materials within each pair of laterally adjacent transistors is L-shaped in the at least one straight vertical cross-section, and the other individual semiconductor material within each pair of laterally adjacent transistors is a mirror image L-shaped in the at least one straight vertical cross-section.

21. The array of claim 20 wherein the pairs of the laterally adjacent transistors are laterally separated from one another further than the individual ones of the transistors within each pair of the laterally adjacent transistors are laterally separated from one another.

22. An array of memory cells, each comprising a capacitor and a transistor extending in a vertical direction, the array comprising rows of word lines and columns of digit lines, comprising: Individual ones of the columns include digit lines underlying channel regions of vertically extending transistors of individual memory cells within the array and interconnecting the transistors in the columns, the channel regions individually including a pair of opposing lateral sides; individual ones of the rows include a word line above the digit line, the word line extending laterally across and operably laterally adjacent to one of the pair of laterally opposing sides of the transistor channel region and interconnecting the transistors in the row, the other one of the pair of laterally opposing sides of the transistor channel region in the row not being operably laterally adjacent to a word line in the row and not being operably laterally adjacent to any other of the word lines; and The capacitors of the individual memory cells within the array individually include: a first capacitor electrode directly abutting an uppermost surface of an upper source / drain region of one of the transistors and extending vertically upward from the uppermost surface, the first capacitor electrode directly abutting less than all of the uppermost surface of the upper source / drain region; a vertically extending capacitor insulator including a pair of laterally opposing sides, one of the laterally opposing sides of the capacitor insulator being operably adjacent to a lateral side of the first capacitor electrode; and A second capacitor electrode extends vertically and includes a pair of laterally opposing sides, one of the laterally opposing sides of the second capacitor electrode being operably adjacent to the other laterally opposing side of the capacitor insulator.

23. The array of claim 22, wherein the first capacitor electrode directly abuts less than half of the uppermost surface of the upper source / drain region.

24. The array of claim 22, wherein more than half of the smallest surface of the first capacitor electrode is directly against the uppermost surface of the upper source / drain region.

25. The array of claim 22, wherein the memory cells within a layer of the memory cells have translational symmetry, wherein individual ones of the memory cells are 1T-1C and occupy 1.0667F 2 wherein "F" is the memory cell pitch obtained horizontally, laterally, and orthogonally through the respective second capacitor electrode lines, the capacitor insulator, and the first capacitor electrode.

26. The array of claim 25, wherein the horizontal region is bounded horizontally by a 1F x 1.0667F rectangle.

27. An array of memory cells, each comprising a capacitor and a transistor extending in a vertical direction, the array comprising rows of word lines and columns of digit lines, comprising: Individual ones of the columns include digit lines underlying channel regions of vertically extending transistors of individual memory cells within the array and interconnecting the transistors in the columns; Individual ones of the rows include a word line above the digit line, the word line extending laterally across and operably laterally adjacent to a lateral side of the transistor channel region and interconnecting the transistors in the row; The capacitors of the individual memory cells within the array individually include: a first capacitor electrode electrically coupled to an upper source / drain region of one of the transistors and extending vertically upward from the upper source / drain region; a vertically extending capacitor insulator including a pair of laterally opposing sides, one of the laterally opposing sides of the capacitor insulator being operably adjacent to a lateral side of the first capacitor electrode; and a second capacitor electrode extending vertically and including a pair of laterally opposing sides, one of the laterally opposing sides of the second capacitor electrode being operably adjacent to the other laterally opposing side of the capacitor insulator, the second capacitor electrodes within the array being longitudinally spaced elongated lines extending horizontally along a line of capacitors, individual ones of the second capacitor electrode lines being shared by capacitors longitudinally along the line of capacitors; and The respective pair of laterally adjacent word lines has at least a portion thereof directly beneath the respective second capacitor electrode line.

28. The array of claim 27 wherein the pairs of the laterally adjacent word lines are laterally separated from one another further than the individual ones of the word lines within each pair of the laterally adjacent word lines are laterally separated from one another.

29. The array of claim 27 wherein the memory cells within a layer of the memory cells have translational symmetry wherein individual ones of the memory cells are 1T-1C and occupy 1.0667F 2 wherein "F" is the memory cell pitch obtained horizontally, laterally, and orthogonally through the respective second capacitor electrode lines, the capacitor insulator, and the first capacitor electrode.

30. The array of claim 29, wherein the horizontal region is bounded horizontally by a 1F x 1.0667F rectangle.

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