Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and a peripheral region around the active region, wherein the peripheral region includes a sealing structure region. The semiconductor device includes a substrate and a seed layer on the substrate. The semiconductor device also includes a composite layer containing gallium nitride located on the seed layer and in the active region and the peripheral region. The semiconductor device also includes a gate electrode, a source electrode, and a drain electrode arranged in the active region and on the composite layer containing gallium nitride, and the source electrode and the drain electrode are respectively located on opposite sides of the gate electrode. The semiconductor device also includes a sealing structure located in the sealing structure region, the sealing structure includes a blocking structure and a sealing member located on the blocking structure, the blocking structure is arranged corresponding to the periphery of the active region, and penetrates the composite layer containing gallium nitride and the seed layer. The present invention can fully protect the electronic components in the active region, thereby improving the yield and quality of the electronic components.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device with a blocking structure and a manufacturing method thereof. Background Art

[0002] In recent years, semiconductor devices have developed rapidly in the fields of computers, consumer electronics, etc. At present, semiconductor device technology has been widely accepted in the product market of metal oxide semiconductor field effect transistors, with a high market share. Semiconductor devices are used in various electronic applications, such as high-power devices, personal computers, mobile phones, digital cameras and other electronic devices. These semiconductor devices are generally manufactured by depositing an insulating layer or dielectric layer, a conductive layer material and a semiconductor layer material on a semiconductor substrate, and then patterning various material layers using a photolithography process. Therefore, circuit devices and components are formed on the semiconductor substrate.

[0003] Among these devices, high-electron mobility transistors (HEMTs) have advantages such as high output power and high breakdown voltage, so they are widely used in high-power applications. Although existing semiconductor devices and their formation methods can cope with their originally intended uses, they still have problems that need to be overcome in various technical aspects of their structure and manufacturing method. Summary of the invention

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes an active region and a peripheral region located around the active region, and the peripheral region includes a sealing structure region. The semiconductor device includes a substrate and a seed layer located on the substrate. The semiconductor device also includes a composite layer containing gallium nitride located on the seed layer and located in the active region and the peripheral region. The semiconductor device also includes a gate electrode, a source electrode, and a drain electrode arranged in the active region and located on the composite layer containing gallium nitride, and the source electrode and the drain electrode are respectively located on opposite sides of the gate electrode. The semiconductor device also includes a sealing structure located in the sealing structure region, the sealing structure includes a blocking structure and a sealing member located on the blocking structure, the blocking structure is arranged around the active region and penetrates the composite layer containing gallium nitride and the seed layer.

[0005] Some embodiments of the present invention provide a method for manufacturing a semiconductor device. The semiconductor device includes an active region and a peripheral region located around the active region, and the peripheral region includes a sealing structure region. The above-mentioned manufacturing method includes providing a substrate. The above-mentioned manufacturing method also includes covering a seed layer on the substrate in the active region and the peripheral region. The above-mentioned manufacturing method also includes forming a composite layer containing gallium nitride on the seed layer in the active region and the peripheral region. The above-mentioned manufacturing method also includes forming a blocking structure in the sealing structure region, the blocking structure is arranged corresponding to the periphery of the active region, and the blocking structure penetrates the composite layer containing gallium nitride and the seed layer. The above-mentioned manufacturing method also includes forming a gate electrode, a source electrode and a drain electrode on the composite layer containing gallium nitride in the active region, and the source electrode and the drain electrode are respectively located on opposite sides of the gate electrode. The above-mentioned manufacturing method also includes forming a sealing member above the blocking structure in the sealing structure region, and the sealing member and the blocking structure form a sealing structure.

[0006] In an embodiment of the present invention, the semiconductor device has an active area and a peripheral area, the peripheral area includes a cutting path and a sealing structure area provided with a sealing structure, the sealing structure area corresponds to the periphery of the active area and is located between the cutting path and the active area; the sealing structure includes a blocking structure and a sealing member located above the blocking structure; the semiconductor device includes a composite layer containing gallium nitride and a seed layer formed above a substrate; the blocking structure at least penetrates the composite layer containing gallium nitride and the seed layer. When the wafer is cut along the cutting path, the blocking structure can effectively block the cracks generated between the composite layer containing gallium nitride and the seed layer from entering the active area, fully protecting the electronic components of the active area, thereby improving the yield and quality of the electronic components; furthermore, the blocking structure is connected to the sealing member above, which can prevent moisture from invading the active area from the cutting section, thereby improving the electrical performance of the components and extending the service life; the blocking structure includes a conductive material, the blocking structure is electrically connected to the sealing member above and is grounded, and can shield the interference signals that may be generated by the outside world to the electronic components of the active area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0008] Figure 1 Schematic diagram of an active region, a peripheral region, and a sealing structure region of a semiconductor device according to some embodiments of the present invention.

[0009] Figure 2 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention.

[0010] FIG. 3A to FIG. 3E Schematic cross-sectional views of various stages of a process for forming a semiconductor device according to some embodiments of the present invention.

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0012] Figure 5 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention.

[0013] Figure 6 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention.

[0014] Figure 7 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention.

[0015] Figure 8 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention.

[0016] Fig. 9 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention.

[0017] A P ~Surrounding area;

[0018] A A ~ Active area;

[0019] A S ~Sealed structure area;

[0020] L S ~ cutting road;

[0021] W A ~Width of the sealing structure area;

[0022] W1~Width of the blocking structure;

[0023] 102~Substrate;

[0024] 104~seed layer;

[0025] 106~buffer layer;

[0026] 108~channel layer;

[0027] 110~Barrier layer;

[0028] 111~composite layer containing gallium nitride;

[0029] 112~gate electrode;

[0030] 120~gate structure;

[0031] 122~gate metal layer;

[0032] 116~source electrode;

[0033] 118~drain electrode;

[0034] 114, 115~dielectric layer;

[0035] 201~groove;

[0036] 160, 180 ~ opening;

[0037] 20, 30, 40, 50, 60, 70, 80 ~ blocking structure;

[0038] 411, 412~closed loop;

[0039] 511, 611, 711, 811-first blocking portion;

[0040] 512, 612, 712, 812-second blocking portion;

[0041] 613~third blocking portion;

[0042] 121~Insulating layer containing silicon;

[0043] 124~Insulation layer;

[0044] 126V, 128V, 129V~guide hole;

[0045] 126M, 128M, 129M ~ metal parts;

[0046] R C ~ Seals;

[0047] S D ~Sealed structure;

[0048] L1~first length;

[0049] L2~second length;

[0050] d1~first spacing;

[0051] d2~second spacing;

[0052] C P ~crack. DETAILED DESCRIPTION

[0053] The present invention provides many embodiments or examples for implementing different components of the provided semiconductor device. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to indicate the relationship between the different embodiments discussed.

[0054] Furthermore, spatially relative terms such as "below", "beneath", "below", "above", "upper" and other similar terms may be used in the following description to simplify the relationship of one element or component to other elements or components as shown in the figures. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0055] Some variations of the embodiments are described below. In the various drawings and illustrated embodiments, similar reference numerals are used to indicate similar elements. It is understood that additional steps may be provided before, during, or after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

[0056] Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In an embodiment of the present invention, the semiconductor device has an active region and a peripheral region, the peripheral region includes a cutting path and a sealing structure region provided with a sealing structure, the sealing structure region corresponds to the periphery of the active region and is located between the cutting path and the active region. According to some embodiments of the present invention, the sealing structure includes a blocking structure and a sealing member located above the blocking structure. In some embodiments, the semiconductor device includes a composite layer containing gallium nitride and a seed layer formed above a substrate, and the blocking structure of the embodiment at least penetrates the composite layer containing gallium nitride and the seed layer. Along the cutting path L S When cutting the wafer, the blocking structure of the embodiment can effectively prevent the cracks generated between the composite layer containing gallium nitride and the seed layer from entering the active region, fully protecting the electronic components in the active region, thereby improving the yield and quality of the electronic components.

[0057] Figure 1 Schematic diagram of an active region, a peripheral region, and a sealing structure region of a semiconductor device according to some embodiments of the present invention. P Located in active zone A AIn some embodiments, the peripheral area A P Contains sealing structure area A S and cutting path L S .like Figure 1 As shown, the sealing structure area A S Located on Cutting Road L S With active area A A Sealing structure area A S According to some embodiments of the present invention, the sealing structure area A S The sealing structure in the embodiment includes a blocking structure and a sealing member located above the blocking structure. S Width W A In the range of 1μm-10μm.

[0058] Figure 2 FIG. 1 is a top view schematic diagram of a blocking structure of a semiconductor device according to some embodiments of the present invention. S A sealing member (not shown) is further disposed above the blocking structure 20, and the sealing member and the blocking structure 20 form a sealing structure. In some embodiments, the sealing member is, for example, a sealing ring, which is disposed to prevent moisture from intruding into the active area A. A In some embodiments, the semiconductor device includes a composite layer containing gallium nitride, and the blocking structure 20 can prevent cracks generated during wafer cutting from entering the active region A. A In some embodiments, the width W1 of the barrier structure 20 is in the range of 1 μm-10 μm.

[0059] FIG. 3A to FIG. 3E Schematic cross-sectional views of various stages of a process for forming a semiconductor device according to some embodiments of the present invention. FIG. 3A to FIG. 3E For example, along the Figure 2 Schematic diagram of the cross-section of each process stage drawn by the section line CC.

[0060] First, Figure 3AAs shown, a substrate 102 is provided. In some embodiments, the substrate 102 includes a ceramic material. The ceramic material includes a metal inorganic material. In some embodiments, the substrate 102 may include silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon dioxide (SiO2), sapphire (Sapphire) or a combination thereof. The sapphire substrate is composed of aluminum oxide and gallium nitride formed thereon. In some embodiments, the substrate 102 may include an alloy semiconductor, such as SiGe, SiGeC, GaAsP or GaInP. In some embodiments, the substrate 102 may be a single crystal substrate, a multi-layer substrate, a gradient substrate, other appropriate substrates or a combination thereof. In some embodiments, the substrate 102 may also include a semiconductor on insulator (SOI) substrate (e.g., a silicon on insulator substrate or a germanium on insulator substrate), and the semiconductor on insulator substrate may include a base plate, a buried oxide layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer.

[0061] In some embodiments, a seed layer 104 is formed on the substrate 102, and the seed layer 104 corresponds to the active region A of the semiconductor device. A and surrounding area A P In some embodiments, the seed layer 104 may be formed of silicon (Si) or other suitable materials. In some embodiments, the method for forming the seed layer 104 may include a selective epitaxy growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, a molecular beam epitaxy process, a solid-phase epitaxial recrystallization (SPER) step after deposition of a doped amorphous semiconductor (e.g., Si), a direct seed transfer method, or other suitable processes.

[0062] In some embodiments, a buffer layer 106 is formed on the seed layer 104. Figure 3A As shown, the buffer layer 106 is disposed in the active region A of the semiconductor device.A and the peripheral region A P In the buffer layer 106 can help slow down the strain of a channel layer 108 formed subsequently above the buffer layer 106 and prevent defects from forming in the upper channel layer 108. In some embodiments, the material of the buffer layer 106 is AlN, GaN, Al x Ga 1-x N (1 < x < 1), the foregoing combinations or similar materials. In some embodiments, the buffer layer 106 can be formed by an epitaxial growth process, such as metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), the foregoing combinations or similar methods. Although in the embodiments as Figure 3A shown, the buffer layer 106 is a single-layer structure, in some other embodiments, the buffer layer 106 can also be a multi-layer structure.

[0063] Next, a channel layer 108 is formed on the buffer layer 106, and the channel layer 108 is located in the active region A of the semiconductor device A and the peripheral region A P In some embodiments, the channel layer 108 includes an undoped group III-V semiconductor material. For example, the channel layer 108 can be formed of undoped gallium nitride (GaN), but the present invention is not limited thereto. In some other embodiments, the channel layer 108 includes AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable group III-V materials or combinations thereof. In some embodiments, molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), other suitable methods or combinations thereof can be used to form the channel layer 108.

[0064] After that, a barrier layer 110 is formed on the channel layer 108. The barrier layer 110 is located in the active region A of the semiconductor device A and the peripheral region A P In some embodiments, the barrier layer 110 includes an undoped group III-V semiconductor material. For example, the barrier layer 110 is formed of undoped aluminum gallium nitride (Al x Ga 1-xN, where 0 < x < 1), but the present invention is not limited thereto. In some other embodiments, the barrier layer 110 may also include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable group III-V materials, or a combination of the foregoing. For example, the barrier layer 110 may be formed on the channel layer 108 by molecular beam epitaxy, metalorganic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the foregoing.

[0065] In some embodiments, the channel layer 108 and the barrier layer 110 include different materials to form a heterointerface between the channel layer 108 and the barrier layer 110. The energy band gap difference of the heteromaterial can cause a two-dimensional electron gas (2DEG) (not shown) to form on this heterointerface. A semiconductor device formed according to some embodiments, such as a high-electron mobility transistor (HEMT), can utilize the two-dimensional electron gas as a conductive carrier.

[0066] In some embodiments of the present invention, the gallium nitride-containing composite layer 111 is disposed in the active region A of the semiconductor device A and the peripheral region A P , and is composed of the buffer layer 106, the channel layer 108, and the barrier layer 110, as Figure 3A shown. However, the gallium nitride-containing composite layer 111 may also include other layer films, and the present invention is not limited thereto. In some other embodiments, a carbon-doped layer (not shown in the figure) may be formed between the buffer layer 106 and the channel layer 108 to increase the breakdown voltage of the semiconductor device.

[0067] Next, according to some embodiments, as Figure 3B shown, a gate electrode 112 is formed on the gallium nitride-containing composite layer 111 located in the active region A A . In some embodiments, the material of the gate electrode 112 may be a conductive material, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi2, a combination of the foregoing, or a similar material, and the gate electrode 112 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or a similar process.

[0068] After that, according to some embodiments, a dielectric layer 114 is formed on the gallium nitride-containing composite layer 111. The dielectric layer 114 conformally covers the gate electrode 112, and the dielectric layer 114 extends to the peripheral region AP . Although Figure 3B In the illustrated embodiment, the dielectric layer 114 is a single-layer structure, but in some other embodiments, the dielectric layer 114 may also be a multi-layer structure.

[0069] In addition, the dielectric layer 114 may be made of silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. Furthermore, the dielectric layer 114 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma chemical vapor deposition (HDPCVD) process or a combination thereof.

[0070] Then, according to some embodiments of the present invention, the material layer is patterned to form a A The gate electrode 112 is provided with openings 160 and 180 on opposite sides thereof, and the peripheral region A is provided with openings 160 and 180 on opposite sides thereof. P Sealing structure area A S A groove 201 is formed in the substrate. Figure 3C 1 is a schematic cross-sectional view of the structure of the openings 160 , 180 and the groove 201 after being manufactured in some embodiments.

[0071] In some embodiments, the trench 201 and the openings 160 and 180 may be formed by an etching process, such as a dry etching process, such as reactive ion etching (RIE), electron cyclotron resonance (ERC) etching, inductively-coupled plasma (ICP) etching or similar dry etching processes.

[0072] In some embodiments, an etching apparatus including an etching chamber can be used to provide a gas supply system for an etchant used in an etching process, a bias power generator that can apply bias power to the etching chamber, a wafer stage, a spray head that can evenly disperse the etchant, and an etching endpoint detector that can monitor the etching signal of the material layer to be removed in real time during the etching process. During the etching process, the etchant is accelerated by the bias electric field in the etching chamber and anisotropically etches the dielectric layer 114 and the underlying gallium nitride-containing composite layer 111 toward the direction of the wafer stage.

[0073] In some embodiments, the dielectric layer 114 and the composite layer 111 containing gallium nitride may be etched in two stages through mask layers with different patterns.

[0074] In some embodiments, a first etching step may be performed through a first mask layer (not shown) to form a first etching pattern in the active region A. A Openings 160, 180 are formed in the sealing structure area A S A recess (not shown) having a depth substantially the same as that of the openings 160 and 180 is formed at a position corresponding to the trench 201. In some embodiments, the openings 160, 180 and the recess extend into the barrier layer 110 and expose the channel layer 108. The depths of the openings 160, 180 and the recess may be determined based on the carrier concentration and carrier mobility of the two-dimensional electron gas (2DEG) of the applied electronic component, such as a high electron mobility transistor. Afterwards, an ashing process may be performed to remove the first mask layer.

[0075] Next, a second mask layer (not shown) and a second etching step are performed to further form the groove 201 by etching the recess corresponding to the groove 201. In some embodiments, in the sealing structure area A S The trench 201 formed in the active region A A The trench 201 extends through the dielectric layer 114, the composite layer 111 containing gallium nitride, and the seed layer 104. In some embodiments, the trench 201 may extend downward into the substrate 102 to remove a portion of the substrate 102. Afterwards, an ashing process may be performed to remove the second mask layer, and the Figure 3C The fabrication of the openings 160 , 180 and the groove 201 is shown.

[0076] Next, according to some embodiments, appropriate materials are deposited in the openings 160 and 180 on opposite sides of the gate electrode 112 and in the trench 201, and patterning steps are performed to form the following structures: Figure 3D The source electrode 116 , the drain electrode 118 , and the blocking structure 20 are shown.

[0077] In some embodiments, a conductive material such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi2, a combination of the foregoing, or the like may be deposited to form the source electrode 116, the drain electrode 118, and the barrier structure 20. In some embodiments, the source electrode 116, the drain electrode 118, and the barrier structure 20 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam evaporation, sputtering, or the like. In some embodiments, after depositing the material layer forming the source and drain, a high temperature thermal process such as a rapid thermal annealing process is further performed to form a source-drain ohmic contact.

[0078] In some embodiments, Figure 3D As shown, the source electrode 116 and the drain electrode 118 are located on and electrically contact the channel layer 108. In some embodiments, the barrier structure 20 penetrates the dielectric layer 114, the composite layer 111 containing gallium nitride, and the seed layer 104, and extends downward into the substrate 102.

[0079] As described in the above example, the same conductive material can be deposited in the trench 201 and the openings 160 and 180, and patterning process can be used to simultaneously form Figure 3D The blocking structure 20, the source electrode 116 and the drain electrode 118 are shown, but the embodiment is not limited thereto. In some other embodiments, the blocking structure 20 may include a material different from that of the source electrode 116 and the drain electrode 118. For example, the blocking structure 20 may be formed of polysilicon or an insulating material such as nitride or oxide. Therefore, the blocking structure 20 and the source electrode 116 and the drain electrode 118 may also be formed using different processes.

[0080] In some embodiments, the material filled in the trench 201 (also referred to as the barrier material) includes a conductive material, a semiconductor material, an insulating material, or a combination thereof. In some embodiments, the barrier material is, for example, a metal, polysilicon, a nitride, an oxide, or a combination thereof. The barrier material including a metal is, for example, Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi2, a combination thereof, or a similar conductive material. In some embodiments, the barrier material can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam evaporation (electron beam evaporation), sputtering, or a similar process to form the barrier structure 20.

[0081] Afterwards, if Figure 3E As shown, according to some embodiments, an insulating layer 124 is formed on the blocking structure 20, the source electrode 116, and the drain electrode 118, and the insulating layer 124 conformably covers the blocking structure 20, the source electrode 116, and the drain electrode 118. The insulating layer 124 extends to the peripheral area A. P .

[0082] Next, according to some embodiments, holes (not shown) are formed in the insulating layer 124 to expose the source electrode 116, the drain electrode 118, and the blocking structure 20. Thereafter, a metal material is deposited on the insulating layer 124 to fill the holes, and a patterning process is performed to form vias 126V, 128V, and 129V and a plurality of metal portions 126M, 128M, and 129M above the vias.

[0083] In some embodiments, such as Figure 3E As shown, the metal portion 126M is located above the via 126V and is electrically connected to the source electrode 116, and the metal portion 128M is located above the via 128V and is electrically connected to the drain electrode 118. In some embodiments, the metal portion 129M is located above the via 129V and is electrically connected to the blocking structure 20. In some embodiments, the materials and formation methods of forming the vias 126V, 128V, 129V and the metal portions 126M, 128M, 129M may be similar or the same as the formation method of the gate electrode, and will not be repeated here.

[0084] According to some embodiments, the sealing structure area A S A sealing member R is provided above the blocking structure 20 in C , seal R C and the blocking structure 20 to form a sealing structure S D In some embodiments, the seal R C The metal part 129M and the guide hole 129V are included. Figure 3E shown.

[0085] In some embodiments, metal portions 126M, 128M, and metal portion 129M are referred to as the first metal layer. Although only the first metal layer and an insulating layer 124 are used as examples in the figure, the subsequent process further includes forming multiple dielectric layers (not shown in the figure) and multiple metal layers (not shown in the figure) alternately stacked on the first metal layer. For example, a first intermetallic dielectric layer (IMD-1), a second metal layer, a second intermetallic dielectric layer (IMD-2), a third metal layer, and the like are sequentially formed on the first metal layer. Each intermetallic dielectric layer also has a via connecting adjacent metal layers. In some embodiments, the sealing structure S D Seal R C The barrier structure 20 includes metal parts of each metal layer located above the barrier structure 20 and vias extending in the dielectric layer between each metal layer to connect the upper and lower metal parts.

[0086] Therefore, in some embodiments, the sealing structure area A is set S Seal R C , including the metal parts of each metal layer and the guide holes extending in each dielectric layer.C For example, a seal ring may be provided to seal around the active area A. A . Seal R C The setting can prevent mechanical damage caused by wafer cutting (die saw) and can seal the R C Ground to shield interference signals. In addition, the seal R C Prevents moisture from entering the active area A from the cutting section A , which affects the performance of electronic components.

[0087] In some embodiments, the blocking structure 20 and the upper sealing member R C In some embodiments, the blocking structure 20 is made of insulating material, and the sealing member R C The sealing member R is physically connected to the barrier structure 20 below. In some embodiments, the barrier structure 20 is made of a conductive material such as metal or polysilicon, so the sealing member R C The barrier structure 20 is electrically connected to the barrier structure 20 below.

[0088] In some embodiments, the semiconductor device includes an epitaxially grown composite layer, such as a composite layer 111 containing gallium nitride. Since the composite layer 111 containing gallium nitride is epitaxially grown from the seed layer 104, the difference in the degree of lattice matching between the composite layer 111 containing gallium nitride and the seed layer 104 is large. Therefore, when the wafer is cut, cracks are easily generated at the interface between the composite layer 111 containing gallium nitride and the seed layer 104, such as Figure 3E The crack C between the buffer layer 106 and the seed layer 104 is shown. P According to some embodiments, the blocking structure 20 can effectively block the crack C P Entering active zone A A .

[0089] Furthermore, in some embodiments, the blocking structure 20 includes a conductive material and can be grounded to shield interference signals. Furthermore, in some embodiments, the blocking structure 20 can also prevent moisture from invading the active region A from the cut section of the composite layer 111 containing gallium nitride. A , which affects the performance of electronic components.

[0090] In addition, although in the semiconductor device illustrated above, the blocking structure 20 is formed after the dielectric layer 114 covers the gate electrode 112, in some other embodiments, the trench can be formed and the blocking material can be filled after the barrier layer 110 is epitaxially formed, so that the formed blocking structure penetrates the composite layer 111 containing gallium nitride and the seed layer 104. When the source electrode 116 and the drain electrode 118 are subsequently formed, a conductive portion is formed on the blocking structure at the same time, so that the sealing member formed on the blocking structure in the subsequent process can be connected to the blocking structure 20 through the conductive portion.

[0091] The semiconductor device of the present invention can be applied to various types of semiconductor devices. In some embodiments, the semiconductor device is a depletion mode (ie, normally-on) high electron mobility transistor (HEMT), such as Figure 3E In some embodiments, the semiconductor device is an enhanced mode (ie, normally-off) high electron mobility transistor.

[0092] Figure 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 4 The processes performed or materials used in the structures shown are Figure 3E The structure shown, the processes implemented and the materials used are the same or similar and will not be described in detail here.

[0093] and Figure 3E The structure shown is different in that Figure 4 The gate electrode of the enhancement mode HEMT shown includes a gate structure 120 and a gate metal layer 122 .

[0094] According to some embodiments of the present invention, a gate structure 120 is formed on the composite layer 111 containing gallium nitride. Figure 4 As shown, the gate structure 120 is formed on the barrier layer 110. In some embodiments, the gate structure 120 may be made of P-type doped gallium nitride. In some other embodiments, the gate structure 120 may include P-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V group materials or combinations thereof. In addition, the formation method of the gate structure 120 may include the aforementioned deposition or epitaxial process, as well as ion implantation or in-situ doping process.

[0095] Furthermore, in some embodiments, a silicon-containing insulating layer 121 is further formed on the barrier layer 110, and the silicon-containing insulating layer 121 conformably covers the gate structure 120. In some embodiments, the material of the silicon-containing insulating layer 121 is, for example, silicon oxide, silicon nitride, silicon oxynitride, a combination of the foregoing, or a similar material. In some embodiments, the silicon-containing insulating layer 121 can be a high-quality thin film formed by atomic layer deposition (ALD), thermal oxidation process, or a similar deposition process. The silicon-containing insulating layer 121, which is a high-quality thin film, is formed on the barrier layer 110 to prevent leakage current of the source electrode 116, the drain electrode 118, and the gate electrode 122 formed subsequently.

[0096] In some embodiments, Figure 4 As shown, a gate metal layer 122 is formed on the dielectric layer 114, and the gate metal layer 122 is connected to the gate structure 120. In some embodiments, the gate metal layer 122 can be made of a conductive material, such as nickel (Ni), gold (Au), a combination of the foregoing, or other suitable materials. A Schottky contact is formed between the gate metal layer 122 and the gate structure 120. In some embodiments, the gate metal layer 122 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or similar processes.

[0097] In some embodiments, Figure 4 As shown, another dielectric layer 115 is formed on the dielectric layer 114, and the dielectric layer 115 conformally covers the gate metal layer 122. In some embodiments, the process and material of the dielectric layer 115 may be similar or the same as the process and material of the dielectric layer 114, and will not be repeated here.

[0098] Afterwards, in active zone A A The source electrode 116 and the drain electrode 118 are formed on opposite sides of the gate metal layer 122. P Sealing structure area A S In some embodiments, the blocking structure 30 is formed. Figure 4 As shown, the source electrode 116 and the drain electrode 118 are located on the channel layer 108 and are in electrical contact with the channel layer 108. In some embodiments, the blocking structure 30 penetrates the dielectric layers 114 and 115, the composite layer 111 containing gallium nitride, and the seed layer 104, and extends into the substrate 102. The process and materials of the blocking structure 30, the source electrode 116, and the drain electrode 118 can refer to the above content, and will not be repeated here.

[0099] Afterwards, the source electrode 116, the drain electrode 118 and the blocking structure 30 are further fabricated to form a device such as a HEMT. Figure 4The guide holes 126V, 128V, 129V and metal parts 126M, 128M, 129M are shown. The metal parts 126M, 128M, and 129M can be regarded as the first metal layer, and other metal layers and intermetallic dielectric layers (not shown) above the first metal layer are continuously formed. According to some embodiments, in the sealing structure area A S A sealing member R is formed above the blocking structure 30 C In some embodiments, one or more vias (including vias 129V) above the blocking structure 30 are connected to one or more metal parts (including metal part 129M) and other structures, so that the sealing structure area A S Seal R C In some embodiments, the seal R C and the blocking structure 30 can be integrated into a sealing structure S D The processes implemented, materials used and structures formed by these related devices can be referred to the above contents and will not be repeated here.

[0100] Figure 5 FIG. 1 is a top view schematic diagram of a blocking structure of a semiconductor device according to some embodiments of the present invention. Figure 2 The illustrated example includes an active area A around A A single closed ring as a blocking structure 20, such as Figure 5 The illustrated blocking structure 40 includes two closed rings 411 and 412 disposed in the sealing structure area A. S In the example, closed loops 411 and 412 correspond to active area A. A The surrounding settings.

[0101] The blocking structure of the embodiment is not limited to Figure 2 , Figure 5 In some embodiments, the blocking structure includes a sealing structure area A. S The plurality of blocking portions are arranged in at least two rows corresponding to the active area A. A around.

[0102] Figure 6 FIG. 1 is a top view schematically showing a blocking structure of a semiconductor device according to some embodiments of the present invention. According to some embodiments, the sealing structure area A S The blocking structure 50 includes a plurality of first blocking portions 511 and a plurality of second blocking portions 512. Figure 6 As shown, the first blocking portion 511 is adjacent to the active region A. A , the second blocking portion 512 is adjacent to the cutting line L S , and the second blocking portion 512 is disposed offset from the first blocking portion 511 .

[0103] According to some embodiments, the first blocking portions 511 are separated from each other, the second blocking portions 512 are separated from each other, and the second blocking portions 512 correspond to the intervals between the first blocking portions 511. Figure 6 As shown, looking down at the substrate, the first blocking portion 511 and the second blocking portion 512 have an elongated upper surface. In some embodiments, the first blocking portions 511 each have a first length L1 and are separated by a first spacing d1, and the second blocking portions 512 each have a second length L2 and are separated by a second spacing d2. In some embodiments, the length of each second blocking portion 512 adjacent to the scribe line LS is greater than that adjacent to the active area A. A The spacing of the first blocking portion 511, that is, the second length L2 is greater than the first spacing d1, so as to effectively prevent the cracks generated by cutting the wafer from reaching the active area A. A .

[0104] In some embodiments, the blocking portions in the same row, for example, the first blocking portion 511 or the second blocking portion 512, may have the same or different lengths, and the first blocking portion 511 or the second blocking portion 512 may be separated by the same or different spacings. Furthermore, in some embodiments, the blocking portions in different rows may have the same or different lengths, for example, the first length L1 may be equal to or different from the second length L2. The blocking portions in different rows may have the same or different spacings, for example, the first spacing d1 may be equal to or different from the second spacing d2. Therefore, Figure 6 The barrier lengths and spacings shown are for illustrative purposes only.

[0105] In some embodiments, looking down at the substrate 102 , the blocking portion includes a rectangle, a square, a circle, an irregular shape, or a combination of the foregoing shapes.

[0106] Figure 7 FIG. 6 is a top view schematic diagram of a blocking structure of a semiconductor device according to some embodiments of the present invention. The blocking structure 60 includes a sealing structure area A S The plurality of blocking portions are arranged in three rows corresponding to the active area A. A Around. Figure 7 As shown, looking down at the substrate, these blocking portions have a square upper surface. In some embodiments, the sealing structure area A S The blocking structure 60 in the embodiment includes a plurality of first blocking portions 611, a plurality of second blocking portions 612 and a plurality of third blocking portions 613. The first blocking portion 611 is adjacent to the active region A. A , the third blocking portion 613 is adjacent to the cutting line L S The first blocking portion 611 and the second blocking portion 612 are staggered, and the second blocking portion 612 and the third blocking portion 613 are staggered to block the cracks C generated between the composite layer containing gallium nitride and the seed layer when the wafer is cut. P Entering active zone A A.

[0107] Figure 8 FIG. 7 is a top view schematic diagram of a blocking structure of a semiconductor device according to some embodiments of the present invention. The blocking structure 70 includes a sealing structure area A S In some embodiments, the blocking structure 70 includes a plurality of blocking portions adjacent to the active region A. A The first blocking portion 711 and the adjacent cutting line L S The first barrier 711 and the second barrier 712 are staggered to block the cracks C generated between the composite layer containing gallium nitride and the seed layer when the wafer is cut. P Entering active zone A A .like Figure 8 As shown, looking down at the substrate, these blocking portions have a circular upper surface.

[0108] Fig. 9 FIG. 8 is a top view schematic diagram of a blocking structure of a semiconductor device according to some embodiments of the present invention. The blocking structure 80 includes a sealing structure area A S In some embodiments, the blocking structure 80 includes a plurality of blocking portions adjacent to the active region A. A The first blocking portion 811 and the adjacent cutting line L S The plurality of second blocking portions 812 are provided, and the first blocking portion 811 and the second blocking portion 812 are arranged in a staggered manner. Fig. 9 As shown, looking down at the substrate, these blocking portions have a rectangular upper surface. Furthermore, blocking portions in different rows may include the same or different materials. In some embodiments, the first blocking portion 811 includes a first conductive material, and the second blocking portion 812 includes a second conductive material, which is different from the first conductive material. In some embodiments, the first blocking portion 811 includes an insulating material, and the second blocking portion 812 includes a conductive material.

[0109] In summary, the semiconductor device of some embodiments of the present invention has an active region A A With surrounding area A P , surrounding area A P Contains sealing structure area A S and cutting path L S . Sealing structure area A S A sealing structure is provided in the active area A. A According to some embodiments of the present invention, the sealing structure area A SThe sealing structure in the embodiment includes a blocking structure and a sealing member located above the blocking structure. The blocking structure of the embodiment at least penetrates the composite layer containing gallium nitride and the seed layer. When the wafer is cut along the cutting line LS, the sealing member above can prevent mechanical damage caused by cutting the wafer. The blocking structure of the embodiment can effectively block the crack C generated between the composite layer containing gallium nitride 111 and the seed layer 104. P Entering active zone A A , fully protect active area A A electronic components, thereby increasing the active area A A Furthermore, in some embodiments, the blocking structure is connected to the upper sealing member to prevent moisture from invading the active area A from the cut section. A In some embodiments, the blocking structure includes a conductive material, and the blocking structure is electrically connected to the upper sealing member and grounded, so as to shield the active area A from the outside world. A Interference signals may be generated by electronic components.

[0110] Although the embodiments of the present invention and their advantages have been described above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises an active region and a peripheral region around the active region, and includes: a substrate; a seed layer located on the substrate and in the active region and the peripheral region; a composite layer containing gallium nitride, located on the seed layer and in the active region and the peripheral region; a gate electrode disposed in the active region and on the composite layer containing gallium nitride; a source electrode and a drain electrode, disposed in the active region and located on the composite layer containing gallium nitride, the source electrode and the drain electrode being located on opposite sides of the gate electrode respectively; and A sealing structure is located in a sealing structure area of ​​the peripheral area. The sealing structure includes a blocking structure and a sealing member located on the blocking structure. The blocking structure is arranged corresponding to the periphery of the active area and penetrates the composite layer containing gallium nitride and the seed layer.

2. The semiconductor device according to claim 1, wherein The invention also includes a cutting line in the peripheral area, wherein the blocking structure in the sealing structure area is located between the cutting line and the active area.

3. The semiconductor device according to claim 1, wherein: The blocking structure extends into the substrate.

4. The semiconductor device according to claim 1, wherein: The invention also comprises a dielectric layer located on the composite layer containing gallium nitride and covering the gate electrode, wherein the barrier structure located in the sealing structure area penetrates the dielectric layer, the composite layer containing gallium nitride and the seed layer.

5. The semiconductor device according to claim 1, wherein: The blocking structure is connected to the sealing member.

6. The semiconductor device according to claim 1, wherein: Also includes: an insulating layer, located above the source electrode, the drain electrode and the blocking structure; a guide hole located in the insulating layer and above the blocking structure; a metal portion, located above the insulating layer and electrically connected to the via; The sealing component includes the metal part and the guide hole.

7. The semiconductor device according to claim 1, wherein The barrier structure includes metal, polysilicon, nitride, oxide, or a combination thereof.

8. The semiconductor device according to claim 1, wherein The blocking structure includes a conductive material and is grounded.

9. The semiconductor device according to claim 1, wherein: The blocking structure includes a closed ring surrounding the active area.

10. The semiconductor device according to claim 1, wherein The blocking structure includes a plurality of blocking portions, and the plurality of blocking portions are arranged in at least two rows corresponding to the periphery of the active area.

11. The semiconductor device according to claim 10, wherein: Looking down at the substrate, the plurality of blocking portions include rectangular, square, circular, irregular shapes or a combination of the aforementioned shapes.

12. The semiconductor device according to claim 1, wherein The blocking structure comprises: A plurality of first blocking portions are disposed adjacent to the periphery of the active region; and A plurality of second blocking portions, adjacent to the plurality of first blocking portions and arranged in a staggered manner with respect to the plurality of first blocking portions; The plurality of first blocking portions are located between the plurality of second blocking portions and the active area.

13. The semiconductor device according to claim 12, wherein: Among the plurality of second blocking portions, a length of each second blocking portion is equal to or greater than a distance between two adjacent first blocking portions.

14. The semiconductor device according to claim 1, wherein: The composite layer containing gallium nitride includes a buffer layer, a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer.

15. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises an active region and a peripheral region around the active region. The manufacturing method comprises: providing a substrate; Covering the substrate in the active region and the peripheral region with a seed layer; forming a composite layer containing gallium nitride on the seed layer in the active region and the peripheral region; forming a barrier structure in a sealing structure region of the peripheral region, wherein the barrier structure is formed corresponding to the periphery of the active region and penetrates the composite layer containing gallium nitride and the seed layer; forming a gate electrode on the composite layer containing gallium nitride in the active region; forming a source electrode and a drain electrode on the composite layer containing gallium nitride in the active region, wherein the source electrode and the drain electrode are located on opposite sides of the gate electrode; and A sealing member is formed above the blocking structure in the sealing structure area, and the sealing member and the blocking structure form a sealing structure.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: Forming the blocking structure includes: forming a trench in the sealing structure region corresponding to the periphery of the active region, wherein the trench at least penetrates the composite layer containing gallium nitride and the seed layer; and A blocking material is deposited in the trench to form the blocking structure.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: Also included is extending the trench into the substrate.

18. The method for manufacturing a semiconductor device according to claim 15, wherein: The method comprises forming the blocking structure between a cutting line and the active area, wherein the cutting line is located in the peripheral area.

19. The method for manufacturing a semiconductor device according to claim 15, wherein: Also includes: forming a dielectric layer on the composite layer containing gallium nitride and covering the gate electrode, wherein the dielectric layer extends to the peripheral region; forming openings on opposite sides of the gate electrode; Forming a trench in the sealing structure region of the peripheral region, the trench corresponding to the periphery of the active region, and the trench penetrating the dielectric layer, the composite layer containing gallium nitride, and the seed layer; as well as A conductive material is deposited in the trench and the plurality of openings to form the blocking structure, the source electrode and the drain electrode.

20. The method for manufacturing a semiconductor device according to claim 15, wherein: Also includes: forming an insulating layer on the source electrode, the drain electrode and the blocking structure; forming a hole in the insulating layer, wherein the hole is located above the blocking structure; Depositing a metal material layer on the insulating layer, wherein the metal material layer fills the hole to form a guide hole; as well as patterning the metal material layer to form a metal portion on the guide hole; The sealing component includes the guide hole and the metal part.

21. The method for manufacturing a semiconductor device according to claim 15, wherein: Forming the blocking structure includes: A closed ring is formed around the circumference of the active area.

22. The method for manufacturing a semiconductor device according to claim 15, wherein: Forming the blocking structure includes: A plurality of blocking parts are formed in the sealing structure area, and the plurality of blocking parts are arranged in a staggered manner to form at least two rows around the periphery corresponding to the active area.

23. The method for manufacturing a semiconductor device according to claim 15, wherein: Forming the composite layer containing gallium nitride includes: forming a buffer layer; forming a channel layer on the buffer layer; and A barrier layer is formed on the channel layer.

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