Control circuits and methods for switching power supplies

Abstract

Embodiments of the present disclosure relate to control circuits and methods for switching power supplies. A control circuit is configured to control a power factor correction (PFC) pre-regulator, which includes a power switch and is configured to operate in a transition mode and a valley skipping mode. The control circuit generates a drive signal based on a current threshold to control switching of the power switch. A current threshold generator in the control circuit is configured to modulate the current threshold based on the number of valleys to be skipped in the valley skipping mode.

Description

Technical Field

[0001] This disclosure relates to a control circuit for a switching power supply. Background Technology

[0002] It is generally known to use devices for actively correcting the power factor (called power factor correction (PFC)) of switching power supplies used in general electronic devices such as computers, televisions, monitors, etc., and for supplying power to fluorescent lamps, namely, switching pre-regulators that draw current from the power lines, which is quasi-sinusoidal and not inversely phase with the supply voltage. Therefore, this type of switching power supply includes a PFC circuit and a DC-DC converter connected to the output of the PFC circuit.

[0003] A typical switching power supply consists of a DC-DC converter and an input stage or circuit (usually a PFC circuit) connected to the power line. The PFC circuit includes a full-wave diode rectifier bridge and a capacitor connected downstream to generate an unregulated DC voltage based on a sinusoidal AC power supply voltage. The capacitor has a sufficiently large capacitance such that there is a relatively small ripple at its terminals compared to a DC or constant voltage level. Therefore, the diodes in the rectifier bridge will only conduct for a small fraction of each half-cycle of the power supply voltage, because the instantaneous value of the power supply voltage is less than the voltage across the capacitor for most of each half-cycle. As a result, the current drawn from the power line consists of a series of short pulses, each with an amplitude approximately 5-10 times the average input current value obtained.

[0004] This has significant consequences. First, the peak value and RMS (root mean square) value of the current absorbed from the power line are much higher than those of sinusoidal current absorption. As a result, the supply voltage on the power line is distorted due to the almost simultaneous pulse absorption by all utilities connected to the power line. Furthermore, in the case of a three-phase power system, the current in the neutral conductor increases dramatically, and the utilization rate of the potential energy or power supplied by the power system is very low. In fact, the waveform of the pulsed current formed by a series of current pulses includes many odd harmonics, which, although they do not contribute to the power supplied to the load, help increase the RMS current absorbed from the power line and thus increase energy consumption on the power line.

[0005] In quantitative terms, this can be expressed entirely by power factor (PF) and total harmonic distortion (THD). PF is the ratio of active power (the power supplied to the load plus the power dissipated therein as heat) to apparent power (the product of RMS voltage and absorbed RMS current). THD is generally the percentage of energy associated with all the larger harmonics relative to the energy associated with the fundamental harmonic. Typically, a power supply with a capacitor filter has a PF between 0.4 and 0.6 and a THD above 100%. A PFC circuit (referred to herein as a PFC pre-regulator) is placed between the rectifier bridge and the input of the DC-DC converter to allow quasi-sinusoidal current that is not inversely phase with the supply voltage to be drawn from the power line, thereby bringing the PF closer to 1 and reducing the THD.

[0006] Figure 1 A PFC pre-regulator, comprising a boost converter 19 and a pulse width modulation (PWM) controller or control circuit 1, is schematically shown. The PWM control circuit 1 has a variable frequency, also referred to as a "transition mode" (TM), because the device operates on the boundary between continuous conduction mode (CCM) and discontinuous conduction mode (DCM), where each of these modes refers to the current I through the inductor L of the boost converter 19. L The characteristics of the control circuit 1 are as follows: Specifically, the control circuit 1 is of the constant on-time (COT) type, where the on-time is denoted as TON and corresponds to the on-period of the power transistor M in each switching cycle of the boost converter 19. According to the COT control method, the on-period or time TON of the power transistor M is used as the control variable, and within each cycle of the AC input power supply voltage Vac, the on-time remains constant at an appropriate value to achieve the desired effect by the boost converter 19 through... Figure 1 The feedback control loop shown represents the desired regulation of the output voltage Vout. The boost topology is the most common topology for PFC pre-regulators and is therefore described as an example in this paper.

[0007] Boost converter 19 includes: a full-wave diode rectifier bridge 2 that receives an input power supply voltage Vac; and an input capacitor C1 that acts as a high-frequency filter, one terminal of which is connected to the diode bridge 2 and the other terminal of which is connected to a reference voltage node, the reference voltage node being in... Figure 1 The input capacitor C1 is marked as GND. Voltage Vin is supplied across the input capacitor C1. Inductor L is connected to one terminal of the input capacitor C1, and the drain terminal of the MOS power transistor M is connected to... Figure 1The inductor L downstream of the inductor shown is connected to one terminal, and the source terminal of the MOS power transistor M is connected to ground GND. The anode of the boost diode D is connected to the common terminal of the inductor L and the transistor M, and the cathode of the boost diode D is connected to the boost or output node OUTN, which has an output capacitor Co connected between the output node and ground GND. The boost converter 19 generates an output voltage Vout across the output capacitor Co, which is a DC voltage. The output voltage Vout is higher than the peak value of the supply voltage Vin, typically 400V for systems powered by European power lines or universal power lines. The output voltage Vout will be provided as a DC-DC converter connected to a PFC pre-regulator ( Figure 1 The input voltage (not shown in the diagram).

[0008] Control circuit 1 should maintain the output voltage Vout at a constant value through a feedback control loop. Control circuit 1 includes an operational error amplifier 3, which is adapted to compare the voltage division value of the output voltage Vout, i.e., the voltage Vr given by Vr = R2 × Vout / (R2 + R1), where resistors R1 and R2 are connected in series with each other and in parallel with the output capacitor Co. Error amplifier 3 receives a reference voltage Vref, for example, 2.5V, at one input, and generates an output error signal Se across capacitor Ce connected between the output of error amplifier 3 and ground GND.

[0009] An error signal Se is provided to the inverting input of PWM comparator 5, while a signal Srs is provided at the non-inverting input of PWM comparator 5. Signal Srs is a voltage ramp generated across capacitor Cc during the time that switch T1, coupled to capacitor Cc powered by current generator Ic, is off, a period that coincides with the on-time of power transistor M. The ramp signal Srs controls the on-time TON of power transistor M. When signals Srs and Se at the input of PWM comparator 5 are equal, the PWM comparator provides a signal to control circuitry or block 6, which is adapted to control the activation and deactivation of power transistor M and, in this case, to turn off the power transistor.

[0010] Control block 6 includes a zero-current detection (ZCD) block 7, whose input receives an auxiliary signal Saux provided by an inductor Lax magnetically coupled to inductor L. The signal Saux represents the signal provided by... Figure 1The inductors L and Lax shown demagnetize the core of the transformer. ZCD block 7 provides a pulse signal to one input of OR gate 8, the other input of which is connected to starter circuit 10, which provides an active signal to OR gate 8 at the initial power-up moment of boost converter 19. OR gate 8 provides an output signal S to the set input S of set-reset (SR) flip-flop 11, which has a reset input R provided by comparator 5. The SR flip-flop generates an output signal Q and an inverted output signal Q' that is opposite to or complementary to signal Q. Signal Q is provided to the input of driver 12, which responds to signal Q by providing a drive signal to control the on and off of power transistor M. Therefore, driver 12 generates a drive signal in response to signal Q to control the on and off of switch M, wherein the drive signal is valid to control the duration of the on-time TON of power switch M, and the drive signal is invalid during the off-time TOFF in each switching cycle Tsw of boost converter 19. The signal Q' generated by SR flip-flop 11 controls the opening and closing of switch T1 coupled across capacitor Cc. When signal Q is active to turn on power switch M, signal Q' is inactive and switch T1 is open, allowing the current generator to provide current Ic to charge capacitor Cc and generate voltage Srs across it. Conversely, when signal Q is inactive to turn off power switch M, signal Q' is active, thus closing switch T1 and driving the non-inverting input of PWM comparator 5 to ground GND to prevent the PWM comparator from providing a reset signal to reset SR flip-flop 11.

[0011] Figure 2A and Figure 2B This indicates that during operation... Figure 1 A timing diagram of some signals generated in the boost converter 19. More specifically, Figure 2A and Figure 2B Each of the figures shows the voltage Vgs between the gate terminal and the source terminal of transistor M, which corresponds to the gate drive voltage supplied to transistor M by driver 12, as referenced above. Figure 1 The discussion also includes the drain-source voltage Vds between the drain and source terminals of the power transistor M and the current I through the inductor L. L .

[0012] The boost converter 19 is typically controlled to operate at a variable switching cycle or frequency, commonly referred to as a switching mode™ operating mode, where the boost converter operates at the boundary between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM). As those skilled in the art will understand, the terms "continuous" and "discontinuous" refer to the current I through the inductor L in the PFC pre-regulator. LFurthermore, in the transition mode of operation TM, the boost converter 19 is typically controlled by constant on-time (COT) control, where the on-time TON of the power transistor M remains constant. In COT control, the on-time TON of the power transistor is used as a control variable, and during each cycle of the input supply voltage, the on-time TON remains constant at an appropriate value to achieve the desired regulation of the output voltage generated by the PFC pre-regulator via a feedback control loop. In the transition mode of operation TM, the operation of the PFC pre-regulator is never precisely at the boundary between the DCM and CCM operating modes, but rather operates slightly in the DCM operating mode, as should be understood by those skilled in the art.

[0013] In fact, typically, when the current in inductor L is zero, transistor M is not conducting, such as... Figure 2A The inductor current I at time t1 in the middle L The voltage Vds is shown. The inductor current I... L The voltage Vds at time t1, when it reaches zero, is still equal to the output voltage Vout (typically 400V). At this point, the stored energy of the parasitic capacitance Cd associated with the drain terminals of the power transistor M and diode D is equal to 1 / 2·Cd·Vout. 2 If the transistor is turned on at time t1, the energy needs to be released and will be consumed by the resistance R of the transistor M. DS(on) In contrast, the conduction of transistor M is delayed until after the voltage Vds decreases. The oscillation of voltage Vds is caused by current I. L This is also caused by the resonant circuit formed by the parasitic capacitance Cd of inductor L and transistor M. If the conduction of inductor L is delayed until the voltage Vds has a decreasing value, the power stored in the parasitic capacitance Cd and dissipated in transistor M when it is turned on is greatly reduced.

[0014] The zero-current detection ZCD circuit 7 in control block 6 allows for a delay in the turn-on of transistor M, causing the transistor to turn on at the valley of the voltage Vds across the transistor (“valley switch”). This delay occurs at… Figure 2A The delay is represented as Td1 in the middle. Figure 2B The delay is represented as Td, and is approximately equal to half the period of the oscillating signal Vds across transistor M. Figure 2A In the middle, the current I L When time Td2 becomes positive, where Td2 > Td1, there exists a situation where transistor M is conducting but the current I in inductor L is still present. L The negative time interval (Td2-Td1), such as Figure 2A As shown.

[0015] Figure 1 , Figure 2A and Figure 2B Constant on-time (COT) control is illustrated. Those skilled in the art will understand that various techniques, such as valley skipping, are used in conjunction with this control to improve performance. Some of these techniques can improve performance in terms of losses, but may adversely affect performance in other ways, such as THD. For example, valley switching ignores or skips the valley of the oscillation signal Vds before turning on transistor M (i.e., valley skipping). This valley skipping causes a delay in the turn-on of transistor M and can reduce switching losses, but it affects the input current drawn from the power line, making it disproportionate to the input voltage, which can increase the THD of the PFC pre-regulator. There is a continuous need for improved control methods and circuits for PFC circuits and switching power supplies. Summary of the Invention

[0016] In one embodiment, a control circuit is configured to control a power factor correction (PFC) pre-regulator, which includes a power switch and is configured to operate in a switching operation mode and a valley-skip operation mode. The control circuit generates a drive signal based on a current threshold to control the switching of the power switch. A current threshold generator in the control circuit is configured to modulate the current threshold according to the number of valleys skipped in the valley-skip operation mode.

[0017] In embodiments of the control circuit, the switching operating mode is an enhanced constant on-time control of the PFC pre-regulator. The number of valleys skipped in the valley-skipping operating mode is one of the following: one valley skip, two valley skips, and three valley skips. In other embodiments, the number of skipped valleys includes operation based on additional valleys skipped, and therefore may also include operation based on four or more valley skips. In some embodiments, the PFC pre-regulator has a boost topology, and in some embodiments of this disclosure, the power switch is a MOS power transistor. The control circuit may also include pulse-width modulation circuitry configured to control the cutoff of the power switch.

[0018] In embodiments of this disclosure, the PFC pre-regulator is configured to receive an AC input power supply voltage, and the control circuitry further includes a slice generator configured to divide a half-cycle of the input power supply voltage into equal time slices and assign a number to each time slice. A current threshold generator receives the number of the current time slice from the slice generator and is further configured to modulate a current threshold based on the number of the current time slice.

[0019] In embodiments of this disclosure, the control circuit further includes a finite state machine configured to generate drive signals to control the power switch to turn off and on.

[0020] In some embodiments, the PFC pre-regulator includes an inductive element coupled to a power switch, and the control circuitry includes a current-sensing comparator comprising a first input coupled to a current-sensing node to receive a current-sensing signal indicating the current through the inductive element, and a second input coupled to a current threshold generator to receive a current threshold. A zero-current-sensing node is configured to provide a signal indicating a zero-current state through the inductive element. The current threshold generator includes a diode having a cathode coupled to the zero-current-sensing node, a plurality of switches, and a plurality of resistors. Each of the plurality of switches is coupled in series with a corresponding resistor of the plurality of resistors between the anode of the diode and the current-sensing node, wherein one of the plurality of switches is activated based on the number of valleys skipped.

[0021] In other embodiments of this disclosure, the PFC pre-regulator includes an inductive element coupled to a power switch, and the control circuitry includes a current-sensing comparator comprising a first input coupled to a current-sensing node to receive a current-sensing signal indicating the current through the inductive element, and a second input coupled to a current threshold generator to receive a current threshold. The current threshold generator includes a plurality of current threshold voltage nodes, each configured to receive a corresponding current threshold voltage. The current threshold generator also includes a plurality of switches, each of which is coupled between a corresponding current threshold voltage node and the second input, wherein one of the switches is activated based on the number of valleys skipped. Attached Figure Description

[0022] The features and advantages of the disclosed embodiments will become clear from the following detailed description, which is illustrated only by way of non-limiting example in the accompanying drawings, in which:

[0023] Figure 1 A controller or control circuit for a switching power supply according to the prior art is shown;

[0024] Figure 2A and Figure 2B It is shown in Figure 1 Timing diagram of some signals generated during the operation of the circuit;

[0025] Figure 3 The diagram shows the signal timing of the valley skip operation of the PFC pre-regulator;

[0026] Figure 4A This is a schematic diagram of a PFC pre-regulator, which implements enhanced constant on-time control to compensate for the effects of factors such as reference. Figure 1 , Figure 2A , Figure 2B and Figure 3The negative current caused by the drain-source voltage resonance of the described power transistor;

[0027] Figure 4B The figure illustrates the process during enhanced constant on-time control. Figure 4A The signal timing diagram of the signals in the PFC pre-conditioner;

[0028] Figure 5 This shows the input current during the half-cycle of the PFC pre-regulator. Figure 4A and Figure 4B Signal diagram of the current threshold used in enhanced constant on-time control;

[0029] Figure 6 The figure illustrates an embodiment of the present disclosure. Figure 4A and Figure 4B The signal diagram of the modulation current threshold is used in combination with enhanced constant on-time control and valley skipping during half-cycle of the input current of the PFC pre-regulator.

[0030] Figure 7 It is for implementation according to embodiments of this disclosure Figure 6 A schematic functional block diagram of a digital power factor correction control circuit with modulation current threshold control.

[0031] Figure 8 The figure illustrates an embodiment according to the present disclosure. Figure 7 Signal diagram of the chip generator operation;

[0032] Figure 9 The figure illustrates an embodiment according to the present disclosure. Figure 6 The state diagram of the operation of a finite state machine;

[0033] Figure 10 The diagram illustrates the... Figure 7 The digital power factor correction control circuit modulates the signal diagram for current thresholds that are skipped by one, two, and three valley values.

[0034] Figure 11 This is for implementation according to another embodiment of the present disclosure. Figure 6 A schematic functional block diagram of an analog power factor correction control circuit with modulation current threshold control; and

[0035] Figure 12 It is used to implement Figure 6 A schematic functional block diagram of another embodiment of an analog power factor correction control circuit with modulation current threshold control. Detailed Implementation

[0036] Embodiments of this disclosure relate to a power factor correction (PFC) control circuit or controller configured to control a boost PFC pre-regulator in multi-mode operation to provide reduced total harmonic distortion (THD), as will be described in more detail below. The term "multi-mode operation" refers to a switching operation mode™ combined with a valley-skip operation mode, each of which will be described in detail below. Various techniques exist for controlling a PFC pre-regulator in switching modes to reduce total harmonic distortion, such as those described in U.S. Patent Nos. 9,154,030 and 9,461,558, each of which is incorporated herein by reference in its entirety without contradicting the specific teachings and definitions set forth herein. However, the valley-skip operation mode reduces the input current Iin drawn from the power line by a disproportionate relationship to the input voltage Vac on the power line, which increases the THD of the PFC pre-regulator. This non-proportional relationship between the input current Iin drawn from the power line and the input voltage Vac has a significant impact near the zero-voltage crossover point of the input voltage, resulting in high crossover distortion, which in turn leads to unacceptably high THD of the PFC pre-regulator. Embodiments of this disclosure allow the PFC pre-regulator to operate in transition mode TM with valley skipping while maintaining an acceptable THD level, as will be described in more detail below.

[0037] Before describing the multi-mode operation of the PFC pre-regulator according to embodiments of the present disclosure, the transition operation mode TM and the valley skip operation mode will again be described briefly and in more detail, respectively. The transition operation mode TM is referenced above. Figure 2A and Figure 2B This is discussed and widely used in boost PFC pre-regulators. In TM mode, the power transistor M( Figure 1 The PFC pre-regulator is turned on for a specified time during each switching cycle, determined by a control loop that can be implemented in various ways, one of which generally... Figure 1 The following is described. After the on-time TON of the power transistor M, the transistor M is turned off until the current through the inductor L reaches zero. The LC resonant circuit formed by the parasitic capacitance Cd of the inductor L and the power transistor M, and the parasitic capacitance of the diode D at node OUTN, as described above, causes the voltage Vds at node OUTN to resonate, and this resonance ends at (2*Vin+Vout), or zero volts if this value is less than zero. If the power transistor M turns on at this time, or more specifically, as described above regarding... Figure 2A and Figure 2B As described above, if the PFC pre-regulator is turned on after a given delay, it will operate near zero-volt switching (ZVS) and zero-current switching, resulting in high efficiency of the PFC pre-regulator, as those skilled in the art will understand.

[0038] refer to Figure 3 The signal timing diagram illustrates the valley skip operation of the PFC pre-regulator. The valley skip operation mode is an extension of the operation transition mode TM, except that in valley skipping, the power transistor M does not conduct after the first resonance, but instead detects the voltage signal V at zero current. ZCD The MOSFET turns on after several resonant cycles (e.g., 1, 2, or 3). Turning on the MOSFET with 2*Vin + Vout or 0 (if this value is less than zero) allows for zero-voltage switching (ZVS) and zero-current switching (ZCS). This mode is frequently used to improve efficiency at low to medium loads. In particular, this mode allows limiting the switching frequency of the PFC pre-regulator. For example, if the switching frequency is higher than the maximum frequency, multi-mode control can change the mode from transition mode TM to one valley skip, and from one valley skip to two valley skips, and so on. Figure 3 The diagram illustrates the zero-current detection voltage signal V. ZCD , which corresponds to Figure 1 The auxiliary signal Saux, which changes with the current I passing through the inductor L. L It oscillates due to the oscillation. Furthermore, Figure 3 This shows a valley value skip, where V ZCD The initial valley value V1 of the signal is "skipped" and is related to... Figure 2A and Figure 2B The gate drive signal V corresponding to VGS GD Instead of responding to the valley value, the power switch M is effectively turned on. Instead, the power switch M is at V... ZCD The signal is activated after a delay of Td / 2 following the end of the first oscillation cycle.

[0039] The embodiments of this disclosure can be used in conjunction with an enhanced constant on-time (eCOT) control algorithm or a boost PFC pre-regulator control loop; however, the embodiments of this disclosure are not limited to use with an eCOT control algorithm. Therefore, reference will be made first to the embodiments of this disclosure before describing them. Figure 4A , Figure 4B and Figure 5 The eCOT control algorithm will be described in more detail. Figure 4A This is a schematic diagram of the PFC pre-regulator 20, which implements enhanced constant on-time (eCOT) control, or compensates for the above reference. Figure 1 , Figure 2A , Figure 2B and Figure 3 The negative current is caused by the resonance of the drain-source voltage Vds of the power transistor M discussed earlier.

[0040] The PFC pre-regulator 20 receives an input AC power supply voltage Vac and generates a regulated output voltage Vout at the output node OUTN. The PFC pre-regulator 20 includes a switch M, preferably a MOS power transistor, and further includes control circuitry 101 adapted to control the on-time TON and off-time TOFF of switch M during each switching cycle Tsw of the pre-regulator. Control circuitry 101 includes a ramp generator comprising elements Ic, Cc, and T1 configured to generate a ramp voltage Srs, and off-circuit devices 5, 11, and 12 configured to determine the final moment of the on-time TON of switch M by comparing the ramp voltage Srs with a first voltage Se. A current detector, preferably a sensing resistor R, is also included. S The value of the current Ics passing through switch M is detected, and a current sensing signal V indicating the value of that current is generated. CS The control circuit 101 includes a synchronizer 50, which is configured to synchronize the start of the ramp voltage Srs, Tstart, with the signal V when the switch M is closed. CS Cross synchronization with another signal Vt having a value other than zero. In particular, the synchronization occurs precisely, or has a short delay or masking time Tleb, as described in more detail in U.S. Patent No. 9,461,558, which is previously cited and incorporated herein by reference.

[0041] The full-wave diode rectifier bridge 2 receives the input voltage Vac. The first and second terminals of the input capacitor C1 (used as a high-frequency filter) are connected to the diode bridge 2 and ground GND, respectively. A voltage Vin is formed across the input capacitor, and an input current Iin is supplied to the input capacitor. The inductor L is connected to the first terminal of the input capacitor C1 and the boost node BN. The drain terminal of the MOS power transistor M is connected to the boost node BN, and the source terminal of the MOS power transistor M is connected to the sensing resistor R. S The diode D is connected to ground (GND). The anode of diode D is connected to the boost node BN, the cathode of diode D is connected to the output node OUTN, the first terminal of output capacitor Co is connected to the output node, and the second terminal of output capacitor Co is connected to ground (GND). The PFC pre-regulator generates an output voltage Vout across output capacitor Co. The amplitude of the output voltage is greater than the maximum peak value of the input voltage, typically 400V for systems powered by European or universal power lines. The generated output voltage Vout is a DC voltage with some ripple, which is then supplied as the input voltage to a DC-DC converter (not shown) connected to the PFC pre-regulator 20.

[0042] In operation, control circuit 101 maintains the output voltage Vout at a relatively constant value by means of a feedback control loop formed through the control circuit. Control circuit 101 includes an operation error amplifier 3, which is adapted to be configured to compare the voltage division value of the output voltage Vout (i.e., the voltage Vr given by Vr = R2 × Vout / (R2 + R1)) with a reference voltage Vref (e.g., its value is equal to 2.5V), and generate an output error signal Se across an external capacitor Ce connected between the output of error amplifier 3 and ground GND.

[0043] An error signal Se is supplied to the inverting input of PWM comparator 5, while a signal Srs is supplied to the non-inverting input of the PWM comparator. Srs is a voltage ramp across capacitor Cc, which is charged by current generator Ic during the period when switch T1 is off, coinciding with the period when transistor M is on. If signals Srs and Se are equal, comparator 5 sends a signal to control block 6, which is adapted to control transistor M and, in this case, turn it off. Block 6 includes a zero-current detection (ZCD) block 7, whose input receives a signal Saux from inductor Lax coupled to inductor L; signal Saux represents the demagnetization of the core of the transformer formed by inductors L and Lax. Block 7 is capable of sending a pulse signal to OR gate 8, another input of which is connected to starter 10, which is adapted to send a signal to OR gate 8 at an initial moment; the output signal S of OR gate 8 is the set input S of set-reset trigger 11, the other input R of which is a signal from the output of comparator 5, and the set-reset trigger 11 has an output signal Q. Signal Q is sent to the input of driver 12, which controls the on or off state of transistor M by means of signal GD.

[0044] When the inductor current Ics is equal to a signal Vt with a value other than zero (which occurs immediately after or simultaneously with the turn-on of the MOS transistor M), synchronizer 50 is adapted to synchronize the triggering of the voltage ramp Srs used to generate the time period TON. Therefore, the duration of time period TON will be substantially consistent with the duration of the positive ramp Srs. Synchronizer 50 includes a voltage generator 90 that generates the signal Vt and a comparator 61, the non-inverting input of which is connected to resistor R. S To receive signal V CS Furthermore, the inverting input of comparator 61 is connected to receive the signal Vt. The voltage Vt generated by voltage generator 90 has a fixed voltage value, and... Figure 4B The value in the middle represents the current threshold voltage V. ISET Comparator 61 will represent the current Ics passing through transistor M from the sensing resistor R. S voltage VCS The signal Vt is compared. Synchronizer 50 also includes logic circuitry, such as NAND gate 62, which receives the output signal Q from RS latch 11 and the output of comparator 61 provided by delay circuit 63. Delay circuit 63 provides a masking time Tleb. NAND gate 62 generates an output signal in response to these received input signals and provides the output signal to control the closing and opening of switch T1, which is part of a ramp generator that generates ramp signal Srs.

[0045] The delay circuit 63 also receives the signal Q, and during a predetermined time Tleb from the instant the signal Q becomes high, the delay circuit provides a low output signal, independent of the output state of the comparator 61. After the time Tleb has elapsed, the delay circuit 63 provides the state or level of the comparator 61's output as its output. The delay circuit 63 is used because when the power transistor M is turned on, interference or noise flows through the sensing resistor R. S And with the inductor current I L Useful signal V CS Overlapping. For example... Figure 4B As shown, this interference will appear as a positive spike called a "leading spike," and the use of control circuit 63 helps to obtain an improved ability to resist this interference, as discussed in more detail in U.S. Patent No. 9,461,558 cited above.

[0046] The control circuit 101 is typically integrated into a silicon chip or integrated circuit, except that the external capacitor Ce is usually an external or "external" component of such integrated circuit.

[0047] Figure 4B Is Figure 4A A timing diagram of some signals generated during the operation of the PFC pre-regulator 20. More specifically, Figure 4B The driving voltage V generated to drive the power transistor M is shown. GD , across sensing resistance R S voltage signal V CS and zero current detection signal V ZCD .

[0048] Figure 5 The figure illustrates the input current Iin during half a cycle of the PFC pre-regulator 20. Figure 4A and Figure 4B The current threshold I used in enhanced constant on-time (eCOT) control SET The signal diagram. Current threshold I. SET Corresponding to by Figure 4A The voltage signal Vt is generated by the voltage generator 90 in the reference. Figure 4AAs shown and described, the parasitic capacitance Cd and inductor L at the boost node BN cause voltage resonance at that boost node, which manifests as... Figure 3 The current sensing signal V shown CS and zero current detection voltage V ZCD When ZCD block 7 detects inductor current I... L When the current is zero, the parasitic capacitance on the boost node BN is charged with Vout, and this capacitance must be discharged before the power transistor M turns on for efficient operation, as previously described. As a result, when the power transistor M turns on, the current I in the inductor L... L From negative value i neg It starts, instead of starting from zero. This generates an inductor current I in each switching half-cycle. L peak I Lpk (see Figure 2A and Figure 2B The peak value I Lpk The peak value is less than the one that would be reached when the inductor current is practically zero when the power switch M is turned on, which increases the THD of the PFC pre-regulator 20.

[0049] Embodiments of this disclosure relate to a control method and circuit that enable optimization or reduction of the total harmonic distortion (THD) of a PFC pre-regulator utilizing valley skip control, as will be described in more detail below. In this specification, the PFC pre-regulator is described as described above with reference to... Figure 4A , Figure 4B and Figure 5 The enhanced constant on-time (eCOT) control described herein, as well as control via valley skipping, are illustrated by way of example in this specification. Embodiments of this disclosure are not limited to eCOT control but may include other control techniques for use in conjunction with valley skipping to control the PFC pre-regulator.

[0050] As referenced above Figure 2A and Figure 2B As described, in standard constant on-time (COT) control, the power transistor M operates under inductor current I... L A specific delay after reaching zero is required for conduction, and a time is required for cutoff after a period calculated by the control loop of the PFC pre-regulator, where the cutoff time is constant within each half-cycle. In eCOT control, the power transistor M is turned on in the same manner as in COT control, but as... Figure 5 As shown, from the inductor current I L Reaching the calculated current threshold I SET Initially, after a time calculated by the control loop, the power transistor M is turned off. In previous methods of eCOT control, the current threshold I... SET In the input current IIN It has a constant value within each half-cycle, such as Figure 5 As shown. Current threshold I SET The value can be obtained from the input current I IN The input half-cycle changes from one input half-cycle to another, but within a given input half-cycle, the current threshold has a constant value. Figure 5 It also shows the input current I IN During the input half-cycle, the inductor current I of the PFC regulator in each switching cycle L The increase and decrease of.

[0051] In embodiments of this disclosure, instead of setting the current threshold I... SET The value of the input current I IN Instead of keeping the current constant for each input half-cycle, the current threshold value for each input half-cycle is adjusted or modulated based on the number of valleys skipped by the valley skip control via the PFC pre-regulator, as will now be referenced. Figure 6 More detailed description. Therefore, embodiments of this disclosure relate to a PFC pre-regulator controlled in multi-mode operation as described above, wherein the term multi-mode operation refers to transition mode™ operation combined with a valley skip operation mode. As mentioned above, transition mode™ operation is assumed to be eCOT control in this specification, although other types of transition mode™ control combined with valley skipping are used in other embodiments of this disclosure.

[0052] refer to Figure 6 The signal diagram illustrates the input current I in the PFC pre-regulator according to an embodiment of the present disclosure. IN The input half-cycle period and Figure 4A and Figure 4B The modulation current threshold I used in combination with eCOT control SET As shown in the figure, the current threshold I SET This varies over time, specifically within the indicated input half-cycle. Current threshold I SET The specific changes or modulations are based on the number of valleys that are skipped in the valley skipping operation mode via the PFC pre-regulator. Figure 6 The figure shows the modulation current threshold I. SET Three examples: When the valley skipping mode is skipping the resonant V ZCD The first modulation current threshold I at a valley of the signal SET1 When the valley skipping mode is skipping the resonant V ZCD The second modulation current threshold I at the two valleys of the signal SET2 When the valley skipping mode is skipping the resonant V ZCD Modulation current threshold I at the three valleys of the signal SET3Therefore, the modulation current threshold I SET1 I SET2 and I SET3 The corresponding modulation current threshold is selected based on the number of skipped valleys, and the selected threshold varies or is modulated within the input half-cycle, such as... Figure 6 As shown. Modulation current threshold I SET The specific value is a function of the number of valleys skipped in the valley skip operation mode of the PFC pre-regulator.

[0053] Used to implement Figure 6 The control circuit for the modulation current threshold control algorithm can be implemented through hardware, software, or a combination of both, and can be integrated into an integrated circuit. Furthermore, the hardware can be implemented using analog or digital circuitry, as will be referred to below. Figures 7-12 Described in more detail. Figures 7-12 The example embodiments are multi-mode embodiments including one, two, and three valley skipping operation modes. Other embodiments of this disclosure include valley skipping modes for skipping a larger number of valleys, wherein for each such valley skipping mode, the current threshold I... SET It has the corresponding function within the input half-cycle.

[0054] Figure 7 An embodiment of the present disclosure is shown, including components for implementing... Figure 6 The PFC pre-regulator 700 is part of the control circuit 701 of the modulation current control algorithm. (Refer to the above reference.) Figure 1 or Figure 4A Components of the PFC pre-regulator 700, which are identical to those described previously, will not be described in detail again, but will only be discussed as needed when describing the control circuit 701. The pre-regulator 700 includes a rectifier 702 configured to rectify the input voltage Vac and provide an input current Iin to generate the input voltage Vin across the input capacitor C1. A ZCD comparator 704 detects the inductor current I via the auxiliary winding Lax. LThe zero-current condition (i.e., zero voltage across Lax) is detected, and a valid ZCD output signal is generated in response to this zero-current state. An event-driven finite state machine (FSM) 706 receives the output signal from the ZCD comparator 704 and controls the on and off states of the power transistor M based on this output signal and other signals, as will be described in more detail below. A timer 708 generates a timing control signal that includes a count for timing the on-time TON of the power transistor M. The timer 708 generates this count for timing the on-time TON based on a timer start signal TS from the FSM 706 and an on-time signal TONS from the voltage control loop circuit device 722 that sets the value of the on-time ON, as will also be described in more detail below. The timer 708 also generates a timer end signal TE, which is supplied to the FSM 706 to indicate that the value of the generated count indicates that the on-time TON has been reached, and in this way, indicates that the timer has timed the on-time TON.

[0055] Analog-to-digital converter (ADC) 710 receives the input voltage Vin and generates a corresponding digital input voltage based on this analog input voltage. This digital input voltage is supplied to chip generator 712 and current threshold generator 714. Chip generator 712 divides the half-cycle of the input voltage Vin into discrete equal-time slices TS, such as... Figure 8 As shown. A half-cycle is divided into N time periods or slices TS. The slice generator assigns a number to each of the N time slices TS to identify the time slice within the half-cycle. In response to the digital value of the input voltage Vin from the ADC 710, the slice generator 712 provides the slice number parameter NUM_SLICE of the current time slice TS to the current threshold generator 714. The current threshold generator 714 then generates a current threshold I that will be utilized by the control circuit 700. SET The instantaneous digital value. This digital current threshold I from generator 714. SET The current is supplied to a digital-to-analog converter (DAC) 716, which converts the digital current threshold into a corresponding analog voltage representing the digital current threshold. This analog voltage is then supplied to the first input of a current-sensing comparator 718. The second input of the current-sensing comparator 718 receives a voltage across the sensing resistor R. S The generated current sensing signal V CS The current sensing comparator 718 generates a comparison signal V. comp The comparison signal V comp In response to current sensing signal V CS Reaching the current threshold I from DAC 716 SETThe corresponding analog voltage is activated. In operation, the current threshold generator 714 generates a digital current threshold I based on the chip number parameter NUM_SLICE from the chip generator 712 and the number of valleys to be skipped parameter NUM_V-SKIP provided by the voltage control loop circuit device 722. SET The NUM_SLICE parameter indicates the current phase of the digital input voltage Vin, causing the digital current threshold I generated by the current threshold generator 714 to... SET It is a function of the phase and the digitized current value of the input voltage Vin (from the ADC 710), i.e., I SET = f(NUM_SLICE, Vin).

[0056] ADC 720 digitizes the output voltage Vout and provides this digitized output voltage to current threshold generator 714 and voltage control loop circuit 722. Voltage control loop circuit 722 generates an on-time signal TONS indicating the on-time TON of switch M, and also generates a parameter NUM_V-SKIP, representing the number of valleys to be skipped, which will be supplied to the current threshold generator and FSM 706. Current threshold generator 714 modulates the current threshold I based on the NUM_SLICE parameter received from chip generator 712, the NUM_V-SKIP parameter received from voltage control loop circuit 722, and the digitized input voltage Vin received from ADC 710. SET .

[0057] In the operation of control circuit 701, ZCD comparator 704 senses the current I through inductor L via the voltage across auxiliary inductor Laux. L The zero-current crossover is detected, and a valid output signal is generated in response to the detection of this zero-current crossover. Then, the FSM 706 responds to the indication current I received from the ZCD comparator 704. L The effective output signal of zero current crossing activates V. GD The signal either turns the power transistor M on (i.e., turns it off) or activates it. The current sensing comparator 718 receives the current threshold I from the DAC 716. SET And this current threshold is compared with the current I through the conducting power transistor M. L The comparison is made between the current sensing signal V and the current sensing signal V. CS Indicator current I L The current sensing comparator 718 responds to V CS The signal reaches the current threshold I SET And activate V comp Signal, which represents current I L The current threshold has been reached. This is in response to receiving a valid V signal from the current sensing comparator 718.comp The FSM 706 activates the timer start signal TS, causing the timer 708 to start counting the on-time TON of the power transistor M.

[0058] Once the count generated by timer 708 reaches the value indicating that the timer has been on for the specified period TON, the timer activates the timer end signal TE. In response to receiving a valid timer end signal TE, FSM 706 deactivates V. GD The signal is cut off (i.e., disconnected) or deactivated by the power transistor M. Current I is detected at the ZCD comparator 704. L When the next zero-current crossover occurs, the FSM reactivates V. GD The signal turns on the power transistor M and begins the next switching cycle of the PFC pre-regulator 700. The FSM706 operates to start the timer 708 with V. CS The signal reaches the current threshold I SET Synchronization, where V CS The signal indicates the current I through inductor L when power transistor M is turned on. L Therefore, in response to the current I flowing through inductor L L Reaching the current threshold I SET Time V comp When the signal becomes active, FSM 706 activates the TS signal, thereby starting timer 708 to time the on-time TON. In this way, FSM 706 starts timer 708 to time the TON time and the current I through inductor L. L Reaching the current threshold I SET synchronous.

[0059] exist Figure 7 In the diagram, control circuitry 701 is shown as including the input voltage node Vin, represented by a square "X". Control circuitry 701 similarly includes a zero-current sensing node ZCD, a gate drive node GD, a current sensing node CS, and an output voltage node VOUT. Control circuitry 701 is typically formed on a chip or integrated circuit, and these nodes represent interconnect pins of such integrated circuits. Various components of control circuitry 701 can be formed using different types of suitable digital circuitry devices, such as suitable software or firmware executed on a microcontroller and memory for storing that software or firmware. Figure 7 (Not shown in the image). Furthermore, in this specification, the PFC pre-regulator 700 can be described as including a "switching circuit device," wherein the switching circuit device includes all or some of the following: rectifier 702, input capacitor C1, coupling inductor L and auxiliary inductor Lax, power transistor M, and sensing resistor R. S Diode D, output node OUTN, and output capacitor Co.

[0060] Figure 9 is a state diagram showing the operation of the FSM 706 according to one embodiment of the present disclosure. The OFF state diagram at the top center of the figure shows the state where the power transistor M is turned off, that is, the gate drive signal VGD is invalid. Starting from the OFF state, in response to the ZCD comparator 704 detecting a zero current state (the voltage of Laux is zero), the FSM 706 enters the state #ZCD++ on the right side and waits to skip an appropriate number of valleys given by the NUM_V-SKIP parameter of the voltage control loop circuit device 722. The parameter #ZCD in this state is the valley skip count generated by the FSM 706 and compared with the NUM_V-SKIP parameter. As long as (#ZCD < NUM_V-SKIP), the FSM 706 remains in this state and thus skips the desired number of valleys, as described above. When the #ZCD count is equal to the number of valley parameters NUM_V-SKIP to be skipped (#ZCD = NUM_V-SKIP), the FSM 706 enters the LEB state and turns on the power transistor M by activating the V GD signal. Once the FSM706 has delayed the blanking time Tleb (as described above regarding Figure 4A and Figure 4B ), the FSM transitions from the LEB state to the WAIT_CS_COMP state and waits in this state until the current I L reaches the current threshold I SET set by the current threshold generator 714, which is indicated by driving the output of the current sense comparator 718 to be valid. In Figure 9 , the comparison signal V comp output of the current sense comparator 718 at the valid level is represented as CSCOMP. For example, once the V CS signal reaches the current threshold I SET , the current sense comparator 718 drives the V comp signal to the valid level (e.g., high level). After skipping the required number of valleys through the #ZCD++ state and delaying the blanking time Tleb in the LEB state, the FSM 706 transitions from the WAIT_CS_COMP state to the TON state in response to the V comp signal from the current sense comparator 718 being at the valid level, which indicates that the current I L has reached the current threshold I SET . The V comp signal at the valid level is represented as CSCOMP in Figure 9 . When V comp ​​When the signal is at a valid high level, the FSM706 evolves from the WAIT_CS_COMP state or transitions to the TON state; otherwise, if V comp If the signal is an invalid low level, the FSM remains in the WAIT_CS_COMP state. As those skilled in the art will understand, V comp The effective level of the signal can be high or low. In the operation of the FSM 706, if V from the current sensing comparator 718 during the LEB state... comp When the signal is driven to an active level, the FSM will enter the WAIT_CS_COMP state and immediately transition from the WAIT_CS_COMP state to the TON state. After the FSM 706 transitions from the WAIT_CS_COMP state to the TON state, the FSM activates the timer start signal TS( Figure 7 The timing of the on-time TON of the power switch M is initiated. The power transistor M remains on for the required on-time TON_REQ, and after this on-time, the FSM 706 turns the transistor off again (disabling V). GD (signal) and the FSM status returns to Figure 9 The top center is in the OFF state and waits again for the ZCD comparator 704 to detect the inductor current I. L The zero current state.

[0061] Figure 10 It shows the current threshold I SET A graph showing the value of I illustrates the final operation of control circuit 701 during the input half-cycle of input voltage Vin as the corresponding value of the current threshold is generated in each time slice TS within the input half-cycle. As previously mentioned, the current threshold I... SET The value of I is a function of the number of valleys skipped; therefore, the current threshold I... SET Three different sets of values, or shown as the current threshold I that skips a valley value. SET1 The current threshold I that skips two valleys SET2 The current threshold I that skips three valleys SET3 .

[0062] Figure 11 This is a schematic diagram of a PFC pre-regulator 1100 according to another embodiment of the present disclosure. The PFC pre-regulator 1100 includes an analog control circuit 1101 for effectively implementing a modulation current threshold I based on the number of skipped valleys. SET The control circuit 1101 is similar to the one described above, as referenced above. Figure 4A Components 1104-1122 that are identical or similar to the corresponding components will no longer be referenced. Figure 11Detailed description. The control circuit 110 includes a current threshold generator 1118, which includes multiple resistors R1-R3 connected in series and switches S1-S3. One end of each switch S1-S3 is coupled to a diode to generate a zero-current detection signal V. ZCD At the ZCD node, the other end of switches S1-S3 is coupled to a current sensing signal V generated thereon. CS The CS node is also coupled to the non-inverting input of the current sensing comparator 1116.

[0063] Switches S1-S3 are controlled such that one of the switches is activated (i.e., closed), and the closed switch corresponds to the currently implemented valley skipping mode. Therefore, in the case of skipping one valley, switch S1 is closed, while switches S2 and S3 are open. In the case of skipping two valleys, switch S2 is closed, while switches S1 and S3 are open; and in the case of skipping three valleys, switch S3 is closed, while switches S1 and S2 are open. Figure 11 The current threshold generator 1118 effectively provides current threshold generation in situations such as Figure 6 The input half-cycle current threshold I is shown. SET The change in the current sensing signal V is adjusted based on the number of valleys skipped when switches S1-S3 are activated and the corresponding values ​​of resistors R1-R3 are adjusted. CS The value of . In this way, the current threshold generator 1118 sends the current sensing signal V CS A voltage is added as a function of the input half-cycle and the number of valleys skipped. The circuitry in control circuit 1101 generates 1VALLEY_SKIP, 2VALLEY_SKIP, and 3VALLEY_SKIP signals to control switches S1-S3.

[0064] Figure 12 This is a schematic diagram of a PFC pre-regulator 1200 according to another embodiment of the present disclosure. The PFC pre-regulator 1200 includes an analog control circuit 1201 for implementing a modulation current threshold I based on the number of skipped valleys. SET The control circuit 1201 is similar to the one described above, as referenced above. Figure 4A Components 1204-1222 that are identical or similar to the corresponding components will no longer be referenced. Figure 12 Detailed description. The control circuit 1201 includes a current threshold generator 1218, which includes components coupled in parallel to receive a corresponding current threshold voltage V. ISET1 V ISET2 and V ISET3Multiple switches S1, S2, and S3 are configured between corresponding nodes. One of switches S1-S3 is activated, with the activated switch based on the number of valleys skipped in the valley skipping operation mode of the PFC pre-regulator 1200. When one valley is being skipped, switch S1 is activated (closed), while switches S2 and S3 are deactivated (i.e., open). When two valleys are being skipped, switch S2 is activated, while switches S1 and S3 are deactivated; when three valleys are being skipped, switch S3 is activated, while switches S1 and S2 are deactivated. Circuitry in control circuitry 1201 generates 1VALLEY_SKIP, 2VALLEY_SKIP, and 3VALLEY_SKIP signals to control switches S1-S3.

[0065] These and other changes may be made to the embodiments in light of the above detailed description. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments to which such claims are entitled, as well as the full scope of their equivalents. Therefore, the claims are not limited by the disclosure.

Claims

1. A control circuit configured to control a power factor correction (PFC) pre-regulator, the PFC pre-regulator including a power switch and configured to operate in a switching operation mode and a valley skip operation mode, the control circuit being configured to generate a drive signal based on a current threshold to control the switching of the power switch, and the control circuit including a current threshold generator configured to modulate the current threshold within half a cycle of an input power supply voltage according to the number of valleys skipped in the valley skip operation mode. The PFC pre-regulator is configured to receive the input power supply voltage, and the control circuitry further includes a slice generator configured to divide a half-cycle of the input power supply voltage into equal time slices and assign a number to each time slice, wherein the current threshold generator receives the number of the current time slice from the slice generator and is further configured to modulate the current threshold based on the number of the current time slice. The control circuit further includes a finite state machine configured to generate the drive signal to control the power switch to turn off and on.

2. The control circuit according to claim 1, wherein the switching operation mode is an enhanced constant on-time control of the PFC pre-regulator.

3. The control circuit according to claim 1, wherein the number of valley values ​​skipped in the valley value skipping operation mode is one of the following: one valley value skipping, two valley value skipping, three valley value skipping, and four or more valley value skipping.

4. The control circuit according to claim 1, The PFC pre-regulator includes an inductive element coupled to the power switch; The control circuit includes: A current sensing comparator includes a first input and a second input, the first input being coupled to a current sensing node to receive a current sensing signal indicating the current through the inductor element, and the second input being coupled to the current threshold generator to receive the current threshold; and A zero-current sensing node is configured to provide a signal indicating a zero-current state of the current flowing through the inductive element; and The current threshold generator includes: A diode having a cathode coupled to the zero-current sensing node; and Multiple switches and multiple resistors, each of the multiple switches and a corresponding resistor of the multiple resistors are coupled in series between the anode of the diode and the current sensing node, wherein one of the multiple switches is activated based on the number of valleys skipped.

5. The control circuit according to claim 1, The PFC pre-regulator includes an inductive element coupled to the power switch; The control circuit includes: A current sensing comparator includes a first input and a second input. The first input is coupled to a current sensing node to receive a current sensing signal indicating the current through the inductor element, and the second input is coupled to a current threshold generator to receive the current threshold. The current threshold generator includes: Multiple current threshold voltage nodes, each configured to receive a corresponding current threshold voltage; and Multiple switches, each of which is coupled between a corresponding current threshold voltage node in a plurality of current threshold voltage nodes and the second input, wherein one of the multiple switches is activated based on the number of valleys skipped.

6. The control circuit according to claim 1, wherein the PFC pre-regulator has a boost topology.

7. The control circuit of claim 1, wherein the control circuit further comprises a pulse width modulation circuit means configured to control the switching of the power switch.

8. The control circuit according to claim 1, wherein the power switch comprises a MOS power transistor.

9. The control circuit of claim 1, wherein the control circuit includes a resistor network comprising a plurality of parallel-coupled resistors configured to generate a plurality of voltages, each of the plurality of voltages corresponding to a corresponding value of the modulated current threshold.

10. A control method for a switching power supply, comprising: A drive signal is generated to control the switching of the power switch in the power factor correction (PFC) pre-regulator, so as to operate the PFC pre-regulator in a switching operation mode and a valley skip operation mode. The current threshold is generated based on the value and phase of the input voltage supplied to the PFC pre-regulator; The current threshold is modulated by the current threshold generator within half a cycle of the input voltage based on the number of valleys skipped in the valley skip operation mode. as well as The drive signal is generated based on the current threshold to control the switching of the power switch. The PFC pre-regulator is configured to receive the input voltage, and modulating the current threshold includes: The half-cycle of the input voltage is divided into equal time slices; Assign a number to each time slice; The current threshold generator receives the current time slice number from the slice generator; and The current threshold is modulated based on the number of the current time slice, and The generation of the drive signal includes generating the drive signal by a finite state machine to control the power switch to turn off and on.

11. The method of claim 10, wherein the PFC pre-regulator includes an inductor coupled to the power switch, and wherein generating the drive signal includes comparing the current through the inductor with the current threshold.

12. The method of claim 11, further comprising: Timing of the power switch being activated in response to the current through the inductor element reaching the current threshold.

13. The method of claim 12, wherein the timing of the on-time of activating the power switch comprises: Activate a digital timer to generate a count indicating the duration for which the power switch has been turned on.

14. The method of claim 10, wherein the switching operation mode is an enhanced constant on-time control operation mode of the PFC pre-regulator.

15. A power factor correction pre-regulator, comprising: A switching circuit device includes an inductive element coupled to a switching element configured to receive a drive signal to control the switching of the switching element, and the switching circuit device is configured to receive an AC input voltage and to generate an output voltage in response to the drive signal based on the AC input voltage. as well as A control circuit, coupled to the switching circuit device, is configured to generate the drive signal to control the switching in a transition operation mode and a valley skip operation mode, and the control circuit is further configured to generate the drive signal based on a current threshold, and to modulate the current threshold within half a cycle of the input voltage according to the number of valleys skipped in the valley skip operation mode. The control circuit includes a resistor network comprising a plurality of parallel-coupled resistors configured to generate a plurality of voltages, each of the plurality of voltages corresponding to a corresponding value of the modulated current threshold, wherein one end of the resistor network is connected to a current sensing node and the other end is connected to a zero current sensing node.

16. The power factor correction pre-regulator of claim 15, wherein the switching circuit device has a boost topology.

17. The power factor correction pre-regulator of claim 15, wherein the control circuit is configured to compare the current through the inductor with a current value of a modulated current threshold, and to generate the drive signal to turn on the switching element in response to the current through the inductor reaching the current value of the modulated current threshold.

18. The power factor correction pre-regulator of claim 15, wherein the control circuitry further comprises a slice generator configured to divide a half-cycle of the input voltage into equal time slices and assign a number to each time slice, and modulate the current threshold based on the number of the current time slice.

19. The power factor correction pre-regulator of claim 18, wherein the control circuit further comprises a finite state machine configured to generate the drive signal to control the switching element to turn off and on.

20. A control method for a switching power supply, comprising: A drive signal is generated to control the switching of the power switch in the power factor correction (PFC) pre-regulator, so as to operate the PFC pre-regulator in a switching operation mode and a valley skip operation mode. The current threshold is generated based on the value and phase of the input voltage supplied to the PFC pre-regulator; The current threshold is modulated within half a cycle of the input voltage based on the number of valleys skipped in the valley skip operation mode. The drive signal is generated based on the current threshold to control the switching of the power switch; as well as Multiple voltages are generated by a resistor network comprising multiple resistors coupled in parallel, each of the multiple voltages corresponding to a corresponding value of the modulated current threshold, wherein one end of the resistor network is connected to a current sensing node and the other end is connected to a zero current sensing node.

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