A level shift circuit

Abstract

The present invention relates to a level shift circuit, wherein the circuit comprises VDD as a chip power supply, GND as a chip ground; HB as a floating power supply on the high side of a half-bridge; HS as a floating ground on the high side of the half-bridge; N1 and N2 as MOSs that bear the high voltage of the half-bridge; resistors R1 and R2 as two resistors that generate a voltage difference; transistors Q1, Q2, Q3, and Q4 form two groups of current mirrors; transistor Q5 is a current source that provides a bias current to a Q1 branch or a Q3 branch respectively, and the magnitude of the bias current is determined by a bias voltage Vb and resistors R3 or R4; P1, P 2 is a switch tube that controls whether the two sets of current mirrors generate current, which is controlled by pulse signals pulse1 and pulse2 respectively; P3 and P4 are sampling switch tubes; R5, R6 resistors and N3 are RS latches to generate initial states; PulseGen module receives DRV_IN signal and generates two low narrow pulse signals pulse1 and pulse2, and RS latch generates output signal DRV_OUT, which controls the subsequent drive circuit; the solution is novel and concise, and can limit the power consumption of the circuit to an extremely low level with accurate power consumption value.

Description

Technical Field

[0001] The invention relates to a level shift circuit, belonging to the technical field of power management. Background Art

[0002] In a high-voltage half-bridge drive circuit, two drive signals need to be generated, one is a high-side drive and the other is a low-side drive. The generation of the high-side drive signal requires a dedicated level shift circuit for voltage domain conversion.

[0003] In applications, high-voltage half-bridge applications range from tens of volts to hundreds of volts, and the driver chip needs to integrate devices that can withstand this voltage for voltage domain conversion. Figure 1 As shown, it is the topological structure of the level conversion circuit of the prior art. VDD is the power supply voltage of the chip; GND is the chip ground, HB is the floating power supply voltage of the high-voltage side of the half-bridge; HS is the floating ground of the high-voltage side of the half-bridge; R1 and R2 are resistors; N1 and N2 are high-voltage MOS to ensure that they can withstand the power supply voltage of the high-voltage side of the half-bridge; PulseGen is a pulse generation module, which selects to generate two pulse signals according to whether the drive signal DRV_IN becomes high or low, and controls N1 or N2; RS latch is a NAND gate latch, which outputs the drive signal DRV_OUT to control the subsequent drive circuit.

[0004] Working principle: When the DRV_IN signal goes high, PulseGen generates a narrow pulse of pulse1, which controls N1 to turn on briefly. For the RS latch, S is high and R is low, so the output DRV_OUT becomes high. Even after the narrow pulse disappears, the RS latch is in the latched state, and DRV_OUT remains high. When the DRV_IN signal goes low, Pulse Gen generates a narrow pulse of pulse2, which controls N2 to turn on briefly. For the RS latch, S is low and R is high, and DRV_OUT becomes low. Even after the narrow pulse disappears, DRV_OUT remains low. Related waveforms are shown below: Figure 2 shown.

[0005] The level shift structure uses narrow pulses to reduce the conduction time of N1 and N2, thereby reducing the power consumption of resistors R1 and R2. However, the difficulty of this structure is that when N1 or N2 is turned on, the voltage at the bottom of R1 or R2 cannot be directly pulled to 0V, otherwise it will cause the gate oxide breakdown of the MOS tube of the RS latch behind, and at the same time, the power consumption on R1 or R2 is still too large and difficult to control; if the voltage at the bottom of R1 or R2 is pulled down too little, the RS latch behind is not easy to flip, so that the DRV_OUT signal cannot be output normally. Therefore, a new solution is urgently needed to solve the above technical problems. Summary of the invention

[0006] The present invention aims at the problems existing in the prior art and provides a level shift circuit. The technical solution can accurately control the offset of the voltage at the lower end of R1 or R2, which can not only ensure the subsequent RS latch to be flipped, but also ensure that the power consumption generated on the resistor is further reduced.

[0007] In order to achieve the above-mentioned purpose, the technical scheme of the present invention is as follows: a level shift circuit, wherein the circuit includes VDD as a chip power supply, usually 10 to 30V; GND as a chip ground; HB as a floating power supply on the high side of a half-bridge, usually tens of volts to hundreds of volts; HS as a floating ground on the high side of a half-bridge; N1 and N2 are MOSs that withstand the high voltage of the half-bridge; resistors R1 and R2 are two resistors that generate a voltage difference; transistors Q1, Q2, Q3, and Q4 form two groups of current mirrors; transistor Q5 is a current source that provides a bias current to the Q1 branch or the Q3 branch, and the magnitude of the bias current It is determined by the bias voltage Vb and the resistor R3 or R4; P1 and P2 are switch tubes that control whether the two sets of current mirrors generate current, and are controlled by the pulse signals pulse1 and pulse2 respectively; P3 and P4 are sampling switch tubes; R5, R6 resistors and N3 are the initial state generated by the RS latch; the PulseGen module receives the DRV_IN signal and generates two low narrow pulse signals pulse1 and pulse2, and the waveform of the narrow pulse signal is shown in the module; the RS latch generates an output signal DRV_OUT, which controls the subsequent drive circuit.

[0008] The emitter of the transistor Q5 is connected to the Source terminals of P1 and P2 respectively, the Gate terminal of P1 is connected to the pulse1 signal, the Drain terminal of P1 is connected to the resistor R3, the other end of the resistor R3 is connected to the collector and base of the transistor Q1, and the base of the transistor Q2, the emitters of the transistors Q1 and Q2 are grounded, the collector of the transistor Q2 is connected to the Source terminal of N1, the Gate terminal of N1 is connected to VDD, the Drain terminal of N1 is connected to the resistor R1, the Source terminal of P3, and the Gate terminal of P4, and the other end of R1 is connected to the floating HB; the Drain terminal of P2 Connect to R4, the other end of R4 is connected to the collector, base of Q3, and base of Q4, the emitters of transistors Q3 and Q4 are grounded, the collector of transistor Q4 is connected to the Source end of N2, the Gate end of N2 is connected to VDD, the Drain end of N2 is connected to resistor R2, the Source end of P4, and the Gate end of P3, and the other end of R1 is connected to the floating HB; the Drain end of P3 is connected to R5 and RS trigger, the other end of R5 is grounded, the Drain end of P4 is connected to R6, the Drain end of N3, and RS trigger, the other end of R6 is grounded, and the Source end of N3 is grounded.

[0009] Furthermore, HB is a floating power supply on the high side of the half-bridge, which is set to tens of volts to hundreds of volts.

[0010] Furthermore, VDD is a chip power supply, which is set to 10-30V.

[0011] Compared with the prior art, the present invention has the following advantages: the technical solution proposes a level shift circuit for half-bridge driving, and the power consumption control of the circuit is extremely accurate and convenient; the entire technical solution is novel, concise and practical, and the level shift circuit proposes a new idea in the design of circuit power consumption, which can limit the circuit power consumption to an extremely low level, the control method is convenient, and the power consumption value is accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of a circuit of the prior art;

[0013] Figure 2 It is a schematic diagram of related waveforms in the prior art;

[0014] Figure 3 It is a schematic diagram of the circuit principle of the present invention;

[0015] Figure 4 This is a schematic diagram of the narrow pulse information obtained by the present invention; DETAILED DESCRIPTION

[0016] In order to deepen the understanding of the present invention, the present embodiment is described in detail below with reference to the accompanying drawings.

[0017] Embodiment 1: A level shift circuit, such as Figure 3As shown in the figure, VDD is the chip power supply, usually 10~30V; GND is the chip ground; HB is the floating power supply of the high side of the half bridge, usually tens of volts to hundreds of volts; HS is the floating ground of the high side of the half bridge; N1 and N2 are MOS that withstand the high voltage of the half bridge; R1 and R2 are two resistors that generate voltage difference; Q1, Q2, Q3, and Q4 form two groups of current mirrors; Q5 is a current source, which provides bias current to the Q1 branch or the Q3 branch respectively, and the size of the bias current is determined by the bias voltage Vb and the resistor R3 or R4; P1 and P2 are used to control whether the two groups of current mirrors generate The switch tubes for generating current are controlled by pulse signals pulse1 and pulse2 respectively; P3 and P4 are sampling switch tubes; R5, R6 resistors and N3 are RS latches to generate initial states; PulseGen module receives DRV_IN signal and generates two low narrow pulse signals pulse1 and pulse2, the waveform of narrow pulse signal is shown in the module; RS latch generates output signal DRV_OUT, which controls the subsequent drive circuit; wherein the emitter of transistor Q5 is connected to the source of P1 and P2 respectively e terminal, the Gate terminal of P1 is connected to the pulse1 signal, the Drain terminal of P1 is connected to the resistor R3, the other end of the resistor R3 is connected to the collector and base of the transistor Q1, and the base of the transistor Q2, the emitters of the transistors Q1 and Q2 are grounded, the collector of the transistor Q2 is connected to the Source terminal of N1, the Gate terminal of N1 is connected to VDD, the Drain terminal of N1 is connected to the resistor R1, the Source terminal of P3, and the Gate terminal of P4, and the other end of R1 is connected to the floating HB; the Drain terminal of P2 is connected to R4, and the other end of R4 is connected to the collector of Q3. The electrode, base, and base of Q4, the emitters of transistors Q3 and Q4 are grounded, the collector of transistor Q4 is connected to the Source end of N2, the Gate end of N2 is connected to VDD, the Drain end of N2 is connected to resistor R2, the Source end of P4, and the Gate end of P3, and the other end of R1 is connected to floating HB; the Drain end of P3 is connected to R5 and RS trigger, the other end of R5 is grounded, the Drain end of P4 is connected to R6, the Drain end of N3, and RS trigger, the other end of R6 is grounded, and the Source end of N3 is grounded. VDD is the chip power supply, set to 10~30V. HB is the floating power supply on the high side of the half-bridge, set to tens of volts to hundreds of volts.

[0018] Working principle:

[0019] When the DRV_IN signal goes high, the pulse1 signal of the PulseGen module generates a low-level narrow pulse, and the Q1 and Q2 current mirrors generate current. The current size of Q1 can be expressed as: Q1 and Q2 can be designed to have a ratio of N:1, and the current of Q2 can be expressed as: The voltage drop across resistor R1 can be expressed as: When designing, match the R1 and R3 resistors, and the voltage drop of the R1 resistor will be always accurate; after the voltage drop occurs on R1, the Gate end of P4 will drop As long as the voltage is greater than the threshold of P4, P4 will be turned on. After P4 is turned on, the S2 signal will be raised to HB.

[0020] Since pulse2 is at a high level at this time, there is no current in the Q3 and Q4 current mirrors, and there is no voltage drop across the R1 resistor, that is, the voltage at the lower end of the R1 resistor is also at a high level HB. For P3, the Gate is at a high level and is not conducting. The S1 signal is kept at a low level HS due to the pull-down of the resistor R5. As mentioned earlier, S2 is at a high level HB at this time, so the latch output DRV_OUT becomes high.

[0021] After the narrow pulse of pulse1, pulse1 becomes high. At this time, there is no current in the two current mirrors Q1, Q2, Q3, and Q4, and there is no voltage drop in R1 and R2. Therefore, P3 and P4 are not turned on. S1 maintains a low level HS due to the pull-down resistor R5, and S2 also maintains a low level HS due to the pull-down resistor R6. The latch is in the hold state at this time, and the output DRV_OUT maintains a high level.

[0022] When the DRV_IN signal becomes low, pulse1 is high and pulse2 is low, then the Q1 and Q2 current mirrors have no current, the Q3 and Q4 current mirrors have current, R1 has no voltage drop, R2 has a voltage drop, and the magnitude of the voltage drop is similar to the expression for R1 described above, so P3 is turned on and P4 is not. The S1 signal becomes high level HB, and the S2 signal is still low level HS due to R6 and N3, so the latch output DRV_OUT becomes low.

[0023] After the narrow pulse of Pulse2, it becomes a high level, there is no current in both sets of current mirrors, P3 and P4 are not turned on, and S1 and S2 become a low level HS due to the pull-down resistor. At this time, the latch is in the holding state and remains at a low level.

[0024] It can be seen that the present invention can not only realize the function of level shift in terms of function, but also has a significant improvement in power consumption. It is easy to design, and the voltage does not need to be very large, it only needs to be greater than the threshold voltage of P3 and P4. Therefore, the power consumption generated by R1 and R2 is completely controllable and the power consumption is extremely low.

[0025] The Pulse Gen module can use simple logic combinations to obtain narrow pulse signals. Figure 4 The width of the narrow pulse can be obtained by adjusting the resistors and capacitors in the figure, which is convenient for adjustment.

[0026] It should be noted that the above embodiments are not intended to limit the protection scope of the present invention, and equivalent changes or substitutions made on the basis of the above technical solutions all fall within the protection scope of the claims of the present invention.

Claims

1. A level shift circuit, characterized in that: The circuit includes VDD as chip power supply, GND as chip ground; HB as floating power supply on the high side of the half bridge; HS as floating ground on the high side of the half bridge; N1 and N2 are MOSs that withstand the high voltage of the half bridge; resistors R1 and R2 are two resistors that generate voltage difference; transistors Q1, Q2, Q3, and Q4 form two groups of current mirrors; transistor Q5 is a current source, which provides bias current for Q1 branch or Q3 branch respectively, and the magnitude of the bias current is determined by the bias voltage Vb and resistor R3 or R4; P1 and P2 are switch tubes that control whether the two groups of current mirrors generate current, which are controlled by pulse signals pulse1 and pulse2 respectively; P3 and P4 are sampling switch tubes; R5, R6 resistors and N3 are RS latches to generate initial states; the PulseGen module receives the DRV_IN signal and generates two low narrow pulse signals pulse1 and pulse2, and the waveform of the narrow pulse signal is shown in the module; the RS latch generates an output signal DRV_OUT, which controls the subsequent drive circuit, The collector of the transistor Q5 is connected to the chip power supply, the emitter of the transistor Q5 is connected to the Source terminals of P1 and P2 respectively, and the base of the transistor Q5 is connected to the bias voltage Vb. The Gate terminal of P1 is connected to the pulse1 signal, the Drain terminal of P1 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the collector and base of the transistor Q1, and the base of the transistor Q2, the emitters of the transistors Q1 and Q2 are grounded, the collector of the transistor Q2 is connected to the Source terminal of N1, the Gate terminal of N1 is connected to VDD, the Drain terminal of N1 is connected to one end of the resistor R1, the Source terminal of P3, and the Gate terminal of P4, and the other end of R1 is connected to the floating power supply HB; the Drain terminal of P2 is connected to one end of R4, and the other end of R4 is connected to the collector and base of Q3, and the base of Q4. The emitter is grounded, the collector of transistor Q4 is connected to the Source end of N2, the Gate end of N2 is connected to VDD, the Drain end of N2 is connected to one end of resistor R2, the Source end of P4, the Gate end of P3, and the other end of R2 is connected to the floating power supply HB; the Drain end of P3 is connected to one end of R5 and the first input end of the RS trigger, the other end of R5 is grounded, the Drain end of P4 is connected to one end of R6, the Drain end of N3, and the second input end of the RS trigger, the other end of R6 is grounded, and the Source end of N3 is grounded; the Gate end of N3 is connected to S1, and the S1 signal is the voltage signal of the resistor R5. HB is the floating power supply of the high side of the half-bridge, which is set to tens of volts to hundreds of volts. VDD is the chip power supply, which is set to 10~30V.

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