Computing Device and Computing System

Abstract

A computing device and a computing system are provided. The computing device may include a main branch target buffer (BTB). The device may include: a micro BTB, separated from the main BTB and smaller than the main BTB, and configured to generate prediction information associated with branch instructions. The device may include: a micro BTB confidence counter, configured to measure the correctness of the prediction information generated by the micro BTB. The device may further include: a micro BTB misprediction rate counter, configured to measure the ratio of mispredictions generated by the micro BTB. The device may further include: micro BTB enabling logic circuitry, configured to enable the use of the prediction information of the micro BTB based at least in part on the values of the micro BTB confidence counter and the micro BTB misprediction rate counter.

Description

Technical Field

[0001] This description relates to computer architectures, and more particularly, to a method and apparatus for controlling the use of a hierarchical branch predictor based on the validity of the results of the hierarchical branch predictor. Background Art

[0002] A Central Processing Unit (CPU) typically predicts the direction and target of branch instructions early in the processing pipeline to improve performance. Information about the type, location, and target of branch instructions is typically cached in a Branch Target Buffer (BTB) accessed using the instruction fetch address, and a Content Addressable Memory (CAM) is used to detect whether the BTB contains a branch mapped to the current fetch window. The BTB can also use a set-associative structure to detect whether the BTB contains a branch mapped to the current fetch window. Conventional BTBs are typically large structures, and when combined with a branch direction predictor, result in at least one cycle penalty (i.e., a bubble) for predicted-taken branches. In some cases, conventional BTBs may even incur a penalty for predicted-not-taken branches.

[0003] Attempts have been made to address this penalty by using a circular buffer or a similar structure to hide the predicted-taken branch bubble, but these methods have limitations. The circular buffer requires all instructions in the loop to be applicable within the circular buffer, not just the branch instruction. Smaller and simpler BTBs that do not include a conditional branch predictor cannot accurately predict branches with dynamic results and will result in performance and energy waste. In addition, smaller and simpler BTBs that do not employ chaining will waste energy on CAM operations. Summary of the Invention

[0004] According to one general aspect, an apparatus may include a main branch target buffer (BTB). The apparatus may include a micro BTB that is separate from and smaller than the main BTB, and the micro BTB is configured to generate prediction information associated with a branch instruction. The apparatus may include a micro BTB confidence counter that is configured to measure the correctness of the prediction information generated by the micro BTB. The apparatus may further include a micro BTB misprediction rate counter that is configured to measure the ratio of mispredictions generated by the micro BTB. The apparatus may further include a micro BTB enable logic circuit that is configured to enable the use of the prediction information of the micro BTB based at least in part on the values of the micro BTB confidence counter and the micro BTB misprediction rate counter.

[0005] According to another general aspect, an apparatus may include a main branch target buffer (BTB). The apparatus may include a micro BTB that is separate from and smaller than the main BTB, and the micro BTB is configured to generate prediction information associated with a branch instruction. The apparatus may include a main BTB confidence counter that is configured to measure the correctness of the prediction information generated by the main BTB. The apparatus may include a main BTB misprediction rate counter that is configured to measure the ratio of mispredictions generated by the main BTB. The apparatus may include a micro BTB enable logic circuit that is configured to enable the use of the prediction information of the micro BTB based at least in part on the values of the main BTB confidence counter and the main BTB misprediction rate counter.

[0006] According to another general aspect, a system may include: a front-end logic portion configured to fetch and predict a sequence of instructions to be executed. The front-end logic portion may include a main branch target buffer (BTB). The front-end logic portion may include a micro BTB that is separate from and smaller than the main BTB, and the micro BTB is configured to generate prediction information associated with a branch instruction. The system may include a heuristic logic circuit that includes a plurality of counters configured to measure the effectiveness of the main BTB and the micro BTB, and determines whether to enable the use of the prediction information of the micro BTB based at least in part on the plurality of counters.

[0007] Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the specification, the drawings, and from the claims.

[0008] A system and / or method for a computer architecture, and more particularly, a method and apparatus for controlling the use of a hierarchical branch predictor based on the validity of the results of the hierarchical branch predictor, substantially as shown in at least one of the accompanying drawings and / or as described in conjunction with at least one of the accompanying drawings, and as more fully set forth in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of an example embodiment of a system according to the disclosed subject matter.

[0010] Figure 2 is a flowchart of an example embodiment of a technique according to the disclosed subject matter.

[0011] Figure 3 is a timing diagram of an example embodiment of a technique according to the disclosed subject matter.

[0012] Figure 4 is a schematic block diagram of an information processing system that may include a device formed in accordance with the principles of the disclosed subject matter.

[0013] Like reference numerals in the various drawings indicate like elements. DETAILED DESCRIPTION

[0014] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings in which some example embodiments are shown. However, the disclosed subject matter may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosed subject matter to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0015] It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. Throughout the specification, like reference numerals refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another. Thus, a first element, first component, first region, first layer, or first section discussed below may be referred to as a second element, second component, second region, second layer, or second section without departing from the teachings of the subject matter of the present disclosure.

[0017] For ease of description, spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another (or others) as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "beneath" or "lower" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly.

[0018] Similarly, for ease of description, electrical terms, such as "high", "low", "pull-up", "pull-down", "1", "0", etc., may be used herein to describe the voltage level or current as shown in the figures relative to other voltage levels or relative to another (or others) element or feature. It will be understood that these electrically related terms are intended to include different reference voltages of the device in use or operation in addition to the voltages or currents depicted in the figures. For example, if the device or signal in the figures is inverted or other reference voltages, currents, or charges are used, an element described as "high" or "pull-up" would then be "low" or "pull-down" compared to the new reference voltage or current. Thus, the exemplary term "high" can include both relatively low or high voltages or currents. The device may additionally be based on different electrical reference frameworks, and the electrically relative descriptors used herein are to be interpreted accordingly.

[0019] The terms used in this disclosure are for the purpose of describing particular example embodiments only and are not intended to limit the subject matter of the disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] Example embodiments are described with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions shown herein but include shape deviations resulting, for example, from manufacturing. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient in the implant concentration rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of regions of the device and are not intended to limit the scope of the subject matter of the disclosure.

[0021] All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the disclosure belongs, unless otherwise defined. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Hereinafter, example embodiments will be explained in detail with reference to the drawings.

[0023] Figure 1 is a block diagram of an example embodiment of a system 100 according to the disclosed subject matter. For example, in various embodiments, system 100 may include a computing device (such as a processor, a system-on-chip (SoC), a laptop computer, a desktop computer, a workstation, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or their virtual machines or virtual computing devices). In various embodiments, system 100 may employ a pipeline architecture including various pipeline stages.

[0024] In such an embodiment, a portion of the pipeline may include fetch logic circuit 102, where the fetch logic circuit 102 is configured to fetch instructions that are correspondingly processed by system 100. The current (at least for this pipeline stage) instruction may be saved or referenced in a Program Counter (PC) 112. Generally, as instructions are fetched sequentially one after another, the PC 112 is incremented. However, occasionally the program does not proceed in order, but instead jumps or branches to a new location. Traditionally, common types of branch instructions include IF statements, loops, subroutine calls or returns, etc. In essence, the program reaches a fork in the road of execution and must decide which path to take.

[0025] Due to the pipelined nature of system 100, this can be very costly. Will the program continue the loop or break out of the loop? Is the IF statement true or false? These options are generally referred to as the branch being "Taken" or "Not Taken". System 100 can pause all execution until the branch instruction is resolved. However, more desirably, system 100 predicts how the branch instruction will be resolved and then speculatively executes the predicted path. If the prediction is correct, then system 100 does not waste any time. Otherwise, system 100 must invalidate all of its speculative work, roll the machine back to the mispredicted branch instruction, and proceed along the other execution path. As a result, there is a great need to improve the prediction accuracy.

[0026] One technique to achieve this is the Branch Target Buffer (BTB). The BTB is a memory that can be addressed by the instruction address (usually the current PC 112) and recalculates the path (Taken / Not Taken, or the target address of the branch) that resolved the branch instruction the last time the branch instruction was encountered. Through this path, the front-end logic circuit or portion 108 can quickly predict the resolution of the branch instruction and proceed.

[0027] In the illustrated embodiment, system 100 may include a main branch target buffer (mBTB) 104 that is typically sized to accommodate a relatively large number of possible addresses (branch instructions) and still be able to return a desired prediction in a relatively fast time period. In various embodiments, the size may vary, but the general tradeoff between speed and size is understood. As described above, mBTB 104 may include a table or data structure, where the table or data structure includes the address of the branch instruction, the address of the target instruction, and a valid bit or flag. In such an embodiment, the valid bit or flag may indicate that data has been explicitly written into mBTB 104 and that it should be considered for acceptable use. The valid bit differentiates valid data (which may be dependent and meaningful) from invalid data (which is assumed to be meaningless; e.g., random bits from an old program run that have not been reset since system startup).

[0028] The fetch logic circuit 102 or prefetch logic circuit 106 may then fetch or retrieve the target instruction indicated by mBTB 104. In various embodiments, this may involve requesting the target instruction from a cache configured to store instructions, such as a level 1 (L1) instruction cache (i-cache or iCache) 120. In such an embodiment, L1 iCache 120 may include a series of tags 124 and be associated with an L1 translation look-aside buffer (TLB) 122. In various embodiments, other or multiple cache levels may be used. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0029] Additionally, in the illustrated embodiment, system 100 may include a return address stack (RAS) 107 for branch instructions that include subroutine calls. When a subroutine call occurs, the return address of the subroutine may be pushed onto RAS 107. When the subroutine completes and returns (via another branch instruction), the return address may be popped from RAS 107 and used as the target address.

[0030] In the illustrated embodiment, a micro branch target buffer (uBTB or μBTB) 114 may be employed. uBTB 114 may differ primarily in size from a traditional mBTB 104. In such an embodiment, uBTB 114 may provide faster performance because there are fewer entries to search. In such an embodiment, uBTB 114 may be primarily used for instruction kernels that have a limited number of instructions that are repetitive or more generally predictable. In various embodiments, this may include loops that can be captured in a small loop buffer.

[0031] In such an embodiment, the uBTB 114 may include a BTB that is smaller than the mBTB 104 and may thus be faster and consume less power. In the illustrated embodiment, the uBTB 114 may provide prediction information that may be received by the front-end logic portion 108 of the system 100. When the information (specifically, the prediction information) from the uBTB 114 has been verified as correct, portions of the front-end logic portion 108 may be powered down and may rely on the uBTB 114 to predict target instructions. In various embodiments, the portions that may be powered down may include the TLB 122, the L1 instruction cache full-tag or micro-tag array 124, the tag comparison logic or branch target address verification logic 106, the mBTB 104, the primary conditional predictor (such as the mBTB predictor 105), and / or the RAS 107. In another embodiment, only the L1 instruction cache may be powered on. It should be understood that the foregoing are merely illustrative examples and the disclosed subject matter is not limited thereto.

[0032] In a particular embodiment, the uBTB 114 may include 128 entries. In such an embodiment, if the basic block covered by the uBTB 114 is large enough and the uBTB 114 is able to correctly predict all branches within a program kernel, the disclosed subject matter may cover a program kernel that fills the entire 64 kilobyte instruction cache. In such an embodiment, this may include program kernels with complex branch patterns, dynamic indirect branches, conditional branches, and subroutine calls and returns, as described below.

[0033] In various embodiments, the penalty for misprediction by the uBTB 114 may be undesirably high. For example, in various embodiments, the mBTB 104 and the primary conditional predictor (such as the mBTB predictor 105) may have been powered down due to high uBTB confidence, in which case a very expensive backend redirection may be required, approximately 15 cycles, compared to a 2-cycle penalty for mBTB redirection by the uBTB). If the accuracy or coverage of the uBTB 114 is too low, the front end 108 may have to redirect the fetch command in order to restart it with the mBTB 104. In addition to the cost of switching power modes, this may introduce bubbles or no-operations (NOOPs), i.e., inactive periods, into the pipeline of the system 100. These bubbles would not exist if the uBTB 114 was not enabled in the first place.

[0034] In some embodiments, the uBTB 114 takes time to train or lock onto a prediction scheme or set of predictions. In various embodiments, for example, this lock time can (temporarily) disable low-latency predictors (such as the uBTB predictor 115), such as Zero-Cycle Always Taken (ZAT) or Zero-Cycle Often Taken (ZOT). This degrades performance by substantially stopping instruction fetch while attempting to allow the uBTB 114 to train. In various embodiments, the uBTB 114 can train itself offline at commit time.

[0035] As briefly mentioned, the uBTB 114 can be associated with multiple or several predictors (such as the uBTB predictor 115) or prediction techniques. For example but not limited to the uBTB loop / anti-loop predictor and / or the uBTB non-loop conditional predictor. Similarly, the mBTB 104 can be associated with its own predictor (such as the mBTB predictor 105) or prediction scheme. In various embodiments, the mBTB predictor 105 can include a predictor that predicts the branch direction of the conditional branches tracked by the mBTB 104. As discussed below, these predictors (such as the uBTB predictor 115 and the mBTB predictor 105) can be independently turned on or off and can even overlap. In some embodiments, the system 100 can be configured to allow testing of the predictors to determine which are effective and accurate and which are not.

[0036] In the illustrated embodiment, the system 100 can include heuristic or enabling logic circuitry 130. In such an embodiment, the enabling logic circuitry 130 can be configured to determine whether the uBTB 114 is performing poorly (or well) and enable / disable the uBTB 114 in favor of the mBTB 104. In some embodiments, disabling the uBTB 114 can include powering off the uBTB 114. However, in another embodiment, disabling can simply include preventing the prediction results of the uBTB 114 from being used. That is, both the uBTB 114 and the mBTB 104 can perform prediction tasks, but only the predictions of the mBTB 104 can be used. In such an embodiment, the uBTB 114 can be given time to train or lock onto a prediction scheme without negatively impacting the system 100, as described above.

[0037] In such an embodiment, the enable logic circuit 130 may be configured to continuously monitor and evaluate the performance of the uBTB 114. The enable logic circuit 130 may compare the accuracy (or other metric) of the uBTB 114 with that of the mBTB 104 and then determine which is more accurate. The enable logic circuit 130 may then enable the use of the prediction of the more accurate BTB. Thus, power and time can be saved.

[0038] In the illustrated embodiment, the system 100 may include several counters or other measurement circuits, such as a uBTB confidence counter 132, a uBTB misprediction rate counter 134, an mBTB confidence counter 142, an mBTB misprediction rate counter 144, and an event counter(s) 146. In this one embodiment, the enable logic circuit 130 may measure the accuracy of the uBTB 114 and the mBTB 104 via the uBTB confidence counter 132 and the mBTB confidence counter 142, and may measure the rate of mispredictions via the uBTB misprediction rate counter 134 and the mBTB misprediction rate counter 144. Further activities of the enable logic circuit 130 may be controlled by various events measured by the event counter(s) 146, as described below.

[0039] In various embodiments, the enable logic circuit 130 may measure when the uBTB 114 and the mBTB 104 (or more precisely, the uBTB predictor 115 and the mBTB predictor 105, respectively) correctly predict which path a branch will take. This may be done during the commit stage of the pipeline stage. In the illustrated embodiment, the system 100 may include a commit logic circuit 190 that determines whether a speculated instruction should have been executed. If so, the result of the instruction processing is committed and the system 100 proceeds. In the case of a branch, the commit logic circuit 190 determines whether the branch is correctly predicted. This data is then fed back to the front end 108, where at the front end 108, the enable logic circuit 130 (or other circuit) compares the committed branch with the prediction and determines the accuracy of the prediction.

[0040] After a branch instruction is committed, both the uBTB confidence counter 132 and the mBTB confidence counter 142 may be updated. The uBTB confidence counter 132 (e.g., the value of the uBTB confidence counter 132) may be compared with the prediction of the uBTB 114. This may be done even if the prediction of the uBTB 114 is not actually used, thus allowing the uBTB 114 to be trained and evaluated for its performance without negatively impacting the system 100. Similarly, the mBTB confidence counter 142 (e.g., the value of the mBTB confidence counter 142) may be compared with the prediction of the mBTB 104.

[0041] In various embodiments, the uBTB confidence counter 132 and the mBTB confidence counter 142 may include a thermometer weighted counter. In such embodiments, if the counter saturates or reaches a threshold, then both may be reset or, in the case of one embodiment, divided by two.

[0042] In the illustrated embodiment, one of the predictors employed by the uBTB 114 (such as the uBTB predictor 115) may include a hash tag predictor. In various embodiments, this may be a version of a hash conditional branch predictor, where the hash conditional branch predictor uses the direction history of a single branch (e.g., taken / not taken) to predict the next direction of that branch. Similarly, the mBTB 104 may include a predictor (such as the mBTB predictor 105), where the predictor includes a different or similar hash-tagged predictor to predict the conditional branch direction. In some embodiments, the hash-tagged predictor of the mBTB 104 may use a longer history composed of the results from all or many branches. For size and timing reasons, the uBTB 114 may employ a smaller predictor.

[0043] In various embodiments, the front end 108 may include counters that measure the accuracy of predictions of the uBTB 114 and / or the mBTB 104 or other prediction schemes. The mBTB prediction counter (represented by the mBTB confidence counter 142 or, in some embodiments, equivalent to the mBTB confidence counter 142) may be a 7-bit counter that tracks the confidence of the mBTB prediction relative to the uBTB prediction. If the mBTB prediction counter is lower than the uBTB confidence counter 132, the enable logic 146 may consider the uBTB 114 to be a better predictor than the mBTB 104.

[0044] The following presents an example set of rules for updating the mBTB confidence counter 142. The term "uBTBCtr" refers to the uBTB confidence counter 132. The term "mBTBPCtr" refers to the mBTB prediction or the mBTB confidence counter 142. For example, in the following description, "== " represents the equality operator, "||" represents the logical "or" operator, ">>" represents a right shift and is equivalent to a division operation, "=" represents the assignment operator, "&&" represents the logical "and" operator, and "++" represents the increment operator.

[0045] If (uBTBCtr == 127 || mBTBCtr == 127):

[0046] / / If either of the two counters saturates at the maximum value, divide both counters by 2

[0047] uBTBCtr >>= 1; mBTBCtr >>= 1;

[0048] Otherwise, if the branch is a graph miss at commit time:

[0049] / / If uBTB does not have the branch, keep the mBTB confidence value

[0050] mBTBCtr = mBTBCtr;

[0051] Otherwise, if the primary predictor correctly predicts taken:

[0052] / / Increment the mBTB predictor confidence on correctly predicted taken branches

[0053] MBTbCTr = MBTbCTr + 1;

[0054] Otherwise:

[0055] / / Saturate at -2 because in one embodiment, relative to uBTB zero bubbles, the mBTB predictor inserts two bubbles to redirect fetch)

[0056] mBTBCtr = mBTBCtr – 2;

[0057] It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0058] The following presents a set of examples of rules for updating the uBTB confidence counter 132. The term "uBTBCtr" refers to the uBTB confidence counter 132. The term "mBTBCtr" refers to the mBTB predictor or mBTB confidence counter 142. "T" refers to a taken branch. And, "NT" refers to a not-taken branch.

[0059] If (uBTBCtr == 127 || mBTBCtr == 127)

[0060] / / If either of the two counters saturates at the maximum value, divide both counters by 2

[0061] uBTBCtr >>= 1; mBTBCtr >>= 1;

[0062] Otherwise, if the branch is a graph miss at commit time:

[0063] / / If uBTB does not have the branch, keep the uBTB predictor confidence value

[0064] uBTBCtr = uBTBCtr;

[0065] Otherwise:

[0066] / / There are branches in uBTB (using the commit logic that does not affect extraction to measure accuracy)

[0067] If the uBTB predictor branches && the prediction result == the actual result && uBTB predictor confidence[3:0] == 15:

[0068] / / Increment the highest confidence prediction of the correct uBTB predictor

[0069] uBTBCtr++;

[0070] Otherwise, if it is a loop / anti-loop branch:

[0071] / / (Loop / anti-loop) = the repeated cadence of (T / N) followed by a single (N / T)

[0072] If the cadence >= 32 && the confidence >= 7 or

[0073] the cadence >= 8 && the confidence >= 11 or

[0074] the cadence >= 4 && the confidence >= 12 or

[0075] the cadence >= 2 && the confidence >= 13 or

[0076] the cadence >= 1 && the confidence >= 14:

[0077] uBTBCtr++; / / Saturate at 127

[0078] Otherwise, if it is a highly T-biased or always T branch:

[0079] uBTBCtr++; / / Saturate at 127

[0080] Otherwise, if it is a highly N-biased or always N branch:

[0081] uBTBCtr++; / / Saturate at 127

[0082] Otherwise:

[0083] uBTBCtr = uBTBCtr; / / Keep the value

[0084] It should be understood that the above is only an illustrative example, and the disclosed subject matter is not limited thereto.

[0085] These uBTB confidence counters 132 and mBTB confidence counters 142 can then be compared. In some embodiments, if the uBTB confidence counter 132 (e.g., the value of the uBTB confidence counter 132) is greater than or equal to the mBTB confidence counter 142 (e.g., the value of the mBTB confidence counter 142), then the uBTB 114 can be enabled and allowed to actually make predictions, or more precisely, have its predictions used by the front end 106. In another embodiment, enabling the uBTB 114 may also have to pass a second test. The enable logic 140 can determine whether the uBTB 114 has a misprediction rate lower than that of the mBTB 104. In the illustrated embodiment, the misprediction rate can be measured as the number of mispredictions per thousand branches (MPK). It should be understood that this is merely an example and the disclosed subject matter is not limited thereto.

[0086] In one embodiment, the misprediction rates can be compared every 256 branches (or at other increments: e.g., 1024 branches, 256 clock cycles, 256 retired instructions, etc.).

[0087] The following gives an example set of rules for updating the uBTB misprediction rate counter 134.

[0088] If 256 branches have been committed:

[0089] Clear the uBTB misprediction rate counter

[0090] Otherwise, if the uBTB misprediction rate counter is saturated at its maximum value:

[0091] Keep the counter at its maximum value

[0092] Otherwise, if the uBTB does not make a commit-time prediction because the uBTB does not contain a branch:

[0093] Keep the counter at its current value

[0094] Otherwise, if the uBTB does not make a correct commit-time prediction:

[0095] Increment the uBTB misprediction rate counter

[0096] Otherwise:

[0097] Keep the current uBTB misprediction rate counter value

[0098] It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0099] The following presents an example set of rules for updating the mBTB misprediction rate counter 144.

[0100] If 256 branches have been committed:

[0101] Clear the mBTB misprediction rate counter

[0102] Otherwise, if the mBTB misprediction rate counter is saturated at its maximum value:

[0103] Keep the counter at its maximum value

[0104] Otherwise, if the branch direction predicted by the sign of the bias weight used for mBTB prediction is inconsistent with the final prediction made by the mBTB predictor:

[0105] Increment the mBTB misprediction rate counter

[0106] Otherwise:

[0107] Keep the current mBTB misprediction rate counter value

[0108] It should be understood that the above is merely an illustrative example, and the disclosed subject matter is not limited thereto.

[0109] In various embodiments, the test may not only be that the uBTB 114 has a misprediction rate lower than that of the mBTB 104, but that it itself has a sufficiently low misprediction rate. For example, in one embodiment, the uBTB 114 may be enabled only if (ignoring the uBTB confidence counter 132 and the mBTB confidence counter 142) the number of uBTB mispredictions is less than 6 MPK, or if the uBTB misprediction rate counter 134 is less than half of the mBTB misprediction rate counter 144 and less than 16 MPK.

[0110] The following presents an example set of rules for updating the mBTB misprediction rate counter 144. "MPKB" is the misprediction per thousand (kilo) branches.

[0111] If (uBTBCtr >= mBTBCtr) && ((uBTB MPKB < 2 * mBTB MPKB) || uBTB MPKB <= 6):

[0112] Allow the uBTB to lock and make predictions (potentially improving performance and saving power)

[0113] Otherwise:

[0114] Prevent the uBTB from locking

[0115] / / Heuristic assumes that uBTB prediction will degrade performance and waste power

[0116] It should be understood that the above is merely an illustrative example, and the disclosed subject matter is not limited thereto.

[0117] Figure 3 A timing diagram showing an exemplary embodiment of the technology according to the disclosed subject matter is shown. Figure 3 Two timing diagrams 300 and 301 are shown, which can be used for two different embodiments of the disclosed subject matter. In various embodiments, one, two, or neither of the techniques described herein is used in conjunction with the system shown in Figure 1 or another system.

[0118] Timing diagram 300 shows the periodic sampling of the collected accuracy data, as described above. In such an embodiment, instead of continuously sampling the accuracy data, the system can sample the accuracy data periodically. In the illustrated embodiment, the sampling can occur every certain number (N) of clock cycles (e.g., 50 cycles, 5000 cycles, etc.). In another embodiment, the sampling can occur based on the occurrence of another metric or event. In some embodiments, the other metric can include a number of retired branches or instructions, a number of mispredictions, a number of events, etc. In some embodiments, the event can include the prediction / commitment of a particular (e.g., tagged) type of instruction or branch (e.g., loop, branch-if-zero, etc.), a threshold reached, etc. It should be understood that these are merely a few illustrative examples, and the disclosed subject matter is not limited thereto.

[0119] As shown in diagram 300, at cycles or times 302 and 304, the enable logic can sample or examine the content of the accuracy data. During the intervening period 306 (between times 302 and 304), the accuracy data can be collected, but no decisions can be made about it.

[0120] In one embodiment, the techniques shown in diagram 300 (or even the techniques shown in diagram 301) can be employed to test the values or accuracies of various predictors (such as Figure 1 shown by the uBTB predictor 115 and the mBTB predictor 105). In such an embodiment, when an event or timer occurs (e.g., times 302 and 304), one or more predictors can be enabled (or disabled). During the intervening period 306 or a short test / training phase, the enable logic can collect data on how well the uBTB or mBTB performs when making predictions with the tested changes. The efficacy of the changes can be evaluated at times 302 and 304.

[0121] In various embodiments, the efficacy of a modified predictor can include measurements such as the misprediction size per thousand branches / instructions, the percentage of time that the uBTB is locked to the evaluated core, etc. In some embodiments, based on the effectiveness of the modified predictor, the enable logic can enable or disable a given predictor, prediction weight, or prediction technique. Since the circuitry used to compute the prediction technique does not need to be powered on, or at least can be left switched off, this can save power for the system.

[0122] Diagram 301 illustrates a training period technique that can be employed. In such an embodiment, the uBTB can be allowed to attempt to train, lock, or converge using a given core or set of instructions. In such an embodiment, the enable logic can allow or enable the use of the prediction results from the uBTB during a training period 312 and then allow the uBTB to continue to be used or disable it during a non - training period 314, as described above.

[0123] In one such embodiment, for example, the training period 312 can last for a relatively short percentage of time, such as 20,000 - 50,000 cycles out of every 100,000 - 1,000,000 cycles. It should be understood that this is merely an example and the disclosed subject matter is not limited thereto.

[0124] The enable logic can maintain statistics based only on the training period 312, or based on both long - term uBTB predictions and then separate uBTB predictions specifically for the current training period 312. When the training period 312 ends, the enable logic can evaluate the efficacy of the uBTB during that period and decide whether to enable the uBTB during the next non - training period 314.

[0125] In one embodiment, if the uBTB is accurately trained or locked by more than a threshold amount during the training period 312, the enable logic can enable the uBTB. If the short - term average during the training period 312 is below the threshold, the uBTB can be disabled during the non - training period 314. Similarly, if the long - term average over several training and non - training periods is below the threshold, the uBTB can be disabled. This process and evaluation can occur again and again, starting each new training period 312.

[0126] In one embodiment, the enable logic can collect data only during the training period 312 and not during the non - training period 314. This can allow the enable logic to power down or reduce power consumption during the non - training period 314.

[0127] In various embodiments, any of these techniques may include inconsistent training periods or sampling times (e.g., long periods and short periods). In such embodiments, the training period may be extended or shortened based on the results of training. In various embodiments, the training period / sampling time may occur based on a triggering event (e.g., a flag branch, the type of branch, other processor events, etc.). In some embodiments, phase detection techniques may be employed to determine when the training period / sampling time should occur.

[0128] Figure 2 is a flowchart of an example embodiment of technique 200 according to the disclosed subject matter. In various embodiments, technique 200 may be used by or generated by a system (such as Figure 1 or Figure 4 systems). Additionally, portions of technique 200 may be used or generated by a timing diagram similar to the timing diagram of Figure 3 . Although, it should be understood that the above are merely a few illustrative examples and the disclosed subject matter is not limited thereto. It should be understood that the disclosed subject matter is not limited to the order or number of actions shown by technique 200.

[0129] Block 202 shows that, in one embodiment, the event counter may be reset to 0 or a known preset value. As described above, the event counter may register a number of events, possibly of multiple types. In the illustrated embodiment, "events" are shown as clock cycles, but it should be understood that this is merely an example.

[0130] Block 204 shows that, in one embodiment, the event counter may be incremented (or decremented) each time an event occurs (e.g., a clock cycle). The event counter is as described above. And the event may include a logical combination of multiple events (e.g., "AND", "OR", etc.).

[0131] Block 206 shows that, in one embodiment, this monitoring and incrementing may occur until a threshold is reached (e.g., zero, 50,000, etc.). In some embodiments, the threshold determination may actually be the modulus of the threshold (e.g., every 50,000th cycle) relative to a fixed value. In another embodiment, the counter may be reset when the sampling period ends. When the threshold has been reached, enabling or heuristic logic may begin to process other training phases or test periods.

[0132] Block 208 shows that, in one embodiment, the uBTB validity or statistical counter may be updated. Similarly, both short-term and long-term counters or statistics are employed, as described above.

[0133] Block 210 shows that, in one embodiment, it can be determined whether the system is already in a training period. If so, the system can continue the training period. If not, the system can start the training period.

[0134] Block 212 shows that, in one embodiment, if the system is in a training mode, the system can determine whether the system should exit the training mode and evaluate the results. In such an embodiment, the decision can be based on whether a second threshold has been met. In various embodiments, the second threshold can be a multiple of the first threshold (e.g., Y*N, where Y can represent the first threshold and N can be a natural number), a different modulus of the threshold (e.g., for a non-resetting counter), or a second event. It should be understood that these are merely illustrative examples and the disclosed subject matter is not limited thereto.

[0135] Block 214 shows that, in one embodiment, if the second threshold is met, the training period can be stopped. In various embodiments, this can include setting a flag or bit indicating the state of the training mode. If the training mode has not ended, technique 200 can return to block 204.

[0136] Block 216 shows that the collected statistical data can be evaluated as described above. As described above, this can include short-term statistical data from the training period and, in some embodiments, can include long-term statistical data.

[0137] Block 218 shows that, in one embodiment, it can be decided whether to enable or disable the uBTB during a non-training period as described above. In one embodiment, the decision can be based on the collected statistical data.

[0138] Blocks 240 and 242 show that heuristic or enabling logic can enable (block 240) or disable (block 242) the uBTB during a non-training period as described above. In some embodiments, an event counter can be reset (block 202) after the training period ends. In another embodiment, the counter can not be reset (return to block 204), but the threshold can be based on multiple values or individual events.

[0139] Block 222 shows that, in one embodiment, if the system is not in a training mode, the system can determine whether the system should enter the training mode. In such an embodiment, the decision can be based on whether a third threshold has been met. In various embodiments, the third threshold can be a multiple of the first threshold or the second threshold (e.g., Z*N, where Z can represent the first threshold or the second threshold and N can be a natural number), a different modulus of the threshold (e.g., for a non-resetting counter), or another event. It should be understood that these are merely illustrative examples and the disclosed subject matter is not limited thereto.

[0140] The box 224 shows that, in one embodiment, any required flag or bit can be set if the training mode should be entered. For the test / training period, the uBTB can be enabled as described above. Depending on the embodiment, the technique 200 can then return to box 202 or box 204.

[0141] In such an embodiment, during the test / training period and during the non-training period, the uBTB can be enabled by a heuristic or enabling logic as described above.

[0142] Figure 4 FIG. is a schematic block diagram of an information processing system 400 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0143] Reference Figure 4 , the information processing system 400 may include one or more devices constructed according to the principles of the disclosed subject matter. In another embodiment, the information processing system 400 may employ or execute one or more techniques according to the principles of the disclosed subject matter.

[0144] In various embodiments, for example, the information processing system 400 may include computing devices such as laptop computers, desktop computers, workstations, servers, blade servers, personal digital assistants, smart phones, tablet computers, and other suitable computers or their virtual machines or virtual computing devices. In various embodiments, the information processing system 400 may be used by a user (not shown).

[0145] The information processing system 400 according to the disclosed subject matter may further include a central processing unit (CPU), a logic or processor 410. In some embodiments, the processor 410 may include one or more functional unit blocks (FUB) or combinational logic blocks (CLB) 415. In such embodiments, the combinational logic block may include various Boolean logic operations (e.g., "NAND", "NOR", "NOT", "XOR"), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinational logic operations may be configured in simple or complex ways to process input signals to obtain desired results. It should be understood that although several illustrative examples of synchronous combinational logic operations are described, the disclosed subject matter is not limited thereto and may include asynchronous operations or a mixture thereof. In one embodiment, the combinational logic operations may include multiple complementary metal oxide semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged as gates to perform logic operations; however, it should be understood that other techniques may be used and are within the scope of the disclosed subject matter.

[0146] The information processing system 400 according to the disclosed subject matter may further include a volatile memory 420 (e.g., random access memory (RAM)). The information processing system 400 according to the disclosed subject matter may further include a non-volatile memory 430 (e.g., hard disk drive, optical memory, NAND or flash memory). In some embodiments, the volatile memory 420, the non-volatile memory 430, or a combination or portion thereof may be referred to as "storage media". In various embodiments, the volatile memory 420 and / or the non-volatile memory 430 may be configured to store data in a semi-persistent or substantially persistent form.

[0147] In various embodiments, information processing system 400 may include one or more network interfaces 440, where the one or more network interfaces 440 are configured to allow information processing system 400 to become part of a communication network and communicate via the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE 802.11n. Examples of cellular protocols may include, but are not limited to: IEEE 802.16m (also known as Advanced Wireless MAN (Metropolitan Area Network), Advanced Long Term Evolution (LTE), Enhanced Data Rate GSM (Global System for Mobile Communications) Evolution (EDGE), Evolved High-Speed Packet Access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fibre Channel, Powerline Communication (e.g., HomePlug, IEEE 1901). It should be understood that the above are merely illustrative examples and the disclosed subject matter is not limited thereto.

[0148] The information processing system 400 according to the disclosed subject matter may also include a user interface unit 450 (e.g., a display adapter, a haptic interface, a human machine interface device). In various embodiments, the user interface unit 450 may be configured to receive input from a user and / or provide output to a user. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or haptic feedback; and the input from the user may be received in any form (including sound, voice, or haptic input).

[0149] In various embodiments, information processing system 400 may include one or more other devices or hardware components 460 (e.g., a display or monitor, a keyboard, a mouse, a camera, a fingerprint reader, a video processor). It should be understood that the above are merely illustrative examples and the disclosed subject matter is not limited thereto.

[0150] The information processing system 400 according to the disclosed subject matter may further include one or more system buses 405. In such an embodiment, the system bus 405 may be configured to communicatively couple the processor 410, volatile memory 420, non-volatile memory 430, network interface 440, user interface unit 450, and one or more hardware components 460. Data processed by the processor 410 or input from outside the non-volatile memory 430 may be stored in the non-volatile memory 430 or the volatile memory 420.

[0151] In various embodiments, the information processing system 400 may include or execute one or more software components 470. In some embodiments, the software components 470 may include an operating system (OS) and / or applications. In some embodiments, the OS may be configured to provide one or more services to the applications and manage or act as an intermediary between the applications and the various hardware components of the information processing system 400 (e.g., processor 410, network interface 440). In such an embodiment, the information processing system 400 may include one or more native applications, where the one or more native applications may be locally installed (e.g., within the non-volatile memory 430) and configured to be directly executed by the processor 410 and directly interact with the OS. In such an embodiment, the native applications may include pre-compiled machine-executable code. In some embodiments, the native applications may include script interpreters (e.g., csh, AppleScript, AutoHotkey) or virtual execution machines (VMs) (e.g., Java virtual machine, Microsoft Common Language Runtime) configured to convert source code or object code into executable code that is then executed by the processor 410.

[0152] A variety of packaging techniques can be used to package the above semiconductor devices. For example, semiconductor devices constructed in accordance with the principles of the disclosed subject matter can be packaged using any one of the following techniques or other techniques known to those skilled in the art: Package On Package (POP) technology, Ball Grid Array (BGA) technology, Chip Scale Package (CSP) technology, Plastic Leaded Chip Carrier (PLCC) technology, Plastic Dual In-line Package (PDIP) technology, die in waffle pack technology, die in wafer form technology, Chip On Board (COB) technology, Ceramic Dual In-line Package (CERDIP) technology, Plastic Metric Quad Flat Package (PMQFP) technology, Plastic Quad Flat Package (PQFP) technology, Small Outline Package (SOIC) technology, Shrink Small Outline Package (SSOP) technology, Thin Small Outline Package (TSOP) technology, Thin Quad Flat Package (TQFP) technology, System In Package (SIP) technology, Multi-Chip Package (MCP) technology, Wafer-level Fabricated Package (WFP) technology, Wafer-level Processed Stack Package (WSP) technology.

[0153] The method steps may be performed by one or more programmable processors, where the one or more programmable processors execute a computer program to perform functions by operating on input data and generating output. The method steps may also be performed by special-purpose logic circuitry (e.g., FPGA (Field Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit)), and the apparatus may be implemented as the special-purpose logic circuitry.

[0154] In various embodiments, a computer-readable medium may include instructions that, when executed, cause a device to perform at least a portion of the method steps. In some embodiments, the computer-readable medium may be included in a magnetic medium, an optical medium, other media, or a combination thereof (e.g., CD-ROM, hard disk drive, read-only memory, flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory article of manufacture.

[0155] Although the principles of the disclosed subject matter have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of these disclosed concepts. Accordingly, it should be understood that the above embodiments are not restrictive but merely illustrative. Thus, the scope of the disclosed concepts will be determined by the broadest permissible interpretation of the appended claims and their equivalents and should not be constrained or limited by the foregoing description. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments.

[0156] This application claims priority to U.S. Patent Application No. 62 / 865,943, filed Jun. 24, 2019, and U.S. Patent Application No. 16 / 565,476, filed Sep. 9, 2019, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A computing device, comprising: A main branch target buffer BTB; A micro BTB, separated from and smaller than the main BTB, and configured to generate prediction information associated with branch instructions; A micro BTB confidence counter, configured to measure the correctness of the prediction information generated by the micro BTB; A micro BTB misprediction rate counter, configured to measure the ratio of mispredictions generated by the micro BTB; And A micro BTB enabling logic circuit, configured to enable the use of the prediction information of the micro BTB at least partially based on the values of the micro BTB confidence counter and the micro BTB misprediction rate counter, Wherein, both the micro BTB confidence counter and the micro BTB misprediction rate counter are updated in response to the submission of branch instructions.

2. The computing device according to claim 1, wherein, The micro BTB enabling logic circuit is configured to compare the values of the micro BTB confidence counter and the micro BTB misprediction rate counter with corresponding thresholds.

3. The computing device according to claim 2, wherein, The corresponding threshold of the micro BTB confidence counter is the value of the main BTB confidence counter; and Wherein, the corresponding threshold of the micro BTB misprediction rate counter is the value of the main BTB misprediction rate counter.

4. The computing device according to claim 1, wherein, The micro BTB enabling logic circuit is configured to: if the micro BTB confidence counter and the micro BTB misprediction rate counter indicate that the micro BTB is a better predictor than the main BTB, enable the use of the prediction information of the micro BTB.

5. The computing device according to claim 1, wherein, The computing device further includes a hash branch predictor circuit; And Wherein, the micro BTB confidence counter is configured to change the value of the micro BTB confidence counter at least partially based on the confidence level of the hash branch predictor circuit.

6. The computing device according to claim 1, wherein, The computing device is configured to update only the micro BTB confidence counter and the micro BTB misprediction rate counter during a periodic sampling interval.

7. The computing device according to claim 1, wherein, The micro BTB enabling logic circuit is configured to enable the micro BTB to generate prediction information but disable the use of the prediction information of the micro BTB in a first mode; and The micro BTB enabling logic circuit is configured to enable the micro BTB to generate prediction information and enable the use of the prediction information of the micro BTB in a second mode.

8. The computing device according to claim 1, wherein, The micro BTB enabling logic circuit is configured to enable the use of the prediction information of the micro BTB during a periodic training interval.

9. A computing device, comprising: A main branch target buffer BTB; A micro BTB, separated from and smaller than the main BTB, and configured to generate prediction information associated with branch instructions; A main BTB confidence counter, configured to measure the correctness of the prediction information generated by the main BTB; A main BTB misprediction rate counter, configured to measure the ratio of mispredictions generated by the main BTB; And A micro BTB enabling logic circuit, configured to enable the use of the prediction information of the micro BTB at least partially based on the values of the main BTB confidence counter and the main BTB misprediction rate counter, Among them, both the main BTB confidence counter and the main BTB misprediction rate counter are updated in response to the submission of a branch instruction.

10. The computing device according to claim 9, wherein, The micro BTB enabling logic circuit is configured to compare the values of the main BTB confidence counter and the main BTB misprediction rate counter with corresponding thresholds.

11. The computing device according to claim 10, wherein, The corresponding threshold of the main BTB confidence counter is the value of the micro BTB confidence counter; and Among them, the corresponding threshold of the main BTB misprediction rate counter is the value of the micro BTB misprediction rate counter.

12. The computing device according to claim 9, wherein, The micro BTB enabling logic circuit is configured to: if the main BTB confidence counter and the main BTB misprediction rate counter indicate that the micro BTB is a better predictor than the main BTB, enable the use of the prediction information of the micro BTB.

13. The computing device according to claim 9, wherein, The computing device further includes a hash branch predictor circuit; And Among them, the main BTB confidence counter is configured to change the value of the main BTB confidence counter at least partially based on the confidence level of the hash branch predictor circuit.

14. The computing device according to claim 9, wherein, The computing device is configured to update only the main BTB confidence counter and the main BTB misprediction rate counter during a periodic sampling interval.

15. The computing device according to claim 9, wherein, The computing device further includes: A micro BTB confidence counter, configured to measure the correctness of the prediction information generated by the micro BTB; and A micro BTB misprediction rate counter, configured to measure the ratio of mispredictions generated by the micro BTB.

16. The apparatus according to claim 9, wherein, A plurality of predictors are associated with the micro BTB, and Among them, the micro BTB enabling logic circuit is configured to enable or disable each predictor in the plurality of predictors at least partially based on a sampling period.

17. A computing system, including: A front-end logic part, configured to extract and predict a series of instructions to be executed; And among them, the front-end logic part includes: A main branch target buffer BTB; A micro BTB, separated from the main BTB and smaller than the main BTB, and configured to generate prediction information associated with a branch instruction; and A heuristic logic circuit, including a plurality of counters configured to measure the effectiveness of the main BTB and the micro BTB, and determining whether to enable the use of the prediction information of the micro BTB at least partially based on the plurality of counters, Among them, the plurality of counters are updated at least partially in response to the submission of a branch instruction.

18. The computing system according to claim 17, wherein, The heuristic logic circuit is configured to compare the prediction accuracies of the main BTB and the micro BTB, and compare the misprediction rates of the main BTB and the micro BTB.

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