Pulse width detection circuit for laser diode pulse generator

Abstract

Embodiments of the present disclosure relate to a pulse width check circuit for a laser diode pulse generator. A pulse signal generator generates a pulse signal whose pulse width is intended to be equal to a given fraction of the pulse width of a reference clock. A reference current source outputs a current having a reference amplitude, and a comparison current source outputs a current having an amplitude that is a function of the reference amplitude and the given fraction. A comparison circuit compares the total current output by one of the reference current source and the comparison current source during a pulse of the reference clock with the total current output by the other of the reference current source and the comparison current source during a pulse of the pulse signal to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock, the number of pulses of the pulse signal being equal to the number of pulses of the reference clock.

Description

Technical Field

[0001] The present application relates to the field of laser driving, and in particular to a circuit for verifying that the pulse width of a pulse driving a laser diode based on the circuit is an expected pulse width. Background Art

[0002] Augmented reality (AR) is a technology that enhances a real-time direct or indirect view of the physical world by overlaying computer-generated imagery. For example, AR technology can be incorporated into a headset worn by a user, so that computer-generated imagery is superimposed on the user's view of the real world. The computer-generated imagery can include information about the real world (e.g., the names of landmarks), information related to the user's own life (e.g., reminders of upcoming appointments), and so on.

[0003] Some augmented reality headsets involve the use of microprojectors that scan RGB lasers in a scanning pattern across a separate screen for each eye at a rate sufficient to form a visible image. These types of augmented reality headsets require precise control of laser power and pulse width to ensure they operate correctly and that these images appear as expected.

[0004] Other augmented reality headsets involve the use of micro-projectors that sweep RGB lasers across each eye in a scanning pattern at a rate sufficient for the eyes to perceive an image. These types of augmented reality headsets particularly require precise control of laser power and pulse width to avoid causing eye discomfort to the user.

[0005] While techniques exist for precisely controlling laser power, techniques for precisely controlling laser pulse width are still needed. Thus, further developments are needed in this area. Summary of the Invention

[0006] The circuit disclosed herein includes: a pulse signal generator that generates a pulse signal whose pulse width is intended to be equal to a given fraction of the pulse width of a reference clock; a reference current source that outputs a current having a reference amplitude; and a comparison current source that outputs a current whose amplitude is a function of the reference amplitude and the given fraction.

[0007] The pulse signal generator further includes a comparison circuit configured to receive the pulse signal and compare a total current output by one of the reference current source and the comparison current source during a plurality of pulses of the reference clock with a total current output by the other of the reference current source and the comparison current source during a plurality of pulses of the pulse signal, the number of the plurality of pulses of the pulse signal being equal to the number of the plurality of pulses of the reference clock. The comparison circuit then determines, based on the comparison, whether a pulse width of the pulse signal is less than or equal to a given fraction of a pulse width of the reference clock.

[0008] The pulse width of the pulse signal is less than or equal to a given fraction of the pulse width of the reference clock, indicating correct operation of the pulse signal generator. The pulse width of the pulse signal is greater than a given fraction of the pulse width of the reference clock, indicating erroneous operation of the pulse signal generator.

[0009] As a non-limiting implementation example, the circuit may include: a laser driver configured to generate a laser drive current based on a pulse signal; and a laser diode driven by the laser drive current to generate laser light. In this non-limiting implementation example, the circuit may also include: a movable mirror device configured to reflect the laser light in a scanning pattern at a rate sufficient to generate an image visible to the human eye. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a block diagram of a micro-projector including a laser system with a pulse width detection circuit according to the present disclosure.

[0011] Figure 1B The reference clock (CKref) and Figure 1A Graph of delayed versions (ck1...ckK) of the reference clock generated by a delay-locked loop.

[0012] Figure 2A yes Figure 1A Schematic block diagram of a first embodiment of a pulse width check circuit.

[0013] Figure 2B It shows Figure 2A A timing diagram of the operation of the pulse width check circuit during a period when no pulse width error is detected.

[0014] Figure 2C It shows Figure 2A A timing diagram of the operation of the pulse width check circuit during detection of a pulse width error.

[0015] Figure 2D The drive of switches S1 and S3 has been reversed. Figure 2A A schematic block diagram of a first embodiment of a pulse width check circuit.

[0016] Figure 3A yes Figure 1B A schematic block diagram of a second embodiment of a pulse width check circuit.

[0017] Figure 3B is one in which the drives of switches S1 and S3 have been reversed Figure 3A A schematic block diagram of a second embodiment of a pulse width check circuit.

[0018] Figure 4A yes Figure 1B Schematic block diagram of a third embodiment of a pulse width check circuit.

[0019] Figure 4B is one in which the drives of switches S1 and S3 have been reversed Figure 3A Schematic block diagram of a third embodiment of a pulse width check circuit.

[0020] Figure 5 is used as Figure 2A 、 Figure 2D and Figure 3A 、 Figure 3B The current generator 22 in the Figure 4A and Figure 4B Schematic diagram of the variable current source of the current generator 21. DETAILED DESCRIPTION

[0021] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but is to be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0022] Now, first refer to Figure 1A A micro projector 10 is described. The micro projector 10 includes a delay locked loop (DLL) 12 that receives a reference clock CKref and outputs K delayed versions of the reference clock CKref, each delayed version having a delay increased by 1 / K of the period of CKref. Figure 1B , which shows a reference clock CKref and K delayed versions of the reference clock generated by the DLL, ck1...ckK. For this example, K is 8 (but can be any integer), so it can be seen that ck1 is delayed by 1 / 8 of the period of CKref, ck2 is delayed by 2 / 8 of the period of CKref, and so on, until ckK (ck8) is delayed by a full period of CKref.

[0023] The pulse decoder 13 receives as input the delayed versions ck1 ... ckK of the reference clock from the DLL and an input code m, and generates a pulse output signal Pulse with a pulse width of m / K and a position fixed within the period of the reference clock CKref. m Therefore, by selecting the value of m, the pulse output signal Pulse m The pulse width and its position within the period of the reference clock CKref.

[0024] The digital block 15 receives the reference clock CKref and the pulse output signal Pulse m , and based on the pulse output signal Pulsem to provide an output signal to a laser driver 16 that drives a laser diode 17. The laser diode 17, when driven, generates laser light (eg, RGB laser light) that impinges on a mirror arrangement 18, which reflects the laser light in a desired scanning pattern to form an image.

[0025] The pulse width detector 14 receives the pulse output signal Pulse from the pulse decoder 13 m , and if the pulse output signal Pulse m Having a pulse width greater than the expected pulse width, the output signal Fault is asserted.

[0026] Digital block 15 also receives the Fault signal and, based on the assertion of the Fault signal, takes appropriate corrective action (e.g., changing the output signals to the laser driver so that they do not drive the laser diode 17, or waiting for multiple assertions of the Fault signal before taking such actions). Digital block 15 provides Reset and Enable signals for controlling the operation of pulse width detector 14 and optionally provides a trim signal Trim to pulse width detector 14 that can be used to adjust the operation of pulse width detector 14 to account for variations in process, temperature, and frequency of the reference clock.

[0027] Now, reference Figure 2A The pulse width detector 14 will be described. First, the structure of the pulse width detector 14 will be described, and then the operation of the pulse width detector 14 will be described.

[0028] The pulse width detector 14 includes a current source 21 connected between the power supply node VDD and the node N1; a switch S1 connected between the node N1 and the node N2; and a current source 22 connected between the node N2 and the ground. The current source 21 provides a current Iref to the node N1, while the current source 22 draws a current IPulse from the node N2. The switch S1 is connected by the Pulse m Signal control (for example, when Pulse m Closed when high, and when Pulse m disconnected when low).

[0029] The input of inverter 23 is connected to node N1 to receive Sense in signal, and its output provides the Sense out Signal, according to the Sense out Signal, generating a Fault flag. Integrating capacitor C is connected between node N1 and ground. Switch S2 connects the input of inverter 23 to the output of inverter 23 and is controlled by the Reset signal (e.g., closed when Reset is high and open when Reset is low).

[0030] Switch S3 is connected between node N2 and node N3 and is controlled by Pulse m The inversion of the signal is used to control (for example, when the Pulse m Closed when low, and when Pulse m The input of inverter 24 is connected to node N3, and its output provides the reference signal ref. Switch S4 connects the input of inverter 24 to the output of inverter 24 and is controlled by the Enable signal (e.g., open when Enable is high and closed when Enable is low).

[0031] A description will now be given of the operation of the pulse width detector 14. It should be noted that during operation, the Enable signal remains high and therefore the switch S4 remains closed.

[0032] The operation is carried out in two phases, namely reset and sense. Generally speaking, the purpose of the reset phase is to set the input and output of the inverter 23 to the threshold voltage of the inverter 23 so that later, when the reset phase ends and the sense phase begins, the voltage Sense in A slight change in the output Sense of inverter 23 will cause out Rapidly rise to VDD or quickly fall to GND. Generally speaking, the purpose of the sensing phase is to m The pulse width is equal to m / K of the period of the reference clock CKref, so that Sense in Increases over time (leading to Sense out signal drops), but if Pulse m The pulse width is greater than the period of the reference clock CKref m / K, then it decreases over time (causing Sense out signal rises); due to Sense in A small change will result in Sense out Therefore, by monitoring the Sense out , you can quickly know the Pulse m Is the pulse width equal to m / K of the reference clock CKref period? m If the pulse width is equal to m / K of the period of the reference clock CKref, the delay locked loop 12 and the pulse decoder 13 operate correctly; m If the pulse width of is greater than m / K of the period of the reference clock CKref, the delay locked loop 12 and the pulse decoder 13 are operating under a fault condition.

[0033] In more detail, during the reset phase, the Reset signal is asserted, thereby closing the switch S2 , short-circuiting the input and output of the inverter 23 , and charging the capacitor C to the threshold voltage of the inverter 23 .

[0034] Can be Figure 2B The function of the reset phase can be seen in Figure 2. At time T0, the reset signal goes high, closing switch S2 and starting the reset phase. It can be seen that then Sense in and Sense out is substantially equal to the threshold voltage of the inverter 23. Although in the graph shown, when the reset signal is asserted at T0, the Sense in and Sense out The voltages of the reference clock CKref (and the pulse signal Pulse m ) become equal after a sufficient number of cycles.

[0035] As should be readily appreciated, the pulse signal continues to pulse during both the reset and sense phases, and therefore, switches S1 and S3 continue to open and close in phase opposite to each other during both the reset and sense phases. The function of inverter 24 is to maintain the voltage bias across current source 22 at substantially the same level when switch S1 is open and when switch S1 is closed. In fact, the voltage generated by inverter 24 is intended to be substantially similar to the voltage at Sense. in Thus, during the reset phase, inverter 23 (whose input and output are short-circuited by switch S2) is sufficiently insensitive to the charge injected by current generators 21 and 22 so as not to switch off those current generators 21 and 22. Alternatively, during the reset phase, current generators 21 and 22 can either be switched off or arranged not to source / sink their respective currents to inverter 23. In either case, the operations to be performed will not interfere with the reset phase, allowing inverter 23 to be accurately set to its threshold voltage.

[0036] The sensing phase will now be described. Once the reset phase is complete, the Reset signal goes low, thereby starting the detection phase and opening the switch S2. The following description will describe the operation during a single pulse of the reference clock CKref, where it should be understood that the Pulse m It is intended to be low for a time equal to 1-(m / K) of the period of CKref and high for a time equal to m / k of the period of CKref. As described, the purpose of the pulse width detector 14 is to verify this condition.

[0037] When Pulse mWhen Pulse is low, switch S1 remains open and current Iref begins to charge capacitor C. m When CKref is high, switch S1 is closed. The magnitude of IPulse is intended to be slightly less than Iref*(K / m) (e.g., slightly less by an amount equal to the Trim current) so that if switch S1 is closed for a time equal to m / K of the period of CKref, the current IPulse drawn is insufficient to cause the Pulse current to be high. m When Ipulse is low, the charge added to capacitor C by Iref is completely discharged from capacitor C; on the contrary, if switch S1 is closed for a time greater than m / K of the period of CKref, the draw of Ipulse is sufficient to discharge the charge from capacitor C more than that at Pulse m When it is low, more charge has been added to the capacitor by Iref.

[0038] Therefore, assuming that, as expected, Pulse m The pulse width of the reference clock CKref is actually m / K, so during each pulse of the reference clock CKref, the capacitor C obtains charge (so Sense in Since the input and output of the inverter 23 are set to the threshold value of the inverter 23 during the reset phase, the Sense in This increase in voltage rapidly causes inverter 23 to turn Sense out Pull to ground.

[0039] This operation (as expected, Pulse m The pulse width of the reference clock CKref is m / K) Figure 2B At time T1, the reset phase ends and the sensing phase begins. It can be seen that Sense in In Pulse m When it is low, it rises, and when it is Pulse m High when falling, however, Sense in The average value of Sense increases over time, so out Rapid descent to touchdown, indicating that pulse is being generated correctly m .

[0040] However, as stated, if Pulse m The pulse width is greater than the pulse width of the reference clock CKref by m / K. During each pulse of the reference clock CKref, the capacitor C loses its charge (therefore, Sense in Since the input and output of the inverter are set to the threshold of the inverter 23 during the reset phase, the Sense inThis decrease in voltage quickly causes inverter 23 to turn Sense out Pull to VDD.

[0041] This operation (in Pulse m The pulse width of the reference clock CKref is greater than the pulse width of the reference clock CKref (m / K) Figure 2C At time T1, the reset phase ends and the sensing phase begins. It can be seen that Sense in In Pulse m When it is low, it rises, and when it is Pulse m High when falling, however, Sense in The average value of Sense decreases over time, so out Rapidly rises to VDD, indicating Pulse m The pulse width of CKref is greater than m / K of the pulse width of the reference clock CKref, and an error or fault has occurred. Therefore, at time T2, the Fault flag turns high.

[0042] It should be noted that although Figure 2A In the example, capacitor C is connected between node N1 and ground, but as Figure 3A As shown, in some cases, a capacitor C can be connected between the input and output of the inverter 23. This will slightly change the reset phase. Figure 3A In the reset phase, during the reset phase, the Reset signal is asserted, thereby closing the switch S2, short-circuiting the input and output of the inverter 23, and discharging the capacitor C across the input and output of the inverter 23. The reset phase is performed at the reference clock CKref (and thus the pulse signal Pulse m ) is performed within a sufficient number of cycles to sufficiently discharge the capacitor as described, thereby setting the voltage at both the input and output of inverter 23 to the threshold voltage of the inverter (e.g., a voltage at which any increase or decrease will quickly cause the output of inverter 23 to rise to VDD or fall to ground).

[0043] After each iteration of the sensing phase, the reset phase is returned. The time between the two reset phases is usually fixed. In more detail, according to the size design of Iref, IPulse and Trim and m and K, the maximum time (in terms of clock cycles) required to cause a fault condition or a known non-fault condition is defined. After this defined time, the reset phase is executed. The number of pulses of the reference clock CKref used for the reset phase depends on the time to discharge the capacitor C, and is therefore related to the capacitance of the capacitor C and the size of the inverter 23.

[0044] In the example given above, the current Iref output by the current source 21 is fixed, wherein the current IPulse output by the current source 22 depends on m / K; however, the reverse is also true, and the current source 22′ can output Iref and the current source 21′ can output IPulse; this implementation is Figure 4A Shown in.

[0045] In this implementation, current source 21' provides IPulse to node N2, while current source 22' draws Iref from node N1. m The complement of the signal, nodes N2 and N1 are selectively coupled through switch S1 (wherein when Pulse m When it is low, switch S1 is closed and Pulse m When Pulse is high, switch S1 is off). Nodes N2 and N3 are selectively coupled via switch S3, which is also driven by Pulse m Signal control (when Pulse m When Pulse is low, switch S3 is off, and when m When Sense is high, switch S3 is closed. Inverter 24 receives input from node N3 and selectively shorts its input and output by switch S4 in response to the Enable signal. in Node N1 receives the input voltage and provides the Sense out The voltage is output. In response to the reset signal, the input and output of the inverter 23 are selectively short-circuited by the switch S2. The capacitor C is coupled between the node N1 and the ground.

[0046] Regarding operation, during the reset phase, the reset signal is asserted, thereby closing switch S2, shorting the input and output of inverter 23, and charging capacitor C to the threshold voltage of inverter 23, thereby setting the input and output of inverter 23 to their threshold voltages. The purpose of operating switch S3 in phase opposite to switch S1 is to maintain the voltage bias across current source 21 at substantially the same level when switch S1 is open and when switch S1 is closed. In the sense phase, the reset signal goes low, thereby starting the sense phase and opening switch S2.

[0047] The magnitude of IPulse is intended to be slightly greater than (Iref) / (1-m / K) (e.g., slightly greater by an amount equal to the Trim current) so that if switch S1 is closed for a time equal to 1-(m / k) of the period of CKref, the current IPulse provided to capacitor C during that time is sufficient to charge capacitor C and is therefore greater than the total discharge of the charge of capacitor C by Iref during the pulse of CKref. This condition indicates that, as expected, Pulse mThe pulse width of is actually m / K (or less than m / K) of the pulse width of the reference clock CKref.

[0048] On the contrary, if the switch S1 is turned off for a time greater than m / K of the period of CKref, the current Ipulse provided to the capacitor C during 1-(m / k) of the period of CKref is insufficient so that the capacitor will not be fully discharged through Iref during the pulse of CKref. This condition indicates that, as described above, Pulse should be avoided as much as possible. m The pulse width of CK is greater than the pulse width of the reference clock CKref by m / K.

[0049] In the case described above, the arrangement and amplitude of the current sources 21 and 22, and which of the switches S1 and S3 is switched by the Pulse m Drive, and which switch of switches S1 and S3 is driven by Pulse m The complement drive makes the m When the pulse width of Sense is equal to or less than m / k of the pulse width of CKref, in will rise, and Sense out However, it should be understood that the core concept described above is to compare Iref with Ipulse to determine Pulse m Is the pulse width of Pulse equal to or less than m / k of the pulse width of CKref (which indicates correct operation), or m Is the pulse width of Pulse greater than m / k of the pulse width of CKref (which indicates an erroneous operation)? m The specific arrangement and amplitude of current sources 21 and 22, and which switch S1 and S3 is controlled by Pulse is determined by any method to determine whether the pulse width of CKref is equal to or less than the pulse width of CKref. m Which of switches S1 and S3 is driven by the Pulse m Complement drive.

[0050] For example, using Figure 2D The arrangement shown, which is Figure 2A The arrangement is the same except that switch S1 here is controlled by Pulse m The complement of the switch S3 is driven by Pulse m Therefore, here, for when Pulse m When the pulse width is equal to or less than the pulse width of CKref by m / k, the Sense in , the amplitude of Ipulse will be set to Iref / (1-m / k) plus the trim current. Similarly, Figure 3B The arrangement shown is similar to Figure 3AThe arrangement is the same except that switch S1 here is controlled by Pulse m The complement of the drive, and the switch S2 is driven by Pulse m The drive, and the amplitude of Ipulse will also be set to Iref / (1-m / k) plus the trim current.

[0051] As another example, see Figure 4B The arrangement of Figure 4A The arrangement is the same except that switch S1 is controlled by Pulse m Driven, and switch S3 is driven by Pulse m The complement drive and the amplitude of Ipulse can be set to (m / k)*Iref minus the trimming current.

[0052] Now, reference Figure 5 For example, Figure 2A 3 . A sample variable current source 22 is described below. Current source 22 includes a current generator 30 that generates the same current as the Iref current described above. Current generator 30 is selectively coupled to the drain of NMOS transistor MN1 via switch Scs0 and directly coupled to the gates of NMOS transistors MN2, MN4, MN6, ..., MNn (as described below).

[0053] The drain of NMOS transistor MN1 is coupled to switch Scs0, its source is coupled to the drain of NMOS transistor MN2, and its gate is tied to a cascode voltage sufficient to keep NMOS transistors MN1 and MN2 turned on in saturation. The drain of NMOS transistor MN2 is coupled to the source of NMOS transistor MN1, the source of NMOS transistor MN2 is coupled to ground, and its gate is coupled to current source 30.

[0054] The drain of NMOS transistor MN3 is selectively coupled to a common node via switch Scs1 to assist in generating the IPulse current. The source of NMOS transistor MN3 is coupled to the drain of NMOS transistor MN4, and the gate of NMOS transistor MN3 is coupled to a cascode voltage sufficient to keep NMOS transistors MN3 and MN4 turned on in saturation. The drain of NMOS transistor MN4 is coupled to the source of NMOS transistor MN3, the source of NMOS transistor MN4 is coupled to ground, and the gate of NMOS transistor MN4 is coupled to current source 30.

[0055] The drain of NMOS transistor MN5 is selectively coupled to a common node via switch Scs2 to facilitate generation of the IPulse current, the source of NMOS transistor MN5 is coupled to the drain of NMOS transistor MN6, and the gate of NMOS transistor MN5 is coupled to a cascode voltage sufficient to keep NMOS transistors MN5 and MN6 on in saturation. The drain of NMOS transistor MN6 is coupled to the source of NMOS transistor MN5, the source of NMOS transistor MN6 is coupled to ground, and the gate of NMOS transistor MN6 is coupled to current source 30.

[0056] It should be noted that variable current source 22 can include any number of transistors and switches arranged similarly to Scs1 / MN3 / MN4 and Scs2 / MN5 / MN6. Therefore, to illustrate this and the final transistor pair in the chain, variable current source 22 is shown as including NMOS transistors MNn1 and MNn2. The drain of NMOS transistor MNn1 is selectively coupled to a common node via switch Scsn to help generate the IPulse current, the source of NMOS transistor MNn1 is coupled to the drain of NMOS transistor MNn2, and the gate of NMOS transistor MNn1 is coupled to a cascode voltage sufficient to keep NMOS transistors MNn1 and MNn2 turned on in saturation. The drain of NMOS transistor MNn2 is coupled to the source of NMOS transistor MNn1, the source of NMOS transistor MNn2 is coupled to ground, and the gate of NMOS transistor MNn2 is coupled to current source 30.

[0057] In operation, switch Scs0 is always closed (unless it is desired that the variable current source 22 be turned off, in which case switch Scs0 may be open), and the number of switches Scs1...Scsn that are closed depends on the value of K / m, thereby generating an IPulse current that is variable and has an amplitude equal to Iref*(K / m).

[0058] Although the variable current source 22 is shown as being drawn with NMOS transistors, it will be appreciated that PMOS transistors could be used instead, and those skilled in the art would understand how to adapt the variable current source 22 to such an arrangement.

[0059] Despite Figure 5 The structure of the variable current source 22 is shown in FIG. 4 , but it should be understood that any type of suitable variable current source 22 (or 21 ′ in the example of FIG. 4 ) may be used, and the present disclosure is not limited to Figure 5 design.

[0060] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments may be conceived without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A pulse width detector comprising: a first current source coupled to the first node; a second current source coupled to the second node; a first switch that selectively couples the first node to the second node in response to a pulse signal, the pulse signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock; as well as a comparison circuit coupled to the first node and configured to determine whether a total current output by the first current source during a plurality of pulses of the reference clock exceeds a total current output by the second current source during a plurality of pulses of the pulse signal, the number of the plurality of pulses of the pulse signal being equal to the number of the plurality of pulses of the reference clock.

2. The pulse width detector of claim 1 , wherein the first switch is closed in response to assertion of the pulse signal; wherein the amplitude of the current output by the first current source is a reference amplitude; and wherein the amplitude of the current output by the second current source is equal to the reference amplitude divided by the given fraction minus the trimming current.

3. The pulse width detector of claim 2, wherein the given fraction is equal to a factor m / K, wherein m and K are selectable.

4. The pulse width detector according to claim 1, wherein a determination that the total current output by the first current source during a plurality of pulses of the reference clock exceeds the total current output by the second current source during a number of pulses of the pulse signal equal to the number of pulses of the reference clock indicates that the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock; and The determination that the total current output by the first current source during multiple pulses of the reference clock is less than the total current output by the second current source during multiple pulses of the pulse signal, a number of which is equal to the number of pulses of the reference clock, indicates that the pulse width of the pulse signal is greater than the given fraction of the pulse width of the reference clock.

5. The pulse width detector according to claim 1 , wherein the comparison circuit comprises: a capacitor coupled between the first node and ground; an inverter having an input coupled to the first node and having an output; as well as a second switch selectively coupling the input of the inverter to the output of the inverter in response to a reset signal; wherein in a reset mode of the comparison circuit, the reset signal is asserted to close the second switch to set the input and the output of the inverter to a threshold voltage of the inverter; as well as Wherein in a sensing mode of the comparison circuit, the reset signal is de-asserted to turn off the second switch, so that the output of the inverter generates an output voltage based on the voltage at the first node.

6. The pulse width detector according to claim 1, further comprising: a third switch selectively coupling the second node to a third node in response to an inversion of the pulse signal; as well as The reference voltage generating circuit is configured to generate a reference voltage according to the voltage at the third node.

7. The pulse width detector of claim 6 , wherein the reference voltage generating circuit comprises an inverter having an input coupled to the third node and an output generating the reference voltage; wherein the reference voltage generated by the inverter is used to maintain a voltage bias across the second current source.

8. The pulse width detector according to claim 1, wherein the comparison circuit comprises: an inverter having an input coupled to the first node and having an output; a capacitor coupled between the input of the inverter and the output of the inverter; as well as a second switch selectively coupling the input of the inverter to the output of the inverter in response to a reset signal; wherein in a reset mode of the comparison circuit, the reset signal is asserted to close the second switch to set the input and the output of the inverter to a threshold value of the inverter; as well as Wherein in a sensing mode of the comparison circuit, the reset signal is de-asserted to turn off the second switch, so that the output of the inverter generates an output voltage based on the voltage at the first node.

9. An electronic circuit comprising: a first current source coupled to the first node; a second current source coupled to the second node; a first switch selectively coupling the first node to the second node in response to a pulse signal; an inverter having an input coupled to the first node and having an output; a capacitor coupled to the input of the inverter; a second switch selectively coupling the input of the inverter to the output of the inverter in response to a reset signal; a third switch selectively coupling the second node to a third node in response to an inversion of the pulse signal; as well as An inverter has an input coupled to the third node.

10. The electronic circuit of claim 9, wherein the capacitor is coupled between the input of the inverter and the output of the inverter.

11. The electronic circuit of claim 9, wherein the capacitor is coupled between the input of the inverter and ground.

12. A method for pulse width detection, comprising: configuring the first current source to generate a reference current having a reference amplitude; configuring the second current source to generate a comparison current having a magnitude equal to the reference current divided by a given fraction of a pulse width of a reference clock; configuring the first current source to continuously provide current to the comparison node; configuring the second current source to draw current from the comparison node during each pulse of a pulse signal, the pulse width of the pulse signal being intended to be equal to the given fraction of the pulse width of the reference clock; as well as By determining whether the total current output by the first current source during multiple pulses of the reference clock exceeds the total current output by the second current source during multiple pulses of the pulse signal, it is determined whether the pulse width of the pulse signal is actually equal to the given fraction of the pulse width of the reference clock, and the number of the multiple pulses of the pulse signal is equal to the number of the multiple pulses of the reference clock.

13. The method of claim 12, wherein the given fraction is equal to a factor m / K, wherein m and K are selectable.

14. The method according to claim 12, wherein a determination that the total current output by the first current source during a plurality of pulses of the reference clock exceeds the total current output by the second current source during a number of pulses of the pulse signal equal to the number of pulses of the reference clock indicates that the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock; and The determination that the total current output by the first current source during multiple pulses of the reference clock is less than the total current output by the second current source during multiple pulses of the pulse signal, a number of which is equal to the number of pulses of the reference clock, indicates that the pulse width of the pulse signal is greater than the given fraction of the pulse width of the reference clock.

15. A pulse width detector comprising: a first current source coupled to the first node; a second current source coupled to the second node; a first switch that selectively couples the first node to the second node in response to a complement of a pulse signal, the pulse signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock; as well as a comparison circuit coupled to the first node and configured to determine whether a total current output by the first current source during multiple pulses of the reference clock exceeds a total current output by the second current source during a complement of multiple pulses of the pulse signal, the number of complements of the multiple pulses of the pulse signal being equal to the number of pulses of the reference clock.

16. The pulse width detector of claim 15 , wherein the first switch is closed in response to de-assertion of the pulse signal; wherein the amplitude of the current output by the first current source is a reference amplitude; and wherein the amplitude of the current output by the second current source is equal to the reference amplitude divided by one minus the given fraction, plus a trimming current.

17. The pulse width detector of claim 16, wherein the given fraction is equal to a factor m / K, wherein m and K are selectable.

18. The pulse width detector according to claim 15, wherein a determination that the total current output by the first current source during a plurality of pulses of the reference clock is less than the total current output by the second current source during a complement of a plurality of pulses of the pulse signal equal in number to the plurality of pulses of the reference clock indicates that the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock; and The determination that the total current output by the first current source during multiple pulses of the reference clock is greater than the total current output by the second current source during the complement of multiple pulses of the pulse signal, a number equal to the number of pulses of the reference clock, indicates that the pulse width of the pulse signal is greater than the given fraction of the pulse width of the reference clock.

19. The pulse width detector according to claim 15, wherein the comparison circuit comprises: a capacitor coupled between the first node and ground; an inverter having an input coupled to the first node and having an output; as well as a second switch selectively coupling the input of the inverter to the output of the inverter in response to a reset signal; wherein in a reset mode of the comparison circuit, the reset signal is asserted to close the second switch to set the input and the output of the inverter to a threshold voltage of the inverter; as well as Wherein in a sensing mode of the comparison circuit, the reset signal is de-asserted to turn off the second switch, so that the output of the inverter generates an output voltage based on the voltage at the first node.

20. The pulse width detector according to claim 15, further comprising: a third switch selectively coupling the second node to a third node in response to the pulse signal; as well as An inverter has an input coupled to the third node and an output generating a reference voltage, wherein the reference voltage is generated by the inverter to maintain a voltage bias across the first current source.

21. The pulse width detector according to claim 15, wherein the comparison circuit comprises: an inverter having an input coupled to the first node and having an output; a capacitor coupled between the input of the inverter and the output of the inverter; as well as a second switch selectively coupling the input of the inverter to the output of the inverter in response to a reset signal; wherein in a reset mode of the comparison circuit, the reset signal is asserted to close the second switch to set the input and the output of the inverter to a threshold value of the inverter; as well as Wherein in a sensing mode of the comparison circuit, the reset signal is de-asserted to turn off the second switch, so that the output of the inverter generates an output voltage based on the voltage at the first node.

22. An electronic circuit comprising: a pulse signal generator that generates a pulse signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock; A reference current source outputs a current with a reference amplitude; a comparison current source, wherein the amplitude of the current outputted is a function of the reference amplitude and the given fraction; as well as The comparison circuit is configured as follows: receiving the pulse signal; comparing a total current outputted by one of the reference current source and the comparison current source during a plurality of pulses of the reference clock with a total current outputted by the other of the reference current source and the comparison current source during a plurality of pulses of the pulse signal, the number of the plurality of pulses of the pulse signal being equal to the number of the plurality of pulses of the reference clock; as well as Whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock is determined based on the comparison.

23. The electronic circuit of claim 22, wherein the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock, indicating proper operation of the pulse signal generator.

24. The electronic circuit of claim 22, wherein the pulse width of the pulse signal is greater than the given fraction of the pulse width of the reference clock, indicating erroneous operation of the pulse signal generator.

25. The electronic circuit of claim 22, wherein the comparison circuit compares the total current output by the reference current source during the plurality of pulses of the reference clock with the total current output by the comparison current source during the plurality of pulses of the pulse signal.

26. The electronic circuit of claim 22, wherein the comparison circuit compares the total current output by the comparison current source during the multiple pulses of the reference clock with the total current output by the reference current source during the multiple pulses of the pulse signal.

27. The electronic circuit of claim 22, further comprising: The laser driver is configured to generate a laser driving current based on the pulse signal.

28. The electronic circuit of claim 27, further comprising: The laser diode is driven by the laser driving current to generate laser light.

29. The electronic circuit of claim 28, further comprising: A movable mirror arrangement is configured to reflect the laser light in a scanning pattern at a rate sufficient to produce an image visible to the human eye.

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