Chip package structure and method of forming the same

Abstract

Embodiments of the present invention provide a chip package structure and a method of forming the same. The method includes forming a first conductive bump and a first ring structure on a chip. The first ring structure surrounds the first conductive bump, the first ring structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate via the first conductive bump.

Description

Technical Field

[0001] The present invention relates to chip packaging structures and methods for forming the same, and more particularly to chip packaging structures having a ring structure and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Typically, semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements.

[0003] Dozens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. Individual dies are separated by dicing the integrated circuits along dicing lines. These individual dies are then packaged separately. By continuously reducing the minimum component size, the semiconductor industry has constantly improved the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), allowing more components to be integrated into a given area. However, as component sizes continue to shrink, manufacturing processes continue to become more difficult to implement. Therefore, reliably packaging high-integration-density electronic components remains a challenge. Summary of the Invention

[0004] According to some embodiments of the present invention, a method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first annular structure on a chip. The first annular structure surrounds the first conductive bump, and the first annular structure and the first conductive bump are made of the same first material, and the chip includes an interconnect structure. The method also includes bonding the chip to a substrate via the first conductive bump. The first annular structure is electrically insulated from the interconnect structure, the first conductive bump, and the substrate.

[0005] According to some embodiments of the present invention, a method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate, and forming a first mask layer on a second surface of the first substrate. The first mask layer has a first opening and a first trench surrounding the first opening. The method also includes electroplating to form a first conductive layer within the first opening and the first trench. The first conductive layer within the first opening forms a first conductive bump, and the first conductive layer within the first trench forms a first annular structure, wherein the first annular structure is electrically insulated from the chip and the first conductive bump. The method further includes removing the first mask layer and bonding the first substrate to a second substrate via the first conductive bump. The first annular structure is electrically insulated from the second substrate.

[0006] According to some embodiments of the present invention, a chip package structure is provided. The chip package structure includes a substrate and a chip on the substrate. The chip package structure also includes a first conductive bump between the chip and the substrate and connected to the chip. The chip package structure further includes a first annular structure between the chip and the substrate and connected to the chip. The first annular structure surrounds the first conductive bump, and the first annular structure and the first conductive bump are made of the same first material. The chip includes interconnect structures, and the first annular structure is electrically insulated from the interconnect structures and the first conductive bump. Attached Figure Description

[0007] The embodiments of the present invention will be better understood through the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1I These are cross-sectional schematic diagrams showing various stages of the process for forming a chip package structure, according to some embodiments.

[0009] Figure 1A-1 According to some embodiments, it is shown Figure 1A A top view of the chip packaging structure.

[0010] Figure 1B-1 According to some embodiments, it is shown Figure 1B A top view of the chip packaging structure.

[0011] Figure 1C-1 According to some embodiments, it is shown Figure 1C A top view of the chip packaging structure.

[0012] Figure 1D-1 According to some embodiments, it is shown Figure 1D A top view of the chip packaging structure.

[0013] Figure 1E-1 According to some embodiments, it is shown Figure 1E A top view of the chip packaging structure.

[0014] Figure 1G-1 According to some embodiments, it is shown Figure 1G A top view of the chip packaging structure.

[0015] Figure 1H-1 According to some embodiments, it is shown Figure 1H A top view of the chip packaging structure.

[0016] Figure 1I-1 According to some embodiments, it is shown Figure 1I A top view of the chip packaging structure.

[0017] Figure 2 This is a top view showing the chip package structure according to some embodiments.

[0018] Figure 3 This is a top view showing the chip package structure according to some embodiments.

[0019] Figure 4 This is a cross-sectional schematic diagram of the chip package structure according to some embodiments.

[0020] Figure 5A This is a top view showing the chip package structure according to some embodiments.

[0021] Figure 5B According to some embodiments, it is shown along Figure 5A A cross-sectional view of the chip package structure with the middle section line I-I'.

[0022] The attached figures are labeled as follows:

[0023] 101: Top surface

[0024] 110: Chip

[0025] 112:Substrate

[0026] 114: Device

[0027] 116: Interconnection Layer

[0028] 116a: Interconnection structure

[0029] 116b: Dielectric layer

[0030] 117a: Conductive pad

[0031] 117b: Conductive pad

[0032] 118: Passivation layer

[0033] 118a: Opening

[0034] 120: Seed crystal layer

[0035] 130: Mask layer

[0036] 132: Opening

[0037] 134: Trench

[0038] 140: Conductive layer

[0039] 142: Conductive bump

[0040] 144: Ring structure

[0041] 144a: Part

[0042] 150: Solder layer

[0043] 150a: Solder ball

[0044] 210:Substrate

[0045] 211: Semiconductor substrate

[0046] 211a: Surface

[0047] 211b: Surface

[0048] 212: Conductive through-hole structure

[0049] 213: Barrier Layer

[0050] 214: Redistributed Structure

[0051] 214a: Insulation layer

[0052] 214b: Wiring layer

[0053] 214c: Conductive via

[0054] 214d: Conductive pad

[0055] 214e: Conductive pad

[0056] 215: Passivation layer

[0057] 215a: Opening

[0058] 216: Insulation layer

[0059] 216a: Opening

[0060] 217: Redistributed Structure

[0061] 217a: Dielectric layer

[0062] 217b: Wiring layer

[0063] 217c: Conductive via

[0064] 218a: Conductive pad

[0065] 218b: Conductive pad

[0066] 219: Buffer Ring

[0067] 219a: Opening

[0068] 220: Seed layer

[0069] 230: Mask layer

[0070] 232: Opening

[0071] 234: Trench

[0072] 240: Conductive layer

[0073] 242: Conductive bump

[0074] 244: Ring structure

[0075] 244a: Part

[0076] 250: Solder layer

[0077] 250a: Solder ball

[0078] 251: Welding ball

[0079] 260: Bottom Fill Layer

[0080] 270: Molding layer

[0081] 272: Top surface

[0082] 280: Seed layer

[0083] 290: Mask layer

[0084] 292: Opening

[0085] 294: Trench

[0086] 300: Chip Packaging Structure

[0087] 310: Conductive layer

[0088] 312: Conductive bump

[0089] 314: Ring structure

[0090] 314a: Part

[0091] 320: Solder layer

[0092] 320a: Solder ball

[0093] 320b: Solder ball

[0094] 410:Substrate

[0095] 412: Insulation layer

[0096] 414: Wiring layer

[0097] 416: Conductive via

[0098] 418: Conductive pad

[0099] 420: Bottom fill layer

[0100] 500: Chip Packaging Structure

[0101] 600: Chip Packaging Structure

[0102] 700: Chip Packaging Structure

[0103] 800: Chip Packaging Structure

[0104] 900: Chip Packaging Structure

[0105] D1: Distance

[0106] D2: Distance

[0107] D3: Distance

[0108] G1: Gap

[0109] G2: Gap

[0110] L: Wiring layer

[0111] SC: Cutting line

[0112] T1: Thickness

[0113] T2: Thickness

[0114] T3: Thickness

[0115] T4: Thickness

[0116] T5: Thickness

[0117] T6: Thickness

[0118] V: Conductive via

[0119] V1: Vertical direction

[0120] W1: Line width

[0121] W2: Width

[0122] W3: Line width

[0123] W4: Width

[0124] W5: Line width

[0125] W6: Width

[0126] W7: Width

[0127] W8: Width Detailed Implementation

[0128] The following provides numerous different embodiments or examples for implementing different components in the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the following description referring to a first component being formed on or above a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of the embodiments of the present invention; this repetition is for simplicity and clarity and does not specify a relationship between the various embodiments and / or states discussed.

[0129] Furthermore, spatial relative terms may be used, such as “under,” “below,” “below,” “above,” “upper,” and similar terms, to facilitate the description of the relationship between one or more elements or components as shown in the figures. These spatial relative terms encompass different orientations of the device in use or operation, as well as the orientations described in the figures. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related descriptions used therein may be interpreted accordingly. It should be understood that additional operations may be provided before, during, and after the method, and some described operations may be replaced or omitted in other embodiments of the method.

[0130] The following describes some embodiments of the present invention. Additional operations may be provided before, during, and after the stages described in these embodiments. Some stages described may be replaced or omitted in different embodiments. Additional components may be added to the semiconductor device structure. Some components described below may be replaced or omitted in different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in other logical orders.

[0131] Some embodiments of this invention may also include other components and processes. For example, test structures may be included to aid in verification testing of three-dimensional (3D) packaged or three-dimensional integrated circuit (3DIC) devices. Test structures may, for example, include test pads formed within a redistribution layer or on a substrate to enable testing of the 3D package or 3D integrated circuit, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0132] Figures 1A to 1IThis is a cross-sectional schematic diagram showing various stages of the process for forming a chip package structure, according to some embodiments. According to some embodiments, such as... Figure 1A As shown, a substrate 112 is provided. In some embodiments, the substrate 112 is made of an elemental semiconductor material, such as silicon or germanium, which has a single crystal, polycrystalline, or amorphous structure.

[0133] In some other embodiments, substrate 112 is made of compound semiconductors, alloy semiconductors, or combinations thereof. Compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, and indium arsenide, while alloy semiconductors include SiGe or GaAsP. According to some embodiments, substrate 112 is also referred to as a semiconductor substrate. Substrate 112 may also comprise multilayer semiconductors, semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or combinations thereof.

[0134] According to some embodiments, such as Figure 1A As shown, a device 114 is formed in and / or on a substrate 112. According to some embodiments, the device 114 includes electronic components. According to some embodiments, the electronic components include active components (e.g., transistors, diodes, or similar components) and / or passive components (e.g., resistors, capacitors, inductors, or similar components).

[0135] According to some embodiments, such as Figure 1A As shown, an interconnect layer 116 for the covering device 114 is formed on the substrate 112. According to some embodiments, such as... Figure 1A As shown, conductive pads 117a and 117b are formed on interconnect layer 116. According to some embodiments, interconnect layer 116 includes interconnect structure 116a and dielectric layer 116b. According to some embodiments, interconnect structure 116a is within dielectric layer 116b.

[0136] According to some embodiments, the interconnect structure 116a includes a wiring layer L and a conductive via V. According to some embodiments, the conductive via V is electrically connected between different wiring layers L. According to some embodiments, the conductive via V is electrically connected between the wiring layer L and the conductive pad 117a.

[0137] According to some embodiments, the conductive via V is electrically connected between the wiring layer L and the device 114. According to some embodiments, the interconnect structure 116a is electrically insulated from the conductive pad 117b. According to some embodiments, the wiring layer L, the conductive via V, and the conductive pads 117a and 117b are made of the same material, such as a metal (e.g., aluminum, copper, silver, gold, nickel, tungsten, or an alloy thereof).

[0138] According to some embodiments, such as Figure 1AAs shown, a passivation layer 118 is formed on interconnect layer 116 covering the edge portions of conductive pads 117a and 117b. According to some embodiments, passivation layer 118 has openings 118a that partially expose conductive pads 117a and 117b. According to some embodiments, passivation layer 118 is made of polyimide, silicon oxide, silicon nitride, undoped silicate glass (USG), or other suitable dielectric materials.

[0139] According to some embodiments, such as Figure 1A As shown, a seed layer 120 is formed on the passivation layer 118 and conductive pads 117a and 117b. According to some embodiments, the seed layer 120 is made of titanium, copper, or similar materials. According to some embodiments, a physical vapor deposition (PVD) process, such as sputtering, is used to form the seed layer 120.

[0140] Figure 1A-1 According to some embodiments, it is shown Figure 1A A top view of the chip package structure. According to some embodiments, Figure 1A It is along Figure 1A-1 A cross-sectional view of the chip package structure with the middle section line I-I'.

[0141] According to some embodiments, such as Figure 1A and Figure 1A-1 As shown, a mask layer 130 is formed on the seed layer 120. According to some embodiments, the mask layer 130 has an opening 132 and a trench 134. According to some embodiments, the opening 132 and the trench 134 partially expose the seed layer 120 on the conductive pads 117a and 117b. According to some embodiments, the trench 134 surrounds the opening 132. According to some embodiments, the mask layer 130 is made of a polymeric material such as a photoresist material.

[0142] According to some embodiments, such as Figure 1A and Figure 1A-1 As shown, conductive layers 140 are formed within openings 132 and trenches 134. According to some embodiments, conductive bumps 142 are formed in each of the conductive layers 140 within the openings 132. According to some embodiments, annular structures 144 are formed in the conductive layers 140 within the trenches 134. According to some embodiments, the annular structures 144 surround the conductive bumps 142.

[0143] In some embodiments, the linewidth W1 of the annular structure 144 is greater than the width W2 of the conductive bump 142. According to some embodiments, an electroplating process is used to form the conductive layer 140. According to some embodiments, the annular structure 144 and the conductive bump 142 are formed simultaneously.

[0144] According to some embodiments, in the electroplating process, since the width of the trench 134 (i.e., W1) is greater than the width of the opening 132 (i.e., W2), the plating current density applied to the seed layer 120 under the trench 134 is less than the plating current density applied to the seed layer 120 under the opening 132. Therefore, according to some embodiments, the thickness T1 of the annular structure 144 is less than the thickness T2 of the conductive bump 142.

[0145] Generally, the region of the interconnect layer 116 adjacent to the predetermined cut line SC is a bump-less region. The peripheral conductive bumps adjacent to the bump-less region may tend to be thicker than the central conductive bumps relatively far from the bump-less region, which may affect the coplanarity of the conductive bumps. According to some embodiments, an annular structure 144 is formed around the conductive bump 142 to separate the conductive bump 142 from the bump-less region. Therefore, according to some embodiments, the coplanarity of the conductive bump 142 is improved. As a result, the yield of the subsequent bonding process to bond the conductive bump 142 to the substrate is improved.

[0146] According to some embodiments, since the width of the trench 134 (i.e., W1) is greater than the width of the opening 132 (i.e., W2), the plating current density applied to the seed layer 120 exposed by the trench 134 is less than the plating current density applied to the seed layer 120 exposed by the opening 132. Therefore, according to some embodiments, the thickness T1 of the annular structure 144 is less than the thickness T2 of the conductive bump 142.

[0147] According to some embodiments, the annular structure 144 is a continuous ring structure that continuously surrounds all conductive bumps 142. According to some embodiments, the conductive layer 140 is made of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Cu), or nickel (Ni).

[0148] According to some embodiments, such as Figure 1A and Figure 1A-1 As shown, a solder layer 150 is formed on the conductive bump 142 and the annular structure 144. According to some embodiments, the solder layer 150 is made of tin (Sn) or other suitable conductive materials with a melting point lower than that of the conductive bump 142.

[0149] According to some embodiments, a plating process, such as electroplating, is used to form the solder layer 150. According to some embodiments, the solder layer 150 on the annular structure 144 is wider than the solder layer 150 on the conductive bump 142. According to some embodiments, the solder layer 150 on the annular structure 144 is thinner than the solder layer 150 on the conductive bump 142.

[0150] Figure 1B-1 According to some embodiments, it is shown Figure 1B A top view of the chip package structure. According to some embodiments, Figure 1B It is along Figure 1B-1 A cross-sectional view of the chip package structure with the middle cut-off line I-I'. According to some embodiments, such as... Figure 1B and Figure 1B-1 As shown, mask layer 130 is removed. According to some embodiments, the removal process includes an ash process and / or a rinsing process.

[0151] Subsequently, according to some embodiments, such as Figure 1B As shown, the seed layer 120, which was originally under the mask layer 130, is removed. According to some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process.

[0152] Subsequently, according to some embodiments, such as Figure 1A and Figure 1B As shown, a reflow process is performed on solder layer 150 to transform solder layer 150 into solder balls 150a. According to some embodiments, such as... Figure 1B-1 As shown, the welding ball 150a on the annular structure 144 is also referred to as a welding electrode or welding ring. According to some embodiments, such as... Figure 1A and Figure 1B As shown, a cutting process is performed along a predetermined cutting line SC to cut the substrate 112, interconnect layer 116 and passivation layer 118 to form chip 110.

[0153] According to some embodiments, each chip 110 includes a portion of a substrate 112, a device 114, a portion of an interconnect layer 116, conductive pads 117a and 117b, and a portion of a passivation layer 118. For simplicity, Figure 1B-1 Only one of the chips 110 is displayed.

[0154] Figure 1C-1 According to some embodiments, it is shown Figure 1C A top view of the chip package structure. According to some embodiments, Figure 1C It is along Figure 1C-1 A cross-sectional view of the chip package structure with the middle cut-off line I-I'. According to some embodiments, such as... Figure 1C and Figure 1C-1 As shown, a substrate 210 is provided. In some embodiments, the substrate 210 is an interposer wafer. According to some embodiments, the substrate 210 includes a semiconductor substrate 211, a conductive via structure 212, a barrier layer 213, a redistribution structure 214, and a passivation layer 215.

[0155] According to some embodiments, the semiconductor substrate 211 has surfaces 211a and 211b. In some embodiments, the semiconductor substrate 211 is made of an elemental semiconductor material, such as silicon or germanium, comprising a single-crystal, polycrystalline, or amorphous structure.

[0156] In some other embodiments, the semiconductor substrate 211 is made of a compound semiconductor, an alloy semiconductor, or a combination thereof. Compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide, while alloy semiconductors include SiGe or GaAsP. The semiconductor substrate 211 may also comprise a multilayer semiconductor, a semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0157] According to some embodiments, a conductive via structure 212 is formed within a semiconductor substrate 211. The conductive via structure 212 may be formed extending from surface 211a into the semiconductor substrate 211. According to some embodiments, a barrier layer 213 is formed on the semiconductor substrate 211. According to some embodiments, the barrier layer 213 is located between the conductive via structure 212 and the semiconductor substrate 211.

[0158] According to some embodiments, the barrier layer 213 is used to prevent material from the conductive via structure 212 from diffusing into the semiconductor substrate 211. According to some embodiments, the barrier layer 213 is further used to electrically insulate the conductive via structure 212 from the semiconductor substrate 211.

[0159] According to some embodiments, the barrier layer 213 is made of a silicon-containing material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, similar materials, or combinations thereof. In some other embodiments, the barrier layer 213 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicon glass (FSG), tetraethyl orthosilicate (TEOS), or similar materials.

[0160] The barrier layer 213 is formed using an oxidation process, a deposition process, a spin coating process, or other suitable processes. According to some embodiments, the deposition process includes a chemical vapor deposition (CVD) process, such as a flowable chemical vapor deposition (FCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition (LPCVD) process, or a similar process.

[0161] In some embodiments, substrate 210 is a device wafer comprising various device elements. In some embodiments, various device elements are formed in and / or on semiconductor substrate 211. For simplicity and clarity, device elements are not shown in the drawings. Examples of various device elements include active elements, passive elements, other suitable elements, or combinations thereof. Active elements may include transistors or diodes (not shown) formed on surface 211a. Passive elements include resistors, capacitors, or other suitable passive elements.

[0162] For example, transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc. Various processes are implemented to form various device components, such as front-end-of-line (FEOL) semiconductor manufacturing processes. Front-end-of-line semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or combinations thereof.

[0163] In some embodiments, an isolation component (not shown) is formed within a semiconductor substrate 211. The isolation component is used to define an active region and electrically isolate various device elements formed within the active region. In some embodiments, the isolation component includes a shallow trench isolation (STI) component, a local oxidation of silicon (LOCOS) component, other suitable isolation components, or a combination thereof.

[0164] According to some embodiments, a redistribution structure 214 is formed on a semiconductor substrate 211. According to some embodiments, the redistribution structure 214 includes an insulating layer 214a, a wiring layer 214b, a conductive via 214c, and conductive pads 214d and 214e. According to some embodiments, an insulating layer 214a is formed on surface 211a. According to some embodiments, a wiring layer 214b is formed within the insulating layer 214a.

[0165] According to some embodiments, such as Figure 1C As shown, the conductive via 214c is electrically connected between different wiring layers 214b and between wiring layer 214b and conductive pad 214d. According to some embodiments, for clarity, Figure 1C Only one of the wiring layers 214b is shown.

[0166] According to some embodiments, the conductive via structure 212 is electrically connected to the conductive pad 214d via wiring layer 214b and conductive via 214c. According to some embodiments, the conductive pad 214d is formed on the insulating layer 214a. According to some embodiments, the conductive pad 214e is electrically insulated from the conductive via 214c and wiring layer 214b.

[0167] According to some embodiments, the conductive via structure 212, wiring layer 214b, conductive via 214c, and conductive pad 214d are made of conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or other suitable materials.

[0168] According to some embodiments, such as Figure 1C As shown, a passivation layer 215 is formed on the redistribution structure 214, covering the edge portions of conductive pads 214d and 214e. According to some embodiments, the passivation layer 215 has openings 215a that partially expose the conductive pads 214d and 214e. According to some embodiments, the passivation layer 215 is made of polyimide, silicon oxide, silicon nitride, undoped silicate glass (USG), or other suitable dielectric materials.

[0169] According to some embodiments, such as Figure 1CAs shown, a seed layer 220 is formed on the passivation layer 215 and conductive pads 214d and 214e. According to some embodiments, the seed layer 220 is made of titanium, copper, or similar materials. According to some embodiments, a physical vapor deposition (PVD) process, such as sputtering, is used to form the seed layer 220.

[0170] Figure 1C-1 According to some embodiments, it is shown Figure 1C A top view of the chip package structure. According to some embodiments, Figure 1C It is along Figure 1C-1 A cross-sectional view of the chip package structure with the middle section line I-I'.

[0171] According to some embodiments, such as Figure 1C and Figure 1C-1 As shown, a mask layer 230 is formed on the seed layer 220. According to some embodiments, the mask layer 230 has an opening 232 and a trench 234. According to some embodiments, the opening 232 and the trench 234 partially expose the seed layer 220 on the conductive pads 214d and 214e. According to some embodiments, the trench 234 surrounds the opening 232. According to some embodiments, the mask layer 230 is made of a polymeric material such as a photoresist material.

[0172] According to some embodiments, such as Figure 1C and Figure 1C-1 As shown, conductive layers 240 are formed within openings 232 and trenches 234. According to some embodiments, conductive bumps 242 are formed within each of the conductive layers 240 within the openings 232. According to some embodiments, annular structures 244 are formed within the conductive layers 240 within the trenches 234. According to some embodiments, the annular structures 244 surround the conductive bumps 242.

[0173] In some embodiments, the linewidth W3 of the annular structure 244 is greater than the width W4 of the conductive bump 242. According to some embodiments, an electroplating process is used to form the conductive layer 240. According to some embodiments, the annular structure 244 and the conductive bump 242 are formed simultaneously.

[0174] According to some embodiments, in the electroplating process, since the width of the trench 234 (i.e., W3) is greater than the width of the opening 232 (i.e., W4), the plating current density applied to the seed layer 220 under the trench 234 is less than the plating current density applied to the seed layer 220 under the opening 232. Therefore, according to some embodiments, the thickness T3 of the annular structure 244 is less than the thickness T4 of the conductive bump 242.

[0175] According to some embodiments, the annular structure 244 is a continuous ring structure that continuously surrounds all the conductive bumps 242. According to some embodiments, the conductive layer 240 is made of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Cu), or nickel (Ni).

[0176] According to some embodiments, such as Figure 1C and Figure 1C-1 As shown, a solder layer 250 is formed on the conductive bump 242 and the annular structure 244. According to some embodiments, the solder layer 250 is made of tin (Sn) or other suitable conductive materials with a melting point lower than that of the conductive bump 242.

[0177] According to some embodiments, a plating process, such as electroplating, is used to form the solder layer 250. According to some embodiments, the solder layer 250 on the annular structure 244 is wider than the solder layer 250 on the conductive bump 242. According to some embodiments, the solder layer 250 on the annular structure 244 is thinner than the solder layer 250 on the conductive bump 242.

[0178] Figure 1D-1 According to some embodiments, it is shown Figure 1D A top view of the chip package structure. According to some embodiments, Figure 1D It is along Figure 1D-1 A cross-sectional view of the chip package structure with the middle cut-off line I-I'. According to some embodiments, such as... Figure 1D and Figure 1D-1 As shown, mask layer 230 is removed. According to some embodiments, the removal process includes an ashing process and / or a rinsing process.

[0179] Subsequently, according to some embodiments, such as Figure 1D As shown, the seed layer 220 originally located under the mask layer 230 is removed. According to some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process. Then, according to some embodiments, such as Figure 1C and Figure 1D As shown, a reflow process is performed on solder layer 250 to transform solder layer 250 into solder balls 250a. According to some embodiments, such as... Figure 1D-1 As shown, the welding ball 250a on the annular structure 244 is also called a welding rod or welding ring.

[0180] According to some embodiments, such as Figure 1E As shown, a chip 110 is disposed on a substrate 210. Subsequently, according to some embodiments, such as... Figure 1B , Figure 1D and Figure 1EAs shown, a reflow process is performed on solder balls 150a and 250a. According to some embodiments, after the reflow process, each solder ball 150a and the solder ball 250a below it melts and mixes together to form solder ball 251. Therefore, according to some embodiments, chip 110 is bonded to substrate 210 via bumps (also known as conductive bumps) 142 and 242 and solder ball 251.

[0181] According to some embodiments, after the chip 110 is bonded to the substrate 210, the annular structure 144 is electrically insulated from the substrate 210. According to some embodiments, the annular structure 244 is electrically insulated from the chip 110.

[0182] Figure 1E-1 According to some embodiments, it is shown Figure 1E A top view of the chip package structure. According to some embodiments, Figure 1E It is along Figure 1E-1 A cross-sectional view of the chip package structure with the middle section line I-I'.

[0183] According to some embodiments, such as Figure 1E and Figure 1E-1 As shown, the annular structure 244 (or the solder ball 250a connected to the annular structure 244) does not overlap with the annular structure 144 (or the solder ball 150a connected to the annular structure 144). That is, according to some embodiments, the annular structures 144 and 244 are misaligned in the direction V1 perpendicular to the surface 211a of the semiconductor substrate 211.

[0184] According to some embodiments, such as Figure 1E As shown, an underfill layer 260 is formed within the gap G1 between the substrate 210 and the chip 110. According to some embodiments, the underfill layer 260 surrounds the bumps 142 and 242, the annular structures 144 and 244, the solder balls 251, and the chip 110. According to some embodiments, a portion of the underfill layer 260 lies between the annular structure 144 and the substrate 210.

[0185] According to some embodiments, a portion of the underfill layer 260 is between the annular structure 244 and the chip 110. According to some embodiments, a portion of the underfill layer 260 is between the annular structures 144 and 244. According to some embodiments, a portion of the underfill layer 260 is between solder balls 150a and 250a. According to some embodiments, the underfill layer 260 comprises a polymer material.

[0186] According to some embodiments, such as Figure 1E and Figure 1E-1As shown, a molding layer 270 is formed on substrate 210. According to some embodiments, the molding layer 270 surrounds chip 110, underfill layer 260, annular structures 144 and 244, bumps 142 and 242, and solder balls 251. According to some embodiments, the molding layer 270 comprises a polymer material.

[0187] According to some embodiments, the formation of the molding layer 270 includes forming a molding material layer (not shown) on the substrate 210, the bottom filler layer 260, and the chip 110; and performing a planarization process on the molding material layer to remove the upper portion of the molding material layer until the top surface 101 of the chip 110 is exposed. According to some embodiments, the top surfaces 101 and 272 of the chip 110 and the molding layer 270 are substantially coplanar.

[0188] According to some embodiments, such as Figure 1F As shown, the lower portion of the semiconductor substrate 211 is removed. According to some embodiments, the removal process includes a chemical mechanical polishing (CMP) process. According to some embodiments, after the removal process, the conductive via structure 212 and the barrier layer 213 are exposed.

[0189] According to some embodiments, the conductive via structure 212 and the barrier layer 213 penetrate through the semiconductor substrate 211. According to some embodiments, when the semiconductor substrate 211 is a silicon substrate, the conductive via structure 212 may also be referred to as a through-substrate via or a through-silicon via (TSV).

[0190] Figure 1G-1 According to some embodiments, it is shown Figure 1G A top view of the chip package structure. According to some embodiments, Figure 1G It is along Figure 1G-1 A cross-sectional view of the chip package structure with the middle cut-off line I-I'. According to some embodiments, such as... Figure 1G and Figure 1G-1 As shown, the semiconductor substrate 211 is flipped up and down.

[0191] According to some embodiments, such as Figure 1G As shown, an insulating layer 216 is formed on surface 211b. According to some embodiments, the insulating layer 216 is used to electrically insulate the wiring layer subsequently formed over the insulating layer 216 from the semiconductor substrate 211. According to some embodiments, the insulating layer 216 has openings 216a respectively on the conductive via structure 212.

[0192] According to some embodiments, the insulating layer 216 is made of a silicon-containing material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, similar materials, or combinations thereof. In some other embodiments, the insulating layer 216 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicon glass (FSG), tetraethoxysilane (TEOS), or similar materials.

[0193] An insulating layer 216 is formed using an oxidation process, a deposition process, a spin coating process, or other suitable processes. According to some embodiments, the deposition process includes a chemical vapor deposition (CVD) process, such as a flowable chemical vapor deposition (FCVD) process, a plasma-assisted chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition (LPCVD) process, or a similar process. According to some embodiments, a photolithography process and an etching process are used to form the opening 216a.

[0194] According to some embodiments, a redistribution structure 217 is formed on the surface 211b of the semiconductor substrate 211. According to some embodiments, the redistribution structure 217 includes a dielectric layer 217a, a wiring layer 217b, and a conductive via 217c. According to some embodiments, the wiring layer 217b and the conductive via 217c are formed within the dielectric layer 217a.

[0195] According to some embodiments, such as Figure 1G As shown, conductive pads 218a and 218b are formed on the redistribution structure 217. According to some embodiments, conductive vias 217c are electrically connected between different wiring layers 217b and between wiring layers 217b and conductive pads 218a. According to some embodiments, for clarity, Figure 1G Only one of the wiring layers 217b is shown.

[0196] According to some embodiments, conductive pad 218b is electrically insulated from conductive via 217c and wiring layer 217b. According to some embodiments, conductive via structure 212 is electrically connected to conductive pad 218a via wiring layer 217b and conductive via 217c.

[0197] According to some embodiments, such as Figure 1G As shown, a buffer ring 219 is formed on conductive pads 218a and 218b. According to some embodiments, the buffer ring 219 has an opening 219a exposing the conductive pad 218a or 218b beneath it. According to some embodiments, the buffer ring 219 is used to buffer stress between the substrate 210 and the bumps subsequently formed on the buffer ring 219.

[0198] According to some embodiments, the buffer ring 219 is made of an elastic material such as a polymer (e.g., polyimide). In some other embodiments (not shown), the buffer layer 219 may be replaced with a buffer layer having openings that expose the conductive pads 218a and 218b.

[0199] According to some embodiments, such as Figure 1G As shown, a seed layer 280 is formed on the redistribution structure 217, conductive pads 218a and 218b, and buffer ring 219. The material of the seed layer 280 may include copper or a copper alloy. The material of the seed layer 280 may include other metals, such as silver, gold, aluminum, and combinations thereof.

[0200] According to some embodiments, such as Figure 1G As shown, a mask layer 290 is formed on the seed layer 280. According to some embodiments, the mask layer 290 has openings 292 and trenches 294 that expose the seed layer 280 on conductive pads 218a and 218b and on a buffer ring 219 adjacent to the conductive pads 218a and 218b. According to some embodiments, the mask layer 290 is made of a polymeric material such as a photoresist material.

[0201] According to some embodiments, such as Figure 1G As shown, conductive layers 310 are formed within openings 292 and trenches 294. According to some embodiments, conductive bumps 312 are formed within each of the conductive layers 310 within opening 292. According to some embodiments, annular structures 314 are formed within the conductive layers 310 within trenches 294. According to some embodiments, the annular structure 314 surrounds the conductive bumps 312. According to some embodiments, the annular structure 314 is electrically insulated from the chip 110 and the conductive bumps 312, 242, and 142.

[0202] In some embodiments, the linewidth W5 of the annular structure 314 is greater than the width W6 of the conductive bump 312. According to some embodiments, an electroplating process is used to form the conductive layer 310. According to some embodiments, the annular structure 314 and the conductive bump 312 are formed simultaneously.

[0203] According to some embodiments, in the electroplating process, since the width of the trench 294 (i.e., W5) is greater than the width of the opening 292 (i.e., W6), the plating current density applied to the seed layer 280 under the trench 294 is less than the plating current density applied to the seed layer 280 under the opening 292. Therefore, according to some embodiments, the thickness T5 of the annular structure 314 is less than the thickness T6 of the conductive bump 312.

[0204] According to some embodiments, the annular structure 314 is a continuous ring structure that continuously surrounds all conductive bumps 312. According to some embodiments, the conductive layer 310 is made of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Cu), or nickel (Ni).

[0205] According to some embodiments, such as Figure 1G and Figure 1G-1 As shown, a solder layer 320 is formed on the conductive bump 312 and the annular structure 314. According to some embodiments, the solder layer 320 is made of tin (Sn) or other suitable conductive materials with a melting point lower than that of the conductive bump 312.

[0206] According to some embodiments, a plating process, such as electroplating, is used to form the solder layer 320. According to some embodiments, the solder layer 320 on the annular structure 314 is wider than the solder layer 320 on the conductive bump 312. According to some embodiments, the solder layer 320 on the annular structure 314 is thinner than the solder layer 320 on the conductive bump 312.

[0207] Figure 1H-1 According to some embodiments, it is shown Figure 1H A top view of the chip package structure. According to some embodiments, Figure 1H It is along Figure 1H-1 A cross-sectional view of the chip package structure with the middle cut-off line I-I'. According to some embodiments, such as... Figure 1G , Figure 1H and Figure 1H-1 As shown, mask layer 290 is removed. According to some embodiments, the removal process includes an ashing process and / or a rinsing process.

[0208] Subsequently, according to some embodiments, such as Figure 1H As shown, the seed layer 280, which was originally under the mask layer 290, is removed. According to some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process.

[0209] Subsequently, according to some embodiments, such as Figure 1G and Figure 1H As shown, a reflow process is performed on solder layer 320 to transform solder layer 320 into solder balls 320a and 320b. According to some embodiments, solder balls 320a are on conductive bumps 312. According to some embodiments, solder balls 320b are on annular structures 314. According to some embodiments, such as... Figure 1H-1 As shown, the 320b welding ball is also called a welding electrode or welding ring.

[0210] According to some embodiments, such as Figure 1H As shown, a dicing process is performed along a predetermined dicing line SC to cut the substrate 210 and the molding layer 270 to form a chip package structure 300. According to some embodiments, for clarity, Figure 1H-1 Only one of the chip package structures 300 is shown.

[0211] Figure 1I-1 According to some embodiments, it is shown Figure 1I A top view of the chip package structure. According to some embodiments, Figure 1I It is along Figure 1I-1 A cross-sectional view of the chip package structure with the middle cut-off line I-I'. According to some embodiments, such as... Figure 1I and Figure 1I-1 As shown, the chip packaging structure 300 is flipped up and down.

[0212] According to some embodiments, such as Figure 1I As shown, the chip package structure 300 is bonded to the substrate 410 via solder balls 320a. According to some embodiments, the solder balls 320b are spaced apart from the substrate 410. According to some embodiments, the solder balls 320b and the annular structure 314 are electrically insulated from the substrate 410 and the chip 110.

[0213] According to some embodiments, conductive bumps 142 and 242 are micro-bumps. According to some embodiments, conductive bump 312 is a controlled collapse chip connection (C4) bump. According to some embodiments, conductive bump 312 is wider than conductive bumps 142 or 242.

[0214] According to some embodiments, substrate 410 includes an insulating layer 412, a wiring layer 414, a conductive via 416, and a conductive pad 418. According to some embodiments, the wiring layer 414 is formed within the insulating layer 412. According to some embodiments, the conductive pad 418 is formed on the insulating layer 412. According to some embodiments, the conductive via 416 electrically connects different wiring layers 414 and between the wiring layer 414 and the conductive pad 418.

[0215] According to some embodiments, such as Figure 1I As shown, an underfill layer 420 is formed between substrates 210 and 410. According to some embodiments, a portion of the underfill layer 420 is between the annular structure 314 (or solder ball 320b) and the substrate 410.

[0216] In some embodiments, a portion of the underfill layer 420 is formed on the substrate 410 and surrounds the chip package structure 300. According to some embodiments, the underfill layer 420 is made of an insulating material, such as a polymer. According to some embodiments, the chip package structure 500 is substantially formed in this step.

[0217] Figure 2This is a top view of a chip package structure 600 according to some embodiments. According to some embodiments, such as... Figure 2 As shown, the chip packaging structure 600 is similar to Figure 1I-1 The chip package structure 500, except that the annular structure 144 of the chip package structure 600 has portions 144a that are spaced apart from each other.

[0218] In some embodiments, portions 144a are spaced approximately the same distance D1 from each other. In some embodiments, conductive bumps 142 are spaced apart by a distance D2. In some embodiments, distance D1 is less than distance D2. In some embodiments, portion 144a is a strip-shaped portion.

[0219] According to some embodiments, the annular structure 244 has portions 244a spaced apart from each other. In some embodiments, the portions 244a are spaced apart from each other by a substantially equal distance D3. According to some embodiments, the distance D3 is less than the distance D2. According to some embodiments, the portion 244a is a strip-shaped portion.

[0220] According to some embodiments, the annular structure 314 has portions 314a spaced apart from each other. In some embodiments, the portions 314a are spaced apart from each other by a substantially equal distance D3. According to some embodiments, the distance D3 is less than the distance D2. According to some embodiments, the portion 314a is a strip-shaped portion.

[0221] Figure 3 This is a top view of a chip package structure 700 according to some embodiments. According to some embodiments, such as... Figure 3 As shown, the chip packaging structure 700 is similar to Figure 2 The chip package structure 600, except that the portion 144a of the annular structure 144 of the chip package structure 700 has a square shape.

[0222] According to some embodiments, a portion 244a of the annular structure 244 of the chip package structure 700 has a square shape. According to some embodiments, a portion 314a of the annular structure 314 of the chip package structure 700 has a square shape.

[0223] Figure 4 This is a cross-sectional schematic diagram of a chip package structure 800 according to some embodiments. According to some embodiments, such as... Figure 4 As shown, the chip packaging structure 800 is similar to Figure 1I The chip package structure 500 is except that the annular structures 144, 244 and 314 of the chip package structure 800 are aligned with each other.

[0224] Figure 5A This is a top view of a chip package structure 900 according to some embodiments. Figure 5BAccording to some embodiments, it is shown along Figure 5A A cross-sectional view of the chip package structure 900 with the mid-section line I-I'. According to some embodiments, such as... Figure 5A and Figure 5B As shown, the chip packaging structure 900 is similar to Figure 4 The chip package structure 800, except that the ring structure 144 is connected to the ring structure 244 via solder balls 251 between the ring structures 144 and 244.

[0225] By adjusting the width W7 of the annular structure 144, the annular structure 144 and the conductive bump 142 can have approximately the same thickness. By adjusting the width W8 of the annular structure 244, the annular structure 244 and the conductive bump 242 can have approximately the same thickness.

[0226] According to some embodiments, such as Figure 5A and Figure 5B As shown, the bottom filling layer 260 is filled into the gap G1 between the substrate 210 and the chip 110 via the gap G2 between the portions 144a of the annular structure 144 or between the portions 244a of the annular structure 244.

[0227] According to some embodiments, a chip package structure and a method for forming the same are provided. The method involves forming a ring structure around conductive bumps on an interconnect layer to separate the conductive bumps from bump-free regions of the interconnect layer adjacent to predetermined dicing lines. Since bump-free regions can affect the coplanarity of the conductive bumps, the ring structure separating the conductive bumps from the bump-free regions improves the coplanarity of the conductive bumps. Therefore, the yield of the bonding process for attaching the conductive bumps to the substrate can be improved.

[0228] According to some embodiments, a method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first annular structure on a chip. The first annular structure surrounds the first conductive bump, and the first annular structure and the first conductive bump are made of the same first material. The chip includes an interconnect structure, and the first annular structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate via the first conductive bump.

[0229] In one embodiment, an electroplating process is used to simultaneously form a first conductive bump and a first annular structure. In one embodiment, the linewidth of the first annular structure is greater than the width of the first conductive bump. In one embodiment, the first annular structure is thinner than the first conductive bump. In one embodiment, the first annular structure is a continuous ring structure. In one embodiment, the first annular structure has multiple portions spaced approximately the same first distance from each other, and forming the first conductive bump and the first annular structure on the chip further includes forming a second conductive bump on the chip, wherein the second conductive bump is adjacent to the first conductive bump and surrounded by the first annular structure, the first conductive bump and the second conductive bump are spaced apart by a second distance, and the first distance is less than the second distance. In one embodiment, the multiple portions include strip-shaped portions. In one embodiment, the method further includes forming a second conductive bump and a second annular structure on the substrate before bonding the chip to the substrate via the first conductive bump, wherein the second annular structure surrounds the second conductive bump, and the second annular structure and the second conductive bump are made of the same second material. After bonding the chip to the substrate, the first conductive bump is bonded to the second conductive bump, and the second annular structure is electrically insulated from the chip. In one embodiment, the method further includes forming an underfill layer between the chip and the substrate after bonding the chip to the substrate via the first conductive bump, wherein a portion of the underfill layer is between the first annular structure and the second annular structure. In one embodiment, the second annular structure does not overlap with the first annular structure.

[0230] According to some embodiments, a method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a first mask layer on a second surface of the first substrate. The first mask layer has a first opening and a first trench surrounding the first opening. The method includes electroplating to form a first conductive layer within the first opening and the first trench. The first conductive layer within the first opening forms a first conductive bump. The first conductive layer within the first trench forms a first annular structure. The first annular structure is electrically insulated from the chip and the first conductive bump. The method includes removing the first mask layer. The method includes bonding a first substrate to a second substrate via the first conductive bump. The first annular structure is electrically insulated from the second substrate.

[0231] In one embodiment, the method further includes forming an underfill layer between the first substrate and the second substrate after bonding the first substrate to the second substrate via a first conductive bump, wherein a portion of the underfill layer is between the first annular structure and the second substrate. In another embodiment, the method further includes forming a second mask layer on the chip before bonding the chip to a first surface of the first substrate, wherein the second mask layer has a second opening and a second trench surrounding the second opening; electroplating a second conductive layer within the second opening and the second trench, wherein the second conductive layer within the second opening forms a second conductive bump, and the second conductive layer within the second trench forms a second annular structure; and removing the second mask layer, wherein after bonding the chip to the first surface, the second conductive bump is bonded to the first surface, the chip includes an interconnect structure, and the second annular structure is electrically insulated from the interconnect structure, the second conductive bump, the first substrate, and the second substrate. In one embodiment, the method further includes forming a third conductive bump and a third annular structure on a first surface of a first substrate before bonding the chip to the first surface, wherein after bonding the chip to the first surface, a second conductive bump is engaged with the third conductive bump, the third annular structure surrounds the third conductive bump, the third annular structure and the third conductive bump are made of the same third material, and the third annular structure is electrically insulated from the chip, the third conductive bump, and the second substrate. In one embodiment, the first annular structure has a plurality of strip-shaped portions, and the plurality of strip-shaped portions are spaced approximately the same distance from each other.

[0232] According to some embodiments, a chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip on the substrate. The chip package structure includes a first conductive bump between the chip and the substrate and connected to the chip. The chip package structure includes a first annular structure between the chip and the substrate and connected to the chip. The first annular structure surrounds the first conductive bump, the first annular structure and the first conductive bump are made of the same first material, the chip includes interconnect structures, and the first annular structure is electrically insulated from the interconnect structures and the first conductive bump.

[0233] In one embodiment, the first annular structure is a continuous ring structure. In another embodiment, the first annular structure has a plurality of spaced-apart portions. In one embodiment, the chip package structure further includes a second conductive bump between the first conductive bump and the substrate; and a second annular structure on the substrate, wherein the second annular structure surrounds the second conductive bump, the second annular structure and the second conductive bump are made of the same second material, and the second annular structure is electrically insulated from the chip. In one embodiment, the chip package structure further includes a third conductive bump on a surface of the substrate, wherein the surface faces away from the chip; and a third annular structure on the surface, wherein the third annular structure surrounds the third conductive bump, the third annular structure and the third conductive bump are made of the same third material, and the third annular structure is electrically insulated from the chip and the third conductive bump.

[0234] The foregoing description outlines components of numerous embodiments to enable those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments.

Claims

1. A method for forming a chip package structure, comprising: A first conductive bump and a first annular structure are formed on a chip, wherein the first annular structure surrounds the first conductive bump, the first annular structure and the first conductive bump are made of the same first material, and the chip includes a first substrate and an interconnect structure disposed on the first substrate; and The chip is bonded to a second substrate via the first conductive bump, wherein a second annular structure is formed on the second substrate, wherein the first annular structure is electrically insulated from the interconnect structure, the first conductive bump and the second substrate, wherein in a top view the first annular structure and the second annular structure are separated by a distance in one direction, and the second annular structure surrounds the first conductive bump.

2. The method for forming a chip packaging structure as described in claim 1, wherein the first conductive bump and the first annular structure are formed simultaneously using an electroplating process.

3. The method for forming a chip packaging structure as described in claim 1, wherein the linewidth of the first annular structure is greater than the width of the first conductive bump.

4. The method for forming a chip packaging structure as described in claim 1, wherein the first annular structure is thinner than the first conductive bump.

5. The method for forming a chip packaging structure as described in claim 1, wherein the first annular structure is a continuous annular structure.

6. The method for forming a chip package structure as claimed in claim 1, wherein the first annular structure has a plurality of portions, the plurality of portions being spaced apart from each other by a substantially equal first distance, and forming the first conductive bump and the first annular structure on the chip further includes: A second conductive bump is formed on the chip, wherein the second conductive bump is adjacent to the first conductive bump and surrounded by the first annular structure, wherein the first conductive bump and the second conductive bump are spaced apart by a second distance, and the substantially equal first distance is smaller than the second distance.

7. The method for forming a chip package structure as claimed in claim 6, wherein the plurality of said portions include strip-shaped portions.

8. The method for forming a chip packaging structure as described in claim 1, further comprising: Before bonding the chip to the second substrate via the first conductive bump, a second conductive bump and a second annular structure are formed on the second substrate, wherein the second annular structure surrounds the second conductive bump, and wherein the second annular structure and the second conductive bump are made of the same second material. After the chip is bonded to the second substrate, the first conductive bump is bonded to the second conductive bump, and the second annular structure is electrically insulated from the chip.

9. The method for forming a chip packaging structure as described in claim 8, further comprising: After the chip is bonded to the second substrate via the first conductive bump, a bottom fill layer is formed between the chip and the second substrate, wherein a portion of the bottom fill layer is between the first annular structure and the second annular structure.

10. The method for forming a chip packaging structure as described in claim 8, wherein the second annular structure does not overlap with the first annular structure.

11. A method for forming a chip package structure, comprising: A chip is provided, wherein the chip includes a first substrate and an interconnect structure disposed on the first substrate; The chip is bonded to a first surface of a second substrate; A first mask layer is formed on a second surface of the second substrate, wherein the first mask layer has a first opening and a first trench surrounding the first opening; A first conductive layer is electroplated in the first opening and the first trench, wherein the first conductive layer in the first opening forms a first conductive bump, and the first conductive layer in the first trench forms a first annular structure, and the first annular structure is electrically insulated from the chip and the first conductive bump, wherein a second annular structure is formed on the chip; Remove the first mask layer; as well as The second substrate is bonded to a third substrate via the first conductive bump, wherein the first annular structure is electrically insulated from the third substrate, wherein in a top view the first annular structure and the second annular structure are separated by a distance in one direction, and the second annular structure surrounds the first conductive bump.

12. The method for forming a chip packaging structure as described in claim 11, further comprising: After the second substrate is bonded to the third substrate via the first conductive bump, a bottom fill layer is formed between the second substrate and the third substrate, wherein a portion of the bottom fill layer is between the first annular structure and the third substrate.

13. The method for forming a chip packaging structure as described in claim 11, further comprising: Before bonding the chip to the first surface of the second substrate, a second mask layer is formed on the chip, wherein the second mask layer has a second opening and a second trench surrounding the second opening; A second conductive layer is electroplated to form a second conductive bump in the second opening and the second trench, wherein the second conductive layer in the second opening forms a second conductive bump, and the second conductive layer in the second trench forms the second annular structure; and The second mask layer is removed, wherein after the chip is bonded to the first surface, the second conductive bump is bonded to the first surface, and the second annular structure is electrically insulated from the interconnect structure, the second conductive bump, the second substrate, and the third substrate.

14. The method for forming a chip package structure as described in claim 13, further comprising: Before bonding the chip to the first surface, a third conductive bump and a third annular structure are formed on the first surface of the second substrate. After bonding the chip to the first surface, the second conductive bump is bonded to the third conductive bump, and the third annular structure surrounds the third conductive bump. The third annular structure and the third conductive bump are made of the same third material, and the third annular structure is electrically insulated from the chip, the third conductive bump, and the third substrate.

15. The method for forming a chip package structure as claimed in claim 11, wherein the first annular structure has a plurality of strip-shaped portions, and the plurality of strip-shaped portions are spaced approximately the same distance from each other.

16. A method for forming a chip package structure, comprising: A first conductive bump and a first annular structure are formed on a chip, wherein the chip includes a first substrate and an interconnect structure disposed on the first substrate, the first annular structure surrounds the first conductive bump, and the top surface of the first annular structure is closer to the chip than the top surface of the first conductive bump. as well as The chip is bonded to a second substrate via the first conductive bump, wherein a second annular structure is formed on the second substrate, wherein the first annular structure is electrically insulated from the interconnect structure, the first conductive bump and the second substrate, wherein in a top view the first annular structure and the second annular structure are separated by a distance in one direction, and the second annular structure surrounds the first conductive bump.

17. The method for forming a chip package structure as described in claim 16, further comprising: After the first conductive bump and the first annular structure are formed on the chip and before the chip is bonded to the second substrate, a first solder layer and a second solder layer are formed on the first conductive bump and the first annular structure, respectively, wherein the first solder layer is thicker than the second solder layer, and the chip is bonded to the second substrate via the first solder layer.

18. The method for forming a chip package structure as described in claim 16, further comprising: Before bonding the chip to the second substrate, a second conductive bump and a second annular structure are formed on the second substrate, wherein the second annular structure surrounds the second conductive bump, and the chip is bonded to the second conductive bump.

19. The method of forming a chip package structure as claimed in claim 18, wherein in the top view of the first annular structure and the second annular structure, the second annular structure surrounds the first annular structure.

20. The method of forming a chip package structure as claimed in claim 16, wherein the first annular structure and the first conductive bump are made of the same material.

21. A chip packaging structure: comprising: A chip includes a first substrate and an interconnect structure disposed on the first substrate; A second substrate, wherein the chip is on the second substrate; A first conductive bump is located between the chip and the second substrate and is connected to the chip; A first annular structure is provided between and connected to the chip and the second substrate, wherein the first annular structure surrounds the first conductive bump, the first annular structure and the first conductive bump are made of the same first material, and the first annular structure is electrically insulated from the interconnect structure and the first conductive bump; and A second annular structure is provided on the second substrate, wherein, in a top view, the first annular structure and the second annular structure are separated by a distance in one direction, and the second annular structure surrounds the first conductive bump.

22. The chip packaging structure of claim 21, wherein the first annular structure is a continuous annular structure.

23. The chip packaging structure of claim 21, wherein the first annular structure has a plurality of portions spaced apart from each other.

24. The chip packaging structure as described in claim 21, further comprising: A second conductive bump is located between the first conductive bump and the second substrate, wherein the second annular structure surrounds the second conductive bump, and the second annular structure and the second conductive bump are made of the same second material.

25. The chip packaging structure of claim 24, wherein the second annular structure is electrically insulated from the chip.

26. The chip packaging structure of claim 25, wherein the second annular structure is electrically insulated from the second conductive bump.

27. The chip packaging structure of claim 24, wherein the second annular structure does not overlap with the first annular structure.

28. The chip packaging structure as described in claim 24, further comprising: A third conductive bump is on a surface of the second substrate, wherein the surface faces away from the chip; as well as A third annular structure on the surface, wherein the third annular structure surrounds the third conductive bump, the third annular structure and the third conductive bump are made of the same third material, and the third annular structure is electrically insulated from the chip and the third conductive bump.

29. The chip packaging structure as described in claim 21, further comprising: A bottom fill layer is provided between the chip and the second substrate, wherein a portion of the bottom fill layer is provided between the first annular structure and the second substrate.

30. The chip packaging structure of claim 21, wherein the first annular structure is thinner than the first conductive bump.

31. A chip packaging structure, comprising: A chip includes a first substrate and an interconnect structure disposed on the first substrate; A second substrate, wherein the chip is on the second substrate; A first conductive bump is located between the chip and the second substrate and is connected to the chip; A first annular structure surrounds the first conductive bump, wherein the first annular structure and the first conductive bump are made of the same first material, the first annular structure is electrically insulated from the first conductive bump, and a first linewidth of the first annular structure is greater than a first width of the first conductive bump; and A second annular structure is provided on the second substrate, wherein, in a top view, the first annular structure and the second annular structure are separated by a distance in one direction, and the second annular structure surrounds the first conductive bump.

32. The chip packaging structure as described in claim 31, further comprising: A second conductive bump is located between the first conductive bump and the second substrate, wherein the second annular structure surrounds the second conductive bump, and the second annular structure and the second conductive bump are made of the same second material.

33. The chip packaging structure of claim 32, wherein a second linewidth of the second annular structure is greater than a second width of the second conductive bump.

34. The chip packaging structure of claim 32, wherein the first annular structure overlaps with the second annular structure.

35. The chip packaging structure of claim 31, wherein a first bottom surface of the first conductive bump is closer to the second substrate than a second bottom surface of the first annular structure.

36. A chip packaging structure, comprising: A chip includes a first substrate and an interconnect structure disposed on the first substrate; A second substrate having a top surface and a bottom surface, wherein the chip is on the top surface of the second substrate; A first conductive bump is located on the bottom surface of the second substrate; A first annular structure is provided on the bottom surface of the second substrate, wherein the first annular structure surrounds the first conductive bump, the first annular structure and the first conductive bump are made of the same first material, and the first annular structure is electrically insulated from the first conductive bump and the second substrate; and A second annular structure is provided on a surface of the chip facing the second substrate, wherein in a top view the first annular structure and the second annular structure are separated by a distance in one direction, and the second annular structure surrounds the first conductive bump.

37. The chip packaging structure as described in claim 36, further comprising: A first solder layer is applied to the first conductive bump. as well as A second solder layer is provided on the first annular structure, wherein the second solder layer is thinner than the first solder layer.

38. The chip packaging structure as described in claim 36, further comprising: A second conductive bump is provided on the bottom surface of the second substrate, wherein the first annular structure further surrounds the second conductive bump. The first annular structure has multiple parts, which are spaced apart from each other by a substantially equal first distance. The first conductive bump and the second conductive bump are spaced apart by a second distance, and the substantially equal first distance is less than the second distance.

39. The chip packaging structure of claim 38, wherein the plurality of said portions are strip-shaped.

40. The chip packaging structure as described in claim 36, further comprising: A third substrate, wherein the second substrate is bonded to the third substrate via the first conductive bump; as well as A bottom filler layer is provided between the second substrate and the third substrate, wherein a portion of the bottom filler layer is provided between the first annular structure and the third substrate.

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