A semiconductor device including vertically stacked semiconductor dies

Abstract

The present invention is titled "Semiconductor Device Comprising Vertically Stacked Semiconductor Dies". The present invention discloses a semiconductor device comprising one or more stacks of semiconductor dies vertically molded together in a package block. The semiconductor dies may comprise memory dies, or memory dies and controller dies.

Description

BACKGROUND OF THE INVENTION

[0001] The strong growth in the demand for portable consumer electronic devices has driven the demand for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, are increasingly widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, rugged design, as well as their high reliability and large capacity, make such storage devices ideally suited for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular phones, and solid state drives.

[0002] Although many different package configurations are known, flash memory cards can generally be fabricated as system-in-packages (SiPs) or multi-chip modules (MCMs), where multiple die are mounted and interconnected on a substrate with a small footprint. The substrate typically can include a rigid dielectric base having conductive layers etched on one or both sides. Electrical connections are formed between the die and the conductive layers, and the conductive layers provide an electrical lead structure for connecting the die to a host device. Once the electrical connections between the die and the substrate are made, the assembly is typically encapsulated in a molding compound that provides a protective package.

[0003] There is currently a drive to provide high-density memory devices for solid state memory drives. One way to provide high-density memory devices is to stack semiconductor die on top of each other. To provide access to the bond pads on the semiconductor die, the die are stacked such that the die are offset to allow wire bonding for electrical connection, or the die are completely overlapped to allow electrical connection through through-silicon vias (TSVs). Overlapped die using TSV connections provide a high-density memory solution. However, TSV is an expensive process and requires additional components, such as an interposer, to connect to a host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a flowchart for forming a semiconductor device according to an embodiment of the technology of the present invention.

[0005] Figure 2 is a perspective view of a semiconductor die according to an embodiment of the technology of the present invention.

[0006] Figure 3 is a perspective view of a stack of multiple die supported on a first temporary carrier according to an embodiment of the technology of the present invention.

[0007] Figure 4 is supported on Figure 3 a temporary carrier of a stack of semiconductor die with the active surface facing outward.

[0008] Figure 5Is a perspective view of a plurality of die stacks supported on a second temporary carrier according to an embodiment of the technology of the present invention.

[0009] Figure 6 Is a semiconductor die stack supported on Figure 5 a temporary carrier, with the active surface facing downwards.

[0010] Figure 7 Is a cross-sectional edge view of a semiconductor die stack supported on Figure 5 a temporary carrier after encapsulation.

[0011] Figure 8 Is a cross-sectional edge view of an encapsulated semiconductor die stack, where Figure 5 the temporary carrier of

[0012] Figure 9 Is Figure 8 a cross-sectional edge view of an encapsulated semiconductor die stack that is inverted and includes an RDL layer.

[0013] Figure 10 Is a cross-sectional edge view of a completed semiconductor device according to an embodiment of the technology of the present invention.

[0014] Figure 11 Is a flowchart for forming a semiconductor device according to an alternative embodiment of the technology of the present invention.

[0015] Figure 12 Is a cross-sectional edge view of an encapsulated and diced semiconductor die stack according to an embodiment of the technology of the present invention.

[0016] Figure 13 Is a cross-sectional edge view of a diced die stack including through-mold vias according to an embodiment of the technology of the present invention.

[0017] Figure 14 Is a cross-sectional edge view of a completed semiconductor device according to an embodiment of the technology of the present invention.

[0018] Figure 15 Is a perspective view of a plurality of die stacks supported on a first temporary carrier according to an alternative embodiment of the technology of the present invention.

[0019] Figure 16 Is a perspective view of a plurality of die stacks supported on a second temporary carrier according to an alternative embodiment of the technology of the present invention, where the active surface faces downwards.

[0020] Figure 17 Is a cross-sectional edge view of a semiconductor die stack supported on Figure 16 a temporary carrier after encapsulation.

[0021] Figure 18 is a cross-sectional edge view of an encapsulated semiconductor die stack, where Figure 17 the temporary carrier has been removed.

[0022] Figure 19 is Figure 8 a cross-sectional edge view of an encapsulated semiconductor die stack that is inverted and includes an RDL layer.

[0023] Figure 20 is a cross-sectional edge view of a completed semiconductor device according to an embodiment of the technology of the present invention.

[0024] Figure 21 is a cross-sectional edge view of an encapsulated and diced semiconductor die stack according to an alternative embodiment of the technology of the present invention.

[0025] Figure 22 is a cross-sectional edge view of a diced die stack including through-mold vias according to an alternative embodiment of the technology of the present invention.

[0026] Figure 23 is a cross-sectional edge view of a completed semiconductor device according to an embodiment of the technology of the present invention. DETAILED DESCRIPTION

[0027] The technology of the present invention will now be described with reference to the accompanying drawings, which in an embodiment relate to a semiconductor device including semiconductor dies that are stacked with aligned active edges for receiving a redistribution layer (RDL) to provide a high-density fan-out memory device. In an embodiment, the semiconductor device includes a plurality of NAND die stacks (with or without a controller ASIC), where each stack has a planar active sidewall connected to a common RDL on which a ball grid array (BGA) for fan-out is provided.

[0028] In another embodiment, the technology of the present invention relates to a semiconductor device (with or without a controller ASIC) that is diced into packages to include a single NAND die stack, where the BGA can be connected to an ASIC (or other) semiconductor bond pad through through-mold vias (TMVs) formed through the molding compound.

[0029] It should be understood that the present invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. In fact, the present invention is intended to cover alternatives, modifications, and equivalents of these embodiments, all of which are included within the scope and spirit of the invention as defined by the appended claims. Additionally, in the following detailed description of the present invention, numerous specific details are given in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention can be practiced without such specific details.

[0030] As used herein, the terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" and their forms are used herein by way of example only and for illustrative purposes, and are not intended to limit the description of the technology, as the items referenced may be exchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "about" mean that the specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ±2.5% of a given dimension.

[0031] Reference will now be made Figure 1 and Figure 11 to the flowcharts of Figures 2 to 10 and [[ID= and the views of ​ to explain embodiments of the present technology. In step 50, a semiconductor wafer (not shown) can be processed into a plurality of semiconductor die 102, a perspective view of one of the plurality of semiconductor die being as shown in

[0032] The semiconductor die 102 can undergo various processes in step 50 to form an integrated circuit on and / or within a first major surface 104 of the semiconductor die 102. After forming the integrated circuit, internal electrical connections can be formed within the semiconductor die 102 to connect the integrated circuit to bond pads 108 on the first major surface 104 of the semiconductor die 102. ​ The electrical interconnections on or within the semiconductor die 102 can further electrically couple the bond pads 108 to edge pads 110. The edge pads 110 can be formed on the first major surface 104 and can extend to an active edge 112 of the semiconductor die 102, which extends generally perpendicular to the first major surface 104. As shown in

[0033] ​ The patterns and quantities of the bonding pads 108 and edge pads 110 shown are by way of example only. In additional embodiments, there may be more or fewer bonding pads 108 and / or edge pads 110 in other patterns. The bottom surface of the die 102 (opposite the main surface 104) may include a die attach film (DAF) layer 114 to enable stacking of semiconductor dies 102.

[0034] The semiconductor die 102 may be, for example, a flash memory die such as a 2D NAND flash memory or 3D BiCS (bit cost scaling), V-NAND, or other 3D flash memory, but other types of dies 102 may be used. These other types of semiconductor dies include but are not limited to controller dies (such as ASICs) or RAMs (such as SDRAM, DDR SDRAM, LPDDR, and GDDR).

[0035] In step 52, one or more semiconductor dies 102 may be stacked on the first temporary carrier 116. As ​ shown, multiple such die stacks 120 may be formed on the first temporary carrier 116. ​ The number of stacks 120 shown on the carrier 116 in [reference] is exemplary only and may vary in additional embodiments. The temporary carrier 116 may be, for example, metal, glass, or silicon. The DAF layer 114 cured to the b-stage may be used to stack individual semiconductor dies 102 on top of each other. The bottommost die 102 of each stack 120 may be adhered to the temporary carrier 116 using the DAF layer 114 of the bottommost die or a temporary adhesive. Such a temporary adhesive may be a laser / UV release type film, a thermal release type film, or a mechanical release type film to allow easy disassembly of the die stack 120, as will be described below.

[0036] As ​ shown in the perspective view of [reference], the semiconductor dies 102 may be mounted in corresponding stacks 120 with the main surface 104 facing up, i.e., away from the temporary carrier 116. The number of dies 102 shown in the stack 120 is by way of example only, and embodiments may include different numbers of semiconductor dies, including, for example, 1, 2, 4, 8, 16, 32, 64, or 128 dies. Other numbers of dies may be present in additional embodiments. The active edges 112 of each semiconductor die 102 are aligned with each other to form a planar active sidewall 122. The edge pads 112 of each corresponding die 102 are exposed at the planar active sidewall 122.

[0037] In step 54, the die stack 120 may be removed from the first temporary carrier (by applying laser / UV light, heat, and / or force, depending on the temporary adhesive) and mounted on the second temporary carrier 126. As​ and ​ As shown in ​ , the die stack 120 can be mounted on the second temporary carrier 126, where the active sidewall 122 faces downward against the second temporary carrier 126. The die 102 in the stack 120 can be heated and / or a force can be applied against one or more of the dies 102 to ensure that the die lies flat against the second temporary carrier 126 to ensure the planarity of the active sidewall 122.

[0038] ​ The number of stacks 120 shown on the second temporary carrier 126 in ​ is merely exemplary and can vary in additional embodiments. The second temporary carrier 126 can be, for example, metal, glass, or silicon and can be or can not be the same material as the first temporary carrier 116. A temporary adhesive (such as, for example, a laser / UV release film, a thermal release film, or a mechanical release film) can be used to adhere the die stack 120 to the second temporary carrier 126 to allow for easy removal of the die stack 120, as will be described hereinafter.

[0039] In step 60, the die stack 120 can then be encapsulated in a molding compound 130, as shown in the cross-sectional edge view of ​ . The molding compound 130 can include, for example, solid epoxy resin, phenolic resin, fused silica, crystalline silica, carbon black, and / or metal hydroxide. Other molding compounds are contemplated. The molding compound can be applied by various known processes, including by compression molding, FFT (no-flow thin) molding, transfer molding, or injection molding techniques. ​ Once the molding compound 130 has hardened, the second temporary carrier 126 can be removed in step 64, as indicated in the cross-sectional edge view of ​ . As described above, the second temporary carrier 126 can be removed by applying laser / UV light, heat, and / or force to the temporary adhesive 128 of the second carrier 126.

[0040] After step 64, the encapsulated die stack 120 can be inverted such that the active sidewall 122 of the stack 120 (previously mounted against the second temporary carrier 126) faces upward. In step 70, a redistribution layer (RDL) 134 can be formed above the active sidewall 122 of each die stack 120 in the molding compound 130, as shown in the cross-sectional edge view of ​ . The RDL 134 can have a first surface 136 that has a pattern of solder bumps that are configured to physically and electrically mate with some or all of the exposed edge pads 112 in the active sidewall 122. The first surface 136 of the RDL 134 can be adhered to the active sidewall 122 through an adhesive layer on the first surface 136 and / or by coupling the solder bumps to the edge pads 112. ​ ​

[0041] After step 64, the encapsulated die stack 120 can be inverted such that the active sidewall 122 of the stack 120 (previously mounted against the second temporary carrier 126) faces upward. In step 70, a redistribution layer (RDL) 134 can be formed above the active sidewall 122 of each die stack 120 in the molding compound 130, as shown in the cross-sectional edge view of ​ . The RDL 134 can have a first surface 136 that has a pattern of solder bumps that are configured to physically and electrically mate with some or all of the exposed edge pads 112 in the active sidewall 122. The first surface 136 of the RDL 134 can be adhered to the active sidewall 122 through an adhesive layer on the first surface 136 and / or by coupling the solder bumps to the edge pads 112. ​ The RDL 134 can have a first surface 136 that has a pattern of solder bumps that are configured to physically and electrically mate with some or all of the exposed edge pads 112 in the active sidewall 122. The first surface 136 of the RDL 134 can be adhered to the active sidewall 122 through an adhesive layer on the first surface 136 and / or by coupling the solder bumps to the edge pads 112.

[0042] RDL 134 may also include an internal pattern of metal interconnects 138 that couples the pattern of solder bumps on the first surface 136 to the pattern of contact pads 140 distributed on the second surface 142 of the RDL 134. The RDL 134 redistributes the edge pads 112 electrically to a fan-out pattern of contact pads 140 on the second surface 142. The contact pads 140 may be distributed on the second surface 142 of the RDL 134 in any of a variety of patterns.

[0043] In step 74, as ​ shown, a pattern of solder balls 146 may be attached to the contact pads 140 on the second surface 142 of the RDL 134 to form the completed semiconductor device 150. The solder balls 144 may be used to solder the semiconductor device 150 to a host device (not shown), such as a printed circuit board.

[0044] The semiconductor device 150 provides a high-density array of semiconductor dies vertically mounted in a molded block. Such semiconductor devices 150 may ideally be used as solid-state drives, thereby providing a large storage capacity in a small form factor. As described above, the number of dies 102 in each die stack 120 and the number of die stacks 120 provided in the molded block may vary depending on the memory storage requirements. In an alternative embodiment, the semiconductor device 150 may be used in applications other than solid-state drives.

[0045] In the above-described embodiment, the semiconductor device 150 includes a plurality of die stacks 120 in a molded block. In another embodiment, the die stacks 120 may be diced after packaging to provide a semiconductor device including individually packaged die stacks. A flowchart of ​ and a view of ​ will now be referred to to explain such an embodiment.

[0046] In ​ the embodiment, steps 50 - 70 are repeated to provide a molded block of packaged die stacks 120 including the RDL 134 (as ​ shown). In step 80, the molded block of packaged die stacks 120 may be diced into molded blocks 154 each including an individual die stack 120, as ​ shown. In an embodiment, solder balls may thereafter be formed on the contact pads 140 on the second surface 142 of the RDL 134.

[0047] However, in another embodiment, the individual blocks 154 may be rotated 90° such that the active sidewalls 122 and the RDL 134 face the side, as ​As shown. Thereafter, in step 82, a through-mold via (TMV) 156 can be formed downward through the molding compound 130 to expose the contact pads 108 on the edge die 102a at the top of the block 154 (from ​ the perspective view). The TMV can be formed mechanically, for example, with a drill bit or optically using a laser.

[0048] In step 84, then solder balls 158 can be mounted to the die bonding pads 108 of the edge die 102a, as ​ shown, to form the completed semiconductor device 160. The solder balls 158 can be used to solder the semiconductor device 160 to a host device (not shown), such as a printed circuit board. The RDL 134 can also be used to electrically couple the dies 102 in the stack 120 other than the edge die 102a to the solder balls 158.

[0049] Forming the solder balls on this side of the separate block 154 has certain advantages. For example, with the thin profile of the dies 102 in a given die stack 120, forming the solder balls on top of the stacked dies provides a thin-height package. In one example, the device 160 can have a length of 20 mm, a width of 16 mm, and a height of 1.0 mm. This is close to the current memory device form factor used in mobile phones and other devices. However, as noted, in alternative embodiments, the solder balls can be formed on the active sidewalls 122.

[0050] The semiconductor device 160 provides a high-density array of semiconductor dies vertically mounted in a molded block. As described above, the number of dies 102 in each semiconductor device 160 can vary depending on the memory storage requirements. The semiconductor device 160 can be used in a variety of applications, including, for example, solid-state drives, mobile phones, computers, cameras, etc.

[0051] In an embodiment, the semiconductor devices 150, 160 can include only memory semiconductor dies 102. However, according to additional aspects of the present inventive techniques, controller dies and / or other components can be incorporated into the semiconductor devices of the present inventive techniques to provide a complete system on a chip. Now reference will be made to ​ describe such embodiments.

[0052] ​ is a cross-sectional edge view of a semiconductor die stack 220 stacked on a first temporary carrier 216 through a temporary adhesive 218. Each die stack 220 can include semiconductor dies 202, which include a plurality of memory dies 202a and a controller die 202b (such as an ASIC). The controller die 202b is shown at the top of the die stack 220 (from ​Perspective view), but in other embodiments, the controller die 202b can be located at other positions within the die stack 220. As described above, each die stack 220 includes an active sidewall 222 that includes exposed edge bond pads 112.

[0053] In ​ , the die stacks 220 have been removed from the first carrier 216 by dissolving the temporary adhesive 218, rotated 90° so that the active sidewalls 222 face downward (from ​ Perspective view) and mounted on the second carrier 226 by a temporary adhesive 228. In addition to the die stacks 220, various electronic components 232 can also be mounted on the temporary carrier 218. These electronic components 232 can include, for example, passive components such as capacitors, resistors, and inductors. In other embodiments, the electronic components 232 can be other components.

[0054] As ​ Shown in the cross-sectional edge view of, the die stacks 220 can then be encapsulated in the molding compound 230 as described above. Once the molding compound 230 has hardened, the second temporary carrier 226 can be removed, as ​ Indicated by the cross-sectional edge view of. As described above, the second temporary carrier 226 can be removed by applying laser / UV light, heat, and / or force to the temporary adhesive 228 of the second carrier 226.

[0055] Next, the encapsulated die stacks 220 can be inverted so that the active sidewalls 222 face upward, as

[0056] ​ Shown. Then, an RDL 234 can be formed on the active sidewalls 222 of each die stack 220 in the molding compound 230. As described above, the RDL 234 can include a first surface 236, mounted to the molding block, including solder bumps that mate with the edge pads 112. The solder bumps are connected to contact pads 240 in the second surface 242 by metal interconnects 238. As ​ Shown, solder balls 246 can then be attached to the contact pads 240 on the second surface 242 of the RDL 134 to form the completed semiconductor device 250. The solder balls 144 can be used to solder the semiconductor device 250 to a host device (not shown), such as a printed circuit board.

[0057] The semiconductor device 250 provides a high-density array of semiconductor dies vertically mounted in a molded block. Such semiconductor devices 250 can ideally be used as solid-state drives, thereby providing a large storage capacity in a small form factor. As described above, the number of dies 202 in each die stack 220 and the number of die stacks 220 provided in the molded block can vary depending on the memory storage requirements. In additional embodiments, the semiconductor device 250 can be used in applications other than solid-state drives.

[0058] ​ The illustrated embodiment includes a plurality of semiconductor die stacks 220 mounted in a molded block, where each die stack includes a memory die 202a and a controller die 202b. In another embodiment, a single stack 220 can include a memory die 202a and a controller die 202b, and the remaining stacks 220 all include memory dies 202a. In such an embodiment, a single controller die 202b in the molded block serves as the controller for all the memory dies in all the stacks 220.

[0059] Instead of being a block for a plurality of die stacks 220, the semiconductor device of the present inventive technique can be divided into semiconductor devices each including a single molded die stack 220. ​ An encapsulated block divided into separate molded blocks 254 is shown, each separate molded block including a separate die stack 220. In an embodiment, solder balls can then be formed on the contact pads 140 on the second surface 242 of the RDL 234.

[0060] However, in another embodiment, the separate block 254 can be rotated 90°, such that the active sidewall 222 and the RDL 234 face the side, as ​ shown. Thereafter, the TMV 256 can be formed downward through the molding compound 230 to expose contact pads 108, for example, on the controller die 202b, at the top of the block 254 (from ​ the perspective view). Next, solder balls 258 can then be mounted to the die bond pads 108 of the controller die 202b, as ​ shown, to form the completed semiconductor device 260. The solder balls 258 can be used to solder the semiconductor device 260 to a host device (not shown), such as a printed circuit board. The RDL 234 can also be used to electrically couple the dies 202 in the die stack 220, other than the edge die 102a, to the solder balls 258.

[0061] Semiconductor device 260 provides a high-density array of semiconductor dies vertically mounted in a molded block. As described above, the number of dies 202 in each semiconductor device 260 can vary depending on the memory storage requirements. Semiconductor device 260 can be used in a variety of applications, including, for example, solid-state drives, mobile phones, computers, cameras, etc.

[0062] In summary, examples of the inventive technology relate to semiconductor devices, including: a plurality of semiconductor die stacks molded together in a package block, each semiconductor die stack including: two or more semiconductor dies, each semiconductor die including: a plurality of bond pads on a first surface of the die, and a plurality of edge pads formed in or on the first surface and extending to an active edge of the semiconductor die adjacent the first surface, the plurality of edge pads being electrically coupled to the plurality of bond pads, the active edges of two or more semiconductor dies being aligned to form an active sidewall; a redistribution layer formed on the active sidewall of the plurality of semiconductor die stacks, the redistribution layer electrically redistributing the positions of the edge pads to fan-out positions on the surface of the redistribution layer; and a plurality of solder balls electrically coupled to the fan-out positions of the redistribution layer and configured to electrically connect the semiconductor device to a host device.

[0063] In another example, the inventive technology relates to semiconductor devices, including: a semiconductor die stack including: two or more semiconductor dies, each semiconductor die including: a plurality of bond pads on a first surface of the die, and a plurality of edge pads formed in or on the first surface and extending to an active edge of the semiconductor die adjacent the first surface, the plurality of edge pads being electrically coupled to the plurality of bond pads, the active edges of two or more semiconductor dies being aligned to form an active sidewall; a molding compound encapsulating the semiconductor die stack into a molded block, wherein the active sidewall is exposed; a redistribution layer formed on the active sidewall of the semiconductor die stack, the redistribution layer electrically coupling the die bond pads of two or more semiconductor dies; and a plurality of solder balls formed in through-mold vias through the surface of the molding compound and electrically coupled to the die bond pads of the semiconductor dies of the semiconductor die stack, the solder balls being configured to electrically connect the semiconductor device to a host device.

[0064] In another example, the technology of the present invention relates to a semiconductor device, comprising: a semiconductor die stack, comprising: two or more semiconductor dies, each semiconductor die comprising: bonding pad means for electrically connecting an integrated circuit in the semiconductor die to a first surface of the semiconductor die, and edge pad means for electrically coupling the bonding pad means to an active edge of the semiconductor die adjacent to the first surface, the active edges of the two or more semiconductor dies being aligned to form an active sidewall; a molding compound that encapsulates the semiconductor die stack into a molded block, wherein the active sidewall is exposed; redistribution means formed on the active sidewall of the semiconductor die stack for electrically coupling die bonding pads of two or more semiconductor dies; and conductive ball means formed in a through-mold via through the surface of the molding compound and electrically coupled to the die bonding pads of the semiconductor dies of the semiconductor die stack for electrically connecting the semiconductor device to a host device.

[0065] The foregoing specific embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen in order to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments with various modifications suited to the particular use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of semiconductor die stacks, the plurality of semiconductor die stacks being molded together in a package block, each semiconductor die stack comprising: Two or more semiconductor dies, each semiconductor die comprising: A plurality of bond pads on a first surface of the die, and A plurality of edge pads formed in or on the first surface and extending to an active edge of the semiconductor die adjacent to the first surface, the plurality of edge pads being spaced apart from the plurality of bond pads on the first surface, and electrical interconnections on or in the semiconductor die electrically coupling the plurality of edge pads to the plurality of bond pads, the active edges of the two or more semiconductor dies being aligned to form an active sidewall; A redistribution layer formed on the active sidewall of the plurality of semiconductor die stacks, the redistribution layer electrically redistributing the positions of the edge pads to fan-out positions on a surface of the redistribution layer; and A plurality of solder balls electrically coupled to the fan-out positions of the redistribution layer and configured to electrically connect the semiconductor device to a host device.

2. The semiconductor device according to claim 1, wherein the plurality of semiconductor die stacks are horizontally stacked on a first temporary carrier and then vertically stacked on a second temporary carrier.

3. The semiconductor device according to claim 2, wherein the plurality of semiconductor die stacks are encapsulated in a molding compound into the package block on the second temporary carrier.

4. The semiconductor device according to claim 1, wherein each stack of the plurality of semiconductor die stacks comprises a plurality of flash memory dies.

5. The semiconductor device according to claim 4, wherein each stack of the plurality of semiconductor die stacks further comprises a controller die that controls the plurality of flash memory dies in each stack of the plurality of stacks.

6. The semiconductor device according to claim 4, wherein one stack of the plurality of semiconductor die stacks further comprises a single controller die that controls the plurality of flash memory dies in all stacks of the plurality of stacks.

7. The semiconductor device according to claim 1, wherein each stack of the plurality of semiconductor die stacks further comprises an electronic component.

8. The semiconductor device according to claim 7, wherein the electronic component comprises a passive component.

9. A semiconductor device, comprising: A semiconductor die stack, comprising: Two or more semiconductor dies, each semiconductor die comprising: A plurality of bond pads on a first surface of the die, and A plurality of edge pads formed in or on the first surface and extending to an active edge of the semiconductor die adjacent to the first surface, the plurality of edge pads being spaced apart from the plurality of bond pads on the first surface, and electrical interconnections on or in the semiconductor die electrically coupling the plurality of edge pads to the plurality of bond pads, the active edges of the two or more semiconductor dies being aligned to form an active sidewall; A molding compound encapsulating the semiconductor die stack into a molded block, with the active sidewall exposed; A redistribution layer formed on the active sidewall of the semiconductor die stack, the redistribution layer electrically coupling the die bond pads of the two or more semiconductor dies; and A plurality of solder balls formed in through-mold vias passing through the surface of the molding compound and electrically coupled to the die bond pads of the semiconductor dies of the semiconductor die stack, the solder balls being configured to electrically connect the semiconductor device to a host device.

10. The semiconductor device according to claim 9, wherein the semiconductor device is diced from a package block including a plurality of such semiconductor devices.

11. The semiconductor device according to claim 9, wherein the two or more semiconductor dies in the semiconductor die stack are horizontally stacked on a first temporary carrier and then vertically stacked on a second temporary carrier.

12. The semiconductor device according to claim 11, wherein the semiconductor die stack is encapsulated in a molding compound on the second temporary carrier.

13. The semiconductor device according to claim 9, wherein the semiconductor die stack includes a plurality of flash memory dies.

14. The semiconductor device according to claim 13, wherein the semiconductor die stack further includes a controller die for controlling the plurality of flash memory dies.

15. The semiconductor device according to claim 9, wherein the plurality of solder balls are soldered to the die bond pads of the controller die of the two or more semiconductor dies.

16. The semiconductor device according to claim 9, wherein the plurality of solder balls are soldered to the die bond pads of the flash memory die of the two or more semiconductor dies.

17. A semiconductor device, comprising: A semiconductor die stack, including: Two or more semiconductor dies, each semiconductor die including: Bond pad means for electrically connecting an integrated circuit in the semiconductor die to a first surface of the semiconductor die, and Edge pad means for electrically coupling the bond pad means to an active edge of the semiconductor die adjacent to the first surface, the edge pad means being spaced apart from the bond pad means on the first surface, and electrical interconnections on or in the semiconductor die electrically coupling the edge pad means to the bond pad means, the active edges of the two or more semiconductor dies being aligned to form an active sidewall; A molding compound that encapsulates the semiconductor die stack into a molded block, with the active sidewalls exposed; A redistribution device formed on the active sidewalls of the semiconductor die stack for electrically coupling the die bond pads of two or more semiconductor dies; and A conductive ball device formed in a through-mold via through the surface of the molding compound and electrically coupled to the die bond pads of the semiconductor dies of the semiconductor die stack for electrically connecting the semiconductor device to a host device.

18. The semiconductor device according to claim 17, wherein the semiconductor die stack includes a plurality of flash memory dies.

19. The semiconductor device according to claim 18, wherein the semiconductor die stack further includes a controller die for controlling the plurality of flash memory dies.

20. The semiconductor device according to claim 17, wherein the conductive ball device is soldered to the die bond pads of the controller die of the two or more semiconductor dies.

21. The semiconductor device according to claim 17, wherein the conductive ball device is soldered to the die bond pads of the flash memory dies of the two or more semiconductor dies.

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