Integrated circuits, power circuits

Abstract

The integrated circuit of the present invention switches a transistor that controls the inductor current based on an inductor current flowing through an inductor to which a voltage from a rectifier circuit that rectifies an AC voltage is applied and an output voltage generated based on the AC voltage. The integrated circuit includes: a comparison circuit that compares the current value of the inductor current with a first current value; and a timing circuit that outputs a first signal indicating that the AC voltage is cut off, based on a first comparison result indicating that the current value of the inductor current is smaller than the first current value, if it is detected that the state in which the current value of the inductor current is smaller than the first current value continues for a specified time.

Description

Technical Field

[0001] The invention relates to an integrated circuit and a power supply circuit. Background Art

[0002] An AC-DC converter is a circuit that generates an output voltage of a target level based on an AC voltage, but generally, if the input AC voltage is cut off, the output voltage decreases. In such a case, since the load of the AC-DC converter may not operate normally, a detection circuit is sometimes provided in the AC-DC converter to detect that the AC voltage has been cut off (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2006-223070 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] Furthermore, a detection circuit for detecting that the AC voltage has been cut off is generally composed of a large number of discrete components, which increases the cost of the AC-DC converter.

[0008] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an integrated circuit capable of detecting that an AC voltage is cut off at a low cost.

[0009] Technical solutions adopted to solve technical problems

[0010] A first method of the present invention for solving the above-mentioned problem is an integrated circuit that switches a transistor that controls the inductor current based on an inductor current flowing through an inductor to which a voltage from a rectifier circuit that rectifies an AC voltage is applied and an output voltage generated based on the AC voltage, and the integrated circuit is characterized in that it includes: a comparison circuit that compares the current value of the inductor current with a first current value; and a timing circuit that outputs a first signal indicating that the AC voltage is cut off when it is detected that the current value of the inductor current is smaller than the first current value for a predetermined time based on a first comparison result indicating that the current value of the inductor current is smaller than the first current value.

[0011] In addition, a second embodiment of the present invention is a power supply circuit that generates an output voltage based on a specified AC voltage, and the power supply circuit is characterized in that it includes: a rectifier circuit that rectifies the specified AC voltage; an inductor to which a voltage from the rectifier circuit is applied; and an integrated circuit that drives a transistor that controls the inductor current based on an inductor current flowing through the inductor and the output voltage, and the integrated circuit includes: a comparison circuit that compares the current value of the inductor current with a first current value; and a timing circuit that outputs a first signal indicating that the AC voltage is cut off when the current value of the inductor current is smaller than the first current value for a specified time based on a first comparison result indicating that the current value of the inductor current is larger than the first current value.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide an integrated circuit capable of detecting that an AC voltage is cut off at low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a diagram showing an example of the AC-DC converter 10 .

[0015] Figure 2 This is a diagram showing an example of the power factor improving IC 25 .

[0016] Figure 3 This is a diagram for explaining the operation of the power factor improving IC 25.

[0017] Figure 4 It is a diagram for explaining the operation of the AC-DC converter 10 when an AC voltage is input.

[0018] Figure 5 This is a diagram for explaining the operation of the power factor improvement IC 25 when the AC voltage is cut off and restored.

[0019] Figure 6 This is a diagram for explaining the operation of the power factor improvement IC 25 when the AC voltage is cut off and restored. DETAILED DESCRIPTION

[0020] Cross-reference to related applications

[0021] This application claims priority based on Japanese Patent Application No. 2018-236164 filed on December 18, 2018, and cites the contents thereof.

[0022] At least the following matters are clear from the description of this specification and the drawings.

[0023] ======Present Implementation Method======

[0024] Figure 1 1 is a diagram showing a configuration of an AC-DC converter 10 as one embodiment of the present invention. The AC-DC converter 10 is a step-up chopper type power supply circuit that generates an output voltage Vout of a target level from an AC voltage Vac of a commercial power supply.

[0025] The load 11 is, for example, a DC-DC converter or an electronic device that operates with a DC voltage, and the microcomputer 12 is, for example, a control circuit that reduces the power consumption of the load 11 when the AC voltage Vac is cut off.

[0026] <<<Overview of AC-DC Converter 10>>>

[0027] The AC-DC converter 10 includes a full-wave rectifying circuit 20 , capacitors 21 , 22 , and 34 , an inductor 23 , a diode 24 , a power factor improving IC 25 , an NMOS transistor 26 , and resistors 30 to 33 .

[0028] The full-wave rectifying circuit 20 performs full-wave rectification on the applied predetermined AC voltage Vac, and inputs the voltage Vrec to the capacitor 21 and the inductor 23. The AC voltage Vac is, for example, 100 to 240 V and has a frequency of 50 to 60 Hz.

[0029] The capacitor 21 smoothes the voltage Vrec, and the capacitor 22 forms a step-up chopper circuit together with the inductor 23, the diode 24, and the NMOS transistor 26. Therefore, the charging voltage of the capacitor 22 becomes a DC output voltage Vout. The output voltage Vout is, for example, 400V.

[0030] The power factor improvement IC 25 is an integrated circuit that improves the power factor of the AC-DC converter 10 and controls the switching of the NMOS transistor 26 so that the level of the output voltage Vout becomes a target level (for example, 400V). Specifically, the power factor improvement IC 25 drives the NMOS transistor 26 based on the inductor current IL flowing through the inductor 23 and the output voltage Vout. In addition, the details of the power factor improvement IC 25 will be described later, but the power factor improvement IC 25 is provided with terminals CS, FB, CONT, COMP, and OUT. In addition, in addition to the above-mentioned five terminals CS, FB, CONT, COMP, and OUT, the power factor improvement IC 25 is provided with terminals, but they are omitted here for convenience.

[0031] The NMOS transistor 26 is a transistor for controlling the power to the load 11 of the AC-DC converter 10. In addition, in the present embodiment, although the NMOS transistor 26 is set to be a MOS (Metal Oxide Semiconductor) transistor, it is not limited to this. The NMOS transistor 26 can be any transistor that can control power, for example, it can also be a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor). In addition, the gate electrode of the NMOS transistor 26 is connected to be driven by a signal from the terminal OUT. In addition, in the present embodiment, in order to suppress switching noise, etc., a resistor 35, a resistor 36 and a diode 37 are connected between the gate electrode of the NMOS transistor 26 and the terminal OUT.

[0032] The resistors 30 and 31 constitute a voltage dividing circuit for dividing the output voltage Vout, and generate a feedback voltage Vfb used when switching the NMOS transistor 26. The feedback voltage Vfb generated at the node where the resistors 30 and 31 are connected is applied to the terminal FB.

[0033] The resistor 32 is a resistor for detecting the inductor current IL, one end of which is connected to the source electrode of the NMOS transistor 26, and the other end of which is connected to the terminal CS. In addition, in the present embodiment, the voltage representing the inductor current IL input to the terminal CS is set to the voltage Vcs. The voltage Vcs can be, for example, a voltage applied to the terminal CS from an inverting amplifier circuit (not shown) that inverts the voltage generated at the resistor 32, using the source electrode of the grounded NMOS transistor 26 as a reference (0V). In this case, as the inductor current IL increases, the voltage Vcs applied to the terminal CS increases. Such positive and negative inversions can also be implemented inside the power factor improvement IC 25.

[0034] Although the details will be described later, the resistor 33 and the capacitor 34 are elements for phase compensation of the power factor improvement IC 25 which is feedback controlled, and are provided between the terminal COMP and the ground.

[0035] <<<Structure of power factor improving IC25>>>.

[0036] Figure 2 2 is a diagram showing an example of the structure of the power factor improvement IC 25. The power factor improvement IC 25 is configured to include a drive signal generation circuit 50, a drive circuit 51, a comparator 52, and a detection circuit 53. Figure 2 For convenience, the terminals are drawn on the Figure 1For example, the terminal CONT is placed on the same side as the terminal OUT, but the wiring and components connected to each terminal are placed on the same side as the terminal OUT. Figure 1 and Figure 2 is the same.

[0037] <<Drive Signal Generating Circuit 50 >>

[0038] The drive signal generating circuit 50 is a circuit that generates a drive signal Vq1 for turning on and off the NMOS transistor 26 based on the voltage Vcs indicating the inductor current IL and the feedback voltage Vfb. The drive signal generating circuit 50 includes comparators 70 and 77, a delay circuit 71, a pulse circuit 72, an on-timer circuit 73, OR gate circuits 74 and 78, an error amplifier circuit 75, an oscillation circuit 76, and an SR flip-flop 79.

[0039] The comparator 70 is a circuit for detecting whether the current value of the inductor current IL is approximately zero. Specifically, the comparator 70 compares the voltage Vcs applied to the terminal CS with the reference voltage Vref1 (for example, several mV) corresponding to the current value Ia (second current value) slightly larger than zero, for example, several mA, to detect whether the current value of the inductor current IL is approximately zero (hereinafter, for convenience, "approximately zero" is simply referred to as zero). In addition, although the details will be described later, in this embodiment, if the voltage Vcs is smaller than the reference voltage Vref1, a high level (hereinafter referred to as H level) signal Vz indicating that the inductor current IL is zero is output from the comparator 70.

[0040] When the H-level signal Vz is output from the comparator 70 , the delay circuit 71 delays the signal Vz by a predetermined time and outputs the signal.

[0041] When the H-level signal Vz is output from the delay circuit 71 , the pulse circuit 72 (first pulse circuit) outputs the H-level pulse signal Vp1 (first pulse signal).

[0042] The start timer circuit 73 (second pulse circuit) outputs a pulse signal Vp2 (second pulse signal) for turning on the NMOS transistor 26 when the power factor improvement IC 25 is started or when the AC voltage Vac is cut off and the pulse signal Vp1 is not output. Specifically, when the pulse signal Vp1 is not output during a predetermined period, the pulse signal Vp2 of the H level is output every predetermined period.

[0043] The OR circuit 74 calculates the logical sum of the pulse signals Vp1 and Vp2 and outputs the result. Therefore, in the present embodiment, the pulse signal Vp1 or the pulse signal Vp2 is output from the OR circuit 74 as the pulse signal Vp3.

[0044] The error amplifier circuit 75 is a circuit that amplifies the error between the feedback voltage Vfb applied to the terminal FB and the predetermined reference voltage Vref0. In addition, the reference voltage Vref0 is a voltage determined according to the output voltage Vout of the target level. In addition, the resistor 33 and the capacitor 34 for phase compensation are connected between the output of the error amplifier circuit 75 and the ground via the terminal COMP. Here, the voltage of the node where the output of the error amplifier circuit 75 is connected to the terminal COMP is set to the voltage Ve.

[0045] Every time the high-level pulse signal Vp3 is input, the oscillation circuit 76 outputs a ramp wave Vr whose amplitude gradually increases.

[0046] The comparator 77 compares the magnitude of the voltage Ve with the ramp wave Vr, and outputs a signal Vc1 as a comparison result. Here, the voltage Ve is applied to the inverting input terminal of the error amplifier circuit 75, and the ramp wave Vr is applied to the non-inverting input terminal of the error amplifier circuit 75. Therefore, when the level of the ramp wave Vr is lower than the level of the voltage Ve, the signal Vc1 becomes a low level (hereinafter referred to as an L level), and when the level of the ramp wave Vr becomes higher than the level of the voltage Ve, the signal Vc1 becomes an H level.

[0047] The OR circuit 78 calculates and outputs the logical sum of the signal Vc1 and a signal Voc (described later) at an H level indicating the occurrence of an overcurrent. Therefore, the signal Vc1 at an H level or the signal Voc is output from the OR circuit 78 as a pulse signal Vp4.

[0048] The input signal Vp3 is input to the S input of the SR flip-flop 79 (drive signal output circuit), and the input signal Vp4 is input to the R input. Therefore, when the signal Vp3 becomes H level, the Q output of the SR flip-flop 79, that is, the drive signal Vq1 becomes H level. On the other hand, when the signal Vp4 becomes H level, the drive signal Vq1 becomes L level.

[0049] <<Drive circuit 51>>

[0050] The driving circuit 51 is a buffer circuit that drives the NMOS transistor 26 based on the driving signal Vq1. Specifically, the driving circuit 51 drives the NMOS transistor 26 having a large gate capacitance, etc., using a signal Vdr having the same logic level as the input signal. In addition, the driving circuit 51 turns on the NMOS transistor 26 based on the driving signal Vq1 at an H level, and turns off the NMOS transistor 26 based on the driving signal Vq1 at an L level.

[0051] <<Comparator 52>>

[0052] The comparator 52 is a circuit for detecting whether the inductor current IL is in an overcurrent state by comparing the voltage Vcs with the reference voltage Vref2. In addition, the so-called "overcurrent" refers to a state in which the inductor current IL becomes a current value Ib (for example, a current value of 90% of the current value allowed in the inductor 23 or the NMOS transistor 26). Therefore, in this embodiment, if the inductor current IL exceeds the current value Ib, the level of the voltage Vref2 is determined so that the voltage Vcs becomes larger than the reference voltage Vref2. In addition, if it is an overcurrent state and the voltage Vcs becomes larger than the reference voltage Vref2, the comparator 52 changes the voltage Voc to the H level. As a result, the drive signal Vq1 becomes the L level, and as a result, the NMOS transistor 26 is turned off.

[0053] <<Detection circuit 53>>

[0054] The detection circuit 53 is a circuit for detecting whether the AC voltage Vac is in a cut-off state. Here, the so-called "state in which the AC voltage Vac is cut off" refers to a state in which, for example, the AC voltage Vac is not supplied to the AC-DC converter 10 and is not applied to the full-wave rectifier circuit 20. The detection circuit 53 is configured to include a comparator 100 and a timing circuit 101.

[0055] The comparator 100 is a circuit that compares the current value of the inductor current IL with the current value Ic based on the magnitude relationship between the voltage Vcs and the voltage Vref3. Here, the "current value Ic (first current value)" is, for example, a positive current value (for example, several tens of mA) that is larger than the current value Ia detected by the comparator 70 and close to zero. In addition, the signal Vc2 output from the comparator 100 as a comparison result becomes an L level when the current value of the inductor current IL is larger than the current value Ic, and becomes an H level when it is smaller than the current value Ic.

[0056] The timing circuit 101 is a circuit for timing the state in which the current value of the inductor current IL is smaller than the current value Ic. Then, if the state in which the current value of the inductor current IL is smaller than the current value Ic continues for a predetermined time Tx, the timing circuit 101 outputs an H-level signal Vd (first signal) indicating that the AC voltage Vac is cut off. On the other hand, when the AC voltage Vac is not cut off, that is, the predetermined AC voltage Vac is supplied to the AC-DC converter 10 and applied to the full-wave rectifier circuit 20, the timing circuit 101 outputs an L-level signal Vd (second signal).

[0057] Here, the "predetermined time Tx" refers to a time set to determine whether the AC voltage Vac is cut off based on the state in which the current value of the inductor current IL is smaller than the current value Ic. Therefore, when the current consumption of the load 11 is a predetermined value, the "predetermined time Tx" is set to be longer than the period in which the inductor current IL becomes smaller than the current value Ic when the AC voltage Vac is applied to the full-wave rectifier circuit 20 and the NMOS transistor 26 is turned on in the half cycle of the AC voltage Vac, and shorter than the half cycle of the AC voltage Vac. For example, when the half cycle of the AC voltage Vac is 10 ms, the predetermined time Tx is set to 1.5 ms, that is, about 10 to 20% of the half cycle.

[0058] The timing circuit 101 includes a D flip-flop 110 , a counter 111 , and a signal output circuit 112 .

[0059] The signal Vc2 is input to the D input of the D flip-flop 110 (holding circuit), and the drive signal Vq1 is inverted and input to the C input of the D flip-flop 110 (holding circuit). Therefore, when the D input is at the H level at the falling timing (timing for turning the NMOS transistor 26 from on to off) when the drive signal Vq1 changes to the L level, that is, when the inductor current IL is smaller than the current value Ic, the Q output changes to the H level. On the other hand, when the D input is at the L level at the timing when the drive signal Vq1 changes to the L level, that is, when the inductor current IL is larger than the current value Ic, the Q output changes to the L level.

[0060] When the Q output of the D flip-flop 110 is at an H level, the counter 111 increments the count value C based on the clock signal CLK of a predetermined period. When the Q output of the D flip-flop 110 is at an L level, the counter 111 resets the count value C. Therefore, if the H-level signal Vc2 (first comparison result) indicating that the inductor current IL is smaller than the current value Ic is held in the D flip-flop 110, the count value C of the counter 111 is incremented. If the L-level signal Vc2 (second comparison result) indicating that the inductor current IL is larger than the current value Ic is held in the D flip-flop 110, the count value C of the counter 111 is reset.

[0061] When the count value C of the counter 111 reaches a predetermined count value C1 corresponding to a predetermined time Tx, the signal output circuit 112 outputs a signal Vd (first signal) at an H level. On the other hand, before the count value C of the counter 111 reaches the count value C1, the signal output circuit 112 outputs a signal Vd (second signal) at an L level.

[0062] ===Operation of Power Factor Improvement IC25 ===

[0063] <<<Input AC voltage Vac>>>

[0064] Reference Figure 3 , the operation of the power factor improvement IC 25 when the AC-DC converter 10 generates the output voltage Vout of the target level according to the specified AC voltage Vac and supplies power to a certain load is described. In addition, here, the operation of the drive signal generation circuit 50 and the drive circuit 51 in the power factor improvement IC 25 is mainly described.

[0065] First, at time t0, when the inductor current IL decreases and reaches the current value Ia, that is, when the voltage Vcs decreases and reaches the reference voltage Vref1, the comparator 70 changes the signal Vz to the H level (at Figure 3 (not shown in the figure) Furthermore, when the time t0 changes to the time t1 after the delay time of the delay circuit 71 has passed, the pulse circuit 72 outputs the pulse signal Vp1.

[0066] Then, when the pulse signal Vp1 is output, the SR flip-flop 79 outputs the driving signal Vq1 at the H level, so that the signal Vdr also becomes the H level. As a result, the NMOS transistor 26 is turned on, and the inductor current IL increases.

[0067] Furthermore, if the pulse signal Vp1 is output, the pulse signal Vp3 also becomes H level, and thus the amplitude of the ramp wave Vr from the oscillation circuit 76 increases. Then, at time t2, if the amplitude level of the ramp wave Vr becomes higher than the level of the voltage Ve, the comparator 77 changes the signal Vc1 to H level. As a result, the SR flip-flop 79 is reset, and the signal Vdr also becomes L level. If the signal Vdr becomes L level, the NMOS transistor 26 is turned off, and thus the inductor current IL gradually decreases. Furthermore, at time t3, if the inductor current IL decreases and becomes the current value Ia, the operation at time t0 is repeated.

[0068] Here, when the AC-DC converter 10 generates the output voltage Vout of the target level according to the predetermined AC voltage Vac and supplies power to a certain load, the feedback voltage Vfb is constant. As a result, the voltage Ve output from the error amplifier circuit 75 is also constant, and thus the period during which the NMOS transistor 26 is turned on (for example, the period from time t0 to time t1) is also constant.

[0069] Furthermore, when the NMOS transistor 26 is turned on, the level of the voltage Vrec obtained by rectifying the AC voltage Vac becomes higher, and the current value of the inductor current IL also becomes larger. Figure 4As shown, the waveform of the peak value of the inductor current IL becomes the same waveform as the voltage Vrec, so that the power factor is improved.

[0070] <<<When the AC voltage Vac is cut off and then restored>>>

[0071] Reference Figure 5 and Figure 6 , the operation of the power factor improvement IC25 when the AC voltage Vac is cut off is described. Figure 6 1 is a diagram showing the details of the changes in the main signals of the power factor improvement IC 25 from the time when the AC voltage Vac is cut off to the time when it is restored. In this embodiment, it is assumed that the AC voltage Vac is cut off at time t100 and the AC voltage Vac is restored at time t101. In addition, here, when the AC voltage Vac is input, the power factor improvement IC 25 performs Figure 3 and Figure 4 The actions shown in .

[0072] like Figure 6 As shown, at time t10 before the AC voltage Vac is cut off, if the signal Vq1 changes to the H level, the NMOS transistor 26 is turned on, and the inductor current IL increases.

[0073] When the signal Vq1 changes to the L level at time t11, the NMOS transistor 26 is turned off, and the inductor current IL decreases. In addition, at the timing when the signal Vq1 changes to the L level at time t11, the D flip-flop 110 of the timing circuit 101 holds the comparison result, that is, the signal Vc2 from the comparator 100. In addition, here, the current value of the inductor current IL is larger than the current value Ic, so the D flip-flop 110 holds the signal Vc2 at the L level. As a result, the Q output of the D flip-flop 110 changes to the L level, and the count value C of the counter 111 is also reset. Therefore, at time t11, the signal Vd from the signal output circuit 112 also changes to the L level.

[0074] Then, at time 100 after time t11, the AC voltage Vac is cut off, so Figure 5 As shown, the level of voltage Vrec decreases rapidly.

[0075] When the signal Vq1 becomes H level at time t12 after the AC voltage Vac is cut off and the inductor current IL becomes zero, the NMOS transistor 26 becomes conductive. Here, at time t12, the voltage Vrec does not drop to zero, so the inductor current IL increases and becomes larger than the current value Ic, for example.

[0076] When the signal Vq1 changes to L level at time t13, the NMOS transistor 26 turns off, and the inductor current IL decreases. Also, at time t13, the D flip-flop 110 holds the signal Vc2 at L level, similarly to time t11. Therefore, at time t13, the Q output of the D flip-flop 110 and the signal Vd are also at L level.

[0077] When the signal Vq1 changes to H level at time t14 after the inductor current IL becomes zero, the NMOS transistor 26 turns on. Here, for example, when the voltage Vrec decreases to zero at time t14, the current value of the inductor current IL also becomes approximately zero and does not increase.

[0078] Then, when the signal Vq1 changes to the L level at time t15, the D flip-flop 110 holds the signal Vc2 which is the comparison result from the comparator 100, similarly to the times t11 and t13. Here, at time t15, the signal Vc2 of the H level is output from the comparator 100, and thus the Q output of the D flip-flop 110 changes to the H level. In addition, when the Q output of the D flip-flop 110 changes to the H level, the counter 111 increments the count value C.

[0079] Furthermore, when a predetermined time has passed from time t15 when the inductor current IL becomes zero and the operation of the pulse circuit 72 substantially stops, to time t16, the timing circuit 73 is turned on instead of the pulse circuit 72 to output the pulse signal Vp2. As a result, the drive signal Vq1 is also turned on as shown in FIG. Figure 6 In addition, from time t16 to time t101 when the AC voltage Vac is restored, the current value of the inductor current IL is approximately zero. Therefore, during this period, the current value of the inductor current IL does not exceed the current value Ic. Therefore, during this period, the counter 111 is not reset, and the count value C continues to increase.

[0080] Then, when the predetermined time Tx has passed from time t15 to time t17, the count value C becomes the predetermined count value C1, so the signal output circuit 112 outputs the H-level signal Vd. As a result, the H-level signal Vd indicating that the AC voltage Vac is cut off is output to the terminal CONT. Figure 1 The microcomputer 12 (control circuit) shown can set the load 11 to which the output voltage Vout is applied to a light load or no load state (a state in which the current consumption is small).

[0081] In addition, if the AC voltage Vac is restored at time t101, Figure 5 As shown in FIG. 1 , the voltage Vrec also rises. As a result, for example, when the NMOS transistor 26 is turned on based on the signal Vq1 at the H level at time t18, the inductor current IL increases.

[0082] Then, if the current value of the inductor current IL is greater than the current value Ic at time t19 when the signal Vq1 changes to the L level, the signal Vc2 indicating the comparison result from the comparator 100 changes to the L level. As a result, the L level signal Vc2 is held in the D flip-flop 110, and the Q output changes to the L level. As a result, the count value C of the counter 111 is reset, and the signal Vd also changes to the L level. In addition, here, the L level signal Vd indicating that the AC voltage Vac has recovered is output to the terminal CONT. Therefore, Figure 1 The microcomputer 12 shown stops the control for setting the load 11 to a light load or no load state.

[0083] Furthermore, when the inductor current IL decreases and the comparator 70 outputs a signal at the H level at time t20, the pulse circuit 72 starts the operation again instead of the start timer circuit 73. Thereafter, for example, the operation from t10 to t12 is repeated. As a result, the AC-DC converter 10 performs Figure 3 and Figure 4 In addition, as described above, the signal Vd from the detection circuit 53 is output to the terminal CONT. Therefore, the user of the power factor improvement IC 25 can understand that the AC voltage Vac is cut off by monitoring the level of the terminal CONT.

[0084] ===Summary===

[0085] The AC-DC converter 10 of the present embodiment has been described above. The power factor improvement IC 25 includes a detection circuit 53 for detecting that the AC voltage Vac is cut off. Therefore, when the AC-DC converter 10 is implemented, it is not necessary to constitute a circuit for detecting the AC voltage Vac with discrete components or the like. Therefore, by using the power factor improvement IC 25, the AC-DC converter 10 can detect that the AC voltage Vac is cut off at a low cost.

[0086] Furthermore, if the AC voltage Vac is cut off and then restored, the inductor current IL also increases. The detection circuit 53 of this embodiment detects the restoration of the AC voltage Vac that was cut off (that is, the application of the AC voltage Vac to the full-wave rectifier circuit 20) based on the comparison result of the current value of the inductor current IL and the current value Ic, that is, the signal Vc2. In this way, the power factor improvement IC 25 can detect not only the cut-off of the AC voltage Vac, but also the restoration.

[0087] In addition, as the timing circuit 101, for example, a charging circuit that charges a capacitor with a predetermined bias current can be used to count the predetermined time Tx. However, if the bias current and the variation in the capacitance of the capacitor are taken into consideration, the predetermined time Tx can be counted with high accuracy by using the counter 111.

[0088] In addition, the D flip-flop 110 of the present embodiment latches (holds) the signal Vc2 which is the comparison result of the comparator 100 at the timing when the NMOS transistor 26 changes from on to off, that is, at the timing when the drive signal Vq1 falls. Usually, when the drive signal Vq1 changes to the L level, the NMOS transistor 26 is in the on state, so when the AC voltage Vac is input, the inductor current IL corresponding to the AC voltage Vac flows. In the present embodiment, the comparison result of the inductor current IL and the current value Ic, that is, the signal Vc2, can be held at the timing when the NMOS transistor 26 is turned on, not at the timing when the NMOS transistor is turned off. Therefore, the detection circuit 53 can detect whether the AC voltage Vac is cut off with high accuracy.

[0089] In this embodiment, after the AC voltage Vac is cut off, the start timer circuit 73 operates to periodically turn on the NMOS transistor 26. Therefore, in this embodiment, the detection circuit 53 can detect the recovery of the AC voltage Vac when performing the cut-off detection.

[0090] Furthermore, the predetermined time Tx is set to be longer than the period during which the inductor current IL becomes smaller than the current value Ic when the AC voltage Vac is applied to the full-wave rectifier circuit 20 and the NMOS transistor 26 is turned on, and shorter than the half cycle of the AC voltage Vac. Therefore, in this embodiment, it is possible to detect whether the AC voltage Vac is cut off in a short time.

[0091] Furthermore, if the interruption of the AC voltage Vac is detected and the H-level signal Vd is output to the terminal CONT, the microcomputer 12 sets the load 11 to a light load state. Therefore, a significant decrease in the output voltage Vout is suppressed, and therefore, when the AC voltage Vac is restored, the output voltage Vout of the target level can be generated in a short time.

[0092] The above-mentioned embodiments are used to facilitate understanding of the present invention, and are not used to limit and explain the present invention. In addition, the present invention can be changed or improved without departing from its main purpose, and its equivalent content is of course also included in the present invention.

[0093] In the present embodiment, the signal Vd from the detection circuit 53 is output to the terminal CONT, but the present invention is not limited to this. For example, a logic circuit or the like may be provided to turn off the NMOS transistor 26 based on the signal Vd at an H level.

[0094] In addition, the counter 111 may decrement the count value C instead of incrementing it. Even when such a counter is used, the same timer circuit 101 as that of the present embodiment can be realized.

[0095] Description of symbols

[0096] 10 AC-DC Converter

[0097] 11 Load

[0098] 12 Microcomputer

[0099] 20 Full-wave rectifier circuit

[0100] 21, 22, 34 Capacitors

[0101] 23 Inductor

[0102] 24, 37 diode

[0103] 25 Power Factor Improvement IC

[0104] 26 NMOS transistors

[0105] 30~33、35、36 Resistors

[0106] 50 driving signal generation circuit

[0107] 51. Driving circuit

[0108] 52, 70, 77, 100 Comparator

[0109] 53 Detection circuit

[0110] 71 Delay Circuit

[0111] 72 Pulse Circuit

[0112] 73 Start timing circuit

[0113] 74, 78 OR gate circuit

[0114] 79 SR Trigger

[0115] 101 Timing Circuit

[0116] 110 D Flip Flop

[0117] 111 Counter

[0118] 112 signal output circuit.

Claims

1. An integrated circuit, The integrated circuit is an integrated circuit for improving the power factor of an AC-DC converter, wherein: The AC-DC converter is a power supply circuit that generates an output voltage based on an AC voltage of a commercial power supply, and includes a rectifier circuit that rectifies the AC voltage, an inductor to which a voltage from the rectifier circuit is applied, and a transistor that controls an inductor current flowing through the inductor, and the integrated circuit switches the transistor based on the inductor current and the output voltage. The integrated circuit is characterized in that it includes: a comparison circuit that compares a current value of the inductor current with a first current value; and A timing circuit, which is based on a first comparison result indicating that the current value of the inductor current is smaller than the first current value, and outputs a first signal indicating that the AC voltage is cut off when it is detected that the current value of the inductor current is smaller than the first current value for a predetermined time.

2. The integrated circuit according to claim 1, wherein: The timing circuit: Based on a second comparison result indicating that the current value of the inductor current is larger than the first current value, a second signal indicating that the AC voltage is applied to the rectifier circuit is output.

3. The integrated circuit according to claim 2, characterized in that The inductor current is a current that increases as the transistor turns on while the AC voltage is applied to the rectifier circuit. The timing circuit comprises: a holding circuit, the holding circuit holding a comparison result of the comparison circuit each time the transistor is turned on; a counter that resets a count value when the holding circuit holds the second comparison result, and changes the count value when the holding circuit holds the first comparison result; and The signal output circuit outputs the first signal when the count value reaches a predetermined count value corresponding to the predetermined time, and outputs the second signal before the count value reaches the predetermined count value.

4. The integrated circuit according to claim 3, characterized in that The holding circuit: The comparison result of the comparison circuit is held based on the timing at which the logic level of the drive signal for switching the transistor changes to a logic level for turning off the transistor.

5. The integrated circuit according to claim 4, characterized in that include: a first pulse circuit that outputs a first pulse signal each time the inductor current decreases and reaches a second current value; a second pulse circuit that outputs a second pulse signal of a predetermined period when the output of the first pulse signal stops; and A drive signal output circuit outputs the drive signal based on the first pulse signal and the second pulse signal.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that The stipulated times are: A time that is longer than a period during a half cycle of the AC voltage during which the current value of the inductor current becomes smaller than the first current value when the AC voltage is applied to the rectifier circuit and the transistor is turned on, and is shorter than a period of the half cycle.

7. The integrated circuit according to any one of claims 1 to 5, characterized in that comprising a terminal for outputting the first signal, The terminal is connected to a control circuit that reduces power consumption of a load to which the output voltage is applied based on the first signal.

8. The integrated circuit according to claim 6, wherein: comprising a terminal for outputting the first signal, The terminal is connected to a control circuit that reduces power consumption of a load to which the output voltage is applied based on the first signal.

9. A power supply circuit, The power supply circuit generates an output voltage according to a prescribed AC voltage, and is characterized in that it includes: A rectifier circuit, which rectifies the specified AC voltage; an inductor to which the voltage from the rectifier circuit is applied; as well as an integrated circuit that drives a transistor that controls the inductor current based on the inductor current flowing through the inductor and the output voltage, The integrated circuit comprises: a comparison circuit that compares a current value of the inductor current with a first current value; as well as A timing circuit that outputs a first signal indicating that the AC voltage is cut off when the current value of the inductor current remains smaller than the first current value for a predetermined time based on a first comparison result indicating that the current value of the inductor current is smaller than the first current value.

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