Storage device based on key-value storage data and operation method thereof

Abstract

A storage device includes: a controller configured to: receive a plurality of key-value pairs from a host, separate a key from each of the plurality of key-value pairs and separate a value from each of the plurality of key-value pairs, and generate a first key stream by merging a plurality of keys separated from the plurality of key-value pairs; and a non-volatile memory configured to store the first key stream. The first key stream is stored in the non-volatile memory separately from the value separated from each of the plurality of key-value pairs.

Description

[0001] Cross-reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0081522 filed on July 5, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a storage device and an operating method of the storage device, and more particularly, to a storage device storing data based on a key value and an operating method of the storage device. Background Art

[0004] Recently, various types of electronic devices have been used. Some electronic devices can store data and can operate based on the stored data. To this end, the electronic device may include a storage device or storage system for storing data, or may store or read data while communicating with an external storage device or storage system.

[0005] Storage devices can be classified in various ways. For example, storage devices can be classified into non-volatile memory (NVM)-based storage and volatile memory-based storage. Even if power is not supplied, non-volatile memory-based storage does not lose data. On the other hand, although data stored in volatile memory-based storage is lost when power supplied to volatile memory-based storage is interrupted, volatile memory-based storage can operate faster than non-volatile memory-based storage.

[0006] For example, storage devices can be classified into block storage, file storage, and object storage. Block storage can manage data based on physical locations, and file storage can manage data based on logical sequences. On the other hand, object storage can manage data based on unique identifiers. Block storage and file storage are useful when there is a large amount of text data, while object storage may be an effective choice when there is a large amount of unstructured data (such as sound data, image data, etc.). As an example of object storage, there is key-value storage, which stores data based on key values. Summary of the invention

[0007] The inventive concept provides a storage device that efficiently manages keys and values ​​and an operating method of the storage device.

[0008] The inventive concept also provides a storage device that efficiently performs compression on keys and values, and an operating method of the storage device.

[0009] According to an exemplary embodiment of the present invention, a storage device includes: a controller configured to: receive a plurality of key-value pairs from a host, separate a key from each of the plurality of key-value pairs and separate a value from each of the plurality of key-value pairs, and generate a first key stream by merging a plurality of keys separated from the plurality of key-value pairs; and a nonvolatile memory configured to store the first key stream. The first key stream is stored in the nonvolatile memory separately from the value separated from each of the plurality of key-value pairs.

[0010] According to an exemplary embodiment of the present invention, a method for operating a storage device, the storage device including a non-volatile memory and a controller for controlling the non-volatile memory, the operating method comprising: the controller receiving a plurality of key-value pairs; the controller generating a first key stream by extracting a key from each of the plurality of key-value pairs; and the controller storing the first key stream in the non-volatile memory.

[0011] According to an exemplary embodiment of the present invention, a method for operating a storage device, the storage device includes a non-volatile memory and a controller for controlling the non-volatile memory, the operating method including: the controller generates a data stream from multiple data pages; the controller stores the data stream in the non-volatile memory; the controller generates a multi-mapping table, the multi-mapping table including: a physical address of a first data page among multiple data pages in the non-volatile memory; and at least one validity bit indicating whether a corresponding page among the multiple data pages included in the data stream is valid; and in response to the first data page among the multiple data pages being invalid, the controller updates the multi-mapping table with a first validity bit indicating whether the first data page is valid. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a storage system according to an example embodiment of the inventive concept;

[0014] Figure 2 is a block diagram illustrating a storage device according to an example embodiment of the inventive concept;

[0015] Figure 3 is a circuit diagram illustrating a memory block included in a memory cell array according to an example embodiment of the inventive concept;

[0016] Figure 4 It is shown Figure 3 A perspective view of a memory block;

[0017] Figure 5 is a conceptual diagram illustrating an operation of a storage device according to an example embodiment of the inventive concept;

[0018] Figure 6 is a flowchart illustrating an operating method of a key value manager according to an exemplary embodiment of the inventive concept;

[0019] Figure 7 is a conceptual diagram illustrating the operation of a key value manager according to an exemplary embodiment of the inventive concept;

[0020] Figure 8 is a flowchart illustrating an operating method of a key value manager according to an exemplary embodiment of the inventive concept;

[0021] Fig.9A is a diagram illustrating blocks according to an example embodiment of the inventive concept,

[0022] Fig. 9B is a diagram illustrating a multi-mapping table according to an exemplary embodiment of the inventive concept;

[0023] Fig.10 is a diagram illustrating operation of a storage system over time according to an example embodiment of the inventive concept;

[0024] Fig.11 is a diagram illustrating operation of a storage system over time according to an example embodiment of the inventive concept;

[0025] Fig.12 is a diagram illustrating operation of a storage system over time according to an example embodiment of the inventive concept;

[0026] Fig.13 is a diagram illustrating operation of a storage system over time according to an example embodiment of the inventive concept;

[0027] Fig.14 is a diagram illustrating operation of a storage system over time according to an example embodiment of the inventive concept;

[0028] Fig.15 is a block diagram illustrating a storage device according to an example embodiment of the inventive concept; and

[0029] Fig.16 is a block diagram illustrating an electronic device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0030] Figure 1 is a block diagram illustrating a memory system according to an example embodiment of the inventive concept.

[0031] Reference Figure 1, the storage system 10 may include a storage device 100 and a host 200, and the storage device 100 may include a controller 110, a data buffer 130, and a non-volatile memory (NVM) 140. The host 200 may communicate with the storage device 100 through various interfaces. For example, the host 200 may be implemented with an application processor (AP) or a system-on-chip (SoC).

[0032] In one embodiment, the storage device 100 may be a key-value storage device or key-value storage, for example, a key-value solid state drive (SSD). A key-value storage device is a device that processes data quickly and simply by using a key-value pair. As used herein, the term "key-value pair" may refer to a pair of a unique key and a value of data corresponding to (i.e., associated with) the key, and may be referred to as a term "tuple" or "key-value tuple". In a key-value pair, a key may be represented by any string, such as a file name, a uniform resource identifier (URI), or a hash, and a value may be any kind of data, such as an image, a user preference file, or a document. Here, the size of the key and value may be variable, and for example, the size of the value may vary with the data included in the value.

[0033] Hereinafter, an embodiment in which the storage device 100 is a key-value storage device will be described, and in the specification, the storage device 100 may have the same meaning as a key-value storage device or a key-value storage. However, the storage device 100 is not limited to a key-value storage device, and may be applied to any object cache system or object storage system that manages data in units of objects. Therefore, the storage device 100 may manage data in units of objects in any manner other than a key-value pair manner.

[0034] The host 200 may send a command CMD for writing data including a key-value pair, such as a write request or a put command, to the storage device 100, and the storage device 100 may write a value VALUE to the nonvolatile memory 140 in response to the command CMD. In one embodiment, the host 200 may send a command CMD including a key KEY, such as a read request or a get command, to the storage device 100, and the storage device 100 may read a value VALUE corresponding to the key KEY from the nonvolatile memory 140 in response to the command CMD.

[0035] The controller 110 may control the nonvolatile memory 140 so that a value is written to the nonvolatile memory 140 in response to a write request from the host 200 or so that a value stored in the nonvolatile memory 140 is read in response to a read request from the host 200. The controller 110 may include a key value manager 120.

[0036] The key value manager 120 may receive a key-value pair included in the command CMD, and may separate a key and a value both included in the key-value pair from each other. For example, the key value manager 120 may separate a plurality of keys KEY from the key-value pair, and may also separate a plurality of values ​​from the key-value pair. The key value manager 120 may extract a plurality of keys KEY included in the key-value pair, and may store the plurality of keys KEY in the data buffer 130. The key value manager 120 may extract a plurality of values ​​VALUE included in the key-value pair, and may store the plurality of values ​​VALUE in the data buffer 130.

[0037] When there are multiple keys KEY up to a certain number or amount of data stored in the data buffer 130, the key value manager 120 may store the stored multiple keys KEY as a key stream in the non-volatile memory 140. When there are multiple values ​​VALUE up to a certain number or amount of data stored in the data buffer 130, the key value manager 120 may store the stored multiple values ​​VALUE as a value stream in the non-volatile memory 140. In one embodiment, the value stream and the key stream may be stored in different areas of the non-volatile memory 140, respectively.

[0038] In one embodiment, the value VALUE may have a larger data volume than the key KEY, and according to the present invention, the key-value manager 120 may separate the key-value pair and manage the key KEY and the value VALUE separately, thereby reducing the input / output data volume for the non-volatile memory 140, and as a result, the data processing capability of the key-value pair may be improved.

[0039] The data buffer 130 may include at least one memory device for storing a key KEY and a value VALUE, and in one example, the data buffer 130 may include a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0040] The non-volatile memory 140 may include a memory cell array MCA, the memory cell array MCA may include memory blocks BLK1 to BLKz, and the memory block BLK1 may include multiple pages PG1 to PGk. Here, each of z and k may be a positive integer and may vary differently depending on the embodiment. For example, a memory block may be a unit of erase, and a page may be a unit of write or read. In some embodiments, the memory cell array MCA may include multiple planes, multiple dies, or multiple chips. In one embodiment, the non-volatile memory 140 may include a flash memory device, for example, a NAND flash memory device. However, the inventive concept is not limited thereto, and the non-volatile memory 140 may include a resistive memory device, such as a resistive RAM (ReRAM), a phase-change RAM (PRAM), or a magnetic RAM (MRAM).

[0041] The storage system 10 may be implemented as, for example, a personal computer (PC), a data server, a network attached storage, an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, etc.

[0042] In some embodiments, the storage device 100 may be an internal memory embedded in an electronic device. For example, the storage device 100 may be an SSD, an embedded universal flash storage (UFS) storage device, or an embedded multimedia card (eMMC). In some embodiments, the storage device 100 may be an external memory that is attachable to and removable from an electronic device. For example, the storage device 100 may include a UFS memory card, a Compact Flash (CF) memory card, a Secure Digital (SD) memory card, a Micro-Secure Digital (Micro-SD) memory card, a Mini-Secure Digital (Mini-SD) memory card, an Extreme Digital (xD) memory card, or a Memory Stick.

[0043] Figure 2 is a block diagram illustrating a storage device according to an example embodiment of the inventive concept.

[0044] Reference Figure 2 , the storage device 100 may include a key value manager 120, a data buffer 130, and a non-volatile memory 140. The key value manager 120 may include a key value extractor 121, a compaction module 122, and a garbage collection module 123. The key value extractor 121 may extract a key KEY and a value VALUE included in a command CMD. The key value extractor 121 may store the extracted key KEY in a key buffer 131 of the data buffer 130, and may store the extracted value VALUE in a value buffer 132 of the data buffer 130. In one embodiment, the key buffer 131 and the value buffer 132 may be configured as separate memory devices, respectively. In another embodiment, the key buffer 131 and the value buffer 132 may be configured as different areas of the data buffer 130, respectively.

[0045] In one embodiment, the key value extractor 121 can manage the physical address of the key KEY stored in the key buffer 131 by using a mapping table, and in one example, the mapping table can be generated as a hash table that stores the hash key corresponding to the key KEY together with the key KEY as a mapping index of the key KEY.

[0046] When the multiple keys KEY stored in the key buffer 131 have a certain amount or more of data, the key value extractor 121 can generate a key stream ST_KEY based on the multiple keys KEY. In one embodiment, the key value extractor 121 can generate the key stream ST_KEY by arranging the multiple keys KEY continuously. In another embodiment, the key value extractor 121 can generate the key stream ST_KEY by merging the multiple keys KEY with the indexes of the values ​​VALUE corresponding to the multiple keys KEY respectively. The key value extractor 121 can store the generated key stream ST_KEY in the first area AR1 of the non-volatile memory 140.

[0047] In one embodiment, the key value extractor 121 may manage the physical address of the key KEY stored in the first area AR1 by using a hash table. For example, the hash table may store a hash key corresponding to the key KEY together with the key KEY as a mapping index of the key KEY.

[0048] When the multiple values ​​VALUE stored in the value buffer 132 have a certain amount of data or more, the key value extractor 121 may generate a value stream ST_VAL based on the multiple values ​​VALUE. In one example, the key value extractor 121 may generate the value stream ST_VAL by arranging the multiple values ​​VALUE continuously. The key value extractor 121 may store the generated value stream ST_VAL in the second area AR2 of the non-volatile memory 140. In one embodiment, the key value extractor 121 may manage the physical addresses of the stored values ​​VALUE in the second area AR2 by using a value table.

[0049] The compression module 122 may perform a compression operation on at least one key stream ST_KEY stored in the first area AR1. Here, the compression operation may refer to an operation of generating a new key stream ST_KEY by deleting a key KEY corresponding to an invalid value (e.g., an obsolete value) VALUE stored in the non-volatile memory 140. In one example, the compression operation may refer to an operation of merging data in a data structure based on a log structured merge (LSM) tree.

[0050] The compression module 122 may read at least one key stream ST_KEY stored in the first area AR1, and may determine an invalid key (e.g., an obsolete key). In one example, the invalid key may be a key KEY corresponding to a value VALUE to which the host issues a delete command. The compression module 122 may generate a new key stream ST_KEY by using only a valid key KEY included in the at least one key stream ST_KEY. The compression module 122 may write the generated new key stream ST_KEY to the first area AR1 of the nonvolatile memory 140.

[0051] According to an embodiment of the inventive concept, when performing a compression operation, the storage device 100 may perform the compression operation by reading only the key stream ST_KEY without reading the value VALUE having a relatively large amount of data, and thus, the amount of data access to the nonvolatile memory 140 may be reduced.

[0052] The compression module 122 may update the validity of the value VALUE corresponding to the invalid key KEY that is the target of the compression operation. In one embodiment, the value table including information about the physical address of the non-volatile memory 140 storing the value VALUE may also include a validity bit indicating validity information about the value VALUE, and the compression module 122 may update the validity bit of the invalid value VALUE. Fig.9A and Fig. 9B Describe this.

[0053] The garbage collection module 123 may perform garbage collection on the nonvolatile memory 140. According to one embodiment of the inventive concept, the hash table may include information about the validity of the key stream ST_KEY, and the garbage collection module 123 may perform garbage collection on the key stream ST_KEY based on the hash table. In addition, the value table may include information about the validity of the value stream ST_VAL, and the garbage collection module 123 may perform garbage collection on the value stream ST_VAL based on the value table.

[0054] Figure 3 is a circuit diagram illustrating a memory block included in a memory cell array according to an example embodiment of the inventive concept.

[0055] Reference Figure 3 , memory cell array (e.g., Figure 1 The MCA) may be a memory cell array of a vertical NAND flash memory and may include a plurality of memory blocks. Each memory block BLK0 may include a plurality of NAND cell strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of cell string selection lines SSL1 to SSL3, and a common source line CSL. Here, according to the embodiment, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of cell string selection lines may vary differently.

[0056] NAND cell strings NS11, NS21, and NS31 are arranged between a first bit line BL1 and a common source line CSL, NAND cell strings NS12, NS22, and NS32 are arranged between a second bit line BL2 and a common source line CSL, and NAND cell strings NS13, NS23, and NS33 are arranged between a third bit line BL3 and a common source line CSL. Each NAND cell string (e.g., NS11) may include a cell string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST connected in series.

[0057] The NAND cell strings commonly connected to one bit line constitute a column. For example, NAND cell strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to the first column, NAND cell strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to the second column, and NAND cell strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

[0058] The NAND cell strings connected to one cell string selection line constitute a row. For example, NAND cell strings NS11, NS12, and NS13 connected to the first cell string selection line SSL1 may correspond to the first row, NAND cell strings NS21, NS22, and NS23 connected to the second cell string selection line SSL2 may correspond to the second row, and NAND cell strings NS31, NS32, and NS33 connected to the third cell string selection line SSL3 may correspond to the third row.

[0059] The cell string selection transistors SST are respectively connected to the corresponding cell string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 are respectively connected to the corresponding word lines WL1 to WL8. The ground selection transistors GST are respectively connected to the corresponding ground selection lines GSL1 to GSL3. The cell string selection transistors SST are connected to the corresponding bit lines BL1 to BL3, and the ground selection transistors GST are connected to the common source line CSL.

[0060] The word lines (e.g., WL1) of the same height are commonly connected to each other, the cell string selection lines SSL1 to SSL3 are separated from each other, and the ground selection lines GSL1 to GSL3 are also separated from each other. For example, when the memory cells connected to the first word line WL1 and included in the NAND cell strings NS11, NS12, and NS13 are programmed, the first word line WL1 and the first cell string selection line SSL1 are selected. The ground selection lines GSL1 to GSL3 may be commonly connected to each other.

[0061] A memory device according to an embodiment of the present invention may store keys and values ​​in different regions of a memory cell array, respectively. In one example, a key may be stored in a first page of a first word line WL1 connected to a memory block BLK0, and a value may be stored in a second page of a fourth word line WL4 connected to the memory block BLK0.

[0062] Figure 4 It is shown Figure 3 A perspective view of the memory blocks.

[0063] Reference Figure 4 , including in a memory cell array (e.g., Figure 1 Each memory block in the MCA is formed in a vertical direction relative to the substrate SUB. Figure 4 The memory block is shown to include two selection lines GSL and SSL, eight word lines WL1 to WL8 , and three bit lines BL1 to BL3 , but the number of each component included in the memory block may actually be greater or less than that set forth above.

[0064] The substrate SUB is of a first conductivity type (e.g., p-type), and a common source line CSL extending in a first direction (e.g., Y direction) and doped with impurities of a second conductivity type (e.g., n-type) is arranged on the substrate SUB. On a region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating films IL extending in the first direction are sequentially arranged in a third direction (e.g., Z direction), and the plurality of insulating films IL are spaced a certain distance from each other in the third direction. For example, each of the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0065] On the region of the substrate SUB between two adjacent common source lines CSL, a plurality of pillars P respectively penetrating the plurality of insulating films IL along the third direction are sequentially arranged along the first direction. For example, the plurality of pillars P may contact the substrate SUB through the plurality of insulating films IL. Specifically, the surface layer S of each pillar P may include a silicon material of the first conductivity type and may be used as a channel region. In addition, the inner layer I of each pillar P may include an insulating material such as silicon oxide, or an air gap.

[0066] In the region between two adjacent common source lines CSL, a charge storage layer CS is arranged along the exposed surfaces of the insulating film IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two adjacent common source lines CSL, gate electrodes GE (such as selection lines GSL and SSL and word lines WL1 to WL8) are arranged on the exposed surface of the charge storage layer CS.

[0067] The drains or drain contacts DR are respectively arranged on the plurality of pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities of the second conductivity type. The bit lines BL1 to BL3 extending in the second direction (eg, X direction) may be arranged on the drains DR to be separated from each other by a certain distance in the first direction.

[0068] Figure 5 is a conceptual diagram illustrating an operation of a memory device according to an example embodiment of the inventive concept.

[0069] Reference Figure 2 and Figure 5 , the key value manager 120 may receive the key-value pair KVP, and may separate the key and the value from each other, both of which are included in the key-value pair KVP. The key value manager 120 may couple the key to the index Idx corresponding to each value, and may store the key coupled to the index Idx in the data buffer 130. In addition, the key value manager 120 may generate a key stream ST_KEY by merging a plurality of keys KEY each coupled to the index Idx, and may store the generated key stream ST_KEY in the first area AR1 of the nonvolatile memory 140.

[0070] Although Figure 5 It is shown that one key stream ST_KEY corresponds to one index Idx, which is only for convenience of description, and the key stream ST_KEY according to an embodiment of the inventive concept may include multiple index-key pairs, wherein the indexes Idx are respectively coupled to the keys.

[0071] The key value manager 120 may generate a hash table HT by using a physical page number (PPN) storing a key stream ST_KEY in the first area AR1 of the nonvolatile memory 140. For example, the hash table HT may store an index of a sorted string table (SS table) including a key of the key stream ST_KEY and a physical address of the nonvolatile memory 140 storing the key of the key stream ST_KEY. The SS table may be a data file including a key-value pair KVP, and the hash table HT may store a file name of the SS table and a physical address storing the key of the SS table.

[0072] The key value manager 120 may store values ​​separated from the key value pair KVP in the data buffer 130 , may generate a value stream ST_VAL by merging a plurality of values ​​stored in the data buffer 130 , and may store the generated value stream ST_VAL in the second area AR2 of the nonvolatile memory 140 .

[0073] The key value manager 120 may generate a value table VT by using the stored value stream ST_VALPPN in the nonvolatile memory 140. For example, the value table VT may store the value stream ST_VAL and the physical address of the nonvolatile memory 140 storing the value stream ST_VAL. In one embodiment, the value table VT may also include a validity bit indicating whether the value VALUE is valid.

[0074] Figure 6 is a flowchart illustrating an operating method of a key value manager according to an example embodiment of the inventive concept.

[0075] Reference Figure 2 and Figure 6 , the key value manager 120 may receive data including a plurality of keys KEY and a plurality of values ​​VALUE (S110), and may generate a key stream ST_KEY by extracting the plurality of keys KEY from the received data (S120). In addition, the key value manager 120 may generate a value stream ST_VAL by extracting the plurality of values ​​VALUE from the received data (S130). The key value manager 120 may store the generated key stream ST_KEY and the generated value stream ST_VAL in the nonvolatile memory 140 (S140). For example, the generated key stream ST_KEY may be stored in the first area AR1 of the nonvolatile memory 140, and the generated value stream ST_VAL may be stored in the second area AR2 of the nonvolatile memory 140.

[0076] According to one embodiment of the inventive concept, the key value manager 120 may store the key KEY and the value VALUE separately from each other in the nonvolatile memory 140 , and may effectively manage data by separately managing the key KEY and the value VALUE.

[0077] Figure 7 is a conceptual diagram illustrating the operation of a key value manager according to an exemplary embodiment of the present invention. In particular, Figure 7 is a diagram illustrating a method in which a key value manager performs a compression operation.

[0078] Reference Figure 2 and Figure 7 , the key value manager 120 may read the invalid key stream ST_IK from the first area AR1 of the non-volatile memory 140. In one embodiment, the key value manager 120 may respond to the host 200 ( Figure 1 ) uses the information about whether the key included in the key stream is valid to update the hash table HT, and the invalid key stream ST_IK can be determined based on the hash table HT. In one example, when the slave host 200 ( Figure 1 )When an erase command for a first value is received, the key value manager 120 may update the hash table HT with a first key corresponding to the first value, so that the first key may be identified based on an index coupled thereto and indicated as invalid.

[0079] The key value manager 120 can generate at least one merged key stream ST_MK by merging invalid key streams ST_IK. In one example, the key value manager 120 can generate a merged key stream ST_MK by deleting invalid keys based on the hash table HT and extracting only valid keys. Therefore, the merged key stream ST_MK can be a key stream that only includes valid keys.

[0080] The key value manager 120 may write the generated merged key stream ST_MK into the first area AR1 of the non-volatile memory 140. The key value manager 120 may update the value table VT by using an invalid value corresponding to an invalid key. In one embodiment, the key value manager 120 may update the value table VT by converting a validity bit corresponding to an invalid value of the value table VT.

[0081] In one embodiment, the key value manager 120 may perform garbage collection on invalid values ​​based on the validity bits of the value table VT. As garbage collection is performed based on the value table VT, invalid values ​​may be deleted from the second area AR2. Fig.9A and Fig. 9B Describe this.

[0082] When performing a compression operation, the key value manager 120 according to one embodiment of the inventive concept can perform merging of invalid keys and values ​​by reading and rewriting keys with relatively small amounts of data without performing data input / output of values ​​with relatively large amounts of data. For example, a compression operation can be performed without input / output of excessive data, and therefore, data processing speed can be increased.

[0083] Figure 8 is a flow chart illustrating an operating method of a key value manager according to an exemplary embodiment of the present invention. In particular, Figure 8 A method of operating a key value manager to cause the key value manager to perform a compression operation is shown.

[0084] Reference Figure 2 and Figure 8 , the key value manager 120 may read a plurality of key streams from the non-volatile memory 140 (S210). In one embodiment, the plurality of key streams read from the non-volatile memory may include at least one invalid key. The key value manager 120 may generate a new key stream by merging the plurality of key streams (S220). In one example, the key value manager 120 may generate a new key stream by removing invalid keys included in the plurality of key streams and merging only valid keys therein.

[0085] The key value manager 120 may store the generated key stream in the non-volatile memory 140 (S230). The key value manager 120 may delete the invalid key stream from the non-volatile memory 140 (S240). In one embodiment, the key value manager 120 may update the value table to indicate the validity bit corresponding to the invalid value stream as invalid, and may delete the invalid value stream by performing garbage collection on the invalid value stream.

[0086] Fig.9A is a diagram illustrating blocks according to an example embodiment of the inventive concept, Fig. 9B is a diagram illustrating a multi-mapping table according to an exemplary embodiment of the present invention. In one example, Fig. 9B The multi-mapping table MMT can represent a hash table or a value table, which has been referred to Figures 1 to 8 It is described.

[0087] Reference Fig.9A , the block BLK may include a plurality of memory cells having different PPNs, respectively (in Fig.9A In one embodiment, the valid data VD or the invalid data ID may include a reference to Figures 1 to 8 The key of the key stream or the value of the value stream described. Either the key stream or the value stream may be referred to as a data stream. In addition, the valid data VD may refer to the host 200 ( Figure 1 ) a value for which a delete command is not issued or a key corresponding thereto, an invalid data ID may refer to the host 200 ( Figure 1 ) The value or key corresponding to which the delete command is issued.

[0088] The block BLK can store a plurality of data segments (ie, pages), and at least some of the data segments can be continuously written to the block BLK. Fig.9A In the example, three data fragments may be continuously written to the first address PPN1, three data fragments may be continuously written to the second address PPN2, three data fragments may be continuously written to the third address PPN3, and three data fragments may be continuously written to the fourth address PPN4.

[0089] Reference Fig. 9B , can be identified by its storage location using the multi-mapping table MMT Fig.9A The multi-mapping table MMT may include an address (e.g., PPN) storing a first data segment (i.e., a head segment or a head page) among the consecutive data segments, and validity bits VD1 to VD3 indicating the validity of the consecutive data segments stored at the above address. In an example, each of the validity bits VD1 to VD3 may include "1" when the data corresponding thereto is valid, and may include "0" when the data corresponding thereto is invalid.

[0090] Refer again Fig.9A and Fig. 9B , because the continuous data segments stored at the first address PPN1 can be the valid data segment VD, the invalid data segment ID and the valid data segment VD, respectively, in sequence, the multi-mapping table MMT can include "1", "0" and "1" as the validity bits VD1 to VD3 corresponding to the first address PPN1 in the stated order. Because all the continuous data segments stored at the second address PPN2 can be the valid data segments VD, the multi-mapping table MMT can include all "1" as the validity bits VD1 to VD3 corresponding to the second address PPN2.

[0091] Since all the consecutive data segments stored at the third address PPN3 may be invalid data segment IDs, the multi-mapping table MMT may include all "0" as validity bits VD1 to VD3 corresponding to the third address PPN3. Since the consecutive data segments stored at the fourth address PPN4 may be valid data segments VD, valid data segments VD, and invalid data segment IDs, respectively and in sequence, the multi-mapping table MMT may include "1", "1", and "0" as validity bits VD1 to VD3 corresponding to the fourth address PPN4 in the stated order.

[0092] In one embodiment, the key value manager 120 ( Figure 2 ) can perform garbage collection by using the multi-mapping table MMT. For example, the key value manager 120 can determine which data (e.g., which key stream or which value stream) is valid by using the multi-mapping table MMT, and can ensure that the non-volatile memory 140 ( Figure 2 ) effective space.

[0093] Fig.10 is a diagram illustrating the operation of a storage system over time according to an example embodiment of the inventive concept. In particular, Fig.10 is a diagram illustrating an embodiment in which a storage system receives a write command.

[0094] Reference Fig.10 , the storage system may include a host 200, a controller 110, and a nonvolatile memory 140. The host 200 may output a first command CMD1 for writing a first key KEY1 and a first value VAL1 to the controller 110 (S310). The controller 110 may separate the first key KEY1 and the first value VAL1 from the first command CMD1 (S320).

[0095] The controller 110 may use the previously stored data in the data buffer 130 ( Figure 2 ) generates a key stream ST_KEY by using the first key KEY1 and the second key KEY2 previously stored in the data buffer 130 ( Figure 2 ) generates a value stream ST_VAL (S330). In one embodiment, the controller 110 may merge the first key KEY1 with the first index idx1 corresponding to the first value VAL1, may merge the second key KEY2 with the second index idx2 corresponding to the second value VAL2, and may merge the first key KEY1 and the second key KEY2 with each other, each of the first key KEY1 and the second key KEY2 undergoing index merging, thereby generating a key stream ST_KEY.

[0096] The nonvolatile memory 140 may store the first key KEY1 at the first address PPN1, and may store the second key KEY2 at the second address PPN2 (S350). In addition, the nonvolatile memory 140 may store the first value VAL1 at the third address PPN3, and may store the second value VAL2 at the fourth address PPN4 (S350). In one embodiment, the first address PPN1 and the second address PPN2 may be physically continuous with each other, and the third address PPN3 and the fourth address PPN4 may be physically continuous with each other. In addition, both the first address PPN1 and the second address PPN2 may be located in a different area from both the third address PPN3 and the fourth address PPN4.

[0097] The controller 110 may make the storage location of the first key KEY1 correspond to the first address PPN1 in the key table KT, and may make the storage location of the second key KEY2 correspond to the second address PPN2 in the key table KT, thereby updating the key table KT ( S360 ).

[0098] The controller 110 may write the third address PPN3 into the value table VT so that the third address PPN3 corresponds to the first index idx1 corresponding to the first value VAL1. In addition, since the first value VAL1 and the second value VAL2 written to the consecutive addresses are valid, the controller 110 may update the value table VT by writing two "1"s as validity bits corresponding thereto (S370).

[0099] The controller 110 according to an embodiment of the inventive concept may not write both addresses of the first value VAL1 and the second value VAL2 written continuously into the value table VT, but may only write the address corresponding to the first value, thereby effectively managing the value table VT. In addition, the controller 110 may cause the value table VT to include validity bits for the continuous values ​​VAL1 and VAL2, thereby effectively managing information on whether the continuous data segments are valid.

[0100] Fig.11 is a diagram illustrating the operation of a storage system over time according to an example embodiment of the inventive concept. In particular, Fig.11 is a diagram illustrating an embodiment in which a memory system receives an erase command.

[0101] Reference Fig.11, the storage system may include a host 200, a controller 110, and a non-volatile memory 140. The host 200 may output a second command CMD2 for erasing a second key KEY2 and a second value VAL2 to the controller 110 (S410). In response to the second command CMD2, the controller 110 may update the key table KT by deleting a portion of the key table KT corresponding to the second key KEY2 (S420). In response to the second command CMD2, the controller 110 may update a second position validity bit of the value table VT from "1" to "0", the second position validity bit indicating whether the second value VAL2 is valid (S430).

[0102] In order to perform the compression operation, the controller 110 may read the key stream ST_KEY from the nonvolatile memory 140 (S440). The controller 110 may generate a merged key stream ST_KEY' by merging the key stream ST_KEY with the separate key stream (S450). In one example, the controller 110 may delete the second key KEY2 in response to the second command CMD2, and may generate a merged key stream ST_KEY' by using both the first key KEY1 included in the key stream ST_KEY and the third key KEY3 included in the separate key stream.

[0103] The controller 110 may store the merged key stream ST_KEY' in the nonvolatile memory 140 (S460), and the nonvolatile memory 140 may store the merged key stream ST_KEY' at the fifth address PPN5 and the sixth address PPN6 (S470). According to one embodiment of the inventive concept, in a compression operation, the controller 110 may read only the key stream ST_KEY having a relatively small amount of data from the nonvolatile memory 140, but not read the value stream ST_VAL having a relatively large amount of data from the nonvolatile memory 140, and may write the merged key stream ST_KEY' to the nonvolatile memory 140. Therefore, the amount of data input / output to the nonvolatile memory 140 for performing the compression operation may be reduced.

[0104] Fig.12 is a diagram illustrating the operation of a storage system over time according to an example embodiment of the inventive concept. In particular, Fig.12 is a diagram illustrating an embodiment in which a storage system performs garbage collection.

[0105] Reference Fig.12, the storage system may include a host 200, a controller 110, and a non-volatile memory 140. The host 200 may output a third command CMD3 for erasing a first key KEY1 and a first value VAL1 to the controller 110 (S510). In response to the third command CMD3, the controller 110 may update the key table KT by deleting a portion of the key table KT corresponding to the first key KEY1 (S520). In response to the third command CMD3, the controller 110 may update a first position validity bit of the value table VT from "1" to "0", the first position validity bit indicating whether the first value VAL1 is valid (S530).

[0106] Since all validity bits corresponding to the first index idx1 are "0", the controller 110 may perform garbage collection to delete the corresponding value stream ST_VAL and the corresponding key stream (S540). In response to the garbage collection request of the controller 110, the nonvolatile memory 140 may delete the first address PPN1 and the second address PPN2 storing the first key KEY1 and the second key KEY2, respectively, and may delete the third address PPN3 and the fourth address PPN4 storing the first value VAL1 and the second value VAL2, respectively (S550).

[0107] Fig.13 is a diagram illustrating the operation of a storage system over time according to an example embodiment of the inventive concept. In particular, Fig.13 is a diagram illustrating an embodiment in which a storage system receives a write command for writing to an SS table.

[0108] Reference Fig.13 , the storage system may include a host 200, a controller 110, and a nonvolatile memory 140. The host 200 may output a first SS table SST1 including a first key KEY1 and a first value VAL1 to the controller 110 (S610). The controller 110 may separate the first key KEY1 and the first value VAL1 from the first SS table SST1 (S620).

[0109] The controller 110 may use the previously stored data in the data buffer 130 ( Figure 2 ) in the first key KEY1 and the second key KEY2, and can generate a first key stream ST_KEY1 by using the previously stored data buffer 130 ( Figure 2 ) to generate a first value stream ST_VAL1 (S630).

[0110] The nonvolatile memory 140 may store the first key KEY1 at the first address PPN1, and may store the second key KEY2 at the next address of the first address PPN1 (S650). In addition, the nonvolatile memory 140 may store the first value VAL1 at the third address PPN3, and may store the second value VAL2 at the next address of the third address PPN3 (S650). Therefore, the nonvolatile memory 140 may store the first key stream ST_KEY1 at the first address PPN1, and store the first value stream ST_VAL1 at the third address PPN3. In addition, the nonvolatile memory 140 may have stored the second key stream ST_KEY2 at the second address PPN2, and stored the second value stream ST_VAL2 corresponding to the second key stream ST_KEY2 at the fourth address PPN4.

[0111] The controller 110 may make the storage location of the first SS table SST1 correspond to the first address PPN1 in the hash table HT, and may make the storage location of the second SS table SST2 correspond to the second address PPN2 in the hash table HT, thereby updating the hash table HT ( S660 ).

[0112] The controller 110 may write the third address PPN3 into the value table VT so that the third address PPN3 corresponds to the first index idx1 corresponding to the first value VAL1. In addition, since the first value VAL1 and the second value VAL2 written into the consecutive addresses are valid, the controller 110 may update the value table VT by writing two "1"s as validity bits corresponding thereto (S670).

[0113] Fig.14 is a diagram illustrating the operation of a storage system over time according to an example embodiment of the inventive concept. In particular, Fig.14 is a diagram illustrating an embodiment in which a storage system receives a merge command.

[0114] Reference Fig.14 , the storage system may include a host 200, a controller 110, and a non-volatile memory 140. The host 200 may output a merge command (or a compression command) for merging a first SS table SST1 and a second SS table SST2 to the controller 110 (S710). The controller 110 may read a first key stream ST_KEY1 and a second key stream ST_KEY2 from the non-volatile memory 140 (S720).

[0115] The controller 110 may merge the first key stream ST_KEY1 and the second key stream ST_KEY2 to generate a third key stream ST_KEY3 (S730). In one example, the controller 110 may delete the second key KEY2 from the first key stream ST_KEY1 read from the non-volatile memory 140, delete the third key KEY3 read from the second key stream ST_KEY2, and may generate the third key stream ST_KEY3 by merging valid keys in the first key stream ST_KEY1 and the second key stream ST_KEY2 (e.g., the first key KEY1 of the first key stream ST_KEY1 and the fourth key KEY4 of the second key stream ST_KEY2).

[0116] The controller 110 may store the third key stream ST_KEY3 in the nonvolatile memory 140 (S740), and the nonvolatile memory 140 may store the third key stream ST_KEY3 at the fifth address PPN5 (S760). According to one embodiment of the inventive concept, in a compression operation, the controller 110 may read only the key streams ST_KEY1 and ST_KEY2 having a relatively small amount of data from the nonvolatile memory 140, but may not read the value streams ST_VAL1 and ST_VAL2 having a relatively large amount of data from the nonvolatile memory 140, and may write the third key stream ST_KEY3 to the nonvolatile memory 140. Therefore, the amount of data input / output to the nonvolatile memory 140 for performing the compression operation may be reduced.

[0117] Fig.15 is a block diagram illustrating a storage device according to an embodiment of the inventive concept.

[0118] Reference Fig.15 , the storage device 100a may include a controller 110a, a volatile memory 130a, and a nonvolatile memory 140. In addition, the controller 110a may include a processor 111, a memory 112, a host interface 113, a volatile memory interface 116, and a nonvolatile memory interface 114, and these components may communicate with each other via a bus 115.

[0119] The processor 111 may include a CPU, a microprocessor, etc., and may control the overall operation of the controller 110. The memory 112 may operate according to the control of the processor 111, and may be used as an operation memory, a buffer memory, a cache memory, etc. For example, the memory 112 may be implemented with a volatile memory such as a DRAM or an SRAM, or a nonvolatile memory such as a PRAM or a flash memory.

[0120] The key value manager 120a may be implemented in firmware or software and may be loaded into the memory 112. In one embodiment, the key value manager 120a may be implemented in a flash translation layer (FTL) and may be loaded into the memory 112. However, the inventive concept is not limited thereto, and the key value manager 120a may be implemented in hardware. Figures 1 to 12 The described operations may be performed by the processor 111 using the key value manager 120a.

[0121] The host interface 113 may provide an interface between the host 200 and the controller 110, for example, an interface according to a Universal Serial Bus (USB), a Multimedia Card (MMC), a Peripheral Component Interconnect Express (PCI-E), an AT Attachment (ATA), a Serial AT Attachment (SATA), a Parallel AT Attachment (PATA), a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), etc. The non-volatile memory interface 114 may provide an interface between the controller 110a and the non-volatile memory 140. For example, a key stream or a value stream may be sent and received between the controller 110a and the non-volatile memory 140 via the non-volatile memory interface 114.

[0122] The volatile memory interface 116 may provide an interface between the controller 110a and the volatile memory 130a. For example, a key table, a value table, or a mapping table MT may be transmitted and received between the controller 110a and the volatile memory 130a.

[0123] The volatile memory 130a may store a mapping table MT. In one example, the volatile memory 130a, similar to Figure 2 The data buffer 130 can also store keys and values. To this end, the volatile memory 130a can be implemented with DRAM. The mapping table MT can include one of a hash table, a key table, and a value table, which has been referred to Figures 1 to 14 It is described.

[0124] According to the inventive concept, the key value manager 120a can perform various operations (e.g., compression operations and garbage collection operations) on keys and values ​​without the intervention of the file system interface or operating system (OS) and block device layer of the host 200, thereby improving the data processing speed.

[0125] Fig.16 is a block diagram illustrating an electronic device according to an example embodiment of the inventive concept.

[0126] Reference Fig.16 , the electronic device 3000 may include a processor 3100, a memory device 3200, a storage device 3300, a modem 3400, an input / output device 3500, and a power supply 3600. In one embodiment, the electronic device 3000 may include a processor 3100, a memory device 3200, a storage device 3300, a modem 3400, an input / output device 3500, and a power supply 3600. Figures 1 to 15 The described embodiment implements a storage device 3300 .

[0127] In one embodiment, the storage device 3300 may receive a key-value pair including a plurality of keys and a plurality of values ​​respectively corresponding to the plurality of keys from a host, and may separate the plurality of keys and the plurality of values ​​from the key-value pair.

[0128] In one embodiment, the storage device 3300 may generate a key stream by coupling an index corresponding to each value to each of a plurality of keys and merging the plurality of keys to which the indexes are respectively coupled. In addition, the storage device 3300 may generate a value stream by merging a plurality of values. In addition, the storage device 3300 may store the generated key stream and the generated value stream in a non-volatile storage device.

[0129] In one embodiment, in the process of compression, the storage device 3300 can only perform data access to the key stream without performing data access to the value stream, thereby deleting invalid keys and generating a key stream including valid keys. Therefore, in the process of compression by the storage device 3300, the amount of access data to the non-volatile storage device can be reduced, and the data processing speed can be improved.

[0130] In one embodiment, the storage device 3300 may also include a validity bit indicating whether each of the key stream and the value stream is valid in the mapping table indicating the storage location of the key stream and the value stream. Therefore, the storage device 3300 can effectively perform garbage collection on the key stream and the value stream.

[0131] In one embodiment, the storage device 3300 may perform the above operations by itself without receiving commands from the processor 3100 .

[0132] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: The controller is configured as: Receive multiple key-value pairs from the host, separating the key from each of the plurality of key-value pairs and separating the value from each of the plurality of key-value pairs, and generating a first key stream by merging a plurality of keys separated from the plurality of key-value pairs; and a non-volatile memory configured to store the first key stream, wherein the first key stream is stored in the non-volatile memory separately from the values ​​separated from each of the plurality of key-value pairs, wherein the controller reads the first key stream and the second key stream from the non-volatile memory in response to a compression command from the host, generates a third key stream by merging the first key stream and the second key stream, and stores the third key stream in the non-volatile memory, wherein the controller generates the third key stream by merging the first valid key of the first key stream and the second valid key of the second key stream, and Each of the first valid key and the second valid key corresponds to a value to which the host does not issue an erase command.

2. The storage device according to claim 1, wherein: The controller is further configured to generate the first key stream by merging a key of a corresponding one of the plurality of key-value pairs with an index corresponding to a value of the corresponding one of the plurality of key-value pairs.

3. The storage device according to claim 1, wherein: The controller is further configured to generate a value stream by merging a plurality of values ​​separated from the plurality of key-value pairs, and store the value stream in the non-volatile memory, and The value stream is stored in the non-volatile memory separately from the first key stream.

4. The storage device according to claim 3, further comprising: A volatile memory is configured to store a hash table and a value table, wherein the hash table includes physical addresses of the first key stream to the third key stream in the non-volatile memory, and the value table includes physical addresses of the value stream in the non-volatile memory.

5. A method for operating a storage device, the storage device comprising a non-volatile memory and a controller for controlling the non-volatile memory, the method comprising: The controller receives a plurality of key-value pairs; The controller generates a first key stream by extracting a key from each of the plurality of key-value pairs; The controller stores the first key stream in the non-volatile memory; as well as The controller performs a compression operation, the compression operation comprising: reading the first keystream and the second keystream from the nonvolatile memory; generating a third key stream by merging the first key stream and the second key stream; and storing the third keystream in the non-volatile memory, Wherein, generating the third key stream includes: generating the third key stream by extracting a first valid key from the first key stream and extracting a second valid key from the second key stream, and Each of the first valid key and the second valid key corresponds to a value among a plurality of values ​​to which the host does not issue an erase command.

6. The operating method according to claim 5, wherein: The generation of the first key stream includes: generating an index for a value of a corresponding one of a plurality of key-value pairs; and A key of a corresponding one of the plurality of key-value pairs is merged with the index.

7. The operating method according to claim 5, further comprising: The controller generates a stream of values ​​by extracting a value from each of the plurality of key-value pairs; as well as The controller stores the stream of values ​​in the non-volatile memory.

8. The operating method according to claim 5, further comprising: The controller generates a hash table including information about a storage location of at least one of the first key stream to the third key stream in the non-volatile memory; as well as The controller updates the hash table with an invalid key corresponding to the invalid value to which the host issued an erase command.

9. The operating method according to claim 8, further comprising: The controller generates a value table, the value table comprising physical addresses of the plurality of values ​​and at least one validity bit each indicating whether a corresponding value is valid; as well as The controller updates the value table with the validity bit of the value corresponding to the invalid key.

10. The operating method according to claim 9, further comprising: The controller performs garbage collection on the value corresponding to the invalid key by using at least one validity bit of the value table.

11. The operating method according to claim 7, further comprising: The controller generates a value table, the value table comprising: a physical address of at least one value included in the value stream; and A plurality of validity bits indicates whether a plurality of values ​​included in the value stream are valid.

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