Non-volatile memory device including temperature compensation circuit

Abstract

A nonvolatile memory device including a temperature compensation circuit is provided. The nonvolatile memory device includes a differential current driver receiving a first differential signal and a second differential signal based on a temperature, and generating a first compensation current and a second compensation current corresponding to a difference between the first differential signal and the second differential signal, a current mirror circuit copying a first current which is a sum of a reference current and the first compensation current to generate a second current having a same value as that of the first current, and adjusting the reference current according to a difference between the second current and the second compensation current, and a trimming circuit generating a program current or a read current based on the adjusted reference current.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0080879, filed on July 4, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Embodiments of the disclosure described herein relate to semiconductor memory, and more particularly, to a non-volatile memory device including a temperature compensation circuit. BACKGROUND

[0003] Semiconductor memory includes non-volatile memory such as phase change memory, ferroelectric memory, magnetic memory, resistive memory, and flash memory. In particular, among non-volatile memory, phase change memory can perform a program operation by changing a resistance value of a memory cell through a current, or can read data stored in a memory cell through a current.

[0004] When a program operation or a read operation is performed on a phase change memory cell, a current for the program operation or the read operation can vary according to a temperature of the phase change memory. That is, the current for the program operation or the read operation must be adjusted (or regulated) considering the temperature of the phase change memory. SUMMARY

[0005] Embodiments of the disclosure provide a non-volatile memory device capable of adjusting a current for an operation of the non-volatile memory device according to a temperature of the non-volatile memory device.

[0006] According to an exemplary embodiment, a non-volatile memory device includes a differential current driver receiving a first differential signal and a second differential signal based on a temperature, and generating a first compensation current and a second compensation current corresponding to a difference between the first differential signal and the second differential signal, a current mirror circuit copying a first current that is a sum of a reference current and the first compensation current to generate a second current having a same value as a value of the first current, and adjusting the reference current according to a difference between the second current and the second compensation current, and a trimming circuit generating a program current or a read current based on the adjusted reference current.

[0007] According to an exemplary embodiment, a nonvolatile memory device includes: a memory cell array including a plurality of memory cells; a temperature sensor that senses a temperature and generates first and second differential signals based on the sensed temperature; a reference current generator that generates a reference current; a current mirror circuit that generates first and second compensation currents corresponding to a difference between the first and second differential signals, duplicates a first current that is a sum of the reference current and the first compensation current to generate a second current having a same value as a value of the first current, and adjusts the reference current according to a difference between the second current and the second compensation current; and a write driver that drives a bit line or a word line connected to the memory cell array based on the adjusted reference current.

[0008] According to an exemplary embodiment, a nonvolatile memory device includes: a memory cell array including a plurality of memory cells; a temperature compensation circuit that adjusts a reference current for driving a bit line or a word line connected to the memory cell array based on first and second differential signals according to a temperature. The temperature compensation circuit includes: (1) a differential current driver that generates first and second compensation currents corresponding to a difference between the first and second differential signals; and (2) a current mirror circuit that duplicates a first current that is a sum of the reference current and the first compensation current to generate a second current having a same value as a value of the first current, and generates an adjusted reference current corresponding to a difference between the second current and the second compensation current.

[0009] According to an exemplary embodiment, a nonvolatile memory device includes: a current source that outputs a bias current having a value corresponding to a temperature compensation size signal; a first transistor connected to a first output terminal of the current source and outputting a first compensation current based on a first differential signal; a second transistor connected to the first output terminal of the current source and outputting a second compensation current based on a second differential signal; a third transistor connected to a second output terminal of the first transistor and outputting a reference current to the second output terminal based on a reference voltage; a fourth transistor connected to a common output terminal of the first and third transistors; a fifth transistor connected to a first gate terminal of the fourth transistor and a third output terminal of the second transistor; and a sixth transistor connected to the third output terminal and outputting an adjusted reference current to the third output terminal. The common output terminal, the first gate terminal of the fourth transistor, and a second gate terminal of the fifth transistor are interconnected. A difference between the first and second differential signals is changed according to the temperature. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above objects and other objects, features and advantages of the disclosed exemplary embodiments will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1is a block diagram of a non-volatile memory device according to disclosed embodiments.

[0012] Figure 2 is a block diagram illustrating an example of a memory cell of Figure 1 is a block diagram illustrating an example of a memory cell of

[0013] Figure 3 is a block diagram illustrating an example of a memory cell of Figure 1 is a block diagram illustrating another example of a memory cell of

[0014] Figure 4 is an exemplary circuit diagram of a memory cell array of Figure 2

[0015] Figure 5 illustrates an example of current pulses causing a program operation and a read operation in a memory cell of Figure 4

[0016] Figure 6 is a diagram illustrating an example of performing a program operation or a read operation on a selected memory cell according to disclosed embodiments.

[0017] Figure 7 is an exemplary block diagram of a current regulator of Figure 1

[0018] Figure 8 is a diagram illustrating an example of a compensation current of Figure 7

[0019] Figure 9 is a circuit diagram illustrating an example of a temperature compensation circuit of Figure 7

[0020] Figure 10 is a circuit diagram illustrating an additional example of a temperature compensation circuit of Figure 9

[0021] Figure 11 is a circuit diagram illustrating another example of a temperature compensation circuit of Figure 7

[0022] Figure 12 is a circuit diagram illustrating another example of a temperature compensation circuit of Figure 7

[0023] Figure 13 illustrates a structure of a non-volatile memory device according to disclosed embodiments.

[0024] Figure 14 illustrates an example of a structure of a non-volatile memory device according to disclosed embodiments.

[0025] Figure 15 ​​​​​​​​is a block diagram of a computing device to which a nonvolatile memory device according to disclosed embodiments is applied. DETAILED DESCRIPTION

[0026] Hereinafter, disclosed embodiments can be described in detail and clearly to the extent that a person of ordinary skill in the art can easily implement the disclosure.

[0027] Figure 1 is a block diagram of a nonvolatile memory device according to disclosed embodiments. Referring to Figure 1 , the nonvolatile memory device 100 can include a memory bank array 110, an address buffer 120, a command buffer 130, a control logic circuit 140, a reference current generator 150, a temperature sensor 160, a current regulator 170, and a data buffer 180.

[0028] The memory bank array 110 can include a first memory bank (bank 1) 111 to an nth memory bank (bank n) 11n. Each of the first memory bank 111 to the nth memory bank 11n can include a memory cell for storing data. The first memory bank 111 to the nth memory bank 11n can independently perform a program operation or a read operation from each other. The program operation can include a set operation of changing a logical value "0" to a logical value "1" and a reset operation of changing a logical value "1" to a logical value "0". The number of memory banks included in the memory bank array 110 is not limited.

[0029] The address buffer 120 can receive an address ADDR from an external device. The address buffer 120 can provide a memory bank address BA in the received address ADDR to the control logic circuit 140. The address buffer 120 can provide a row address RA and a column address CA in the received address ADDR to the memory bank array 110. The address buffer 120 can provide the row address RA and the column address CA to the memory bank selected by the control logic circuit 140 based on the memory bank address BA.

[0030] The command buffer 130 can receive a command CMD from an external device. The command buffer 130 can provide the received command CMD to the control logic circuit 140.

[0031] The control logic circuit 140 can control an operation of the nonvolatile memory device 100. The control logic circuit 140 can receive a control signal CTRL from an external device. The control logic circuit 140 can receive a memory bank address BA from the address buffer 120, and can receive a command CMD from the command buffer 130. The control logic circuit 140 can perform an operation based on the control signal CTRL, the memory bank address BA, and the command CMD.

[0032] The control logic circuit 140 can provide a temperature compensation control signal TC to the current regulator 170. For example, the control logic circuit 140 can receive the temperature compensation control signal TC from an external device through a control signal CTRL. The temperature compensation control signal TC is a signal for controlling a value of the operating current Ir generated by the current regulator 170. As such, a magnitude of the operating current Ir generated from the current regulator 170 can vary based on the temperature compensation control signal TC. The temperature compensation control signal TC can be determined according to a characteristic based on a temperature of the memory cells of the memory cell array 110, but the disclosure is not limited thereto.

[0033] The reference current generator 150 can generate a reference current Iref for various operations of the non-volatile memory device 100. For example, a program current for a program operation or a read current for a read operation can be generated based on the reference current Iref. The reference current generator 150 can provide the generated reference current Iref to the current regulator 170. The reference current generator 150 can provide a reference voltage Vref to the current regulator 170 to deliver the reference current Iref to the current regulator 170. The current regulator 170 can receive the reference current Iref based on the provided reference voltage Vref. For example, the reference current generator 150 can include a bandgap reference (BGR) circuit.

[0034] The temperature sensor 160 can sense a temperature of the non-volatile memory device 100. The temperature sensor 160 can generate a first differential signal DS1 and a second differential signal DS2 according to (based on) the sensed temperature. A difference between the first differential signal DS1 and the second differential signal DS2 can vary according to the sensed temperature. For example, the first differential signal DS1 and the second differential signal DS2 can be identical at a reference temperature. In this case, a difference between the first differential signal DS1 and the second differential signal DS2 can increase in a positive direction as the sensed temperature becomes higher than the reference temperature, and can increase in a negative direction as the sensed temperature becomes lower than the reference temperature. For example, the differential signals DS1 and DS2 can be voltage signals or current signals. The generated differential signals DS1 and DS2 can be provided to the current regulator 170.

[0035] The current regulator 170 can generate an operating current Ir to be provided to the memory cell array 110 based on the differential signals DS1 and DS2 and the reference current Iref. The current regulator 170 can adjust the reference current Iref according to a temperature of the non-volatile memory device 100, and can generate the operating current Ir. In detail, the current regulator 170 can generate a compensation current based on the differential signals DS1 and DS2 and the temperature compensation control signal TC. The current regulator 170 can adjust, regulate, or calibrate the reference current Iref based on the generated compensation current.

[0036] The current regulator 170 can generate an operating current Ir according to the operation of the non-volatile memory device 100. For example, when the non-volatile memory device 100 performs a programming operation, the current regulator 170 can generate an operating current Ir corresponding to the programming current value. When the non-volatile memory device 100 performs a read operation, the current regulator 170 can generate an operating current Ir corresponding to the read current value.

[0037] An operating current Ir can be provided to the memory array 110. The memory array 110 can perform various operations, including programming and reading operations, based on the operating current Ir.

[0038] Data buffer 180 can exchange data signal DQ with one of the memory banks selected from memory banks 111 to 11n. In addition, data buffer 180 can exchange data signal DQ with external devices.

[0039] As described above, the non-volatile memory device 100 may include components (e.g., a reference current generator 150, a temperature sensor 160, and a current regulator 170) that regulate the operating current Ir supplied to the memory array 110 based on the temperature of the non-volatile memory device 100. Thus, the non-volatile memory device 100 can perform various operations based on the temperature-dependent operating current Ir. For example, the non-volatile memory device 100 can regulate the programming current based on temperature and perform a programming operation; alternatively, the non-volatile memory device 100 can regulate the read current based on temperature and perform a read operation.

[0040] Figure 2 It is shown Figure 1 A block diagram of an example of a memory bank array. Figure 2 Storage 200 can be Figure 1 One of the first memory bank 111 to the nth memory bank 11n. (Refer to...) Figure 2 The storage unit 200 may include a memory cell array 210, a row decoder 220, a row driver 230, a column decoder 240, a write driver 250, and a sense amplifier 260.

[0041] The memory cell array 210 may include memory cells connected to word lines WL and bit lines BL. For example, memory cells in each row may be connected to one word line. Memory cells in each column may be connected to one bit line BL. For example, the memory cell array 210 may include phase-change memory cells.

[0042] The memory cell array 210 can be divided into a first cell region 211 to an m-th cell region 21m. Each of the first cell region 211 to the m-th cell region 21m can include memory cells corresponding to at least one bit line. Here, "m" which is the number of divided regions can correspond to the number of write drivers 250. For example, one cell region and one write driver can be defined as one bay in the memory bank 200.

[0043] The row decoder 220 is connected to the memory cell array 210 through the word line WL. The row decoder 220 can receive a row address RA from the address buffer 120. The row decoder 220 can select one of the word lines WL based on the row address RA. For example, the row decoder 220 can be configured to apply a selection voltage or a selection current to the selected word line. Also, the row decoder 220 can be configured to apply a non-selection voltage or a non-selection current to the unselected word line. Figure 1

[0044] The row driver 230 can apply a selection voltage or a selection current to the word line WL through the row decoder 220. For example, the row driver 230 can apply a program voltage to the word line WL in a program operation. The row driver 230 can apply a read voltage to the word line WL in a read operation.

[0045] The column decoder 240 is connected to the memory cell array 210 through the bit line BL. The column decoder 240 can receive a column address CA from the address buffer 120. The column decoder 240 can select at least one of the bit lines BL based on the column address CA. The selected bit line can be driven by the write driver 250 based on an operation current Ir. For example, in a program operation, the selected bit line can be driven by the write driver 250 based on a program current. In a read operation, the selected bit line can be driven by the write driver 250 based on a read current. Figure 1

[0046] The write driver 250 can drive the bit line BL based on the operation current Ir. In detail, the write driver 250 can drive the selected bit line such that the operation current Ir flows to the selected bit line. For example, in a program operation, the write driver 250 can drive the bit line BL based on the data signal DQ such that the operation current Ir flows to the bit line BL. In this case, the operation current Ir can correspond to a program current. As such, data can be written into the memory cell connected to the selected word line. For example, in a read operation, the write driver 250 can drive the bit line BL such that the operation current Ir flows to the bit line BL. In this case, the operation current Ir can correspond to a read current.

[0047] ​​For example, the write circuit 250 can write data by performing a set operation or a reset operation on the selected memory cell and changing a resistance value of the selected memory cell.

[0048] The sense amplifier 260 can read data from the selected memory cell by sensing a voltage of the bit line BL. For example, the sense amplifier 260 can read data by determining a range of a resistance value of the selected memory cell based on the sensed voltage. As such, the sense amplifier 260 can transfer a data signal DQ to Figure 1 the data buffer 180 of FIG. 1.

[0049] Figure 3 is a block diagram illustrating another example of a bank of a bank array of FIG. 1. In an example embodiment, Figure 1 the bank 300 of FIG. 1 can be one of the first bank 111 to the nth bank 11n of FIG. 1. Referring to Figure 3 , the bank 300 can include a memory cell array 310, a column decoder 320, a column driver 330, a row decoder 340, a write driver 350, and a sense amplifier 360. Figure 1 The operation of the bank 300 of FIG. 1 is similar to the operation of the bank 200 of FIG. 1, and thus additional description will be omitted to avoid redundancy. Figure 3 Figure 3 The memory cell array 310 can be divided into a first cell region 311 to an m-th cell region 31m. Each of the first cell region 311 to the m-th cell region 31m can include memory cells corresponding to at least one word line. Here, "m" which is the number of divided regions can correspond to the number of write drivers 350. For example, one cell region and one write driver can be defined as one section in the bank 300. Figure 2 The column decoder 320 can select at least one of the bit lines BL based on the column address CA. For example, the column decoder 320 can be configured to apply a selection voltage or a selection current to the selected bit line. Also, the column decoder 320 can be configured to apply a non-selection voltage or a non-selection current to the unselected bit line.

[0050] The column driver 330 can apply a selection voltage or a selection current to the bit line BL through the column decoder 320. For example, the column driver 330 can apply a program voltage to the bit line BL in a program operation. The column driver 330 can apply a read voltage to the bit line BL in a read operation.

[0051] The column driver 330 can apply a selection voltage or a selection current to the bit line BL through the column decoder 320. For example, the column driver 330 can apply a program voltage to the bit line BL in a program operation. The column driver 330 can apply a read voltage to the bit line BL in a read operation.

[0052]

[0053] ​​The row decoder 340 can select at least one of the word lines WL based on the row address RA. The selected word line can be driven by the write driver 350 based on the operation current Ir. For example, in a program operation, the selected word line can be driven by the write driver 350 based on a program current. In a read operation, the selected word line can be driven by the write driver 350 based on a read current.

[0054] The write driver 350 can drive the word lines WL based on the operation current Ir. In detail, the write driver 350 can drive the selected word line such that the operation current Ir flows to the selected word line. For example, in a program operation, the write driver 350 can drive the word lines WL based on the data signal DQ such that the operation current Ir flows to the word lines WL. In this case, the operation current Ir can correspond to a program current. As such, data can be written into the memory cells connected to the selected bit line. For example, in a read operation, the write driver 350 can drive the word lines WL such that the operation current Ir flows to the word lines WL. In this case, the operation current Ir can correspond to a read current.

[0055] The sense amplifier 360 can read data from the selected memory cell by sensing a voltage of the word line WL.

[0056] As described above, according to the disclosed embodiments, the write driver 250 or the write driver 350 can be set such that the operation current Ir flows through the bit line BL or the word line WL. Hereinafter, for the convenience of description, a detailed example for generating the operation current Ir will be described with reference to Figure 2 of the memory cell array 210.

[0057] Figure 4 is Figure 2 An exemplary circuit diagram of the memory cell array of the memory cell array 210. Referring to Figure 4 The memory cell array 210 includes memory cells MC. The memory cells MC can be arranged in rows and columns. The memory cells MC in a row can be connected to the first word line WL1 to the i-th word line WLi. The memory cells MC in a column can be connected to the first bit line BL1 to the j-th bit line BLj.

[0058] Each memory cell MC can be connected to one word line and one bit line. Each memory cell MC can include a selection element SE and a resistance element RE.

[0059] As Figure 4As shown, a resistor element RE can be connected between a word line from the first word line WL1 to the i-th word line WLi and a select element SE, and the select element SE can be connected between the resistor element RE and a bit line from the first bit line BL1 to the j-th bit line BLj. However, the disclosure is not limited to this. For example, the select element SE can be connected between a word line from the first word line WL1 to the i-th word line WLi and the resistor element RE, and the resistor element RE can be connected between the select element SE and a bit line from the first bit line BL1 to the j-th bit line BLj.

[0060] The resistive element RE may have a resistance value that changes through a set or reset operation. The resistive element RE may include a phase change material, the resistance of which varies depending on whether it is crystalline or amorphous. Specifically, the phase change material may have both amorphous and crystalline states, with the amorphous state having a relatively large resistance and the crystalline state having a relatively small resistance. Data can be written to each memory cell MC as the phase of the phase change material changes due to Joule heating generated by ambient temperature and the current flowing through the resistive element RE.

[0061] Figure 4 The example shown is that the selection element SE is a diode, but the disclosure is not limited thereto. For example, the selection element SE can be implemented using a switching element (e.g., a transistor).

[0062] Figure 5 Showing the cause Figure 4 Examples of current pulses for programming and reading operations in a memory cell. Figure 5 In the diagram, the horizontal axis represents time, and the vertical axis represents current.

[0063] Reference Figure 4 and Figure 5 Examples of current pulses flowing through the resistive element RE during programming operations are provided, as are examples of current pulses flowing through the resistive element RE during reading operations. Specifically, when a reset operation is performed, the RESET pulse flows through the resistive element RE of the selected memory cell; when a set operation is performed, the SET pulse flows through the resistive element RE of the selected memory cell. The RESET pulse can be provided for a shorter duration than the SET pulse and can have a higher current level than the SET pulse. When a read operation is performed, the READ pulse flows through the resistive element RE of the selected memory cell. The READ pulse can have a lower current level than the RESET and SET pulses.

[0064] when Figure 5The temperature of the resistive element RE can sharply increase and can sharply decrease during a short time period when the RESET pulse shown in FIG. 1 flows through the resistive element RE. In this case, the phase change material of the resistive element RE can have an amorphous state and can have a high resistance value (i.e., a logic value of "0"). When the SET pulse shown in FIG. 1 flows through the resistive element RE, the temperature of the resistive element RE can slowly increase and can slowly decrease. In this case, the phase change material of the resistive element RE can have a crystalline state and can have a low resistance value (i.e., a logic value of "1"). Figure 5

[0065] When the READ pulse shown in FIG. 1 flows through the resistive element RE, the voltage of the bit line can vary according to the resistance value of the resistive element RE. The data value stored in the selected memory cell can be determined from the voltage value of the bit line. Figure 5

[0066] Referring to FIG. 1, the memory cell SMC connected to the first word line WL1 and the first bit line BL1 can be selected for a programming operation or a read operation. Figure 5 An example of writing data into a selected memory cell based on RESET pulses and SET pulses having different current levels is described, but the disclosure is not limited thereto. For example, in a reset operation and a set operation, the resistive element RE can have a molten state by allowing a same level of current to flow through the resistive element RE. In this case, the resistance value of the resistive element RE can be changed by differently determining a time to cool the resistive element RE. For example, when the resistive element RE is rapidly cooled, the phase change material of the resistive element RE can have an amorphous state and can have a high resistance value. When the resistive element RE is slowly cooled, the phase change material of the resistive element RE can have a crystalline state and can have a low resistance value.

[0067] Figure 6 is a diagram illustrating an example of performing a program operation or a read operation on a selected memory cell according to an embodiment of the disclosure. Referring to Figure 6 The memory cell SMC connected to the second word line WL2 and the second bit line BL2 can be selected for a program operation or a read operation.

[0068] In the program operation, the row driver 230 can apply a program voltage to the second word line WL2 connected to the selected memory cell SMC, and the write driver 250 can drive the second bit line BL2 so that a program current IPGM flows to the second bit line BL2 connected to the selected memory cell SMC. In this case, a non-selection voltage (e.g., 0 V) can be applied to the remaining word lines and the remaining bit lines. The write driver 250 can drive the second bit line BL2 based on an operating current Ir provided from the current regulator 170 of FIG. 1. In this case, the operating current Ir can correspond to the program current IPGM. Figure 1

[0069] ​​​When the programming current IPGM flows to the second bit line BL2, the sum of the ON current Ion flowing through the selected memory cell SMC and the OFF current Ioff flowing through the unselected memory cells connected to the second bit line BL2 can be the same as the programming current IPGM. The OFF current Ioff flowing through each unselected memory cell can be a leakage current. In this case, the programming current IPGM can need to be allowed to have a current level for the reset operation or the set operation for the ON current Ion flowing through the selected memory cell SMC.

[0070] When the temperature of the nonvolatile memory device 100 changes, the value of the OFF current Ioff flowing through each unselected memory cell can change. For example, when the temperature increases, the value of the OFF current Ioff can increase. Also, when the temperature of the nonvolatile memory device 100 changes, the value of the ON current Ion required for the programming operation can change. For example, when the temperature increases, the value of the ON current Ion required for the reset operation or the set operation can decrease. As such, the value of the programming current IPGM required for the programming operation can change according to the temperature of the nonvolatile memory device 100. That is, the value of the operating current Ir delivered to the write driver 250 can change according to the temperature.

[0071] In the read operation, the row driver 230 can apply a read voltage to the second word line WL2 connected to the selected memory cell SMC, and the write driver 250 can drive the second bit line BL2 so that a read current IREAD flows to the second bit line BL2 connected to the selected memory cell SMC. In this case, a non-selection voltage (e.g., 0 V) can be applied to the remaining word lines and the remaining bit lines. The write driver 250 can drive the second bit line BL2 based on the operating current Ir provided from the current regulator 170 of FIG. 1. In this case, the operating current Ir can correspond to the read current IREAD. Figure 1

[0072] When the read current IREAD flows to the second bit line BL2, the sum of the ON current Ion flowing through the selected memory cell SMC and the OFF current Ioff flowing through the unselected memory cells connected to the second bit line BL2 can be the same as the read current IREAD. The OFF current Ioff flowing through each unselected memory cell can be a leakage current. In this case, the read current IREAD can need to be allowed to have a current level for the ON current Ion flowing through the selected memory cell SMC for the read operation.

[0073] ​When the temperature of the non-volatile memory device 100 changes, the value of the OFF current Ioff flowing through each unselected memory cell can change. Furthermore, when the temperature of the non-volatile memory device 100 changes, the value of the ON current Ion required for the read operation can change. Thus, the value of the read current IREAD required for the read operation can change according to the temperature of the non-volatile memory device 100. In other words, the value of the operating current Ir transmitted to the write driver 250 can change according to the temperature.

[0074] As mentioned above, the value of the operating current Ir supplied to the write driver 250 during programming and reading operations can vary depending on the temperature. (See reference...) Figure 1 The current regulator 170 can adjust the value of the operating current Ir supplied to the write driver 250. Hereinafter, reference will be made to... Figures 7 to 12 Describes a current regulator 170 that adjusts the value of the operating current Ir according to temperature.

[0075] Figure 7 yes Figure 1 An exemplary block diagram of a current regulator. (Refer to...) Figure 7 The current regulator 170 may include a temperature compensation circuit 171 and a trimming circuit 174. The temperature compensation circuit 171 may include a differential current driver 172 and a current mirror circuit 173.

[0076] The differential current driver 172 can receive differential signals DS1 and DS2 generated based on the temperature of the non-volatile memory device 100 from the temperature sensor 160, and can receive a temperature compensation control signal TC from the control logic circuit 140. The differential current driver 172 can generate compensation currents Itc1 and Itc2 based on the differential signals DS1 and DS2 and the temperature compensation control signal TC. In this case, the difference between the compensation currents Itc1 and Itc2 can vary according to the differential signals DS1 and DS2 and the temperature compensation control signal TC. Because the differential signals DS1 and DS2 depend on the temperature, the difference between the compensation currents Itc1 and Itc2 can vary according to the temperature.

[0077] The current mirror circuit 173 can receive the compensation current Itcl and the compensation current Itc2 from the differential current driver 172. The current mirror circuit 173 can receive the reference voltage Vref corresponding to the reference current Iref from the reference current generator 150. For example, the current mirror circuit 173 can replicate the reference current Iref generated from the reference current generator 150 based on the reference voltage Vref. The current mirror circuit 173 can generate the compensation reference current Icr based on the reference current Iref and the compensation current Itcl and the compensation current Itc2. For example, the compensation reference current Icr can have a value obtained by adding the difference (Itcl-Itc2) of the compensation current Itcl and the compensation current Itc2 to the reference current Iref. When the difference (Itcl-Itc2) is positive, the compensation reference current Icr can be greater than the reference current Iref. When the difference (Itcl-Itc2) is negative, the compensation reference current Icr can be less than the reference current Iref. In an exemplary embodiment, the sign of the difference (Itcl-Itc2) can vary according to the temperature compensation control signal TC. As such, the current mirror circuit 173 can adjust the reference current Iref according to the temperature of the nonvolatile memory device 100, and can generate the compensation reference current Icr. Alternatively, the differential current driver 172 can be included in the current mirror circuit 173.

[0078] The current mirror circuit 173 can output the compensation reference current Icr to the trimming circuit 174. In detail, the current mirror circuit 173 can output the compensation reference current Icr to the trimming circuit 174 by providing the compensation reference voltage Vcr corresponding to the compensation reference current Icr to the trimming circuit 174.

[0079] The trimming circuit 174 can receive the compensation reference voltage Vcr corresponding to the compensation reference current Icr from the current mirror circuit 173. For example, the trimming circuit 174 can replicate the compensation reference current Icr generated from the current mirror circuit 173 based on the compensation reference voltage Vcr.

[0080] The trimming circuit 174 can trim the compensation reference current Icr according to the operation of the nonvolatile memory device 100, and can generate the operation current Ir. For example, in a program operation, the trimming circuit 174 can trim the compensation reference current Icr, and can generate the operation current Ir for performing a reset operation or a set operation. In a read operation, the trimming circuit 174 can trim the compensation reference current Icr, and can generate the operation current Ir for performing a read operation.

[0081] In a particular operation (e.g., a program operation or a read operation), the value of the operation current Ir generated from the trim circuit 174 can vary according to the compensation reference current Icr provided from the temperature compensation circuit 171. That is, the value of the operation current Ir can vary according to the temperature in the particular operation. For example, the operation current Ir generated for a program operation at a first temperature can be different from the operation current Ir generated for a program operation at a second temperature.

[0082] The trim circuit 174 can output the generated operation current Ir to the write driver 250. For example, the write driver 250 can receive the operation current Ir by copying the operation current Ir generated from the trim circuit 174.

[0083] Figure 8 is a graph illustrating an example of the compensation current of Figure 7 In Figure 8 , the horizontal axis indicates a difference (DS2 - DS1) between the second differential signal DS2 and the first differential signal DS1, and the vertical axis indicates the value of the compensation current. Here, the difference (DS2 - DS1) can correspond to the temperature of the nonvolatile memory device 100.

[0084] Referring to Figure 8 , as the difference (DS2 - DS1) increases, the first compensation current Itc1 can increase, and the second compensation current Itc2 can decrease. When the difference (DS2 - DS1) is "0", the first compensation current Itc1 can be the same as the second compensation current Itc2. As the difference (DS2 - DS1) decreases, the first compensation current Itc1 can decrease, and the second compensation current Itc2 can increase. Here, the sum of the first compensation current Itc1 and the second compensation current Itc2 can be the maximum compensation current value Imc. That is, as the difference (DS2 - DS1) varies according to the temperature, the compensation current Itc1 and the compensation current Itc2 can vary within the maximum compensation current value Imc.

[0085] In an exemplary embodiment, the maximum compensation current value Imc can be adjusted to adjust the size of the compensation reference current Icr. In detail, the control logic circuit 140 can generate a temperature compensation control signal TC for adjusting the maximum compensation current value Imc. The differential current driver 172 can adjust the size of the compensation current Itcl and the compensation current Itc2 at the same ratio based on the temperature compensation control signal TC. For example, in a case where each of the compensation current Itcl and the compensation current Itc2 is increased at the same ratio based on the temperature compensation control signal TC, the maximum compensation current value Imc can also be increased at the same ratio. The current mirror circuit 173 can generate the compensation reference current Icr based on the compensation current Itcl and the compensation current Itc2 adjusted according to the temperature compensation control signal TC. As such, the compensation reference current Icr generated at a certain temperature can vary according to the temperature compensation control signal TC.

[0086] In an exemplary embodiment, the differential signals DS1 and DS2 transmitted to the differential current driver 172 can be selectively swapped to adjust the magnitude of the compensation reference current Icr. For example, the differential signals DS1 and DS2 can be swapped such that the second differential signal DS2 is transmitted to the first input line to which the first differential signal DS1 is transmitted, and the first differential signal DS1 is transmitted to the second input line to which the second differential signal DS2 is transmitted. Specifically, the control logic circuit 140 can generate a temperature compensation control signal TC for swapping the differential signals DS1 and DS2. The differential current driver 172 can swap the differential signals DS1 and DS2 based on the temperature compensation control signal TC, and can generate compensation currents Itc1 and Itc2. For example, based on the temperature compensation control signal TC, the first differential signal DS1 can be transmitted to the first input line, and the second differential signal DS2 can be transmitted to the second input line. The differential current driver 172 can generate a first compensation current Itc1 with a first current value i1 and a second compensation current Itc2 with a second current value i2 based on a first value v1, which is the difference (DS2–DS1). In this case, because the first compensation current Itc1 is greater than the second compensation current Itc2, the current mirror circuit 173 can generate a compensation reference current Icr that is greater than the reference current Iref. For example, based on the temperature compensation control signal TC, the second differential signal DS2 can be transmitted to the first input line, and the first differential signal DS1 can be transmitted to the second input line. The differential current driver 172 can generate a first compensation current Itc1 with a second current value i2 and a second compensation current Itc2 with a first current value i1 based on a second value v2, which is the difference (DS2–DS1). In this case, because the first compensation current Itc1 is less than the second compensation current Itc2, the current mirror circuit 173 can generate a compensation reference current Icr that is less than the reference current Iref. Thus, the compensation reference current Icr generated at a specific temperature can vary according to the temperature compensation control signal TC.

[0087] The following will refer to Figures 9 to 12 A more comprehensive description Figure 7 Configuration of temperature compensation circuit 171.

[0088] Figure 9 It is shown Figure 7 A circuit diagram of an example temperature compensation circuit. (Refer to...) Figure 9 The temperature compensation circuit 271 may include a differential current driver 272 and a current mirror circuit 273.

[0089] The differential current driver 272 can include a current source CS, a first transistor TR1, and a second transistor TR2. The current source CS can output a bias current, the magnitude of which is selected based on a temperature compensation magnitude signal TC_A. That is, the level of the current output based on the temperature compensation magnitude signal TC_A can be variable.

[0090] The temperature compensation magnitude signal TC_A can be included in a temperature compensation control signal TC of Figure 7 For example, the temperature compensation magnitude signal TC_A can be a binary code. The current output from the current source CS can be the same as a maximum compensation current value Imc of Figure 8 Thus, as described with reference to Figure 8 the maximum compensation current value Imc can be adjusted based on the temperature compensation magnitude signal TC_A.

[0091] A first end (or terminal) of the first transistor TR1 can be connected to an output terminal of the current source CS, and a second end of the first transistor TR1 can be connected to a first node N1 of the current mirror circuit 273. A first differential voltage Vd1 as a first differential signal DS1 can be applied to a gate terminal of the first transistor TR1. A first end of the second transistor TR2 can be connected to the output terminal of the current source CS, and a second end of the second transistor TR2 can be connected to a second node N2 of the current mirror circuit 273. A second differential voltage Vd2 as a second differential signal DS2 can be applied to a gate terminal of the second transistor TR2. That is, the differential voltage Vd1 and the differential voltage Vd2 determined according to the temperature of the nonvolatile memory device 100 can be provided to the first transistor TR1 and the second transistor TR2.

[0092] In a case where the first transistor TR1 and the second transistor TR2 have substantially the same characteristics, the current output from the current source CS can be distributed into the first transistor TR1 and the second transistor TR2 according to the differential voltage Vd1 and the differential voltage Vd2. As such, the first transistor TR1 can output a first compensation current Itc1 based on the first differential voltage Vd1, and the second transistor TR2 can output a second compensation current Itc2 based on the second differential voltage Vd2. The first compensation current Itc1 thus output can be provided to the first node N1 of the current mirror circuit 273, and the second compensation current Itc2 thus output can be provided to the second node N2 of the current mirror circuit 273.

[0093] The current mirror circuit 273 can include third through sixth transistors TR3 through TR6. A power supply voltage VDD can be applied to a first terminal of the third transistor TR3, and a second terminal of the third transistor TR3 can be connected to the first node N1. A reference voltage Vref can be applied to a gate terminal of the third transistor TR3. The third transistor TR3 can generate a reference current Iref based on the reference voltage Vref.

[0094] A first terminal of the fourth transistor TR4 can be connected to the first node N1 and a gate terminal of the fourth transistor TR4, and a ground voltage VSS can be applied to a second terminal of the fourth transistor TR4. A current flowing from the first node N1 to the fourth transistor TR4 can be a current (Iref+Itc1) that is a sum of the reference current Iref and a first compensation current Itc1, according to the reference current Iref and the first compensation current Itc1 provided to the first node N1.

[0095] A first terminal of the fifth transistor TR5 can be connected to the second node N2, and a ground voltage VSS can be applied to a second terminal of the fifth transistor TR5. A gate terminal of the fifth transistor TR5 can be connected to the gate terminal of the fourth transistor TR4. The fifth transistor TR5 can replicate the current (Iref+Itc1) flowing to the fourth transistor TR4, and can generate the same current (Iref+Itc1) as a value of the current (Iref+Itc1) flowing through the fourth transistor TR4. As such, the current (Iref+Itc1) can flow from the second node N2 to the fifth transistor TR5.

[0096] A power supply voltage VDD can be applied to a first terminal of the sixth transistor TR6, and a second terminal of the sixth transistor TR6 can be connected to the second node N2. A gate terminal of the sixth transistor TR6 can be connected to the second terminal of the sixth transistor TR6. The sixth transistor TR6 can generate a compensation reference current Icr, and can output the compensation reference current Icr to the second node N2. Because a second compensation current Itc2 is input from the differential current driver 272 to the second node N2, and the current (Iref+Itc1) flows from the second node N2 to the fifth transistor TR5, the compensation reference current Icr can be represented by Equation 1 below.

[0097] [Equation 1]

[0098] Icr = Iref + Itc1 - Itc2

[0099] Referring to Equation 1, the compensation reference current Icr can have a value obtained by adding the difference (Itc1-Itc2) of the compensation current Itc1 and the compensation current Itc2 to the reference current Iref. Because the difference (Itc1-Itc2) varies according to the differential voltage Vd1 and the differential voltage Vd2 and the temperature compensation magnitude signal TC_A, the compensation reference current Icr based on the temperature of the nonvolatile memory device 100 can be generated through the sixth transistor TR6.

[0100] When the compensation reference current Icr is generated, the compensation reference voltage Vcr can be output from the gate terminal of the sixth transistor TR6. The compensation reference voltage Vcr can be provided to the trimming circuit 174 of Figure 7 . In this way, the trimming circuit 174 can reproduce the compensation reference current Icr generated from the current mirror circuit 273 based on the compensation reference voltage Vcr.

[0101] According to the temperature compensation circuit 271 of Figure 9 , the difference (Itc1-Itc2) of the compensation current Itc1 and the compensation current Itc2 can maintain the same sign at a certain temperature. For example, the difference (Itc1-Itc2) can be positive at a certain temperature. In this case, the compensation reference current Icr can increase at the certain temperature. However, because of various circumstances such as memory cell characteristics, it is necessary to increase or decrease the compensation reference current Icr at the certain temperature.

[0102] Hereinafter, the temperature compensation circuit 271 capable of increasing or decreasing the compensation reference current Icr will be described with reference to Figure 10 .

[0103] Figure 10 is a circuit diagram illustrating an additional example of the temperature compensation circuit of Figure 9 . Referring to Figure 10The differential current driver 272 may further include a switching circuit 274. The switching circuit 274 can receive a first differential voltage Vd1 as a first differential signal DS1 and a second differential voltage Vd2 as a second differential signal DS2. Based on the temperature compensation symbol signal TC_S, the switching circuit 274 can output one of the differential voltages Vd1 and Vd2 to the first input line L1 and the remaining differential voltage of Vd1 and Vd2 to the second input line L2. The differential voltages Vd1 and Vd2 transmitted to the first input line L1 and the second input line L2, respectively, can be switched based on the temperature compensation symbol signal TC_S. The first input line L1 can be connected to the gate terminal of the first transistor TR1, and the second input line L2 can be connected to the gate terminal of the second transistor TR2. Thus, the differential voltages Vd1 and Vd2 transmitted to the gate terminals of the first transistor TR1 and the second transistor TR2, respectively, can be switched based on the temperature compensation symbol signal TC_S. Here, the temperature compensation symbol signal TC_S may be included in the circuit from... Figure 7 The temperature compensation control signal TC is provided by the control logic circuit 140.

[0104] like Figure 10 As shown, based on the temperature compensation symbol signal TC_S, a second differential voltage Vd2 can be applied to the gate terminal of the first transistor TR1, and a second differential voltage Vd1 can be applied to the gate terminal of the second transistor TR2. In this case, with Figure 9 In contrast, differential voltages Vd1 and Vd2 can be applied to different gate terminals. The first transistor TR1 can output a first compensation current Itc1 based on the second differential voltage Vd2, and the second transistor TR2 can output a second compensation current Itc2 based on the first differential voltage Vd1. Thus, the compensation currents Itc1 and Itc2 output from the differential current driver 272 can have different values ​​depending on the voltage distribution. Figure 9 The values ​​of the compensation current Itc1 and the compensation current Itc2 are obtained.

[0105] For example, when Figure 9 When the difference (Itc1-Itc2) between the compensation current Itc1 and the compensation current Itc2 is positive, Figure 10 The difference (Itc1-Itc2) between the compensation current Itc1 and the compensation current Itc2 can be a negative number of the same magnitude. In this case, Figure 9 The compensation reference current Icr can be greater than the reference current Iref, and Figure 10 The compensation reference current Icr can be less than the reference current Iref. Therefore, when the differential signals DS1 and DS2 are exchanged through the switching circuit 274, the compensation reference current Icr generated at a specific temperature can be changed.

[0106] As described above, when the input differential signals DS1 and DS2 are exchanged in accordance with the temperature compensation sign signal TC_S, the compensation reference current Icr can become greater or smaller than the reference current Iref.

[0107] Figure 11 is a circuit diagram illustrating another example of a temperature compensation circuit of Figure 7 Referring to Figure 11 , the temperature compensation circuit 371 can include a differential current driver 372 and a current mirror circuit 373. Since the configuration of the current mirror circuit 373 is substantially the same as that of the current mirror circuit 273 of Figure 9 , the temperature compensation circuit 371 will be described with reference to the differential current driver 372.

[0108] The differential current driver 372 can include a current source CS, a first transistor TR1, and a second transistor TR2. The current source CS can output a bias current, the magnitude of which is predetermined. A first differential voltage Vd1 is applied to a gate terminal of the first transistor TR1 as a first differential signal DS1, and a second differential voltage Vd2 is applied to a gate terminal of the second transistor TR2 as a second differential signal DS2.

[0109] An example in which each of the first transistor TR1 and the second transistor TR2 is implemented with one transistor is illustrated in Figure 11 , but each of the first transistor TR1 and the second transistor TR2 can be one transistor selected from among a plurality of transistors based on the temperature compensation magnitude signal TC_A. In this case, the width of each of the first transistor TR1 and the second transistor TR2 can vary according to at least one transistor. The width of the first transistor TR1 and the second transistor TR2 can be selected based on the temperature compensation magnitude signal TC_A. As illustrated in Figure 11 , when the width of the first transistor TR1 and the second transistor TR2 is selected by the same temperature compensation magnitude signal TC_A, the width of the first transistor TR1 and the second transistor TR2 can be the same.

[0110] When the width of the first transistor TR1 and the second transistor TR2 is selected, the values of the compensation currents Itc1 and Itc2 output by the first transistor TR1 and the second transistor TR2 can be adjusted according to the selected width. When the width of the first transistor TR1 and the second transistor TR2 varies based on the temperature compensation magnitude signal TC_A, the values of the compensation currents Itc1 and Itc2 can vary. As such, as described with reference to Figure 8 , the maximum compensation current value Imc can vary, and the value of the compensation reference current Icr can vary.

[0111] Although in the above description, the temperature compensation circuit 371 is described as being implemented with the differential current driver 372 and the current mirror circuit 373, the temperature compensation circuit 371 can be implemented with another configuration.Figure 11 The temperature compensation circuit 371, which is not shown, but like the temperature compensation circuit 271 of Figure 10 , can also include a switching circuit capable of switching the differential signal DS1 and the differential signal DS2. In this case, the temperature compensation circuit 371 can switch the input differential signal DS1 and the differential signal DS2 according to the temperature compensation sign signal TC_S.

[0112] Figure 12 is a circuit diagram illustrating another example of a temperature compensation circuit of Figure 7 . Referring to Figure 12 , the temperature compensation circuit 471 can include a differential current driver 472 and a current mirror circuit 473. Since the configuration of the current mirror circuit 473 is substantially the same as that of the current mirror circuit 273 of Figure 9 , the temperature compensation circuit 471 will be described with reference to the differential current driver 472.

[0113] The differential current driver 472 can include a first transistor TR1, a second transistor TR2, a seventh transistor TR7, and an eighth transistor TR8. A power supply voltage VDD can be applied to a first terminal of the seventh transistor TR7, and a second terminal and a gate terminal of the seventh transistor TR7 can be interconnected. As a first differential signal DS1, a first differential current Id1 can be input to the second terminal of the seventh transistor TR7. In this case, a first differential voltage Vid1 can be generated at the gate terminal of the seventh transistor TR7 based on the first differential current Id1. The first differential voltage Vid1 thus generated can be provided to a gate terminal of the first transistor TR1.

[0114] The power supply voltage VDD can be applied to a first terminal of the eighth transistor TR8, and a second terminal and a gate terminal of the eighth transistor TR8 can be interconnected. As a second differential signal DS2, a second differential current Id2 can be input to the second terminal of the eighth transistor TR8. In this case, a second differential voltage Vid2 can be generated at the gate terminal of the eighth transistor TR8 based on the second differential current Id2. The second differential voltage Vid2 thus generated can be provided to a gate terminal of the second transistor TR2.

[0115] The power supply voltage VDD can be applied to a first terminal of the first transistor TR1, and the first differential voltage Vid1 can be applied to a gate terminal of the first transistor TR1. The first transistor TR1 can output a first compensation current Itc1 based on the first differential voltage Vid1.

[0116] A power voltage VDD can be applied to a first terminal of the second transistor TR2, and a second differential voltage Vid2 can be applied to a gate terminal of the second transistor TR2. The second transistor TR2 can output a second compensation current Itc2 based on the second differential voltage Vid2.

[0117] The widths of the first transistor TR1 and the second transistor TR2 can be selected based on the temperature compensation size signal TC_A. When the widths of the first transistor TR1 and the second transistor TR2 are selected, the values of the compensation currents Itc1 and Itc2 output through the first transistor TR1 and the second transistor TR2 can be adjusted according to the selected widths. As such, as described with reference to Figure 8 the maximum compensation current value Imc can vary, and the value of the compensation reference current Icr can vary.

[0118] Although not shown in Figure 12 , like the temperature compensation circuit 271 of Figure 10 , the temperature compensation circuit 471 can further include a swapping circuit capable of swapping the differential signal DS1 and the differential signal DS2. In this case, the temperature compensation circuit 471 can swap the input differential signal DS1 and the differential signal DS2 according to the temperature compensation sign signal TC_S. As such, the differential voltage Vid1 and the differential voltage Vid2 delivered to the gate terminals of the first transistor TR1 and the second transistor TR2, respectively, can be swapped.

[0119] As described above, each of the temperature compensation circuit 271, the temperature compensation circuit 371, and the temperature compensation circuit 471 according to the disclosed embodiments can generate the compensation currents Itc1 and Itc2 based on the differential currents Id1 and Id2 and the differential voltages Vd1 and Vd2 as the differential signals DS1 and DS2.

[0120] As described with reference to Figures 9 to 12 , the temperature compensation circuit 271, the temperature compensation circuit 371, and the temperature compensation circuit 471 according to the disclosed embodiments can be implemented with transistors. In this case, the temperature compensation circuit 271, the temperature compensation circuit 371, and the temperature compensation circuit 471 can not include a capacitor and a feedback loop. Accordingly, the power consumption of each of the temperature compensation circuit 271, the temperature compensation circuit 371, and the temperature compensation circuit 471 according to the disclosed embodiments can be reduced, and the area of each of the temperature compensation circuit 271, the temperature compensation circuit 371, and the temperature compensation circuit 471 can be minimized. Further, the temperature compensation circuit 271, the temperature compensation circuit 371, and the temperature compensation circuit 471 have no stability problem due to the feedback loop.

[0121] Figure 13 A structure of a nonvolatile memory device according to disclosed embodiments is shown. Referring to Figure 13 , the nonvolatile memory device 500 includes a plurality of memory cells MC. Each memory cell MC can include a selection element SE and a resistance element RE as described with reference to Figure 4 The memory cells MC can be disposed between word lines extending in a first direction and bit lines extending in a second direction perpendicular to the first direction. In this case, the selection elements SE and the resistance elements RE can be arranged in a third direction. For example, the resistance elements RE can be connected between the first word line WL1 and the selection elements SE, and the selection elements SE can be connected between the resistance elements RE and the first bit line BL1.

[0122] The plurality of memory cells MC can be disposed in a first layer (Layer 1) or can be disposed in a second layer (Layer 2). In this case, the memory cells MC of the second layer can be stacked in the third direction with respect to the memory cells MC of the first layer. As shown in Figure 13 , the memory cells MC of the first layer can be connected between the first to fourth word lines WL1 to WL4 and the first to fourth bit lines BL1 to BL4, and the memory cells MC of the second layer can be connected between the fifth to eighth word lines WL5 to WL8 and the first to fourth bit lines BL1 to BL4. In this case, the first to fourth bit lines BL1 to BL4 can be connected to both the memory cells MC of the first layer and the memory cells MC of the second layer. However, the disclosure is not limited thereto. For example, the bit lines can be separately provided for each layer.

[0123] As described with reference to Figures 1 to 12 , the nonvolatile memory device 500 can drive the word lines or the bit lines disposed to cross each other based on the adjusted program current or the adjusted read current.

[0124] Figure 13 An example of a structure of the nonvolatile memory device 500 is shown, in which the number of word lines, the number of bit lines, and the number of layers can be variously changed or modified, in which the word lines and the bit lines are disposed to cross each other.

[0125] Figure 14 An example of a structure of a nonvolatile memory device according to disclosed embodiments is shown. Referring to Figure 14 , the nonvolatile memory device 600 can include a peripheral layer and a memory cell layer. The peripheral layer can include a first layer L1, and the memory cell layer can include a second layer L2 to an n-th layer Ln.

[0126] The peripheral layer can include various peripheral circuits of the nonvolatile memory device 600. For example, as described with reference to Figures 1 to 12The peripheral layer can include a current regulator 670 that regulates an operating current of the nonvolatile memory device 600. The peripheral layer can be disposed at a lowermost end in a direction opposite to the third direction.

[0127] The memory cell layer can include a plurality of memory cells. Each memory cell of the plurality of memory cells can be connected to one word line and one bit line. The memory cell layer can be disposed on / over the peripheral layer in the third direction. In this case, the second layer L2 to the nth layer Ln can be stacked in the third direction. For example, the first layer L1 can be disposed on a first base, and the second layer L2 can be disposed on a second base. In this case, the second base can be disposed on the first layer L1.

[0128] As described with reference to Figures 1 to 12 The nonvolatile memory device 600 can drive a word line or a bit line disposed in the layers L2 to Ln based on the regulated programming current or the regulated read current. In an exemplary embodiment, the nonvolatile memory device 600 can regulate an operating current for each layer, and can drive a word line or a bit line. For example, the nonvolatile memory device 600 can drive a first word line WL1 or a first bit line BL1 of a first memory cell MC1 connected to the second layer L2 based on a first read current IREAD1 or a first programming current IPGM1. The nonvolatile memory device 600 can drive a third word line WL3 or a third bit line BL3 of a third memory cell MC3 connected to the nth layer Ln based on a third read current IREAD3 or a third programming current IPGM3. In this case, the first read current IREAD1 and the third read current IREAD3 can be different, and the first programming current IPGM1 and the third programming current IPGM3 can be different at the same temperature. For example, the current can be regulated so that a relatively large current flows to a layer having a relatively high position in the third direction.

[0129] In an exemplary embodiment, the nonvolatile memory device 600 can adjust an operating current according to a position of a memory cell in the same layer, and can drive a word line or a bit line. For example, in the second layer L2, the first memory cell MC1 can be connected to the first word line WL1 and the first bit line BL1, and the second memory cell MC2 can be connected to the second word line WL2 and the second bit line BL2. In this case, a length of a current path through which a current flows from the first word line WL1 to the first bit line BL1 through the first memory cell MC1 can be shorter than a length of a current path through which a current flows from the second word line WL2 to the second bit line BL2 through the second memory cell MC2. The nonvolatile memory device 600 can drive the first word line WL1 or the first bit line BL1 connected to the first memory cell MC1 of the second layer L2 based on the first read current IREAD1 or the first program current IPGM1. The nonvolatile memory device 600 can drive the second word line WL2 or the second bit line BL2 connected to the second memory cell MC2 of the second layer L2 based on the second read current IREAD2 or the second program current IPGM2. In this case, the first read current IREAD1 and the second read current IREAD2 can be different, and the first program current IPGM1 and the second program current IPGM2 can be different at the same temperature. For example, the current can be adjusted so that a relatively large current flows to a memory cell corresponding to a current path having a relatively long length.

[0130] As described above, the nonvolatile memory device 600 can adjust an operating current for driving a word line or a bit line based on a layer of a memory cell and a position of the memory cell as well as a temperature. The operating current according to the layer and the position can be adjusted by the current regulator 670, but the disclosure is not limited thereto. For example, the operating current can be adjusted by a separate circuit. As described above, the nonvolatile memory device 600 according to the disclosure can adjust an operating current according to a layer and a position. Figure 14 As with the nonvolatile memory device 600 according to the disclosure, a nonvolatile memory device having various structures can adjust an operating current according to a layer and a position.

[0131] Figure 15 is a block diagram of a computing device to which a nonvolatile memory device according to an embodiment of the disclosure is applied. Referring to Figure 15 , the computing device 1000 can include a processor 1100, a memory controller 1200, a main memory 1300, a system interconnection 1400, a storage device 1500, a user interface 1600, and a modem 1700. The computing device 1000 can be implemented with one of various computing devices, such as a desktop computer, a notebook computer, a data server, an application server, a smart phone, and a smart pad.

[0132] The processor 1100 can be a central processing unit (CPU) or an application processor (AP) that performs various operations. The processor 1100 can control various components of the computing device 1000 to perform a programming operation, a read operation, or any other operation. For example, the processor 1100 can access the main memory 1300 by using the memory controller 1200.

[0133] The memory controller 1200 can allow the main memory 1300 to perform a programming operation or a read operation under the control of the processor 1100. For example, the memory controller 1200 can provide a command CMD, an address ADDR, and a control signal CTRL to the main memory 1300 so that a data signal DQ is stored therein.

[0134] The main memory 1300 can receive the address ADDR, the command CMD, and the control signal CTRL from the memory controller 1200. The main memory 1300 can exchange the data signal DQ with the memory controller 1200. The main memory 1300 can include a non-volatile memory device 100, a non-volatile memory device 500, and a non-volatile memory device 600 described with reference to FIGS. 1 to 6. Figures 1 to 14 One of the non-volatile memory devices 100, 500, and 600 described can be included in the main memory 1300. For example, the main memory 1300 can generate a compensation current based on a differential signal according to a temperature of the main memory 1300. The main memory 1300 can adjust a current required for a programming operation or a read operation based on the generated compensation current.

[0135] The system interconnection 1400 can provide a channel between components of the computing device 1000. The system interconnection 1400 can be implemented in one of various standards, such as Peripheral Component Interconnect Express (PCIe) and Advanced Microcontroller Bus Architecture (AMBA).

[0136] The storage device 1500 can serve as an auxiliary memory of the computing device 1000. The storage device 1500 can have a slower access speed than the main memory 1300 and can have a higher storage capacity than the main memory 1300. The storage device 1500 can include a hard disk drive (HDD), a solid state drive (SSD), a portable memory, or the like.

[0137] The user interface 1600 can exchange information with a user. The user interface 1600 can include a user input interface (such as a keypad, a mouse, a touch panel, or a microphone) that receives information from a user and a user output interface (such as a monitor, a speaker, or a motor) that provides information to a user.

[0138] The modem 1700 is configured to perform wired communication or wireless communication with an external device. The modem 1700 can be configured to implement at least one of various standards such as Long Term Evolution (LTE), Ethernet, Wireless Fidelity (Wi-Fi), and Bluetooth. In an exemplary embodiment, the modem 1700 can be included within the processor 1100.

[0139] According to the disclosed nonvolatile memory device, a temperature compensation circuit can adjust a current associated with an operation of the nonvolatile memory device according to a temperature of the nonvolatile memory device.

[0140] Further, since the temperature compensation circuit included in the disclosed nonvolatile memory device is implemented with transistors rather than capacitors, an area of the temperature compensation circuit can become smaller, and power consumption can be reduced.

[0141] As is conventional in the art, embodiments can be described and shown in terms of blocks which perform one or more functions. These blocks (which can be referred to herein as units or modules, among other examples) are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive and active electronic components, optical components, hardwired circuits, and the like. The circuits that make up the blocks can be selectively driven by firmware and / or software. For example, the circuits can be implemented in one or more semiconductor chips, or on a substrate such as a printed circuit board. The circuits that make up the blocks can be implemented by dedicated hardware, or by a processor such as one or more programmed microprocessors and associated circuitry, or by a combination of dedicated hardware and a processor for performing some functions of the blocks. Each block of the embodiments can be physically separated from, or combined with, other blocks, without departing from the scope of the disclosure. Similarly, the blocks can be physically combined into more complex blocks without departing from the scope of the disclosure. Aspects of the embodiments can be implemented by instructions stored in non-transitory storage media and executed by a processor.

[0142] While the disclosure has been described with reference to the examples disclosed herein, it is understood that various changes and modifications can be suggested by those skilled in the art without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A nonvolatile memory device, comprising: a differential current driver configured to receive first and second differential signals based on temperature, and to generate first and second compensation currents corresponding to a difference between the first and second differential signals; a current mirror circuit configured to replicate a first current that is a sum of a reference current and the first compensation current to generate a second current having a same value as the first current, and to adjust the reference current according to a difference between the second current and the second compensation current; and a trim circuit configured to generate a program current or a read current based on the adjusted reference current. a control logic circuit configured to generate a temperature compensation magnitude signal for adjusting a maximum compensation current value that is a sum of the first and second compensation currents.

2. The nonvolatile memory device of claim 1, further comprising:

3. The nonvolatile memory device of claim 2, wherein: in response to the temperature compensation magnitude signal corresponding to a first value at a predetermined temperature, the current mirror circuit generates the adjusted reference current at a first current level, and in response to the temperature compensation magnitude signal corresponding to a second value at the predetermined temperature, the current mirror circuit generates the adjusted reference current at a second current level different from the first current level. a control logic circuit configured to generate a temperature compensation sign signal for selectively swapping the first and second differential signals to be input to the differential current driver.

4. The nonvolatile memory device of claim 1, further comprising:

5. The nonvolatile memory device of claim 4, wherein: in response to the temperature compensation sign signal corresponding to a first value at a predetermined temperature, the current mirror circuit generates the adjusted reference current that is greater than the reference current, and in response to the temperature compensation sign signal corresponding to a second value at the predetermined temperature, the current mirror circuit generates the adjusted reference current that is less than the reference current.

6. The nonvolatile memory device of claim 1, further comprising: a memory cell array including a plurality of memory cells; and a write driver configured to drive a bit line or a word line connected to the plurality of memory cells based on the program current in a program operation, and to drive the bit line or the word line based on the read current in a read operation. each memory cell of the plurality of memory cells includes a phase change material.

7. The nonvolatile memory device of claim 6, wherein, each memory cell of the plurality of memory cells is disposed between a word line extending in a first direction and a bit line extending in a second direction perpendicular to the first direction.

8. The nonvolatile memory device of claim 6, wherein, 9. The nonvolatile memory device of claim 6, wherein: a peripheral circuit including the differential current driver, the current mirror circuit, and the trim circuit is disposed on a first substrate, the memory cell array is disposed on a second substrate, and the second substrate is disposed on the peripheral circuit.

10. The nonvolatile memory device of claim 6, wherein: the plurality of memory cells includes first memory cells disposed in a first layer and second memory cells disposed in a second layer on the first layer, and the first memory cells and the second memory cells are disposed in a same direction. The write driver drives the first bit line or the first word line connected to the first memory cell based on the first program current or the first read current, and drives the second bit line or the second word line connected to the second memory cell based on a second program current different from the first program current or a second read current different from the first read current.

11. The nonvolatile memory device of claim 6, wherein: the plurality of memory cells includes a first memory cell connected to a first word line and a first bit line and a second memory cell connected to a second word line and a second bit line, the write driver drives the first word line or the first bit line based on the first program current or the first read current, and drives the second word line or the second bit line based on a second program current different from the first program current or a second read current different from the first read current, and a length of a first current path through which a current flows from the first word line to the first bit line of the first memory cell is different from a length of a second current path through which a current flows from the second word line to the second bit line of the second memory cell.

12. The nonvolatile memory device of claim 1, wherein, a difference between the first differential signal and the second differential signal increases in a positive direction as the temperature becomes higher than a reference temperature, and increases in a negative direction as the temperature becomes lower than the reference temperature.

13. A nonvolatile memory device, comprising: an array of memory cells including a plurality of memory cells; a temperature sensor configured to sense a temperature, and to generate a first differential signal and a second differential signal based on the sensed temperature; a reference current generator configured to generate a reference current; a current mirror circuit configured to generate a first compensation current and a second compensation current corresponding to a difference between the first differential signal and the second differential signal, to copy a first current that is a sum of the reference current and the first compensation current to generate a second current having a same value as a value of the first current, and to adjust the reference current according to a difference between the second current and the second compensation current; and a write driver configured to drive a bit line or a word line connected to the array of memory cells based on the adjusted reference current.

14. The nonvolatile memory device of claim 13, further comprising: control logic circuitry configured to generate a temperature compensation magnitude signal used to adjust a maximum compensation current value that is a sum of the first compensation current and the second compensation current.

15. The nonvolatile memory device of claim 14, wherein, the current mirror circuit includes: a current source configured to output a bias current of the maximum compensation current value based on the temperature compensation magnitude signal; a first transistor connected to an output terminal of the current source and configured to output the first compensation current based on the first differential signal; and a second transistor connected to the output terminal of the current source and configured to output the second compensation current based on the second differential signal.

16. The nonvolatile memory device of claim 13, further comprising: the control logic circuitry is configured to generate a temperature compensation sign signal used to selectively swap the first differential signal and the second differential signal to be input to the current mirror circuit.

17. The nonvolatile memory device of claim 16, wherein, the current mirror circuit includes: a switching circuit configured to transfer one of the first differential signal and the second differential signal as a first switched differential signal to a first input line and the other of the first differential signal and the second differential signal as a second switched differential signal to a second input line based on a temperature compensation size signal; a current source configured to output a bias current; a first transistor connected to an output terminal of the current source and configured to output one of a first compensation current and a second compensation current based on the first switched differential signal provided through the first input line; and a second transistor connected to the output terminal of the current source and configured to output the other of the first compensation current and the second compensation current based on the second switched differential signal provided through the second input line.

18. The nonvolatile memory device of claim 13, wherein, The current mirror circuit includes: a first transistor configured to output a reference current based on a reference voltage provided from a reference current generator; a second transistor configured to receive a first current which is a sum of the reference current output from the first transistor and a first compensation current; a third transistor configured to replicate the first current to generate a second current; and a fourth transistor configured to generate an adjusted reference current corresponding to a difference between the second current and a second compensation current.

19. A non-volatile memory device, comprising: a current source configured to output a bias current having a value corresponding to a temperature compensation size signal; a first transistor connected to a first output terminal of the current source and configured to output a first compensation current based on a first differential signal; a second transistor connected to the first output terminal of the current source and configured to output a second compensation current based on a second differential signal; a third transistor connected to a second output terminal of the first transistor and configured to output a reference current to the second output terminal based on a reference voltage; a fourth transistor connected to a common output terminal of the first transistor and the third transistor; a fifth transistor connected to a first gate terminal of the fourth transistor and a third output terminal of the second transistor; and a sixth transistor connected to the third output terminal and configured to output an adjusted reference current to the third output terminal, wherein: the common output terminal, the first gate terminal of the fourth transistor, and a second gate terminal of the fifth transistor are interconnected, and a difference between the first differential signal and the second differential signal is changed according to a temperature.

20. The non-volatile memory device of claim 19, further comprising: an array of memory cells including a plurality of memory cells; and a write driver configured to drive a bit line or a word line connected to the array of memory cells based on the adjusted reference current. ​

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