A shielded gate MOSFET device with integrated NPN punch-through transistor

Abstract

The present invention discloses a shielded gate MOSFET device with an integrated NPN through-transistor, comprising a cell structure, wherein the cell structure comprises a drain metal, an N+ substrate, an N-type drift region, and a source metal stacked in sequence from bottom to top; a P-type base region is provided in the inner upper layer of the N-type drift region, and an N-type heavily doped region and a P-type heavily doped region are provided on the inner upper surface of the P-type base region in close contact; two adjacent trench gate structures are formed on the upper surface of the N-type drift region between two adjacent P-type base regions; a P-type lightly doped region is provided between two adjacent trench gate structures; each trench gate structure comprises an N+Poly gate and an N-type source contact region arranged up and down; the N+Poly gate and the N-type source contact region are respectively wrapped by an oxide layer. The present invention further optimizes the current capability and voltage capability of the shielded gate MOSFET device.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductor devices, and in particular to a shielded gate MOSFET device integrating an NPN through-transistor. Background Art

[0002] With the development of power electronic systems, power semiconductor devices, as the core of power conversion and power application, are widely used in important fields such as transportation, military defense, and energy conversion. As an important component of power semiconductor devices, power MOSFET devices play an important role in the field of power conversion due to their advantages such as fast switching speed, high input impedance, low driving power, and good frequency characteristics. Power MOSFET has experienced a development from horizontal to vertical, from planar gate to trench gate. Among them, the vertical double-diffused metal oxide semiconductor field effect metal tube device (TrenchVertical Double-diffused MOSFET, Trench VDMOS) with a trench gate structure not only changes the conductive channel into a vertical direction, but also uses trench technology to eliminate the influence of the parasitic JFET resistance of the planar structure, greatly reducing the cell size while reducing the conduction loss of the device, and is widely used in the low-voltage field.

[0003] In the low-voltage application field of power devices, the on-resistance Ron0 and the gate charge Qg are two important parameters of the device. Reducing the on-resistance is beneficial to reducing the conduction loss of the device, and reducing the gate charge is beneficial to reducing the switching loss of the device. For traditional Trench VDMOS devices, due to the strong coupling between the gate electrode and the drain electrode, the gate-drain capacitance increases, thereby reducing the switching speed of the device and increasing the switching loss of the device. In order to improve the performance of trench gate VDMOS, shielded gate trench MOSFET (Split-Gate Trench MOSFET, SGT MOSFET) structure has been proposed at home and abroad. On the one hand, the shielding gate can be used to reduce the overlapping area between the gate and the drain, thereby greatly reducing the gate-drain capacitance of the device; on the other hand, the shielding gate can be used as a field plate buried in the body to assist in the depletion of carriers in the drift region, effectively improving the depletion capacity of the drift region of the device, optimizing the electric field distribution in the drift region, so that SGT MOSFET devices generally have lower on-resistance and higher breakdown voltage. Therefore, SGT MOSFET has become the main development direction in optimizing the switching characteristics of power MOS. Its device structure is as follows: Figure 1 shown.

[0004] However, in order to optimize the breakdown characteristics and switching performance of SGT MOSFET devices and enhance the reliability of the oxide layer of the device, the insulating dielectric layer around the shield gate in the SGT MOSFET trench is generally thicker. This makes the further reduction of the cell device size limited by process conditions and the reliability of the device's insulating dielectric layer, thereby limiting the further optimization of the device's on-resistance and current capability. Summary of the invention

[0005] The purpose of the present invention is to provide a shielded gate MOSFET device with an integrated NPN punch-through transistor, so as to further optimize the current capability and voltage capability of the shielded gate MOSFET device.

[0006] In order to achieve the above purpose, the following technical solutions are adopted:

[0007] A shielded gate MOSFET device with an integrated NPN punch-through transistor comprises a cellular structure, wherein the cellular structure comprises a drain metal, an N+ substrate, an N-type drift region, and a source metal stacked in sequence from bottom to top; a P-type base region is provided in the inner upper layer of the N-type drift region, and an N-type heavily doped region and a P-type heavily doped region contacting each other are provided on the inner upper surface of the P-type base region; two adjacent trench gate structures are formed on the upper surface of the N-type drift region between two adjacent P-type base regions; a P-type lightly doped region is provided between two adjacent trench gate structures; each trench gate structure comprises an N+Poly gate and an N-type source contact region arranged up and down; the N+Poly gate and the N-type source contact region are respectively wrapped by an oxide layer.

[0008] Preferably, an N-type doped region is provided on the upper surface of the P-type lightly doped region to further ensure that a vertical NPN triode structure can be realized after the P-type lightly doped region is inverted.

[0009] Preferably, the depth of the P-type lightly doped region is greater than the depth of the N+Poly gate, so as to realize a shallower P-type base region structure, thereby forming a punch-through NPN transistor structure when the device is turned on.

[0010] Preferably, the oxide layer between the N-type source contact region and the N-type drift region is a thick oxide layer, and the oxide layers in other parts are thin oxide layers.

[0011] Preferably, the N-type source contact region is connected to the source metal.

[0012] The distance between two adjacent trench gate structures in the present invention is relatively narrow, which ensures that the partial P-type lightly doped region controlled by the gate is completely inverted during the device startup process, thereby forming a complete vertical NPN triode structure.

[0013] By adopting the above scheme, the beneficial effects of the present invention are:

[0014] Based on the traditional shielded gate MOSFET device structure, a shielded gate MOSFET device with an integrated NPN punch-through transistor is proposed: by introducing a P-type lightly doped region between two adjacent trench gate structures, when the device is turned on, the part of the P-type lightly doped region controlled by the gate is completely inverted, thereby forming a longitudinal NPN punch-through structure between the two adjacent trench gate structures, providing a new current path to optimize the current capability of the device; when the device is turned off, the P-type lightly doped region with a lower doping concentration between the two adjacent trench gate structures serves as a new voltage-withstand structure, which can increase the breakdown voltage of the device on the basis of the traditional structure and improve the voltage-withstand capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the transverse cross-sectional structure of an existing shielded gate MOSFET device;

[0016] Figure 2 It is a schematic diagram of the transverse cross-sectional structure of the present invention;

[0017] Figure 3 Based on Figure 2 A schematic diagram of a transverse cross-sectional structure formed by an auxiliary NPN punch-through transistor;

[0018] The accompanying drawings illustrate:

[0019] 1—N-type heavily doped region, 2—P-type heavily doped region,

[0020] 3—P-type base region, 4—N-type drift region,

[0021] 5—N+ substrate, 6—drain metal,

[0022] 7—Source metal, 8—N+Poly gate,

[0023] 9—N-type source contact region, 10—P-type lightly doped region,

[0024] 11—oxide layer, 12—N-type doped region. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] In order to further optimize the current capability and breakdown characteristics of the device, the present invention proposes a shielded gate MOSFET device with an integrated NPN punch-through transistor based on the traditional SGT MOSFET device. The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings:

[0027] Reference Figure 2 As shown, the present invention provides a shielded gate MOSFET device with an integrated NPN punch-through transistor, including a cellular structure, wherein the cellular structure includes a drain metal 6, an N+ substrate 5, an N-type drift region 4, and a source metal 7 stacked in sequence from bottom to top; a P-type base region 3 is provided on the inner upper layer of the N-type drift region 4, and an N-type heavily doped region 1 and a P-type heavily doped region 2 contacting each other are provided on the inner upper surface of the P-type base region 3; two adjacent trench gate structures are formed on the upper surface of the N-type drift region 4 between two adjacent P-type base regions 3, and the P-type heavily doped region 2 is arranged adjacent to the trench gate structure; a P-type lightly doped region 10 is provided between two adjacent trench gate structures; each trench gate structure includes an N+Poly gate 8 and an N-type source contact region 9 arranged up and down; the N+Poly gate 8 and the N-type source contact region 9 are respectively wrapped by an oxide layer 11.

[0028] An oxide layer 11 is arranged between the trench gate structure and the N-type drift region 4, the P-type base region 3, the source metal 7, the P-type lightly doped region 10, and the P-type heavily doped region 2, wherein the lower surface and part of the side surface of the oxide layer 11 are in contact with the N-type drift region 4, the upper surface of the oxide layer 11 is in contact with the source metal 7, and the side surface of the oxide layer 11 is also in contact with the P-type base region 3, the P-type lightly doped region 10, and the P-type heavily doped region 2; in addition, the N+Poly gate 8 and the N-type source contact region 9 in the trench gate structure are also isolated by the oxide layer 11.

[0029] The main improvement of this structure is that: during the device opening process, the NPN triode structure formed by the inversion of the P-type lightly doped region 10 around the trench is used to enhance the current capability of the device; when the device is in the off state, the P-type lightly doped region 10 between the two trench gate structures is used to improve the voltage resistance of the device, thereby further optimizing the current capability and voltage resistance of the device while ensuring good switching characteristics of the device. At the same time, in order to further ensure that the P-type lightly doped region 10 between the two trench gate structures can form a connected N-type region after inversion along the surface of the two trench gate structures, such as Figure 3 As shown, an N-type doped region 12 may be provided on the surface of the P-type lightly doped region 10 to ensure the formation of a connected inverted N-type region, thereby ensuring the formation of a complete vertical NPN transistor and achieving the beneficial effects of the present invention.

[0030] The oxide layer 11 between the N-type source contact region 9 and the N-type drift region 4 is a thick oxide layer, and the oxide layers 11 in other parts are all thin oxide layers; the oxide layers 11 in other parts refer to the oxide layers 11 on the upper surface and side surfaces of the N+Poly gate 8, and the oxide layer 11 isolated between the N+Poly gate 8 and the N-type source contact region 9. The N-type source contact region 9 is connected to the source metal 7.

[0031] The principle of the present invention is as follows:

[0032] Based on the traditional shielded gate MOSFET device structure, a P-type lightly doped region 10 is introduced between two adjacent trench gate structures. The doped region has a low concentration, a narrow width, and a depth that is only slightly greater than the depth of the control gate (N+Poly gate) in the trench gate structure, so most of the P-type lightly doped region 10 is controlled by the gate. When the gate voltage is applied to the device, the distance between the two adjacent trench gate structures is narrow, that is, the width of the P-type lightly doped region 10 is narrow, so the part of the P-type lightly doped region 10 controlled by the gate can achieve complete inversion, while the small part of the P-type lightly doped region 10 not controlled by the gate still maintains P-type doping and its depth is small. Therefore, when the device is turned on, the proposed new device can form a longitudinal NPN punch-through structure between two adjacent trench gate structures, thereby providing a new current path and optimizing the current capability of the device. The device is turned off when no voltage is applied to the gate, and there is no inversion change in the P-type lightly doped region between two adjacent trench gate structures, thereby realizing the structural change between the on state and the off state; at the same time, since the doping concentration of the P-type lightly doped region 10 is relatively low, the breakdown voltage of the device can be increased on the basis of the traditional shielded gate MOSFET device structure, thereby improving the device's voltage resistance.

[0033] To sum up, based on the traditional shielded gate trench MOSFET device structure, a shielded gate MOSFET device with an integrated NPN punch-through transistor is realized by introducing a P-type lightly doped region 10 between two adjacent trench gate structures. On the basis of ensuring good switching characteristics of the device, a new current path is provided when the device is turned on, and a new voltage-withstand structure is introduced when the device is turned off, thereby achieving further optimization of the current characteristics and voltage-withstand characteristics of the traditional shielded gate MOSFET device.

[0034] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A shielded gate MOSFET device with an integrated NPN punch-through transistor, comprising a cell structure, characterized in that: The cell structure includes a drain metal, an N+ substrate, an N-type drift region, and a source metal stacked in sequence from bottom to top; a P-type base region is provided in the upper layer inside the N-type drift region, and an N-type heavily doped region and a P-type heavily doped region contacting each other are provided on the upper surface inside the P-type base region; two adjacent trench gate structures are formed on the upper surface of the N-type drift region between two adjacent P-type base regions; a P-type lightly doped region is provided between two adjacent trench gate structures; each trench gate structure includes an N+Poly gate and an N-type source contact region arranged up and down; the N+Poly gate and the N-type source contact region are respectively wrapped by an oxide layer; An N-type doped region is provided on the upper surface of the P-type lightly doped region; The depth of the P-type lightly doped region is greater than the depth of the N+ Poly gate; When the device is turned on, part of the P-type lightly doped region controlled by the gate is completely inverted, while a small part of the P-type lightly doped region not controlled by the gate still maintains P-type doping to form a longitudinal NPN punch-through structure between two adjacent trench gate structures.

2. The shielded gate MOSFET device with integrated NPN punch-through transistor according to claim 1, characterized in that: The thickness of the oxide layer between the N-type source contact region and the N-type drift region is greater than the thickness of the oxide layer at other locations.

3. The shielded gate MOSFET device with integrated NPN punch-through transistor according to claim 1, characterized in that: The N-type source contact region is connected to the source metal.

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