A negative electrode protection circuit for a lithium battery

Abstract

The present invention provides a lithium battery negative electrode protection circuit, which includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a triode, a first resistor and a second resistor. Among them, the second NMOS transistor to the fifth NMOS transistor are connected in series and are connected in parallel with the first NMOS transistor after the series connection. The source electrode of the first NMOS transistor is connected to the power supply, the drain electrode of the first NMOS transistor is grounded, the emitter of the triode is connected to the source electrode of the first NMOS transistor and is commonly connected to the power supply, the collector of the triode is connected to the drain electrode of the first NMOS transistor and is commonly grounded, the first resistor is connected in parallel with the third NMOS transistor, and the fourth NMOS transistor and the fifth NMOS transistor are connected in series and then connected in parallel with the second resistor. The technical solution provided by the present invention can further reduce the design cost of the battery protection integrated circuit and improve the safety and reliability of the protection circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a negative electrode protection circuit for a lithium battery. Background Art

[0002] Currently, in portable applications, lithium-ion batteries are widely used for power supply. Due to the stability problems of lithium-ion batteries, a battery protection IC is generally used as the protection circuit of the battery system. In addition to providing protections such as overcharge and over-discharge of the battery, charging and discharging current limits, etc., the battery protection IC also needs to prevent damage to the lithium battery and the IC itself when the battery and the charger are connected in reverse.

[0003] Common structures of existing negative electrode protection ICs for lithium batteries include a single power NMOS structure and a dual power NMOS structure. The existing single power NMOS structure can only be used at low voltages. When the battery charger is plugged in or touched between VDD and VM, the VM voltage will appear as an instant high voltage, which may cause damage to the IC with a single power NMOS structure; the dual power NMOS can be applied to the scenario where an instant high voltage appears at VM, but the cost of using the dual power NMOS is relatively high, and the chip size area is relatively large.

[0004] Therefore, how to reduce the design cost of the battery protection integrated circuit and how to improve the safety and reliability of the protection circuit have always been the goals that the industry urgently needs to improve. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a negative electrode protection circuit for a lithium battery, which can reduce the design cost of the battery protection integrated circuit and improve the safety and reliability of the protection circuit.

[0006] The present invention provides a negative electrode protection circuit for a lithium battery. The circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a triode, a first resistor, and a second resistor. Among them, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are connected in series and are connected in parallel with the first NMOS transistor after being connected in series. The source electrode of the first NMOS transistor is connected to the power supply, the drain electrode of the first NMOS transistor is grounded, the emitter of the triode is connected to the source electrode of the first NMOS transistor and is commonly connected to the power supply, the collector of the triode is connected to the drain electrode of the first NMOS transistor and is commonly grounded, the first resistor is connected in parallel with the third NMOS transistor, and the fourth NMOS transistor and the fifth NMOS transistor are connected in series and then connected in parallel with the second resistor.

[0007] Preferably, the substrate of the first NMOS transistor is connected to the positive electrodes of both diodes in the first group, and the negative electrodes of the two diodes in the first group are respectively connected to the source and the drain of the first NMOS transistor.

[0008] Preferably, the source of the second NMOS transistor is connected to the power supply, the drain of the second NMOS transistor is connected to the source of the third NMOS transistor, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the drain of the first NMOS transistor and they are grounded together. The two ends of the first resistor are respectively connected to the source and the drain of the third NMOS transistor, the two ends of the second resistor are respectively connected to the source of the fourth NMOS transistor and the drain of the fifth NMOS transistor, and the base of the triode is connected to the source of the third NMOS transistor.

[0009] Preferably, the substrate of the second NMOS transistor is connected to the positive electrodes of both diodes in the second group, and the negative electrodes of the two diodes in the second group are respectively connected to the source and the drain of the second NMOS transistor.

[0010] Preferably, the substrate of the third NMOS transistor is connected to the positive electrodes of both diodes in the third group, and the negative electrodes of the two diodes in the third group are respectively connected to the source and the drain of the third NMOS transistor.

[0011] Preferably, the substrate of the fourth NMOS transistor is connected to the positive electrodes of both diodes in the fourth group, and the negative electrodes of the two diodes in the fourth group are respectively connected to the source and the drain of the fourth NMOS transistor.

[0012] Preferably, the substrate of the fifth NMOS transistor is connected to the positive electrodes of both diodes in the fifth group, and the negative electrodes of the two diodes in the fifth group are respectively connected to the source and the drain of the fifth NMOS transistor.

[0013] Preferably, the internal structure of the first NMOS transistor includes a deep N-well arranged at the bottom layer, a high-voltage P-well and two N-wells stacked on the deep N-well and spaced from each other, and a P-well away from the deep N-well. The high-voltage P-well is stacked at the middle position on the deep N-well. The two N-wells are respectively located on both sides of the high-voltage P-well and are respectively stacked at the edge positions on the deep N-well. The P-well is adjacent to one of the N-wells.

[0014] Preferably, the high-voltage P well includes a P-type substrate and two doped regions on both sides of the P-type substrate. The P-type substrate serves as the substrate of the first NMOS transistor, the two doped regions together serve as the source of the first NMOS transistor, the two N wells together serve as the drain of the first NMOS transistor, the doped regions of the N well and the doped regions of the high-voltage P well together serve as the gate of the first NMOS transistor, and the P well away from the deep N well is grounded.

[0015] Preferably, the internal structure of any one of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor includes a deep N well disposed at the bottom layer, a P well and two N wells stacked on the deep N well and closely adjacent to each other, and a P well away from the deep N well. The P well stacked on the deep N well is located at the middle position on the deep N well, and the two N wells are respectively located at the edge positions on the deep N well.

[0016] Preferably, the P well stacked on the deep N well includes two P-type substrates and two doped regions. The two P-type substrates together serve as the substrate of the second NMOS transistor, the two doped regions respectively serve as the source and drain of the second NMOS transistor, and the gate of the second NMOS transistor is disposed between the two doped regions. The P well away from the deep N well is grounded.

[0017] The technical solution provided by the present invention has the following advantages: By changing the structure of the single-power NMOS substrate selection circuit, this single-power NMOS can meet the application requirements of high voltage that appears instantaneously when the charger is plugged in or unplugged; at the same time, it protects the IC in the forward and reverse connection applications of the charger and the battery, can reduce the design cost of the battery protection integrated circuit, and improve the safety and reliability of the protection circuit. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of a lithium battery negative electrode protection circuit in an embodiment of the present invention;

[0019] Figure 2 It is a cross-sectional view of the internal structure of the first NMOS transistor and the second NMOS transistor in an embodiment of the present invention;

[0020] Figure 3 It is a schematic structural diagram of a lithium battery negative electrode protection circuit in another embodiment of the present invention. Detailed Embodiment

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] The following will provide a detailed description of a lithium battery negative electrode protection circuit provided by the present invention.

[0023] Please refer to Figure 1 , which is a schematic flow diagram of a lithium battery negative electrode protection circuit in an embodiment of the present invention.

[0024] In this embodiment, the lithium battery negative electrode protection circuit is specifically a high-voltage lithium battery negative electrode protection circuit applied to a single power NMOS, which can further reduce the design cost of the battery protection integrated circuit and improve the safety and reliability of the protection circuit.

[0025] In this embodiment, the lithium battery negative electrode protection circuit includes a first NMOS transistor MN, a second NMOS transistor MN0, a third NMOS transistor MN1, a fourth NMOS transistor MN2, a fifth NMOS transistor MN3, a triode QN, a first resistor R1, and a second resistor R2. Among them, the first NMOS transistor MN is a power NMOS transistor, and the drain-source voltage of the first NMOS transistor MN can reach up to more than ten volts at most. The triode QN is the parasitic triode NPN of the first NMOS transistor.

[0026] In this embodiment, the second NMOS transistor MN0, the third NMOS transistor MN1, the fourth NMOS transistor MN2, and the fifth NMOS transistor MN3 are connected in series and then connected in parallel with the first NMOS transistor MN. Specifically, the source of the second NMOS transistor MN0 is connected to the power supply voltage VM, the drain of the second NMOS transistor MN0 is connected to the source of the third NMOS transistor MN1, the drain of the third NMOS transistor MN1 is connected to the source of the fourth NMOS transistor MN2, the drain of the fourth NMOS transistor MN2 is connected to the source of the fifth NMOS transistor MN3, the drain of the fifth NMOS transistor MN3 is connected to the drain of the first NMOS transistor MN and is commonly grounded to GND. The two ends of the first resistor R1 are respectively connected to the source and drain of the third NMOS transistor MN1, the two ends of the second resistor R2 are respectively connected to the source of the fourth NMOS transistor MN2 and the drain of the fifth NMOS transistor MN3, and the base of the triode QN is connected to the source of the third NMOS transistor MN1.

[0027] In this embodiment, the source of the first NMOS transistor MN is connected to the power supply voltage VM, the drain of the first NMOS transistor MN is grounded to GND, the emitter of the triode QN is connected to the source of the first NMOS transistor MN and is jointly connected to the power supply voltage VM, the collector of the triode QN is connected to the drain of the first NMOS transistor MN and is jointly grounded to GND. The first resistor R1 is connected in parallel with the third NMOS transistor MN1. Specifically, one end of the first resistor R1 is connected to the source of the third NMOS transistor MN1, and the other end of the first resistor R1 is connected to the drain of the third NMOS transistor MN1. The fourth NMOS transistor MN2 and the fifth NMOS transistor MN3 are connected in series and then connected in parallel with the second resistor R2. Specifically, one end of the second resistor R2 is connected to the source of the fourth NMOS transistor MN2, and the other end of the second resistor R2 is connected to the drain of the fifth NMOS transistor MN3.

[0028] In this embodiment, the lithium battery negative electrode protection circuit further includes five groups of two diodes.

[0029] In this embodiment, the substrate BULK of the first NMOS transistor MN and the anodes of the first group of two diodes are both connected, and the cathodes of the first group of two diodes are respectively connected to the source and the drain of the first NMOS transistor MN.

[0030] In this embodiment, the substrate BULK of the second NMOS transistor MN0 and the anodes of the second group of two diodes are both connected, and the cathodes of the second group of two diodes are respectively connected to the source and the drain of the second NMOS transistor MN0.

[0031] In this embodiment, the substrate BULK of the third NMOS transistor MN1 and the anodes of the third group of two diodes are both connected, and the cathodes of the third group of two diodes are respectively connected to the source and the drain of the third NMOS transistor MN1.

[0032] In this embodiment, the substrate BULK of the fourth NMOS transistor MN2 and the anodes of the fourth group of two diodes are both connected, and the cathodes of the fourth group of two diodes are respectively connected to the source and the drain of the fourth NMOS transistor MN2.

[0033] In this embodiment, the substrate BULK of the fifth NMOS transistor MN3 and the anodes of the fifth group of two diodes are both connected, and the cathodes of the fifth group of two diodes are respectively connected to the source and the drain of the fifth NMOS transistor MN3.

[0034] Please refer to Figure 2 , which is the internal structure sectional view of the first NMOS transistor and the second NMOS transistor in an embodiment of the present invention.

[0035] In this embodiment, the left side of the figure shows the internal structure cross-section of the first NMOS transistor MN, and the right side of the figure shows the internal structure cross-section of the second NMOS transistor MN0. The internal structures of the third NMOS transistor MN1, the fourth NMOS transistor MN2, and the fifth NMOS transistor MN3 are the same as that of the second NMOS transistor MN0. In the figure, HVP represents a high-voltage P-well, PW and NW respectively represent a P-well and an N-well, and DN represents a deep N-well. The withstand voltage between DN and GND is very high, which can ensure the high-voltage requirements from GND to VM, as well as the positive and reverse connection applications of the battery and the charger.

[0036] In this embodiment, the internal structure of the first NMOS transistor MN includes a deep N-well DN disposed at the bottom layer, a high-voltage P-well HVP and two N-wells NW stacked on the deep N-well DN and spaced apart from each other, and a P-well PW away from the deep N-well DN. The high-voltage P-well HVP is stacked at the middle position on the deep N-well DN. The two N-wells NW are respectively located on both sides of the high-voltage P-well HVP and are stacked at the edge positions on the deep N-well DN. The P-well PW is adjacent to and spaced apart from one of the N-wells NW, and the P-well PW is grounded to GND.

[0037] In this embodiment, the high-voltage P-well HVP internally includes a P-type substrate (P+) and two doped regions (N+) located on both sides of the P-type substrate. The P-type substrate serves as the substrate B of the first NMOS transistor MN, and the two doped regions (N+) together serve as the source S of the first NMOS transistor MN. The two N-wells NW together serve as the drain D of the first NMOS transistor MN. The doped regions of the N-well and the doped regions of the high-voltage P-well HVP together serve as the gate G of the first NMOS transistor MN. The P-well PW away from the deep N-well DN is grounded to GND.

[0038] In this embodiment, the internal structure of any one of the second NMOS transistor MN0, the third NMOS transistor MN1, the fourth NMOS transistor MN2, and the fifth NMOS transistor MN3 includes a deep N-well DN disposed at the bottom layer, a P-well PW and two N-wells NW stacked on the deep N-well DN and closely adjacent to each other, and a P-well PW away from the deep N-well DN. The P-well PW stacked on the deep N-well DN is located at the middle position on the deep N-well DN, and the two N-wells NW are respectively located at the edge positions on the deep N-well DN.

[0039] In this embodiment, the P-well PW stacked on the deep N-well DN internally includes two P-type substrates (P+) and two doped regions (N+). The two P-type substrates (P+) together serve as the substrate B of the second NMOS transistor. The two doped regions (N+) respectively serve as the source S and the drain D of the second NMOS transistor. The gate G of the second NMOS transistor is disposed between the two doped regions (N+). The P-well away from the deep N-well is grounded to GND, and the two N-wells NW are connected to the deep N-well DN.

[0040] In this embodiment, the protection IC is protected when the power supply voltage VM is in the range of -10V to +5V with respect to the ground GND voltage. The working principle of the high-voltage lithium battery negative electrode protection circuit for a single power NMOS of the present invention will be described below according to Figure 1 and Figure 2 :

[0041] 1. The first NMOS transistor MN is turned on, and the VM voltage is lower than GND. At this time, the second NMOS transistor MN0 is turned on, and MN1 to MN3 are turned off. The BULK potential selects VM, such as when charging a lithium battery;

[0042] 2. The first NMOS transistor MN is turned on, and the VM voltage is higher than GND. At this time, the second NMOS transistor MN0 is turned off, and MN1 to MN3 are turned on. The BULK potential selects GND, such as when discharging a lithium battery;

[0043] 3. The first NMOS transistor MN is turned off, and the VM voltage is lower than GND. If the substrate selection circuit still works normally, then at this time the second NMOS transistor MN0 is turned on, and MN1 to MN3 are turned off. The BULK potential selects VM; if the substrate selection circuit does not work, then MN0 to MN3 are turned off. When a momentary negative high voltage (such as -10V) appears at VM, the charge can be discharged from GND to VM through the second resistor R2, the first resistor R1, and the triode QN; at this time, D0 and D3 are forward-biased, D1 and D2 are reverse-biased, and the voltage across D0 is equal to the V be voltage of the triode QN. Since the size of the first NMOS transistor MN is large, the BULK voltage will be close to VM. The reverse voltage across D1 and D2 is expressed as follows:

[0044]

[0045] By dividing the voltage of VM through R1 and R2, the momentary high voltage of VM can be prevented from breaking down D1 and D2; at the same time, the current of the path from GND to VM is determined by the resistances of R1 and R2, and this state will not damage the IC;

[0046] 4. The first NMOS transistor MN is turned off, and the VM voltage is higher than GND. If the substrate selection circuit still works normally, then at this time the second NMOS transistor MN0 is turned off, and MN1 to MN3 are turned on. The BULK potential selects GND; if the substrate selection circuit does not work, then MN0 to MN3 are turned off. When a momentary positive voltage (such as +5V) appears at VM, the path from VM to GND is D0, R1, and R2 or QN, R1, and R2 at this time. Since D0 is reverse-biased, there is no current in this path, the voltage drop across the resistors R1 and R2 is 0V, the BULK potential is equal to GND, and the voltage across D0 is equal to the voltage difference from VM to GND. Similarly, this state can be protected from damage to the IC;

[0047] As can be seen from the above, the circuit of the present invention can well protect the lithium battery and the IC itself under various application conditions, reduce the chip cost. At the same time, there is a parasitic triode QN in the power transistor MN of the present invention, which has a high surge current protection function.

[0048] In addition, the present invention also provides another negative electrode protection circuit for a higher voltage lithium battery with a single power NMOS, such as Figure 3 , so as to meet the different breakdown voltage requirements of the VM terminal.

[0049] Figure 3 The power transistors MN and MN0 to MN in N+1 The cross-sectional view is as shown in Figure 2 At the same time, the breakdown voltage of the power transistor MN needs to meet the negative voltage requirement of VM. For example, if the maximum value of VM reaches -30V, the breakdown voltage of each diode of MN to the ground needs to reach more than 30V. At the same time, the diode of the second NMOS transistor MN0 to the ground also needs to be more than 30V.

[0050] The circuit principle is the same as that of the previous protection circuit. Figure 3 The circuit of Figure 3 can protect the battery when a high voltage appears during the instant of plugging and unplugging the charger, and at the same time prevent the IC from being damaged in various applications. N+1 The circuit can meet the voltage range of VM as: -N * 5V to +5V. For example, if N = 4, it can meet the variation range of VM as -20V to +5V. At the same time, 4 resistors are required to divide the voltage of VM. When a negative voltage appears at the VM terminal and MN and MN0 to MN N are all turned off, adding resistors R1 to R N can divide the voltage of the VM terminal to prevent the body diodes D1 to D

[0051] from being broken down by VM. N+1 When a positive voltage (+5V) appears at the VM terminal and MN and MN0 to MN N are all turned off, the path from VM to GND is D0, R1 to R N or QN, R1 to R N . Since D0 is reverse-biased, the voltage drop of the resistors R1 to R

[0052] Figure 3 is 0V, and the BULK potential is equal to GND. This state will not damage the IC either.

[0053] The technical solution provided by the present invention has the following advantages: By changing the structure of the single-power NMOS substrate selection circuit, this single power NMOS can meet the application requirements of high voltage occurring instantaneously during charger plugging and unplugging; at the same time, it protects the IC in the forward and reverse connection applications of the charger and the battery, can reduce the design cost of the battery protection integrated circuit, and improve the safety and reliability of the protection circuit.

[0054] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A negative electrode protection circuit for a lithium battery, characterized in that, The circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a triode, a first resistor, and a second resistor. Among them, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are connected in series and are connected in parallel with the first NMOS transistor after the series connection. The source of the first NMOS transistor is connected to the power supply, the drain of the first NMOS transistor is grounded, the emitter of the triode is connected to the source of the first NMOS transistor and is jointly connected to the power supply, the collector of the triode is connected to the drain of the first NMOS transistor and is jointly grounded, the first resistor is connected in parallel with the third NMOS transistor, and the fourth NMOS transistor and the fifth NMOS transistor are connected in series and then connected in parallel with the second resistor; The substrate of the first NMOS transistor is connected to the positive electrodes of both diodes in the first group, and the negative electrodes of the two diodes in the first group are respectively connected to the source and the drain of the first NMOS transistor; The internal structure of the first NMOS transistor includes a deep N-well arranged at the bottom layer, a high-voltage P-well and two N-wells stacked on the deep N-well and spaced from each other, and a P-well away from the deep N-well. The high-voltage P-well is stacked in the middle position on the deep N-well, the two N-wells are respectively located on both sides of the high-voltage P-well and are respectively stacked on the edge positions of the deep N-well, and the P-well is adjacent to one of the N-wells; The high-voltage P-well internally includes a P-type substrate and two doping regions located on both sides of the P-type substrate. The P-type substrate serves as the substrate of the first NMOS transistor, the two doping regions jointly serve as the source of the first NMOS transistor, the two N-wells jointly serve as the drain of the first NMOS transistor, the doping regions of the N-wells and the doping regions of the high-voltage P-well jointly serve as the gate of the first NMOS transistor, and the P-well away from the deep N-well is grounded.

2. The lithium battery anode protection circuit according to claim 1, characterized in that, The source of the second NMOS transistor is connected to the power supply, the drain of the second NMOS transistor is connected to the source of the third NMOS transistor, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the drain of the first NMOS transistor and is jointly grounded. The two ends of the first resistor are respectively connected to the source and the drain of the third NMOS transistor, the two ends of the second resistor are respectively connected to the source of the fourth NMOS transistor and the drain of the fifth NMOS transistor, and the base of the triode is connected to the source of the third NMOS transistor.

3. The lithium battery anode protection circuit according to claim 1, characterized in that The substrate of the second NMOS transistor is connected to the positive electrodes of both diodes in the second group, and the negative electrodes of the two diodes in the second group are respectively connected to the source and the drain of the second NMOS transistor.

4. The lithium battery anode protection circuit according to claim 1, wherein The substrate of the third NMOS transistor is connected to the positive electrodes of both diodes in the third group, and the negative electrodes of the two diodes in the third group are respectively connected to the source and the drain of the third NMOS transistor.

5. The lithium battery negative electrode protection circuit according to claim 1, characterized in that The substrate of the fourth NMOS transistor is connected to the positive electrodes of the two diodes in the fourth group, and the negative electrodes of the two diodes in the fourth group are respectively connected to the source electrode and the drain electrode of the fourth NMOS transistor.

6. The lithium battery negative electrode protection circuit according to claim 1, characterized in that, The substrate of the fifth NMOS transistor is connected to the positive electrodes of the two diodes in the fifth group, and the negative electrodes of the two diodes in the fifth group are respectively connected to the source electrode and the drain electrode of the fifth NMOS transistor.

7. The lithium battery anode protection circuit according to claim 1, wherein The internal structure of any one of the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor includes a deep N-well disposed at the bottommost layer, a P-well and two N-wells stacked on the deep N-well and closely adjacent to each other, and a P-well away from the deep N-well. The P-well stacked on the deep N-well is located at the middle position on the deep N-well, and the two N-wells are respectively located at the edge positions on the deep N-well.

8. The lithium battery anode protection circuit according to claim 7, characterized in that, The P-well stacked on the deep N-well includes two P-type substrates and two doping regions. The two P-type substrates together serve as the substrate of the second NMOS transistor, and the two doping regions respectively serve as the source electrode and the drain electrode of the second NMOS transistor. The gate of the second NMOS transistor is disposed between the two doping regions, and the P-well away from the deep N-well is grounded.

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