Circuit board and its manufacturing method

Abstract

The present invention provides a circuit board and a manufacturing method thereof, including: a core board, provided with a groove body, the groove body includes a plurality of first sub-groove bodies and a plurality of second sub-groove bodies located below the first sub-groove bodies and corresponding to the positions of the first sub-groove bodies; a chip component, disposed in the groove body; the chip component includes a plurality of first chips located in the first sub-groove bodies and a plurality of second chips located in the second sub-groove bodies; wherein, each first chip is connected in series with the second chip corresponding to its position to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to a first power signal layer, and the other end is connected to a ground wire layer. In this way, a plurality of chips are buried in the circuit board to achieve the thinning and miniaturization of the circuit board.

Description

Technical Field

[0001] This application relates to the technical field of chip embedding, and particularly to a circuit board and a manufacturing method thereof. Background Art

[0002] With the increasing perfection of the circuit board preparation process, the electronic packaging technology has become more and more mature.

[0003] Today's electronic packaging not only needs to provide protection for chips, but also needs to meet the increasing requirements of performance, reliability, heat dissipation, power distribution, etc. at a certain cost. At the same time, due to the user's demand for ultra-thin, miniaturized, and multi-functional products, the existing circuit boards have low integration in the manufacturing process, and relatively high power consumption and cost.

[0004] Therefore, it is particularly necessary to provide a circuit board with high integration, low power consumption, and low cost. Summary of the Invention

[0005] This application mainly provides a circuit board and a manufacturing method thereof to achieve the thinning and miniaturization of the circuit board.

[0006] To solve the above technical problems, a technical solution provided by the present invention is: providing a circuit board, including: a core board, provided with a slot, the slot including a plurality of first sub-slots and a plurality of second sub-slots located below the first sub-slots and corresponding to the positions of the first sub-slots; a chip component, disposed in the slot; the chip component including a plurality of first chips located in the first sub-slots and a plurality of second chips located in the second sub-slots; wherein, each of the first chips is connected in series with the corresponding second chip to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to a first power signal layer, and the other end is connected to a ground wire layer.

[0007] Wherein, the circuit board further includes: a first circuit layer, disposed on one side of the core board; a second circuit layer, disposed on the side of the core board away from the first circuit layer; a first insulating layer, disposed between the core board and the first circuit layer; a second insulating layer, disposed between the core board and the second circuit layer; wherein, the first circuit layer includes the first power signal layer and a control signal layer; the second circuit layer includes the ground wire layer and a second power signal layer.

[0008] Wherein, the circuit board further includes: a first power signal layer disposed on one side of the core board; a second power signal layer disposed on the side of the core board away from the first power signal layer; a first insulating layer disposed between the core board and the first power signal layer; a second insulating layer disposed between the core board and the second power signal layer; a control signal layer on the side of the first power signal layer away from the core board; a ground wire layer on the side of the second power signal layer away from the core board; a third insulating layer between the first power signal layer and the control signal layer; and a fourth insulating layer between the second power signal layer and the ground wire layer.

[0009] Wherein, each of the first chip and the second chip includes: a second connection terminal and a third connection terminal on the side close to the first circuit layer, and a first connection terminal close to the second circuit layer; wherein, the first connection terminal of the first chip is coupled to the second connection terminal of the second chip corresponding to its position; the second connection terminal of the first chip is coupled to the first power signal layer, the third connection terminal of the first chip is coupled to the control signal layer, the third connection terminal of the second chip is coupled to the control signal layer, and the first connection terminal of the second chip is connected to the ground wire layer.

[0010] Wherein, the second insulating layer has a first conductive hole at the position corresponding to the first connection terminal of the first chip to connect the second power signal layer to the first connection terminal of the first chip; the first insulating layer has a second conductive hole at the position corresponding to the second connection terminal of the second chip to connect the first power signal layer to the second connection terminal of the second chip; there is a third conductive hole between the first chip and the second chip to connect the first power signal layer and the second power signal layer, and further connect the first connection terminal of the first chip to the second connection terminal of the second chip, so as to connect the first chip and the second chip in series to form a plurality of chip groups.

[0011] Wherein, the first insulating layer has a fourth conductive hole at the position corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer; or the first insulating layer and the third insulating layer have a fourth conductive hole at the position corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer.

[0012] Wherein, a fifth conductive hole is provided at a position of the first insulating layer corresponding to the second connection terminal of the first chip to connect the second connection terminal of the first chip to the first power signal layer; a sixth conductive hole is provided at a position of the second insulating layer corresponding to the first connection terminal of the second chip to electrically connect the first connection terminal of the second chip to the ground wire layer; or a fifth conductive hole is provided at a position of the first insulating layer corresponding to the second connection terminal of the first chip to connect the second connection terminal of each first chip to the first power signal layer; a sixth conductive hole is provided at positions of the second insulating layer and the fourth insulating layer corresponding to the first connection terminal of the second chip to electrically connect the second connection terminal of each second chip to the ground wire layer.

[0013] To solve the above problems, another technical solution provided by the present invention is: providing a method for manufacturing a circuit board, including: providing a core board; opening a groove in the core board, the groove including a plurality of first sub-grooves and a plurality of second sub-grooves located below the first sub-grooves and corresponding to the positions of the first sub-grooves; placing a chip component in the groove, the chip component including a plurality of first chips located in the first sub-grooves and a plurality of second chips located in the second sub-grooves, wherein each first chip is connected in series with the second chip corresponding to its position to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground wire layer.

[0014] Among them, placing a chip component in the slot body, the chip component includes a plurality of first chips located in the first sub-slot body and a plurality of second chips located in the second sub-slot body; among them, each of the first chips is connected in series with the corresponding second chip to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and after one end of the plurality of chip groups is connected to the first power signal layer and the other end is connected to the ground wire layer, the steps include: setting a first circuit board on one side of the core board, and setting a second circuit layer on the side of the core board away from the first circuit layer; among them, the first circuit layer includes a first power signal layer and a control signal layer, and the second circuit layer includes a ground wire layer and a second power signal layer; setting a first insulating layer between the core board and the first circuit layer, and setting a second insulating layer between the core board and the second circuit layer; or setting a first power signal layer on one side of the core board, and setting a second power signal layer on the side of the core board away from the first power signal layer; setting a first insulating layer between the core board and the first power signal layer, and setting a second insulating layer between the core board and the second power signal layer; setting a control signal layer on the side of the first power signal layer away from the core board, and setting a ground wire layer on the side of the second power signal layer away from the core board; setting a third insulating layer between the first power signal layer and the control signal layer, and setting a fourth insulating layer between the second power signal layer and the ground wire layer.

[0015] Among them, the method further includes: setting a first conductive hole at a position of the second insulating layer corresponding to the first connection terminal of the first chip, setting a second conductive hole at a position of the first insulating layer corresponding to the second connection terminal of the second chip, and setting a third conductive hole penetrating the core board, the first insulating layer and the second insulating layer between the first chip and the second chip to connect the first connection terminal of the first chip to the second connection terminal of the second chip; setting a fifth conductive hole at a position of the first insulating layer corresponding to the second connection terminal of the first chip to connect the second connection terminal of the first chip to the first power signal layer; setting a sixth conductive hole at a position of the second insulating layer corresponding to the first connection terminal of the second chip to connect the first connection terminal of the second chip to the ground wire layer; setting a fourth conductive hole at a position of the first insulating layer corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer.

[0016] The beneficial effects of the present invention are different from the prior art. The circuit board provided by the present invention includes a core board, and a groove is formed on the core board. The groove includes a plurality of first sub-grooves and a plurality of second sub-grooves located below the first sub-grooves and corresponding to the positions of the first sub-grooves; a chip component is disposed in the groove; the chip component includes a plurality of first chips located in the first sub-grooves and a plurality of second chips located in the second sub-grooves; wherein, each first chip and the second chip corresponding to its position are connected in series to form a plurality of chip groups; the plurality of chip groups are connected in parallel to each other, and one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground wire layer. In this way, the chip is embedded into the circuit board and combined with the circuit board to realize the thinning and miniaturization of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic structural diagram of the first embodiment of the circuit board of the present invention;

[0018] Figure 2 is a schematic structural diagram of the groove of the circuit board of the present invention;

[0019] Figure 3 is a schematic structural diagram of the second embodiment of the circuit board of the present invention;

[0020] Figure 4 is a schematic flow chart of the first embodiment of the manufacturing method of the circuit board of the present invention;

[0021] Figure 5 is a schematic flow chart of the second embodiment of the manufacturing method of the circuit board of the present invention;

[0022] Figure 6 is a schematic flow chart of the third embodiment of the manufacturing method of the circuit board of the present invention;

[0023] Figure 7 is a schematic flow chart of the fourth embodiment of the manufacturing method of the circuit board of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0025] Please refer to Figure 1 , which is a schematic structural diagram of the first embodiment of the circuit board of the present invention. It includes: a core board 11 and a chip component 12; a groove is formed on the core board 11. Please refer to Figure 2, the slot body includes a plurality of first sub - slot bodies 111 and a plurality of second sub - slot bodies 112 located below the first sub - slot bodies 111. In this embodiment, the first sub - slot bodies 111 and the second sub - slot bodies 112 are arranged in an array, and the second sub - slot bodies 112 are located below the first sub - slot bodies 111 and correspond to the first sub - slot bodies 111 one by one. The chip assembly 12 includes a first chip 121 located in the first sub - slot body 111 and a second chip 122 located in the second sub - slot body 112. This embodiment is described by taking three first chips 121 and three second chips 122 as examples. Figure 1 The structural schematic diagram shown is a side view of the circuit board.

[0026] In this embodiment, one first chip 121 is correspondingly placed in one first sub - slot body 111, and one second chip 122 is correspondingly placed in one second sub - slot body 113. In another embodiment, multiple chips can also be placed in one slot body. This embodiment is described by taking one chip placed in one slot body as an example.

[0027] Figure 1 The circuit board shown further includes a first circuit layer 15 and a second circuit layer 14. The first circuit layer 15 and the second circuit layer 14 are respectively arranged on both sides of the core board 11 and are connected to the core board 11 through a first insulating layer 17 and a second insulating layer 16. Specifically, the first insulating layer 17 is arranged between the core board 11 and the first circuit layer 15 for connecting the core board 11 and the first circuit layer 15; the second insulating layer 16 is arranged between the core board 11 and the second circuit layer 14 for connecting the core board 11 and the second circuit layer 14.

[0028] In this application, the material of the core board 11 is a copper - clad laminate. The copper - clad laminate is the basic material for making a circuit board, including a base substrate and a copper foil covering the substrate. The base substrate is made by impregnating materials such as paper substrate, glass fiber cloth substrate, synthetic fiber cloth substrate, non - woven fabric substrate, composite substrate, etc. with resin to make adhesive sheets, and then combining multiple adhesive sheets. Copper foil is covered on one side or both sides of the made base substrate, and then hot - pressed and cured to make the copper - clad laminate. The first insulating layer 17 and the second insulating layer 16 are prepregs, which are used as the inter - layer bonding layers during lamination. Specifically, the prepreg is mainly composed of resin and reinforcing materials. When making a multi - layer circuit board, glass fiber cloth is usually used as the reinforcing material, impregnated with resin glue, and then pre - baked by heat treatment to make a thin sheet. It will soften under heating and pressure, solidify after cooling, and has viscosity, and can bond adjacent two layers during the high - temperature pressing process.

[0029] In this embodiment, the first chip 121 located in the first sub - slot body 111 and the second chip 122 located in the second sub - slot body 112 are connected in series with each other to form a plurality of chip groups, and the plurality of chip groups are connected in parallel, that is, one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground wire layer.

[0030] Specifically, both the first chip 121 and the second chip 122 include a first connection terminal, a second connection terminal, and a third connection terminal. Among them, the second connection terminal and the third connection terminal are located on the side close to the first circuit layer, and the first connection terminal is located on the side close to the second circuit layer. When the first chip 121 and the second chip 122 are connected in series to form a chip group, the first connection terminal of the first chip 121 is connected to the second connection terminal of the second chip 122 corresponding to its position. When each chip group is connected in parallel, one end of the chip group is connected to the first power signal layer, and the other end is connected to the ground wire layer.

[0031] As Figure 1 shown, the first circuit layer 15 in the circuit board in this embodiment includes a non-connected first power signal layer 151 and a control signal layer 152; the second circuit layer 14 includes a non-connected second power signal layer 141 and a ground wire layer 142.

[0032] In this embodiment, to achieve the series connection of the first chip 121 and the second chip 122, that is, to achieve the connection between the first connection terminal of the first chip 121 and the second connection terminal of the second chip 122, the second insulating layer 16 has a first conductive hole 181 at the position corresponding to the first connection terminal of the first chip 121 to connect the second power signal layer 141 to the first connection terminal of the first chip 121. The first insulating layer 17 has a second conductive hole 182 at the position corresponding to the second connection terminal of the second chip 122 to connect the first power signal layer 151 to the second connection terminal of the second chip 122. There is a third conductive hole 183 passing through the core board 11, the first insulating layer 17, and the second insulating layer 16 between the first chip 121 and the second chip 122 to connect the first power signal layer 151 and the second power signal layer 141, and further connect the first connection terminal of the first chip 121 to the second connection terminal of the second chip 122 to connect the first chip 121 and the second chip 122 in series.

[0033] In this embodiment, to achieve the parallel connection of the chip sets, the second connection terminals of each first chip 121 are connected to each other, and the first connection terminals of each second chip 122 are connected to each other. Specifically, to connect the second connection terminals of each first chip 121 to each other, the first insulating layer 17 has a fifth conductive hole 185 at the position corresponding to the second connection terminal of the first chip 121, so as to connect the second connection terminal of each first chip 121 to the first power signal layer 151; the second connection terminals of the first chips 121 are connected in parallel through the first power signal layer 151. To connect the first connection terminals of each second chip 122 to each other, the second insulating layer 16 has a sixth conductive hole 186 at the position corresponding to the first connection terminal of the second chip 122, so as to connect the first connection terminal of each second chip 122 to the ground wire layer 142; the first connection terminals of the second chips 122 are connected in parallel through the ground wire layer 142.

[0034] Furthermore, in this embodiment, the first insulating layer 17 has a fourth conductive hole 184 at the position corresponding to the third connection terminals of the first chip 121 and the second chip 122, and the fourth conductive hole 184 is used to connect the third connection terminals of the first chip 121 and the second chip 122 to the control signal layer 152.

[0035] The circuit board shown in this embodiment realizes the thinning and miniaturization of the embedded circuit board by embedding multiple first chips 121 and second chips 122 in the circuit board, and making the first chips 121 and the corresponding second chips 122 connected in series to form chip sets, and connecting the chip sets in parallel, and can achieve the purpose of short signal transmission distance and reduced signal loss.

[0036] Please refer to Figure 3 , which is a schematic structural diagram of the second embodiment of the circuit board of the present invention. It includes: a core board 21 and a chip assembly 22; a groove is formed on the core board 21, please refer to Figure 2 , the groove includes a plurality of first sub-grooves 111 arranged in rows, and a plurality of second sub-grooves 112 located below the first sub-grooves 111. The chip assembly 22 includes a first chip 221 located in the first sub-groove 111 and a second chip 222 located in the second sub-groove 112. In this embodiment, three first chips 221 and three second chips 222 are taken as examples for illustration. Figure 3 The schematic structural diagram of the circuit board shown is a side view of the circuit board.

[0037] Figure 3The circuit board shown also includes a first power signal layer 251 and a second power signal layer 241. The first power signal layer 251 and the second power signal layer 241 are respectively disposed on both sides of the core board 21 and are connected to the core board 21 through a first insulating layer 271 and a second insulating layer 261. Specifically, the first insulating layer 271 is disposed between the core board 21 and the first power signal layer 251 for connecting the core board 21 and the first power signal layer 251; the second insulating layer 261 is disposed between the core board 21 and the second power signal layer 241 for connecting the core board 21 and the second power signal layer 241.

[0038] The circuit board shown in this embodiment also includes a third insulating layer 272, a fourth insulating layer 262, a control signal layer 252, and a ground wire layer 242. Among them, the control signal layer 252 is located on the side of the first power signal layer 251 away from the core board 21, and the ground wire layer 242 is located on the side of the second power signal layer 241 away from the core board 21. The third insulating layer 272 is located between the first power signal layer 251 and the control signal layer 252 for bonding the first power signal layer 251 and the control signal layer 252, and the fourth insulating layer 262 is located between the second power signal layer 241 and the ground wire layer 242 for bonding the second power signal layer 241 and the ground wire layer 242.

[0039] Specifically, both the first chip 221 and the second chip 222 include a first connection terminal, a second connection terminal, and a third connection terminal. When the first chip 221 and the second chip 222 are connected in series to form a chip group, the first connection terminal of the first chip 221 is connected to the second connection terminal of the second chip 222 corresponding to its position. When each chip group is connected in parallel with each other, one end of the chip group is connected to the first power signal layer 251, and the other end is connected to the ground wire layer 242. Specifically, the second connection terminal of the first chip 221 is connected to the first power signal layer 251, and the first connection terminal of the second chip 222 is connected to the ground wire layer 242.

[0040] As Figure 3As shown in the figure, in this embodiment, to achieve the series connection of the first chip 221 and the second chip 222, that is, to achieve the connection between the first connection terminal of the first chip 221 and the second connection terminal of the second chip 222, a first conductive hole 281 is provided at the position of the second insulating layer 261 corresponding to the first connection terminal of the first chip 221 to connect the second power signal layer 241 to the first connection terminal of the first chip 221. A second conductive hole 282 is provided at the position of the first insulating layer 271 corresponding to the second connection terminal of the second chip 222 to connect the first power signal layer 251 to the second connection terminal of the second chip 222. A third conductive hole 183 passing through the core board 21, the first insulating layer 271 and the second insulating layer 261 is provided between the first chip 221 and the second chip 222 to connect the first power signal layer 251 and the second power signal layer 241, and further connect the first connection terminal of the first chip 221 and the second connection terminal of the second chip 222 to connect the first chip 221 and the second chip 222 in series.

[0041] In this embodiment, to achieve the parallel connection of multiple chip groups, the second connection terminals of each first chip 221 are connected to each other and connected to the first power signal layer 251, and the first connection terminals of each second chip 222 are connected to each other and connected to the ground wire layer 242. Specifically, to achieve the connection of the second connection terminals of each first chip 221 to each other, a fifth conductive hole 285 is provided at the position of the first insulating layer 271 corresponding to the second connection terminal of the first chip 221 to connect the second connection terminal of each first chip 221 to the first power signal layer 251; the second connection terminals of the first chip 221 are connected in parallel through the first power signal layer 251. To achieve the parallel connection of the second chips 222, the first connection terminals of each second chip 222 are connected to each other. Specifically, to achieve the connection of the first connection terminals of each second chip 222 to each other, a sixth conductive hole 286 is provided at the position of the second insulating layer 261 corresponding to the first connection terminal of the second chip 222 to connect the first connection terminal of each second chip 222 to the ground wire layer 242; the first connection terminals of the second chip 222 are connected in parallel through the ground wire layer 242.

[0042] Furthermore, in this embodiment, a fourth conductive hole 284 is provided at the position of the first insulating layer 271 and the third insulating layer 272 corresponding to the third connection terminals of the first chip 221 and the second chip 222, and the fourth conductive hole 284 is used to connect the third connection terminals of the first chip 221 and the second chip 222 to the control signal layer 252.

[0043] The circuit board shown in this embodiment embeds multiple first chips 221 and second chips 222 in the circuit board, and makes the first chips 221 and the corresponding second chips 222 in series to form a chip group, and makes the chip groups in parallel with each other, so as to realize the thinning and miniaturization of the embedded circuit board, and can achieve the purpose of short signal transmission distance and reduced signal loss.

[0044] Please refer to Figure 4 , which is a schematic flowchart of the first embodiment of the manufacturing method of the circuit board of the present invention. It includes: Step S41: Provide a core board.

[0045] In this application, the material of the core board is a copper clad laminate. The copper clad laminate is the basic material for manufacturing a circuit board, including a base board and a copper foil covering the base. The base board is made by impregnating materials such as a paper base board, a glass fiber cloth base board, a synthetic fiber cloth base board, a non-woven fabric base board, and a composite base board with resin to make a bonding sheet, which is made up of multiple bonding sheets combined, and a copper foil is covered on one or both sides of the made base board, and then hot-pressed and cured to make a copper clad laminate.

[0046] Step S42: Open slots on the core board. The slots include a plurality of first sub-slots and a plurality of second sub-slots located below the first sub-slots and corresponding to the positions of the first sub-slots.

[0047] Use etching, laser drilling, mechanical drilling and other methods to open slots on the core board. In this application, since multiple chips are placed in an array, the slots include first sub-slots and second sub-slots located below the first sub-slots, and the positions of the first sub-slots and the second sub-slots correspond one by one.

[0048] Step S43: Place a chip component in the slots. The chip component includes a plurality of first chips located in the first sub-slots and a plurality of second chips located in the second sub-slots. Among them, each first chip is in series with the corresponding second chip to form a plurality of chip groups; the plurality of chip groups are in parallel with each other, and one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground wire layer.

[0049] Set a chip component in the slots. The chip component includes a first chip and a second chip. The first chip is placed in the first sub-slot, and the second chip is placed in the second sub-slot. And the first chip is in series with the corresponding second chip one by one to form a chip group, and the plurality of chip groups are in parallel with each other, that is, one end of the plurality of chip groups is connected to the first power signal layer, and the other end is connected to the ground wire layer.

[0050] Specifically, please refer to Figure 5 , which is a schematic flowchart of the second embodiment of the manufacturing method of the circuit board of the present invention. Compared with the first embodiment shown above Figure 4 , the difference is that after step S43, it further includes:

[0051] Step S51: Set a first circuit board on one side of the core board, and set a second circuit layer on the side of the core board away from the first circuit layer; wherein, the first circuit layer includes a first power signal layer and a control signal layer, and the second circuit layer includes a ground layer and a second power signal layer.

[0052] Set the first circuit layer and the second circuit layer on both sides of the core board. Specifically, both the first circuit layer and the second circuit layer are circuit networks fabricated on a copper layer. The first power signal layer and the control signal layer are different circuit networks on the first circuit layer respectively, and the ground layer and the second power signal layer are different circuit networks on the second circuit layer respectively.

[0053] Step S52: Set a first insulating layer between the core board and the first circuit layer, and set a second insulating layer between the core board and the second circuit layer.

[0054] Set a first insulating layer between the core board and the first circuit layer to bond the core board and the first circuit layer. Set a second insulating layer between the core board and the second circuit layer to bond the core board and the second circuit layer. Specifically, the first insulating layer and the second insulating layer are prepregs, which serve as the interlayer bonding layer during lamination. Specifically, the prepregs are mainly composed of resin and reinforcing materials. When manufacturing a multilayer circuit board, fiberglass cloth is usually used as the reinforcing material, which is impregnated with resin glue solution and then pre-baked by heat treatment to form a thin sheet. It will soften under heating and pressure, solidify after cooling, and has viscosity, and can bond adjacent two layers during the high-temperature pressing process.

[0055] Please refer to Figure 6 , which is a schematic flow diagram of the third embodiment of the manufacturing method of the circuit board of the present invention. Compared with the Figure 4 first embodiment shown, the difference lies in that after step S43, it further includes:

[0056] Step S61: Set a first power signal layer on one side of the core board, and set a second power signal layer on the side of the core board away from the first power signal layer.

[0057] Wherein, both the first power signal layer and the second power signal layer are located on both sides of the core board, and the first power signal layer and the second power signal layer are circuit layers fabricated with copper layers.

[0058] Step S62: Set a first insulating layer between the core board and the first power signal layer, and set a second insulating layer between the core board and the second power signal layer.

[0059] Wherein, the first insulating layer and the second insulating layer are prepregs, which will not be elaborated here.

[0060] Step S63: A control signal layer is disposed on a side of the first power signal layer away from the core board, and a ground line layer is disposed on a side of the second power signal layer away from the core board.

[0061] Among them, the control signal layer and the ground line layer are also circuit layers made of copper layers. Specifically, the control signal layer is located outside the first power signal layer, and the ground line layer is located outside the second power signal layer.

[0062] Step S64: A third insulating layer is disposed between the first power signal layer and the control signal layer, and a fourth insulating layer is disposed between the second power signal layer and the ground line layer.

[0063] Among them, the fourth insulating layer and the third insulating layer are the same as the first insulating layer and the second insulating layer, and are all prepregs, which will not be elaborated here.

[0064] Please refer to Figure 7 , which is a schematic flowchart of the fourth embodiment of the manufacturing method of the circuit board of the present invention. Compared with the second embodiment shown above Figure 5 and the third embodiment shown in Figure 6 , the difference is that it further includes:

[0065] Step S71: A first conductive hole is disposed at a position of the second insulating layer corresponding to the first connection terminal of the first chip, a second conductive hole is disposed at a position of the first insulating layer corresponding to the second connection terminal of the second chip, and a third conductive hole penetrating through the core board, the first insulating layer and the second insulating layer is disposed between the first chip and the second chip to connect the first connection terminal of the first chip to the second connection terminal of the second chip.

[0066] The first connection terminal of the first chip is connected to the second connection terminal of the second chip through the first conductive hole connecting the first connection terminal of the first chip and the second power signal layer, the second conductive hole connecting the second connection terminal of the second chip and the first power signal layer, and the third conductive hole connecting the second power signal layer and the first power signal layer, so that the first chip and the second chip form a mutually connected chip group in series.

[0067] Step S72: A fifth conductive hole is disposed at a position of the first insulating layer corresponding to the second connection terminal of the first chip to connect the second connection terminal of the first chip to the first power signal layer; and a sixth conductive hole is disposed at a position of the second insulating layer corresponding to the first connection terminal of the second chip to connect the first connection terminal of the second chip to the ground line layer.

[0068] The fifth conductive via connects the second connection terminal of the first chip to the first power signal layer, and the sixth conductive via connects the first connection terminal of the second chip to the ground layer to connect the chip sets in parallel with each other.

[0069] Step S73: A fourth conductive via is provided at a position of the first insulating layer corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer.

[0070] The fourth conductive via connects the third connection terminals of the first chip and the second chip to the control signal layer.

[0071] The circuit board and its manufacturing method provided by the present invention realize the thinning and miniaturization of the circuit board by arranging multiple chips in an array and embedding them in the circuit board. And multiple chips are regularly connected in series and in parallel in the circuit board, so that the signal transmission distance is short and the signal loss is reduced.

[0072] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A circuit board, characterized in that, including a core board, which is provided with a groove body. The groove body includes a plurality of first sub-groove bodies and a plurality of second sub-groove bodies located on one side of the first sub-groove bodies and corresponding to the positions of the first sub-groove bodies. The first sub-groove bodies and the second sub-groove bodies are arranged in an array; a chip assembly, which is arranged in the groove body; the chip assembly includes a plurality of first chips located in the first sub-groove bodies and a plurality of second chips located in the second sub-groove bodies; wherein, each of the first chips is connected in series with the corresponding second chip to form a plurality of chip groups; the plurality of chip groups are connected in parallel with each other, and one end of the plurality of chip groups is connected to a first power signal layer, and the other end is connected to a ground wire layer; a first circuit layer, which is arranged on one side of the core board; a second circuit layer, which is arranged on the side of the core board away from the first circuit layer; a first insulating layer, which is arranged between the core board and the first circuit layer; a second insulating layer, which is arranged between the core board and the second circuit layer; wherein, the first circuit layer includes the first power signal layer and a control signal layer; the second circuit layer includes the ground wire layer and a second power signal layer; wherein, each of the first chips and the second chips includes: a second connection terminal and a third connection terminal on the side close to the first circuit layer, and a first connection terminal close to the second circuit layer; the second insulating layer has a first conductive hole at the position corresponding to the first connection terminal of the first chip to connect the second power signal layer to the first connection terminal of the first chip; the first insulating layer has a second conductive hole at the position corresponding to the second connection terminal of the second chip to connect the first power signal layer to the second connection terminal of the second chip; a third conductive hole penetrating through the core board, the first insulating layer and the second insulating layer is provided between the first chip and the second chip to connect the first power signal layer and the second power signal layer, and further connect the first connection terminal of the first chip to the second connection terminal of the second chip, so as to connect the first chip and the second chip in series to form a plurality of chip groups.

2. The circuit board according to claim 1, wherein The circuit board further includes: a first power signal layer, which is arranged on one side of the core board; a second power signal layer, which is arranged on the side of the core board away from the first power signal layer; a first insulating layer, which is arranged between the core board and the first power signal layer; a second insulating layer, which is arranged between the core board and the second power signal layer; a control signal layer located on the side of the first power signal layer away from the core board; a ground wire layer located on the side of the second power signal layer away from the core board; a third insulating layer located between the first power signal layer and the control signal layer; a fourth insulating layer located between the second power signal layer and the ground wire layer.

3. The circuit board according to claim 2, wherein The first connection terminal of the first chip is coupled to the second connection terminal of the second chip corresponding to its position; the second connection terminal of the first chip is coupled to the first power signal layer, the third connection terminal of the first chip is coupled to the control signal layer, the third connection terminal of the second chip is coupled to the control signal layer, and the first connection terminal of the second chip is connected to the ground layer.

4. The circuit board according to claim 3, wherein the first insulating layer has a fourth conductive hole at a position corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer; or the first insulating layer and the third insulating layer have a fourth conductive hole at a position corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer.

5. The circuit board according to claim 3, wherein the first insulating layer has a fifth conductive hole at a position corresponding to the second connection terminal of the first chip to connect the second connection terminal of the first chip to the first power signal layer; the second insulating layer has a sixth conductive hole at a position corresponding to the first connection terminal of the second chip to electrically connect the first connection terminal of the second chip to the ground layer; or the first insulating layer has a fifth conductive hole at a position corresponding to the second connection terminal of the first chip to connect the second connection terminal of each first chip to the first power signal layer; the second insulating layer and the fourth insulating layer have a sixth conductive hole at a position corresponding to the first connection terminal of the second chip to electrically connect the second connection terminal of each second chip to the ground layer.

6. A method for manufacturing a circuit board, characterized in that, comprising: providing a core board; opening a slot on the core board, the slot including a plurality of first sub-slots and a plurality of second sub-slots located on one side of the first sub-slots and corresponding to the positions of the first sub-slots, and the first sub-slots and the second sub-slots are arranged in an array; placing a chip component in the slot, the chip component including a plurality of first chips located in the first sub-slots and a plurality of second chips located in the second sub-slots, wherein each first chip and the second chip corresponding to its position are connected in series to form a plurality of chip groups; the plurality of chip groups are connected in parallel to each other, and one end of the plurality of chip groups is connected to the first power signal layer and the other end is connected to the ground layer; providing a first circuit layer on one side of the core board and a second circuit layer on the side of the core board away from the first circuit layer; wherein, the first circuit layer includes a first power signal layer and a control signal layer, and the second circuit layer includes a ground layer and a second power signal layer; providing a first insulating layer between the core board and the first circuit layer and a second insulating layer between the core board and the second circuit layer; or A first power signal layer is provided on one side of the core board, and a second power signal layer is provided on the side of the core board away from the first power signal layer; A first insulating layer is provided between the core board and the first power signal layer, and a second insulating layer is provided between the core board and the second power signal layer; A control signal layer is provided on the side of the first power signal layer away from the core board, and a ground wire layer is provided on the side of the second power signal layer away from the core board; A third insulating layer is provided between the first power signal layer and the control signal layer, and a fourth insulating layer is provided between the second power signal layer and the ground wire layer; A first conductive hole is provided at a position of the second insulating layer corresponding to the first connection terminal of the first chip to connect the second power signal layer to the first connection terminal of the first chip; A second conductive hole is provided at a position of the first insulating layer corresponding to the second connection terminal of the second chip to connect the first power signal layer to the second connection terminal of the second chip; A third conductive hole penetrating through the core board, the first insulating layer and the second insulating layer is provided between the first chip and the second chip to connect the first power signal layer and the second power signal layer, and further connect the first connection terminal of the first chip to the second connection terminal of the second chip, so as to connect the first chip and the second chip in series to form a plurality of chip groups.

7. The manufacturing method according to claim 6, wherein The method further includes: A fifth conductive hole is provided at a position of the first insulating layer corresponding to the second connection terminal of the first chip to connect the second connection terminal of the first chip to the first power signal layer; and a sixth conductive hole is provided at a position of the second insulating layer corresponding to the first connection terminal of the second chip to connect the first connection terminal of the second chip to the ground wire layer; A fourth conductive hole is provided at a position of the first insulating layer corresponding to the third connection terminals of the first chip and the second chip to connect the third connection terminals of the first chip and the second chip to the control signal layer.

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