Edge exclusion control

Abstract

The present disclosure provides methods and apparatuses for controlling the process uniformity at the edge region of a semiconductor wafer. In some embodiments, the methods include exposing the edge region to a process gas such as an etch gas and / or an inhibition gas. The present disclosure also provides an exclusion ring assembly including a plurality of ring members, which can be implemented to provide control of the process environment at the wafer edge.

Description

[0001] Incorporation by reference

[0002] The PCT application form is submitted simultaneously with this specification as part of this application. Each application for which this application claims the benefit or priority thereof as identified in the PCT application form submitted simultaneously is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] One challenge in semiconductor processing is to achieve processing uniformity over a wide area as large as the wafer being processed. Controlling the semiconductor processing environment at the edge regions of a semiconductor wafer presents particular challenges. In particular, discontinuities at the edge regions can make uniform processing difficult to achieve. In addition, the edge regions provide fluid flow channels to the underside of the semiconductor. This allows process gases to enter the underside of the semiconductor wafer, where unwanted processing may occur.

[0004] The background description provided here is for the purpose of generally presenting the background of the disclosure. The work of the currently named inventors is neither expressly nor implicitly admitted to be prior art to the disclosure to the extent that it is described in this background art section and in the aspects of the description that could not have been determined to be prior art at the time of filing the application. Summary of the Invention

[0005] One aspect of the present disclosure may be implemented as an apparatus that includes: an exclusion ring assembly configured for processing a semiconductor wafer of a nominal diameter D, the exclusion ring assembly including: an upper annular ring having an outer diameter and an inner diameter less than D; and a lower annular ring having an outer diameter and an inner diameter less than D, wherein the upper annular ring is disposed above the lower annular ring to define an annular gas flow channel between the upper annular ring and the lower annular ring.

[0006] In some embodiments, the annular gas flow channel has an inner diameter and an outer diameter, and a width defined by a gap between the upper annular ring and the lower annular ring, and wherein the width at the inner radius of the annular gas flow channel is less than the width at the outer radius of the annular gas flow channel.

[0007] In some embodiments, the gap between the upper annular ring and the lower annular ring at the inner diameter of the lower annular ring is less than the gap between the upper annular ring and the lower annular ring at the outer diameter of the lower annular ring.

[0008] In some embodiments, the gap between the upper annular ring and the lower annular ring at the inner diameter of the lower annular ring is no greater than 0.1 inch.

[0009] In some embodiments, the inner diameter of the upper annular ring is smaller than the inner diameter of the lower annular ring.

[0010] In some embodiments, the upper annular ring includes an upper surface that is substantially parallel to a reference plane perpendicular to the central axis of the upper annular ring. In some such embodiments, the lower annular ring further includes an inner edge and an inclined surface extending from the inner edge to the upper surface. In some such embodiments, the lower annular ring includes an upper surface that is substantially parallel to a reference plane perpendicular to the central axis of the lower annular ring. In some such embodiments, the upper annular ring further includes an inner edge and an inclined surface extending from the inner edge to the upper surface. In some such embodiments, the inclination of the inclined surface of the upper annular ring is greater than the inclination of the inclined surface of the lower annular ring.

[0011] In some embodiments, the apparatus further includes a susceptor configured to support the semiconductor wafer, the susceptor including a gas injector configured to inject gas at an edge region of the wafer.

[0012] In some embodiments, the apparatus further includes a susceptor supporting the exclusion ring structure, the susceptor including an upper surface and a recess in the upper surface defining a gas passage.

[0013] In some embodiments, the recess is at a distance Y from the center of the susceptor, the distance Y being greater than the inner diameter of the lower annular ring.

[0014] Aspects of the present disclosure may be implemented as a deposition chamber comprising: a susceptor including an upper surface and an annular recess in the upper surface, the annular recess being configured to be in fluid connection with a backside gas source; an exclusion ring assembly mounted on the susceptor, wherein the exclusion ring assembly includes an upper annular ring having an inner diameter and an outer diameter, wherein the upper annular ring is disposed above the lower annular ring to define a lower annular gas flow channel between the upper annular ring and the lower annular ring; and a showerhead disposed above the susceptor and the exclusion ring assembly to define an upper annular gas flow channel between the showerhead and the upper annular ring.

[0015] Aspects of the present disclosure can be implemented as a method, comprising: providing a circular wafer on the pedestal in the deposition chamber including the exclusion ring assembly described herein, the circular wafer having a nominal diameter D, where D is greater than the inner diameters of the upper annular ring member and the lower annular ring member, and where the exclusion ring assembly is disposed above the outer edge of the circular wafer; providing a radial flow of process gas above the circular wafer through the showerhead; and providing backside gas to the edge of the circular wafer through the annular recess in the pedestal.

[0016] In some embodiments, the method further comprises depositing a uniform film from the center of the circular wafer to at least 2 mm or at least 1 mm from the edge of the circular wafer by the process gas.

[0017] Another aspect of the present disclosure can be implemented as a method, comprising: selectively exposing an edge region of a wafer to a gas containing a deposition inhibitor; and exposing an upper surface and an edge region of the wafer to a deposition gas to deposit a film on the upper surface.

[0018] In some embodiments, deposition on the edge region is inhibited such that the film is selectively deposited on the upper surface. In some embodiments, the film is uniform within a range up to 2 mm from the edge of the wafer. In some embodiments, the film is uniform within a range up to 1 mm from the edge of the wafer.

[0019] In some embodiments, the selective exposure to the deposition inhibitor and the exposure to the deposition gas are performed simultaneously. In some embodiments, the selective exposure to the deposition inhibitor is performed before the exposure to the deposition gas.

[0020] In some embodiments, the method further includes: depositing a first film on the upper surface and the edge region before selectively exposing the edge region of the wafer to the gas containing the deposition inhibitor. In some embodiments, the film is a tungsten-containing film, and the deposition inhibitor is a nitrogen-containing compound.

[0021] In some embodiments, selectively exposing an edge region of a wafer to a gas containing a deposition inhibitor comprises: exposing titanium nitride (TiN) to the gas. In some embodiments, the wafer is disposed on a pedestal, and the edge region is disposed below an edge exclusion ring mounted on the pedestal. In some embodiments, the method includes: selectively exposing an edge region of a wafer to a gas containing a deposition inhibitor comprises introducing the gas through the pedestal into the edge region.

[0022] In some such embodiments, transitioning from selectively exposing an edge region of the wafer to a gas comprising the deposition inhibitor to exposing an upper surface and an edge region of the wafer to the deposition gas to deposit a film on the upper surface includes increasing a distance between the excluder ring and the wafer.

[0023] In some embodiments, the method further comprises repeatedly: selectively exposing an edge region of a wafer to a gas containing a deposition inhibitor; and exposing an upper surface and the edge region of the wafer to the deposition gas to deposit a film on the upper surface.

[0024] Another aspect of the present disclosure is implemented as a method, comprising: depositing a nucleation layer on at least a portion of a bevel and an upper surface of a wafer; selectively processing the bevel of the wafer; and depositing a bulk layer on the wafer except for the bevel.

[0025] In some embodiments, selectively treating the bevel includes selectively inhibiting nucleation at the bevel. In some such embodiments, selectively treating the bevel includes selectively etching the nucleation layer at the bevel. In some embodiments, the nucleation layer and the bulk layer are tungsten-containing films.

[0026] Another aspect of the present disclosure may be implemented as a method comprising: flowing a process gas containing a deposition gas over an upper surface of a wafer and passing over an edge of the wafer; flowing a treatment gas over the edge of the wafer; and flowing a process gas containing a deposition gas over an upper surface of the wafer and passing over the edge of the wafer to deposit a film on the upper surface without depositing a film on the edge of the wafer.

[0027] In some embodiments, flowing the process gas includes pulling a vacuum on the back side of the wafer. In some embodiments, the process gas is flowed with an edge exclusion ring in a raised position shielding an edge of the wafer. In some such embodiments, the process gas is flowed with the edge exclusion ring in a lowered position.

[0028] Another aspect of the present disclosure relates to a method comprising: exposing an upper surface and an edge region of a wafer to a deposition gas to deposit a uniform film on the upper surface; and exposing the edge region of the wafer to a gas containing an etchant.

[0029] Another aspect of the present disclosure relates to a method of manufacturing an exclusion ring assembly for processing a semiconductor substrate having a nominal diameter D. The method may involve forming a green body and firing the green body to form a ceramic body, which may optionally be ground to form the exclusion ring assembly. In some embodiments, the exclusion ring assembly may include an upper annular ring having an outer diameter and an inner diameter less than D; and a lower annular ring having an outer diameter and an inner diameter less than D, wherein the upper annular ring is disposed above the lower annular ring to define an annular gas flow channel between the upper annular ring and the lower annular ring. The upper annular ring and the lower annular ring may be formed as separate connectable components or as a single piece. According to many embodiments, the exclusion ring assembly may be made of ceramic (e.g., alumina (Al2O3) or aluminum nitride (AlN)). A method of manufacturing a pedestal including the exclusion ring assembly is also provided. The method may involve manufacturing the exclusion ring assembly and attaching or otherwise disposing the exclusion ring assembly on a pedestal surface.

[0030] These and other aspects are further described below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A An isometric view depicting an example of an exclusion ring mounted on a wafer support that may be used in implementations of the present disclosure is shown.

[0032] Figure 1B An isometric exploded view showing examples of an exclusion ring, a wafer, and a wafer support that may be used in implementations of the present disclosure is shown.

[0033] Figure 1C and 1D A bottom view and a top view, respectively, showing examples of an exclusion ring that may be used in implementations of the present disclosure are shown.

[0034] Figure 1E An enlarged cross-sectional detail view showing an exclusion ring and a wafer that may be used in implementations of the present disclosure is shown.

[0035] Figure 2 A schematic view showing an exemplary configuration of a pedestal including backside gas injection and an exclusion ring that may be used in implementations of the present disclosure is shown.

[0036] Figure 3 A schematic view showing process gas and backside gas streamlines during deposition using an exemplary configuration of a pedestal including backside gas injection and an exclusion ring is shown.

[0037] Figure 4A and 4B are flowcharts showing certain operations in an example of a method of adjusting deposition at the edge of a wafer according to an implementation of the present disclosure.

[0038] Figure 5A and 5B is a flowchart showing certain operations in an example of a method for depositing tungsten (W) or a W-containing film according to an implementation of the present disclosure.

[0039] Figure 6A and 6B showing according to Figure 5A and 5B the schematic configuration of the exclusion ring 600 and the wafer during the deposition process in an example of the tungsten deposition method described above.

[0040] Figure 7A and 7B shows a schematic diagram of a susceptor configuration including backside gas injection and an exclusion ring that can be used in an implementation of the present disclosure.

[0041] Figure 8 shows an exemplary exclusion ring assembly having two ring members mounted on a substrate support according to an implementation of the present disclosure.

[0042] Figure 9A is Figure 8 an isometric cross-sectional view of the exclusion ring assembly, susceptor, and wafer shown in Figure 9B and Figure 9A is a detailed view of the indicated area in

[0043] Figure 9C and 9D shows a schematic diagram of the process gas flow lines of an exclusion ring assembly having two ring members at different showerhead - upper ring member clearances.

[0044] Figure 10A , 10B , and 10C respectively show a top view, a side view, and a bottom view of an example of the lower ring member of an exclusion ring assembly having two ring members according to an implementation of the present disclosure.

[0045] Figure 11A , 11B and 11C respectively show a top view, a side view, and a bottom view of an example of the upper ring member of an exclusion ring assembly having two ring members according to an implementation of the present disclosure.

[0046] Figure 12 shows a detailed view of a portion at the inner circumferences of the upper and lower ring members of an example of a ring assembly having two ring members according to an implementation of the present disclosure.

[0047] Figure 13 shows an example of the tungsten (W) growth delay time varying with the deposition thickness.

[0048] Figure 14Schematic diagram of an example of a processing chamber suitable for deposition and processing processes according to an implementation of the present disclosure.

[0049] Figure 15 Schematic diagram of an example of a processing apparatus suitable for deposition and processing processes according to an implementation of the present disclosure. Detailed implementation

[0050] Examples of various implementations are shown in the accompanying drawings and further described below. It should be understood that the discussion herein is not intended to limit the claims to the specific implementations described. On the contrary, it is intended to cover permutations, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the disclosed subject matter. Various implementations of the subject matter may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail in order not to obscure the subject matter described herein.

[0051] Methods and apparatuses for controlling processing uniformity at the edge region of a semiconductor wafer are provided herein. In some implementations, the methods include exposing the edge region to a processing gas such as an etching gas and / or an inhibiting gas. An exclusion ring assembly including a plurality of rings is also provided herein, which can be implemented to provide control of the processing environment at the wafer edge.

[0052] Implementations of using an exclusion ring during semiconductor processing to practice the methods herein. An exclusion ring (also referred to as a minimum overlap exclusion ring or MOER) mounted on a wafer support can be used to manage the gas flow and processing environment along the wafer edge. Examples of exclusion rings that can be used in implementations of the methods described herein are described below with reference to Figures 1A - 1E for description.

[0053] In Figure 1A , an isometric view of an exclusion ring mounted on a wafer support is depicted. The exclusion ring 100 can be used to manage the gas flow and processing environment along the edge of the wafer 101, the edge of which can be supported by the wafer support 103. Figure 1B An isometric exploded view showing the exclusion ring 100, the wafer 101, and the wafer support 103 is shown.

[0054] Figure 1C and 1DThe bottom view and top view of the exclusion ring are shown respectively. The exclusion ring 100 can be broadly described as a thin annular ring member having an inner diameter 120 and an outer diameter 122. In some implementations, the exclusion ring 100 may include a plurality of tongues 104 that project radially from the outer periphery of the annular ring member 102. The upper surface 106 and the lower surface 108 of the exclusion ring 100 (which may also be referred to as the first and second surfaces herein) may be substantially parallel to a reference plane perpendicular to the central axis of the annular ring member. It should be understood that the terms "upper" and "lower" with respect to the exclusion ring are relative terms in the context of this application, which refer to the surfaces of the exclusion ring that appear as "upper" and "lower" when the exclusion ring is used in a semiconductor processing environment, rather than any arbitrary upper and lower defined by the orientation of the exclusion ring in any given situation. In addition, there may be portions of the upper surface 106 and the lower surface 108 that are not parallel to the reference plane. For example, the lower surface 108 of the exclusion ring 100 may be characterized by a recess that allows the exclusion ring 100 to be disposed above the semiconductor wafer without resting on the semiconductor wafer, such that the depth of the recess may be greater than the nominal thickness of the semiconductor wafer. The inner diameter 122 of the exclusion ring 100 may be smaller than the nominal diameter of the semiconductor wafer, and thus when used in the methods described herein, there may be some radial overlap between the semiconductor wafer and the exclusion ring 100, for example, between 0.05" and 0.5". The recess may be included within an intermediate diameter greater than the nominal diameter of the semiconductor wafer. The portion of the lower surface 108 where the transition to the recess occurs may be inclined, and thus the transition portion may represent a restricted area where the lower surface is not parallel to the reference plane. However, overall, the upper surface 106 and the lower surface 108 may be substantially parallel to the reference plane such that most of the radial distance of the surfaces is parallel to the reference plane. The upper surface 106 and the lower surface 108 may be offset from each other by a distance greater than the nominal thickness of the semiconductor wafer.

[0055] The upper surface 106 of the exclusion ring 100 may include an inclined portion, as Figure 1E shown in Figure 1E an example of an enlarged cross-sectional detail view showing the edge of the wafer 103 and the exclusion ring 100. As shown, the upper surface 106 includes an inclined portion 111. The wafer 103 is disposed in the recess 109 of the exclusion ring 100 such that the edge 104 of the wafer is directly disposed below the exclusion ring 100. The edge 104 of the wafer 101 is a chamfered edge such that it slopes from the horizontal upper surface of the wafer. Deposition of material on the chamfer can be avoided while maintaining good uniformity on the horizontal top surface. For example, after depositing a relatively thick (e.g. ) film (e.g. tungsten), a chemical mechanical planarization (CMP) process can be performed to planarize the film. Avoiding deposition on the chamfered edge is useful because deposition on the chamfered edge will not be removed by planarization.

[0056] In the deposition of materials such as tungsten, the exclusion ring can be used to regulate the deposition at the edge of the wafer.Figure 2 Shows a schematic view of a pedestal (or other wafer support) including a dorsal gas injection and evacuation ring. Dorsal gas (e.g., argon (Ar) and / or hydrogen (H2)) can be made to flow to prevent deposition gas (e.g., tungsten hexafluoride / hydrogen (WF6 / H2) or tungsten chloride / hydrogen (WCl x / H2)) from reaching the edge of wafer 201. The evacuation ring 200 prevents dorsal deposition by guiding the flow of dorsal gas at the edge of the wafer 201 in the space established by the evacuation ring 200, the wafer support 203, and the wafer 201. As Figure 2 shown, the evacuation ring 200 extends above the wafer 201, and there is a gap between the top of the wafer 201 and the evacuation ring 200. One or more of the overhang, the gap, and the gap between the evacuation ring 200 and the showerhead (not shown), as well as the flow rate and type of the dorsal gas, can be adjusted to control the deposition profile at the edge.

[0057] In Figure 3 the example shown, in the deposition of tungsten (W), the Ar / H2 flow as indicated by the streamline 310 below the evacuation ring 300 pushes back the deposition gas (e.g., WF6 / H2 or WCl x / H2), thus preventing it from reaching the edge of the wafer 301 and therefore avoiding the deposition of tungsten at the edge. The profile of the evacuation ring 300 is such that the streamline 312 of the gas flow traveling radially outward above the wafer from the showerhead bends upward around the ring. This upward bending reduces the concentration of WF6 or other tungsten precursor gas on the wafer surface near the ring.

[0058] Figure 3 The technique depicted in Figure 3 is effective in eliminating tungsten deposition at the wafer bevel and at the same time provides uniform deposition up to 3 mm from the edge. That is, for a 300 mm wafer (150 mm radius),

[0059] Figure 4A and 4BA flowchart showing certain operations for adjusting deposition at the wafer edge. In a particular embodiment, deposition at the edge is inhibited and / or removed, and at the same time uniform deposition is provided up to a certain distance from the edge (including up to 2 mm from the edge, or up to 1 mm from the edge). That is, for a 300 mm wafer, uniform deposition can be provided from 0 to 148 mm (2 mm from the edge) or from 0 to 149 mm (1 mm from the edge) from the center of the wafer, while avoiding deposition on the beveled edge. Other values in the range of 1 mm - 3 mm from the edge can be implemented using the methods and apparatuses described herein. According to many embodiments, these methods can be used to provide a thickness non-uniformity of less than 1% up to a certain distance on the wafer, where the non-uniformity is measured as 100% multiplied by (half of the maximum deviation of the thickness (tmax - tmin) divided by the average thickness).

[0060] First, in Figure 4A Method 400 can be used to inhibit deposition on the beveled edge. The edge region of the wafer is exposed to a gas containing a deposition inhibitor (401). For the deposition of tungsten or tungsten-containing films, the deposition inhibitor can be a nitrogen-containing compound, such as nitrogen (N2), ammonia (NH3), or hydrazine (N2H4). The inhibition can be a plasma or thermal (non-plasma) treatment. Ammonia or hydrazine can be used for thermal treatment. In some embodiments, the thermal inhibition treatment is performed at a temperature in the range of 250 °C to 450 °C. At these temperatures, exposing a previously formed tungsten nucleation layer to NH3 results in an inhibitory effect. Other potential inhibitory chemicals (such as nitrogen (N2) or hydrogen (H2)) can be used for thermal inhibition at higher temperatures (such as 900 °C). However, for many applications, these high temperatures exceed the thermal budget. Hydrogen-containing nitridants (such as ammonia and hydrazine) can be used at lower temperatures suitable for back-end-of-line (BEOL) applications.

[0061] In some embodiments, the inhibition can involve a chemical reaction between the inhibitor substance and the feature surface to form a thin layer of a compound material such as silicon nitride (SiN), or involve surface effects such as adsorption that passivate the Si or other surfaces without forming a compound material layer. In some embodiments, a thin tungsten layer can be present on the beveled surface and form a tungsten nitride layer.

[0062] In some embodiments, the inhibition treatment can be applied before or after the deposition of the nucleation layer or bulk layer on the wafer. For example, the inhibition treatment can be performed on a wafer including a barrier layer (such as a titanium nitride (TiN) or tungsten nitride (WN) layer), a tungsten nucleation layer, or a tungsten bulk layer on the exposed surface.

[0063] Expose the upper surface of the wafer to a deposition gas (403). For example, deposition can be carried out by atomic layer deposition (ALD) or chemical vapor deposition (CVD) methods. In the former, the wafer is exposed to alternating pulses of reactant gases. In the example of tungsten deposition, tungsten-containing precursors such as tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), tungsten pentachloride (WCl5), tungsten hexacarbonyl (W(CO)6), or tungsten-containing organometallic compounds can be used. In some embodiments, the pulse of the tungsten-containing precursor is pulsed together with a reducing agent (such as hydrogen (H2), diborane (B2H6), silane (SiH4), or germane (GeH4)). In the CVD method, the wafer is simultaneously exposed to reactant gases.

[0064] In some embodiments, since the beveled edges have been passivated, even if some deposition gas reaches the beveled edges, the film will not be deposited there. In some embodiments, the film may be deposited, but to a lesser extent compared to the upper surface of the wafer. Block 403 can occur after block 401, or block 403 can partially or completely overlap with block 401.

[0065] In Figure 4B it, method 410 can be used to etch the film deposited on the beveled edges. Block 405 involves exposing the upper surface of the wafer to reactant gases to deposit a film. For example, the deposition can be an ALD or CVD method. The edge region of the wafer is exposed to an etchant (407). For example, to etch a tungsten film, nitrogen trifluoride (NF3) or molecular fluorine (F2) can be used. Block 407 can occur after block 405, or block 407 can partially or completely overlap with block 405.

[0066] In some embodiments, a method can include edge suppression, uniform upper surface deposition, and edge etching. Any one or the entire cycle of these operations can be repeated one or more times to achieve the desired profile.

[0067] Figure 5A and 5B shows a method for depositing tungsten (W) or a W-containing film. First, in Figure 5A it, in method 500, the wafer is exposed to reactant gases to deposit a W nucleation layer (501) everywhere on the wafer. The deposition of the W nucleation layer is described below, and it can involve pulsed nucleation layer (PNL) or atomic layer deposition (ALD) processes. In some embodiments, during this stage, there is deposition on the beveled edges of the wafer. There is also uniform deposition everywhere on the wafer. According to many embodiments, the uniform deposition can reach at least a threshold distance from the edge, such as at least 2 mm from the center of the wafer outward (1.7 mm from the 0.3 mm bevel), or at least 1 mm from the edge of the wafer outward (0.7 mm from the 0.3 mm bevel).

[0068] The nucleation layer is thin, for example about The deposition on the beveled edges (if any) can be uniform or discontinuous. Next, the edge region of the wafer is exposed to a gas (503) containing an inhibiting chemical. The inhibition of tungsten nucleation is further described below. The flow of the inhibiting gas is controlled so that the upper surface of the wafer is not exposed to the inhibiting chemical. The techniques for controlling the gas are further described below with reference to Figure 6A , 6B , 7A, and 7B. Blocks 501 and 503 are examples of blocks 401 and 403, respectively, in the process according to Figure 4A .

[0069] The wafer is exposed to a reactant gas to deposit a bulk tungsten layer (505) on the upper surface. The deposition of the W bulk layer is described below and may involve ALD or CVD processes. Since nucleation on the beveled edges has been inhibited, there is a significant nucleation delay there, preventing tungsten growth. Figure 13 Shows the W growth delay time as a function of deposition thickness. It can be seen that the growth delay is significant, especially on thin tungsten layers such as the nucleation layer. The upper surface of the wafer is not inhibited (at least out to the desired radius, e.g., 0.7 mm or 1.7 mm from the bevel), and has a uniform deposition thereon.

[0070] It should be noted that block 505 can occur after block 503 is completed, or can overlap completely or partially with block 503. If it overlaps, the edge region is exposed to the inhibiting gas, and at the same time the top of the wafer is exposed to the deposition gas. This approach can be implemented when the inhibiting gas is chemically inert to the deposition gas or is chemically compatible with the deposition gas.

[0071] In Figure 5B , in operation 501, the wafer is exposed to a reactant gas to deposit a W nucleation layer everywhere on the wafer, as described above for Figure 5A . Next, the edge region is exposed to a gas containing a W etchant to remove the deposited film (502). The W etchant chemical is described below. The flow of the etchant gas is controlled so that the upper surface of the wafer is not exposed to the etchant chemical. The techniques for controlling the gas are further described below with reference to Figure 6A , 6B , 7A, and 7B. Blocks 501 and 502 are examples of blocks 405 and 407, respectively, in the process according to Figure 4B .

[0072] Next, in operation 505, the wafer is exposed to a reactant gas to deposit a bulk tungsten layer on the upper surface, as described above with respect to Figure 5AAs described above. Since the nucleation layer on the edge bevel has been removed to expose the underlying surface (e.g., titanium nitride (TiN)), tungsten will not grow there. The upper surface of the wafer has a uniform deposition (at least outward to the desired radius (e.g., at 0.7 mm or 1.7 mm from the bevel)).

[0073] It should be noted that block 505 can occur after block 502 is completed, or can completely or partially overlap with block 502. If it overlaps, the edge region is exposed to the etchant gas, and at the same time the top of the wafer is exposed to the deposition gas.

[0074] Figure 6A Shows a schematic configuration of the exclusion ring 600 and the wafer during the deposition process, according to the example described above with respect to Figure 5A and 5B As discussed, a vacuum is used to direct the process gas streamlines under and around the edge of the exclusion ring 600, while an inhibitor and / or etchant gas source is used to process the edge. The amount of process gas pulled downward by the draw to control the wafer uniformity near the edge, while the amount of process gas and / or the number of its pulses in the cavity at least partially control the bevel and backside deposition.

[0075] First, a W nucleation layer is deposited over the entire wafer (including the edge). Unlike the configuration shown in Figure 3 in which at least some of the process gas streamlines 312 bend around the exclusion ring 300, in this embodiment, at least some of the process gas is pulled under the ring by a vacuum. For example, this vacuum can be pulled through a pedestal having a radial vacuum capability. The result is a nucleation layer 620 that extends throughout the wafer, including at the bevel. Next, a wafer edge treatment is applied. This operation can occur at the same or a different workstation or chamber as the nucleation layer deposition. Here, an inhibitor gas (e.g., NH3) or an etchant gas (e.g., NF3) (also referred to as a treatment gas) is added under the edge ring to treat the edge. The gas can be added through the backside gas manifold as appropriate. An inert gas (e.g., Ar) flow can be used to prevent the diffusion of the inhibitor or etchant gas. In some embodiments, the treatment gas can be diluted. By appropriately controlling the vacuum, the treatment gas flow rate and concentration, and the gap distance between the exclusion ring and the wafer, the wafer region exposed to the treatment gas is controlled (it should be noted that the treatment gas can be added at any suitable location near the edge, including along the backside or through the ring).

[0076] As a result, the edge region 622 is inhibited and / or etched, but the remainder of the upper surface of the film is not inhibited or etched. Next, a vacuum is again applied to fully deposit the body layer 624. Although the vacuum pulls the process gas downward around the wafer edge (thus ensuring uniform deposition on the upper surface up to at least the threshold radius), the tungsten film does not grow on the inhibited or etched surface as described above.

[0077] Figure 6B Shows another example of the exclusion ring 600 and the schematic configuration of the wafer during the deposition process according to the example described above with respect to Figure 5A and 5B This example is similar to the example of Figure 6A , but a common vacuum implementation can be utilized instead of a vacuum pulled across the pedestal. In Figure 6A , the vacuum is used to direct the process gas streamlines below the exclusion ring 600 and around the wafer edge, while an inhibitor and / or etchant gas source is used to process the edge. The amount of process gas pulled downward to direct the streamlines controls the wafer uniformity near the edge, while the amount of process gas and / or the number of its pulses in the cavity at least partially controls the bevel angle and backside deposition.

[0078] In Figure 6A , a W nucleation layer is deposited everywhere on the entire wafer (including the edge). Here, the deposition is performed with the exclusion ring 600 lifted away from the wafer. This causes the common vacuum to pull the process gas above and below the exclusion ring 600. The process gas pulled above the exclusion ring is pulled through the gap between the exclusion ring 600 and the showerhead (not shown). Thus, the amount of gas flowing below the exclusion ring 600, and thus the deposition on the edge, can be controlled by the size of the gap between the wafer and the exclusion ring 600 relative to the size of the gap between the exclusion ring and the showerhead. In the example of Figure 6B , the result is a nucleation layer 620 extending everywhere on the wafer (including at the bevel angle). Next, wafer edge treatment is applied. This operation can occur at the same or a different workstation or chamber as the nucleation layer deposition. Here, an inhibitor gas (such as NH3) or an etchant gas (such as NF3) (also referred to as a process gas) is introduced below the exclusion ring 600 to process the edge. The gas can be introduced through the backside gas manifold as appropriate. An inert gas stream (such as Ar) can be used to prevent the diffusion of the inhibitor or etchant gas. In some embodiments, the process gas can be diluted. Here, the exclusion ring 600 is positioned relative to Figure 6AIt descends to the raised position in [the description]. That is, it can be fully lowered or lowered to an intermediate level. This is to prevent the process gas from flowing through the rest of the wafer. According to many embodiments, the gas may or may not be pulled under the wafer through a common vacuum. By appropriately controlling the common vacuum, the process gas flow rate and concentration, and the gap distance between the exclusion ring 600 and the wafer, the area of the wafer exposed to the process gas is controlled. The process gas can be introduced at any suitable position near the edge (including positions along the backside or through the ring).

[0079] As a result, the edge region 622 is inhibited and / or etched, but the rest of the upper surface of the film is not inhibited or etched. Then, the exclusion ring 600 is raised to completely deposit the body layer 624. Although the common vacuum pulls the process gas downward around the wafer edge (thus ensuring uniform deposition on the upper surface up to at least the threshold radius), the tungsten film does not grow on the inhibited or etched surface as described above.

[0080] Figure 7A and 7B is a schematic diagram of an additional configuration for edge processing according to many embodiments. In Figure 7A , the process gas (such as NH3 or NF3) is introduced from the backside through the base 703, similar to Figure 6A or 6B. Here, the exclusion ring 700 provides a physical barrier 715 for the backside process gas, which establishes an exclusion zone near the bevel of the wafer 701 (for example, between 0 and 1 mm or between 0 and 2 mm from the edge). Ar or other inert gases can be made to flow in other areas to prevent the process gas from diffusing outside the exclusion zone. In Figure 7B , the process gas can flow from the top side instead of the back side, or the process gas can flow from the top side in addition to the back side, and the Ar flow prevents the process gas from diffusing. The baffle 707 that extends the showerhead 705 can provide a physical barrier for the diffusion of the process gas toward the center of the wafer.

[0081] This document also provides an exclusion ring and related equipment including multiple planes to guide the process gas flow. Figure 8 An exclusion ring assembly 800 having two ring members mounted on a substrate support 803 is shown. The substrate support 803 is shown as supporting a substrate (in this example, a wafer 803). The substrate support 803 includes an annular recess 844 that is in fluid communication with a backside gas source, and the backside gas can flow through the annular recess 844.

[0082] The exclusion ring assembly 800 includes a lower and an upper ring. The lower ring guides the backside gas flow to prevent backside deposition, or backside and edge deposition, while the upper ring guides the process gas near the substrate at the edge to control the deposition there. In this way, the prevention of backside and edge deposition and the uniform deposition up to the threshold distance required for uniform deposition are decoupled. According to various embodiments, the lower and upper rings may be fixed or movable relative to each other. The amount of gas directed to the threshold edge can be controlled by the gap between the showerhead 805 and the upper ring; by moving the upper ring closer to the showerhead 805, more flow enters the gap between the lower and upper rings, increasing the deposition at the edge. Exemplary implementations of the edge ring assembly are further described below.

[0083] Figure 9A is Figure 8 an isometric cross-sectional view of the exclusion ring assembly, pedestal, and wafer shown in, and Figure 9B is Figure 9A a detailed view of the indicated area in. The ring assembly 900 includes an upper ring 930 and a lower ring 932 and is mounted on the pedestal 903. The upper ring 930 is offset from the lower ring 932 to define a lower annular gas flow channel 934. It should be noted that in the lower annular gas flow channel 934, there may be connections (not shown) between the upper ring 930 and the lower ring 932; these connections may be small enough so as not to impose a non-negligible obstruction to the gas flow. A vacuum can be drawn to pull the process gas through the lower annular gas flow channel 934 and between the showerhead (not shown) and the upper ring 930. The amount of gas directed to the threshold edge can be controlled by the relative sizes of the lower annular gas flow channel 934 and the gas flow region between the upper ring 930 and the showerhead. For implementations where the upper ring 930 is fixed relative to the lower ring 932, the amount of gas can be controlled by the gap between the showerhead and the upper ring 930: by moving the upper ring 930 closer to the showerhead 805, more flow enters the gap between the lower and upper rings, increasing the deposition (or other processing) at the edge. This is further described below with respect to Figure 9C and 9D

[0084] Figure 9C and 9D provide schematic diagrams of the process gas streamlines 912 of the exclusion ring assembly 900 for different showerhead-upper ring gaps. The ring assembly 900 includes an upper ring 930 and a lower ring 932, which may be fixed relative to each other. The annular gap between the upper ring 930 and the showerhead 905 defines an annular gas flow channel 936. In Figure 9C , the upper ring 930 is closer to the showerhead 905 than in Figure 9Dfarther away; thus in Figure 9C than in Figure 9D more process gas (such as represented by process gas streamline 912) is drawn through the annular gas channel 936. In Figure 9D where the showerhead 905 is closer to the upper ring member 930, more process gas (such as represented by process gas streamline 912) is drawn through the lower annular gas channel 934 than in Figure 9C where the showerhead 905 is farther from the upper ring member 930. Thus, in Figure 9D the concentration of the process gas is greater at the edge threshold distance. The threshold distance can be the distance where uniform processing is desired, such as shown at point 905 in Figure 9C and 9D ; point 905 is a point on a circle that defines an exclusion zone between the bevel and the circle. Gas can be injected to provide flow through the annular recess 944 in the susceptor 903; this can avoid deposition on the bevel and the backside, as described above. In some implementations, it can be controlled to avoid deposition in the exclusion zone, as described above. In this way, the relative sizes of the upper annular gas channel 936 and the lower annular gas channel 934 provide control of the process gas concentration (and thus deposition or other processing) at the exclusion ring boundary, which is at least partially decoupled from preventing backside and edge processing. In Figure 9C and 9D 's example, the susceptor - showerhead distance can be changed, for example, by raising or lowering the susceptor.

[0085] According to various embodiments, such as Figure 8 and the ring assemblies including upper and lower ring members described in 9A - 9D can be used in any of the above methods for exposing the edge region to an inhibitor or etchant gas. In other embodiments, such a ring assembly can be used in methods without selectively inhibiting or etching the edge region; that is, the ring assembly itself can provide sufficient control of the process gas concentration at the exclusion zone boundary, and the backside gas prevents edge deposition to provide uniform deposition and negligible deposition in the exclusion zone. According to many embodiments, the exclusion ring assembly can be used in deposition processing to provide non - uniformity of less than 1% up to at least 2 mm or 1 mm from the wafer edge, where non - uniformity is measured as half of 100% (the maximum deviation of the thickness (t max - t min ) divided by the average thickness).

[0086] With respect to Figures 10A - 10C and Figures 11A - 11C the characteristics of the upper and lower ring members of the ring assembly are described. First, Figure 10A 、 10B10C, 11C respectively show a top view, a side view, and a bottom view of an example of the lower ring member 1032, which has an inner diameter 1020 and an outer diameter 1022. Figure 10A Three recesses 1070 are shown in the upper surface of Figure 10A ; these recesses 1070 receive the cylinders of the upper ring member. Other features may be present on the lower ring member, such as the tongues or other features described with respect to the exclusion ring 100 above.

[0087] Figure 11A , 11B 10C, 11C respectively show a top view, a side view, and a bottom view of an example of the upper ring member 1030. Three cylinders 1172 protruding from the lower surface are shown; these cylinders 1172 fit within the recesses 1070 in the lower ring member 1032. Other features may be present on the upper ring member, such as those described above with respect to the exclusion ring 100. It should be understood that the recesses may be located in the upper ring member and the cylinders in the lower ring member, or the ring members may be physically connected by any suitable connection.

[0088] In some embodiments, the inner diameter 1122 of the upper ring member is less than the inner diameter 1022 of the lower ring member, such that the upper ring member extends inwardly above the lower ring member. In some other embodiments, the inner diameter 1022 of the lower ring member may be less than the inner diameter 1122 of the upper ring member. If the inner diameter of the upper ring member (ID upper ) is too large relative to the inner diameter of the lower ring member (ID lower ), the upper ring member may not effectively direct the process gas. If the inner diameter of the upper ring member (ID upper ) is too small, it accumulates gas at a location further from the edge than desired. In some embodiments, for a ring assembly for a 300 mm wafer, the upper ring member may extend from 0.04 inches less than the lower ring member to more than 0.12 inches beyond the lower ring member:

[0089] ID lower -0.12 inches ≤ ID upper ≤ ID lower +0.04 inches

[0090] It should be understood that these parameters may vary depending on factors including wafer size, deviation between the ring members, etc.

[0091] Figure 12 Shows a detailed view of a portion of the ring assembly 1200 at the inner circumferences of the upper and lower ring members. As described above with respect to the exclusion ring 100 in Figures 1A - 1E , each of the upper ring member 1230 and the lower ring member 1232 has substantially parallel upper and lower (or first and second) surfaces. In Figure 12 Figures 1A - 1E the exclusion ring 100, each of the upper ring member 1230 and the lower ring member 1232 has substantially parallel upper and lower (or first and second) surfaces. In Figure 12Among them, the upper ring member 1230 has an upper surface 1206a and a lower surface 1208a, which are substantially parallel to each other and substantially parallel to a reference plane perpendicular to the central axis of the annular ring member. The lower ring member 1232 has an upper surface 1206b and a lower surface 1208b, which are substantially parallel to each other and substantially parallel to a reference plane perpendicular to the central axis of the annular ring member. In Figure 12 In an example, the lower ring member 1232 further includes a recess 1209, which enables the ring assembly 1200 to be disposed above the wafer.

[0092] Each of the upper ring member 1230 and the lower ring member 1232 has an inclined surface adjacent to its corresponding upper surface. The upper ring member 1230 includes an inclined upper surface 1211a, while the lower ring member includes an inclined upper surface 1211b. It should be noted that although the upper surface 1206a and the inclined upper surface 1211a are depicted as being separated by an edge, in some of the described solutions, there will be an arc between these upper surfaces, as Figure 1E depicted. Thus, the inclined upper surface 1211a can be an inclined portion of the upper surface 1206a or a separate surface. Similarly, the inclined upper surface 1211b can be an inclined portion of the upper surface 1206b or a separate surface. The inclination angle of the inclined upper surface 1211a of the upper ring member 1230 is greater than the inclination angle of the inclined upper surface 1211b of the lower ring member 1230. An exemplary inclination angle of the inclined upper surface 1211a of the upper ring member 1230 is in the range of 15 degrees to 80 degrees with respect to the horizontal plane. An exemplary inclination angle of the inclined upper surface 1211b of the lower ring member 1232 is in the range of 1 degree to 45 degrees with respect to the horizontal plane.

[0093] In Figure 12 In an example, the upper ring member 1230 further has an inclined lower surface 1213, which can be an inclined portion of the lower surface 1208a or a separate surface separated by an edge. The annular gas flow channel 1234 can be defined by the inclined lower surface 1213, the lower surface 1208a, the inclined upper surface 1211b, and the upper surface 1206b. The inclination degrees of the inclined upper surface 1211b and the inclined lower surface 1213 can be such that the deviation (D1) of the upper and lower ring members at the inner opening of the annular gas channel 1234 is less than the deviation (D2) at the outlet of the annular gas channel. In Figure 12 In an example, since the upper surface 1206b is parallel to the lower surface 1208a, the deviation D2 is the same as the deviation at the outlet. This is to provide fine control at the inner end of the upper ring member by bringing the upper ring member closer to the wafer surface and at the same time reducing the flow restriction in the annular gas channel itself. In one example, the distance D1 can be 0.062 inches, while D2 can be 0.125 inches.

[0094] In Figure 12In the example, the upper ring member 1230 includes an inner surface 1214a, and the lower ring member includes an inner surface 1214b. In some implementations, these inner surfaces may be omitted. Exemplary dimensions of the above inner surfaces may range from 0 (if absent) to 0.08 inches.

[0095] The exclusion ring assembly as described above may be a ceramic material, including alumina or aluminum nitride. A method of manufacturing the exclusion ring assembly is also provided, and it may include forming a green body from ceramic powder, firing the green body, and then grinding it to form any of the above exclusion ring assemblies. The upper and lower ring members may be manufactured as separate components or a single component. The exclusion ring assembly may be attached to the base or disposed on the base without attachment. In some embodiments, guides on the base may be used to hold the exclusion ring in place. In some embodiments, the base may be cast or welded, brazed, and machined. A base with appropriate guides may be formed.

[0096] Although the above description mainly describes the use of the exclusion ring in the context of tungsten deposition, these exclusion rings can be implemented for the following processes: uniform processing up to a threshold distance from the wafer edge without processing at the edge or properly processing the edge, using any relevant semiconductor processing operations. Relevant processing operations include the operation of radially distributing process gas from the showerhead in the chamber. Processes in a continuous flow state (for which uniformity up to very close to the substrate edge (without deposition on the substrate edge or backside) is desired) may be advantageous. These processes include any CVD or ALD operations, which include the deposition of conductive or dielectric materials, including (but not limited to) tungsten nitride (WN) and tungsten carbide (WC), titanium-containing materials (such as titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), titanium carbide (TiC), and titanium aluminide (TiAl)), aluminum-containing materials, nickel-containing materials, ruthenium-containing materials, cobalt-containing materials, molybdenum-containing materials, etc.

[0097] In some implementations, the methods described herein involve depositing a nucleation layer before depositing the bulk layer. As described above, the nucleation layer is deposited over the entire wafer, including on the beveled surfaces of the wafer. The nucleation layer is typically a thin conformal layer that promotes the subsequent deposition of bulk material thereon. For example, the nucleation layer may be deposited on the wafer surface before any filling of features and / or at subsequent time points during feature filling (e.g., via interconnects). For example, in some implementations, the nucleation layer may be deposited after etching tungsten in the features and before the initial tungsten deposition.

[0098] In some implementations, a pulse nucleation layer (PNL) technique is used to deposit a nucleation layer. In the PNL technique for depositing a tungsten nucleation layer, pulses of a reducing agent, an optional purge gas, and a tungsten-containing precursor are sequentially injected into a reaction chamber and purged from the reaction chamber. This process is repeated in a cyclic manner until a desired thickness is achieved. PNL generally encompasses any cyclic process that sequentially adds reactants to react on a semiconductor substrate, including atomic layer deposition (ALD) techniques. The PNL technique for depositing a tungsten nucleation layer is described in the following U.S. patents and patent publications: U.S. Patent Nos. 6,635,965; 7,005,372; 7,141,494; 7,589,017; 7,772,114; 7,955,972; and 8,058,170, and U.S. Patent Publication No. 2010-0267235, all of which are hereby incorporated by reference in their entireties. The nucleation layer thickness can depend on the nucleation layer deposition method and the desired quality of the bulk deposition. Generally, the nucleation layer thickness is sufficient to support high-quality, uniform bulk deposition. Examples can be in the range of and

[0099] Although examples of PNL deposition are provided above, the methods described herein are not limited to a particular method of tungsten nucleation layer deposition, but include the deposition of a bulk tungsten film on a tungsten nucleation layer formed by any of the following methods: including PNL, ALD, CVD, and physical vapor deposition (PVD). Additionally, in some implementations, bulk tungsten can be directly deposited in a feature without using a nucleation layer. For example, in some implementations, the feature surface and / or the underlying layer that has been deposited support the deposition of bulk tungsten. In some implementations, a bulk tungsten deposition process without using a nucleation layer can be performed. For example, U.S. Patent Application No. 13 / 560,688, filed on July 27, 2012 (incorporated herein by reference), describes the deposition of a tungsten bulk layer without a nucleation layer.

[0100] In many implementations, tungsten nucleation layer deposition can involve exposure to a tungsten-containing precursor, such as tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), and tungsten hexacarbonyl (W(CO)6). In some implementations, the tungsten-containing precursor is a halogen-containing compound, such as WF6. Organometallic compounds and fluorine-free precursors, such as MDNOW (methylcyclopentadienyl-dicarbonylnitrosyl-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitrosyl-tungsten), can also be used.

[0101] Examples of reducing agents can include boron-containing reducing agents that include diborane (B2H6) and other boranes, silicon-containing reducing agents that include silane (SiH4) and other silanes, hydrazine, and germane. In some implementations, pulses of a tungsten-containing precursor can be alternated with pulses of one or more reducing agents, e.g., S / W / S / W / B / W, etc., where W represents the tungsten-containing precursor, S represents the silicon-containing precursor, and B represents the boron-containing precursor. In some implementations, a separate reducing agent may not be used, e.g., the tungsten-containing precursor may undergo thermal or plasma-assisted decomposition.

[0102] According to various implementations, hydrogen may or may not flow in the background. Additionally, in some implementations, one or more processing operations can be performed after deposition of the tungsten nucleation layer and before deposition of the tungsten bulk. Treating the deposited tungsten nucleation layer to have a lower resistivity is described, for example, in the following U.S. patents and patent publications: U.S. Patent Nos. 7,772,114 and 8,058,170, and U.S. Patent Publication No. 2010-0267235, which are incorporated herein by reference.

[0103] Furthermore, the methods described herein are not limited to tungsten deposition, but can be implemented to deposit other materials that can be used to deposit a nucleation layer, as described below.

[0104] Body deposition

[0105] As described above, bulk deposition of tungsten can be performed across the entire wafer. In many implementations, bulk deposition of tungsten can be performed by CVD processing, in which a reducing agent and a tungsten-containing precursor are flowed into a deposition chamber to deposit a bulk fill layer in the features. An inert carrier gas can be used to transport one or more of the reaction streams, which may or may not be premixed. Unlike PNL or ALD processing, this operation typically involves continuous flow of reactants until a desired amount has been deposited. In certain implementations, the CVD operation can be performed in multiple stages, where multiple periods of continuous and simultaneous flow of reactants are separated by periods in which the flow of one or more reactants is diverted.

[0106] Many tungsten-containing gases, including (but not limited to) WF6, WCl6, and W(CO)6, can be used as the tungsten-containing precursor. In certain implementations, the tungsten-containing precursor is a halogen-containing compound, such as WF6. In certain implementations, the reducing agent is hydrogen, but other reducing agents can be used, including silane (SiH4), disilane (Si2H6), hydrazine (N2H4), diborane (B2H6), and germane (GeH4). In many implementations, hydrogen is used as the reducing agent in CVD processing. In some other implementations, a tungsten precursor that can decompose to form the bulk tungsten layer can be used. Other types of processing, including ALD processing, can also be used to perform bulk deposition.

[0107] Examples of the temperature can be in the range of 200 °C to 500 °C. According to various implementations, any of the CVD W operations described herein can employ low-temperature CVD W filling (e.g., at about 250 °C to 350 °C, or at about 300 °C).

[0108] Deposition can continue according to various implementations until a certain feature profile is achieved, a certain wafer edge profile is achieved, and / or a certain amount of tungsten is deposited. In some implementations, deposition time and other relevant parameters can be determined by modeling and / or trial and error. In some implementations, the processing chamber can be equipped with various sensors to perform in-situ metrology measurements for endpoint detection of the deposition operation. Examples of in-situ metrology include optical microscopy and X-ray fluorescence (XRF) for determining the thickness of the deposited film.

[0109] It should be understood that the tungsten film described herein can include certain amounts of other compounds, dopants, and / or impurities (such as nitrogen, carbon, oxygen, boron, phosphorus, sulfur, silicon, germanium, etc.), depending on the specific precursors and processes used. The tungsten content in the film can be in the range of 20% to 100% (atomic percentage) tungsten. In many implementations, the film is tungsten-rich, having at least 50% (atomic percentage) tungsten, or even at least about 60%, 75%, 90%, or 99% (atomic percentage) tungsten. In some implementations, the film can be a mixture of metallic or elemental tungsten (W) and other tungsten-containing compounds (such as tungsten carbide (WC), tungsten nitride (WN), etc.).

[0110] CVD and ALD deposition of these materials may involve the use of any suitable precursors. For example, CVD and ALD deposition of tungsten nitride may include the use of halogen-containing and halogen-free tungsten- and nitrogen-containing compounds, as further described below. CVD and ALD deposition of titanium-containing layers may include the use of titanium-containing precursors, examples of which include tetrakis(dimethylamino)titanium (TDMAT) and titanium chloride (TiCl4) and, if appropriate, one or more co-reactants. CVD and ALD deposition of tantalum-containing layers may include the use of precursors such as pentakis(dimethylamino)tantalum (PDMAT) and TaF5 and, if appropriate, one or more co-reactants. CVD and ALD deposition of cobalt-containing layers may include the use of precursors such as tris(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt, bis(cyclopentadienyl)cobalt, and dicopper hexacarbonyl butylacetylene and one or more co-reactants. CVD and ALD deposition of nickel-containing layers may include the use of precursors such as cyclopentadienyl allyl nickel (CpAllylNi) and MeCp2Ni. CVD and ALD deposition of molybdenum may include the use of precursors such as molybdenum hexafluoride (MoF6), molybdenum pentachloride (MoCl5), molybdenum dichloride dioxide (MoO2Cl2), molybdenum oxychloride tetrachloride (MoOCl4), and molybdenum hexacarbonyl (Mo(CO)6). Examples of co-reactants may include N2, NH3, N2H4, N2H6, SiH4, Si3H6, B2H6, H2, and AlCl3.

[0111] Tungsten etching

[0112] Tungsten etching can be performed by exposing tungsten to one or more etchant species that can react with tungsten. Examples of etchant species include halogen species and halogen-containing species. Examples of initial etchant species that can be used to remove tungsten-containing materials include nitrogen trifluoride (NF3), tetrafluoromethane (CF4), tetrafluoroethylene (C2F4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), chlorotrifluoromethane (CF3Cl), sulfur hexafluoride (SF6), and molecular fluorine (F2). In some implementations, these species can be activated and contain radicals and / or ions. For example, the initial etchant species can be passed through a remote plasma generator and / or subjected to in-situ plasma. However, for the implementations described above with respect to Figure 5B 、 Figures 6A - 6B 、 Figure 7A and 7B, tungsten is typically exposed to non-plasma etchant vapors.

[0113] In addition to the examples provided above, any well-known etchant chemicals can also be used to etch tungsten-free films and tungsten-containing films. For example, fluorine-containing compounds (such as NF3) can be used to etch titanium-containing compounds (such as TiN and TiC). In some implementations, chlorine-containing compounds (such as Cl2 and BCl3) can be used to etch, for example, TiAl, TiAlN, nickel-containing compounds, and cobalt-containing compounds.

[0114] According to many implementations, some or all of the etching operations can be performed in the same chamber where other operations (including deposition and / or processing operations) are performed, or in a dedicated etching chamber. In many implementations, etching is performed until certain characteristics of the deposited tungsten are removed, or certain profiles are achieved. For example, etching can be performed until the tungsten nucleation layer at the bevel is removed. In some implementations, the etching endpoint of specific etching process parameters can be determined by modeling and / or trial and error of the specific edge geometry and the profile and amount of the etched deposited tungsten. In some implementations, the processing chamber can be equipped with various sensors to perform in-situ metrology measurements to identify the degree of removal. Examples of in-situ metrology include optical microscopy and XRF for measuring film thickness. In addition, infrared (IR) spectroscopy can be used to detect the amount of tungsten fluoride (WF x ) or other by-products generated during etching. In some implementations, the underlying layer can be used as an etch stop layer. Optical emission spectroscopy (OES) can also be used to monitor etching. According to many implementations, the etching of tungsten may be more or less preferred (or non-preferred) for the underlying layer. For example, the etching may be preferred for W with an underlying layer such as Ti or TiN used as an etch stop layer. In some implementations, the etching can be performed on W and Ti or TiN with an underlying dielectric used as an etch stop layer.

[0115] Inhibition of tungsten nucleation

[0116] As described in U.S. Patent Publication No. 20170365513, inhibition can involve exposure to an activating substance that passivates the surface of the feature. A thermal inhibition treatment is provided. The thermal inhibition treatment generally involves exposing the feature to a nitrogen-containing compound (such as ammonia (NH3) or hydrazine (N2H4)) to non-conformally inhibit the feature near the feature opening. In some embodiments, the thermal inhibition treatment is performed at a temperature in the range of 250°C to 450°C. At these temperatures, exposing the previously formed tungsten nucleation layer to NH3 causes an inhibitory effect. Other potential inhibitory chemicals (such as nitrogen (N2) or hydrogen (H2)) can be used for thermal inhibition at higher temperatures (such as 900°C). However, for many applications, these high temperatures exceed the thermal budget. In addition to ammonia, other hydrogen-containing nitriding agents (such as hydrazine) can also be used at lower temperatures suitable for backend-of-line (BEOL) applications.

[0117] Surface nitridation can passivate it. Subsequent tungsten deposition on the nitrided surface is significantly delayed compared to a conventional bulk tungsten film. In addition to NF3, fluorocarbons (such as CF4 or C2F8) can also be used. However, in some implementations, the inhibitor is fluorine-free to avoid etching during selective inhibition.

[0118] In addition to the tungsten surface, nucleation can be inhibited on the liner / barrier layer surface (such as the TiN and / or WN surface). Any chemical that inhibits these surfaces can be used. Inhibiting chemicals can also be used to adjust the inhibition profile, where different ratios of the active inhibitor substance are used. For example, for the inhibition of the W surface, nitrogen can have a stronger inhibitory effect than hydrogen; the operation of adjusting the ratio of N2 to H2 gas in the forming gas can be used to adjust the profile.

[0119] In some implementations, the substrate can be heated or cooled before inhibition. A predetermined temperature of the substrate can be selected to induce a chemical reaction between the characteristic surface and the inhibitor substance and / or to promote the adsorption of the inhibitor substance, as well as to control the rate of the reaction or adsorption. For example, the temperature can be selected to have a high reaction rate so that more inhibition occurs near the gas source.

[0120] In some embodiments, the inhibition can involve a chemical reaction between a thermal inhibitor substance and the characteristic surface to form a thin layer of WN compound material. In some embodiments, the inhibition can involve a surface effect that passivates the surface without forming a compound material layer, such as adsorption.

[0121] If a tungsten nucleation layer is present, it can be exposed to NH3 or other inhibitory vapors to selectively inhibit the wafer at the wafer edge. In some embodiments, if a bulk tungsten or tungsten-containing layer is present, a reducing agent / tungsten-containing precursor / nitrogen-containing inhibitory chemical can be used to form WN on the bulk layer. These reactants can be introduced sequentially (e.g., B2H6 / WF6 / NH3 pulses) or simultaneously. Any suitable reducing agent (such as diborane or silane) and any suitable tungsten-containing precursor (such as tungsten hexafluoride or tungsten hexacarbonyl) can be used.

[0122] Although the above description focuses on tungsten deposition, aspects of the present disclosure can also be implemented in the case of depositing other materials. For example, edge exclusion control can be performed using other materials, including other tungsten-containing materials (such as tungsten nitride (WN) and tungsten carbide (WC)), titanium-containing materials (such as titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), titanium carbide (TiC), and titanium aluminide (TiAl)), tantalum-containing materials (such as tantalum (Ta), tantalum nitride (TaN)), and nickel-containing materials (such as nickel (Ni) and nickel silicide (NiSi)). For example, a nitrogen-containing gas can be used for the inhibition of cobalt materials.

[0123] Equipment

[0124] The methods presented herein can be implemented in various types of deposition equipment available from various suppliers. Examples of suitable equipment include Novellus Concept-1 ALTUS TM , Concept 2 ALTUS TM , Concept-2 ALTUS-S TM , Concept 3 ALTUS TM deposition systems, and any of ALTUS Max TM or various other commercially available chemical vapor deposition (CVD) tools. Workstations in single-station and multi-station deposition equipment can be used to perform the above methods.

[0125] Figure 14 FIG. shows an apparatus 1460 that can be used in accordance with the various methods described above. The deposition station 1400 has a substrate support 1403 that supports a wafer during deposition. An exclusion ring 1400 and a showerhead 1405 are shown. As described above, process gases can be fed through the showerhead 1405, where the substrate support is equipped with a vacuum and, in some embodiments, with a disposal gas source as shown.

[0126] In various embodiments, gas sensors, pressure sensors, temperature sensors, etc. can be used to provide information about the status of the workstation. Examples of workstation sensors that can be monitored during deposition include mass flow controllers, pressure sensors (e.g., pressure gauges), thermocouples located in the pedestal, and infrared detectors to monitor the presence of one or more gases in the workstation. In certain embodiments, a controller 1474 is used to control the process conditions of the workstation. Details regarding the type of controller are further discussed below with reference to Figure 15 and the discussion regarding this figure applies to both the workstation and chamber controllers. Sensors (e.g., 1476) can be used to provide information to the controller 1474.

[0127] Figure 15 FIG. shows an example of a multi-station apparatus that can be used in conjunction with certain embodiments. The apparatus 1500 includes a processing chamber 1501 that houses a number of workstations. The processing chamber can house at least two workstations, or at least three workstations, or at least four workstations or more. Figure 15Device 1500 is shown having four workstations 1531, 1532, 1533, and 1534. In some embodiments, all workstations in the multi-station device 1500 having a processing chamber 1501 can be exposed to the same pressure environment, which is controlled by the system controller 1574. Sensors (not shown) may also include pressure sensors to provide chamber pressure readings. However, each workstation can have separate temperature conditions or other conditions.

[0128] In a deposition process, typically a wafer to be processed enters workstation 1531 through a load lock. At this station, a tungsten nucleation layer deposition process can be performed. The wafer can then be transferred to workstation 1532 for edge handling as described above. Then CVD depositions can be performed at workstations 1533 and 1534. Alternatively, one station can be reserved for edge etching.

[0129] The system controller 1574 can control the transfer, workstations, and the status of the processing chamber, such as the pressure of the chamber. The system controller 1574 (which can include one or more physical or logical controllers) controls some or all of the operations of the processing chamber 1500. The system controller 1574 can include one or more memory devices and one or more processors. In some implementations, the system controller 1574 is part of a system that can be part of the above example. Such a system can include a semiconductor processing device that includes one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems can be integrated with electronics for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronics can be integrated into the system controller, which can control various components or sub-parts of one or more systems. Depending on the processing parameters and / or the type of system, the system controller can be programmed to control any process disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools, and / or load locks connected or interfaced to a specific system.

[0130] Broadly speaking, a system controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and so on. The integrated circuits can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions transmitted to the controller in various individually set forms (or program files), and the settings define the operating parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer for performing one or more process steps during the preparation or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0131] In some implementations, the system controller can be part of or coupled to a computer, which is integrated with, coupled to, or in other words connected to the system through a network or a combination thereof. For example, the controller can be in the "cloud" or be all or part of a wafer fab host system, thereby allowing remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, to change the parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system through a network, which can include a local network or the Internet. The remote computer can include a user interface that allows the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some embodiments, the system controller receives instructions in the form of data that specify the parameters for each process step to be performed during one or more operations. It should be understood that the parameters can be for the type of process to be performed as well as the type of tool that the controller is configured to connect to or control. Thus, as described above, the system controller can be distributed, for example, by including one or more discrete controllers that are connected together through a network and work towards a common goal (e.g., the processes and controls described herein). An example of a distributed controller for these purposes can be one or more integrated circuits on a chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which combine to control the processes on the chamber.

[0132] Exemplary systems can include, but are not limited to: a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, an orbital chamber or module, and any other semiconductor processing system that can be associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0133] As described above, depending on one or more process steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, a cluster tool, other tool interfaces, adjacent tools, adjoining tools, tools located throughout the factory, a host, another controller, or a tool used in a material handling that transports a container of wafers between tool locations and / or load ports in a semiconductor manufacturing facility.

[0134] Patterning method / device

[0135] The devices / methods described above can be used in combination with a lithographic patterning tool or process, for example, for fabricating or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, such tools / processes will be used or operated together in a common manufacturing facility. Lithographic patterning of a film generally includes some or all of the following steps, each step enabling multiple viable tools: (1) coating a photoresist on a workpiece (i.e., a substrate) using a spin coater or spray tool; (2) curing the photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible light or UV or x-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thus pattern it using a tool such as a wet bench; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma-assisted etch tool; and (6) removing the resist using a tool such as a radio frequency or microwave plasma resist stripper.

Claims

1. An apparatus for semiconductor processing, comprising: An exclusion ring assembly configured for processing a semiconductor wafer of a nominal diameter D, the exclusion ring assembly comprising: An upper annular ring having an outer diameter and an inner diameter less than D, and A lower annular ring having an outer diameter and an inner diameter less than D, Wherein: The upper annular ring is disposed above the lower annular ring to define an annular gas flow channel between the upper annular ring and the lower annular ring, A pedestal having an upper surface configured to support the semiconductor wafer, and The pedestal is configured to apply a vacuum to the annular gas flow channel, and A showerhead disposed above the pedestal and configured to cause a process gas to flow over the semiconductor wafer supported by the pedestal; And A gas source fluidly connected to the showerhead and configured to direct the process gas to the showerhead; wherein: The annular gas flow channel has an inlet that is at an acute angle relative to the central axis of the upper annular ring when looking from the upper annular ring towards the lower annular ring, and The annular gas flow channel and the pedestal are configured such that when the process gas flows over the semiconductor wafer, the vacuum applied to the annular gas flow channel causes the process gas to flow through the inlet and into the annular gas flow channel.

2. The apparatus according to claim 1, wherein the annular gas flow channel has an inner diameter and an outer diameter, and a width defined by a gap between the upper annular ring and the lower annular ring, and wherein the width at the inner diameter of the annular gas flow channel is less than the width at the outer diameter of the annular gas flow channel.

3. The apparatus according to claim 1, wherein the gap between the upper annular ring and the lower annular ring at the inner diameter of the lower annular ring is less than the gap between the upper annular ring and the lower annular ring at the outer diameter of the lower annular ring.

4. The apparatus according to claim 1, wherein the gap between the upper annular ring and the lower annular ring at the inner diameter of the lower annular ring is not greater than 0.1 inches.

5. The apparatus according to claim 1, wherein the inner diameter of the upper annular ring is less than the inner diameter of the lower annular ring.

6. The apparatus according to claim 1, wherein the upper annular ring comprises an upper surface that is substantially parallel to a reference plane perpendicular to the central axis of the upper annular ring.

7. The apparatus according to claim 6, wherein the upper annular ring further comprises an inner edge and an inclined surface extending from the inner edge to the upper surface.

8. The apparatus according to claim 7, wherein the lower annular ring comprises an upper surface that is substantially parallel to a reference plane perpendicular to the central axis of the lower annular ring.

9. The apparatus according to claim 8, wherein the lower annular ring further comprises an inner edge and an inclined surface extending from the inner edge to the upper surface.

10. The apparatus according to claim 9, wherein the inclination of the inclined surface of the upper annular ring is greater than the inclination of the inclined surface of the lower annular ring.

11. The apparatus according to claim 1, further comprising a susceptor configured to support the semiconductor wafer, the susceptor including a gas injector configured to inject gas at an edge region of the semiconductor wafer.

12. The apparatus according to claim 1, further comprising a susceptor that supports the exclusion ring assembly, the susceptor including an upper surface and a recess in the upper surface that defines a gas passage.

13. The apparatus according to claim 12, wherein the recess is spaced from the center of the susceptor by a distance Y, the distance Y being greater than the inner radius of the lower annular ring.

14. A deposition chamber comprising: a susceptor including an upper surface and an annular recess in the upper surface, the annular recess being configured to be in fluid connection with a backside gas source; an exclusion ring assembly mounted on the susceptor, the exclusion ring assembly including an upper annular ring having an inner diameter and an outer diameter and a lower annular ring having an inner diameter and an outer diameter, wherein the upper annular ring is disposed above the lower annular ring to define a lower annular gas flow channel between the upper annular ring and the lower annular ring, wherein the lower annular gas flow channel has an inlet that is at an acute angle with respect to the central axis of the upper annular ring when looking from the upper annular ring towards the lower annular ring; and a showerhead disposed above the susceptor and the exclusion ring assembly to define an upper annular gas flow channel between the showerhead and the upper annular ring; wherein: the susceptor is configured to apply a vacuum to the lower annular gas flow channel, and the showerhead is configured to direct a process gas flow over a semiconductor wafer supported by the susceptor; and a gas source in fluid connection with the showerhead and configured to direct the process gas to the showerhead; wherein: the lower annular gas flow channel and the susceptor are configured such that when the process gas flows over the semiconductor wafer, the vacuum applied to the lower annular gas flow channel causes the process gas to flow through the inlet and into the lower annular gas flow channel.

15. A method for semiconductor processing, the method comprising: providing a circular wafer on the susceptor in the deposition chamber according to claim 14, the circular wafer having a nominal diameter D, where D is greater than the inner diameters of the upper annular ring and the lower annular ring, and wherein the exclusion ring assembly is disposed above an outer edge of the circular wafer; providing a radial flow of a process gas above the circular wafer through the showerhead; and providing a backside gas to an outer edge of the circular wafer through the annular recess in the susceptor.

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