Method for manufacturing semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device that is suitable for achieving low wiring resistance between multilayered semiconductor elements that are bonded via an adhesive layer. The method of the present invention is as follows. First, a chip stack (W) is prepared that includes a chip (10) having a circuit forming surface (10a), a chip (20) having a main surface (20a) and a back surface (20b), and an adhesive layer (30) containing a SiOC-based polymer. Next, in the chip stack (W), an etching process is performed from the chip (20) side through a mask pattern that masks a portion of the main surface (20a) side of the chip (20) to form a hole (H) that penetrates the chip (20) and the adhesive layer (30) to reach the wiring pattern (12b) in the chip (10). Next, an insulating film (41) is formed on the inner surface of the hole (H). Next, the insulating film (41) on the bottom surface of the hole (H) is removed. Next, the chip stack (W) is subjected to a cleaning process (oxygen plasma treatment and / or Ar sputtering treatment). Next, a conductive portion is formed in the hole (H).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device having a stacked structure including a plurality of semiconductor elements. This application claims priority to Japanese Patent Application No. 2018-101929 filed in Japan on May 28, 2018, the contents of which are incorporated herein by reference. Background Art

[0002] In recent years, with the main purpose of further increasing the density of semiconductor devices, technology development has been carried out for manufacturing semiconductor devices having a three-dimensional structure in which multiple semiconductor chips or semiconductor elements are integrated in the thickness direction. As one of such technologies, the so-called WOW (Wafer on Wafer) process is known. In the WOW process, a given number of semiconductor wafers made of multiple semiconductor elements are stacked in sequence to form a structure in which the semiconductor elements are arranged in multiple stages in the thickness direction. The wafer stack is singulated into semiconductor devices through a cutting process. Technologies related to such WOW processes are described in, for example, the following patent documents 1 and 2.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-4835

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2016-178162 Summary of the invention

[0007] Problems to be solved by the invention

[0008] In the WOW process, a through hole that penetrates the wafer, i.e., a through electrode, is formed to electrically connect semiconductor elements formed on different wafers in a wafer stack. The through electrode is formed, for example, by the following steps: a step of forming a hole in the wafer that penetrates the wafer in its thickness direction by reactive ion etching, and a step of filling the hole with a conductive material.

[0009] On the other hand, it is considered to use an adhesive in the bonding of the wafers to be multilayered. Furthermore, in order to form a through electrode that is conductive to the semiconductor element of the lower wafer on the upper wafer stacked on the wafer via the adhesive layer, it is necessary to form a hole by reactive ion etching in the hole forming process in a manner that penetrates the upper wafer and the adhesive layer connected directly below it. Such a hole is filled with a conductive material.

[0010] However, if the adhesive layer is subjected to reactive ion etching, etching residues are likely to be generated in the formed holes. When an adhesive is used in wafer bonding, in the conventional WOW process, the etching residues may sometimes cause the wiring resistance between semiconductor elements that should be electrically connected by through electrodes to increase.

[0011] The present invention has been conceived under the circumstances described above, and an object of the present invention is to provide a method for achieving low wiring resistance between multilayered semiconductor elements, which is suitable for a method of manufacturing a semiconductor device in which semiconductor elements are multilayered by stacking semiconductor wafers with an adhesive layer interposed therebetween.

[0012] Solutions to the problem

[0013] The method for manufacturing a semiconductor device provided by the present invention is a method for multi-layering a semiconductor element by stacking semiconductor wafers with an adhesive layer interposed therebetween, and the method includes at least the following first to sixth steps.

[0014] In the first step, a wafer stack is prepared. The wafer stack has a stacked structure, which includes: a first wafer having a circuit forming surface including a wiring pattern and a back surface opposite to the circuit forming surface, a second wafer having a main surface and a back surface opposite to the main surface, and an adhesive layer containing a SiOC-based polymer and sandwiched between the circuit forming surface of the first wafer and the back surface of the second wafer. SiOC-based polymers refer to polymers containing at least silicon, oxygen, and carbon in constituent elements, and include SiOCH-based polymers that also contain hydrogen. The carbon ratio in the SiOC-based polymer is, for example, 20 to 70% by mass, the hydrogen ratio is, for example, 2 to 20% by mass, the oxygen ratio is, for example, 10 to 40% by mass, and the silicon ratio is, for example, 3 to 40% by mass. The circuit forming surface refers to the surface on the side of the wafer where a semiconductor element is made and a so-called rewiring layer is formed on the element. The main surface refers to the surface on the side of the wafer where a semiconductor element is made.

[0015] In the second step, in the wafer stack, an etching process is performed from the second wafer side through a mask pattern that masks a portion of the main surface side of the second wafer, so as to form a hole that penetrates the second wafer and the adhesive layer and reaches the wiring pattern in the first wafer. In the etching process, reactive ion etching is preferably performed. In addition, the portion of the wiring pattern facing the hole becomes the bottom surface of the hole.

[0016] In the third step, an insulating film is formed on the inner surface including the wall surface and the bottom surface of the hole. In the fourth step, the portion of the insulating film on the wiring pattern in the hole (ie, the portion of the insulating film located on the bottom surface of the hole) is etched and removed.

[0017] In the fifth step, the wafer stack having the holes formed therein is subjected to a cleaning process. The cleaning process includes an oxygen plasma cleaning process and / or an argon sputtering cleaning process.

[0018] In the sixth step, a conductive portion is formed by filling the hole after the cleaning step with a conductive material. The formed conductive portion is structurally and electrically connected to the wiring pattern of the circuit forming surface of the first wafer. The conductive portion becomes a through electrode for electrically connecting the semiconductor element from the first wafer and the semiconductor element from the second wafer in the manufactured semiconductor device. It is preferred that a barrier layer is formed on the hole wall surface before the sixth step. In addition, the conductive material filling method in the sixth step is preferably an electroplating method.

[0019] In the manufacturing method of the semiconductor device of the present invention, as described above, the conductive portion of the through electrode for electrically connecting the semiconductor elements is structurally connected and electrically connected to the wiring pattern of the circuit forming surface of the first chip. Such a bump-free structure is suitable in that a short conductive path is realized between multilayered semiconductor elements. In the conventional WOW process, a bump electrode electrically connected to the through electrode of the through chip is formed on the surface of the chip, and sometimes the electrical connection between semiconductor elements in different chips is realized through the bump electrode. In contrast, in the manufacturing method of the semiconductor device of the present invention, the conductive portion of the through electrode is directly connected to the wiring pattern in the first chip, and a bump-free structure is formed in the electrical connection between semiconductor elements located in different chips. Such a bump-free structure is suitable in that a short conductive path is realized between multilayered semiconductor elements as described above. There is a tendency that the shorter the conductive path between multilayered semiconductor elements, the smaller the resistance of the conductive path or wiring between the elements.

[0020] In addition, the manufacturing method of the semiconductor device of the present invention is a method of multi-layering semiconductor elements by stacking semiconductor wafers through an adhesive layer, as described above, and the adhesive layer bonding the wafers contains a SiOC-based polymer. At the same time, in the present method, a cleaning treatment including an oxygen plasma cleaning treatment and / or an argon sputtering cleaning treatment is performed on the wafer stack formed with holes penetrating the wafer and the adhesive layer in the fifth step. The present invention has obtained the following insight: These structures are suitable in terms of forming a low contact resistance between the conductive portion or through-electrode formed in the hole and the wiring pattern on the circuit forming surface of the first wafer. For example, as shown in the embodiments and comparative examples described later. There is a tendency that the smaller the contact resistance between the conductive portion or through-electrode in the hole and the wiring pattern on the circuit forming surface of the first wafer, the smaller the resistance of the conductive path as a whole or the wiring as a whole between the semiconductor elements electrically connected by the through-electrode in the manufactured semiconductor device.

[0021] As described above, the method for manufacturing a semiconductor device is suitable for achieving low wiring resistance between multilayered semiconductor elements bonded via an adhesive layer. Such a method for manufacturing a semiconductor device is suitable in that it suppresses high-speed signal transmission with low power consumption in the manufactured semiconductor device, and is also suitable in that it suppresses attenuation of high-frequency signals.

[0022] When an oxygen plasma cleaning treatment is performed in the fifth step of the method for manufacturing a semiconductor device, the treatment time is preferably 5 to 120 seconds, more preferably 10 to 60 seconds, and more preferably 15 to 40 seconds. When an argon sputtering cleaning treatment is performed, the treatment time is preferably 0.5 to 5 minutes, and more preferably 2 to 4 minutes. In addition, the cleaning treatment of the fifth step preferably includes an oxygen plasma cleaning treatment and an argon sputtering cleaning treatment thereafter. In this case, the cleaning treatment preferably includes a sulfuric acid cleaning treatment between these treatments. These configurations are preferred in that low contact resistance is achieved between the conductive portion or through-electrode formed in the hole and the wiring pattern on the circuit forming surface of the first chip.

[0023] The adhesive layer preferably comprises a siloxane-based organic-inorganic hybrid adhesive, and more preferably a cured product of an adhesive composition comprising a polyorganosilsesquioxane containing a polymerizable functional group (a polyorganosilsesquioxane containing a polymerizable group). A siloxane-based organic-inorganic hybrid adhesive refers to an adhesive polymer material comprising a structural unit having a siloxane bond and an organic group bonded to the silicon forming the siloxane bond. Such an adhesive layer is suitable for achieving a reduction in the curing temperature for forming the adhesive layer and suppressing damage to components in a wafer as an adherend while achieving high heat resistance.

[0024] The thickness of the adhesive layer is preferably 5 μm or less. Such a structure is suitable for shortening the conductive portion or through-electrode formed by the present method, and therefore is suitable for reducing the resistance of the entire conductive path or wiring between semiconductor elements electrically connected through the through-electrode. In addition, the adhesive layer containing the siloxane organic-inorganic hybrid adhesive is also suitable for exerting sufficient chip bonding strength when it is thin to this extent.

[0025] The thickness of the second wafer is preferably 20 μm or less, more preferably 15 μm or less. Such a structure is suitable for shortening the conductive portion or through-electrode formed by this method, and therefore suitable for reducing the resistance of the entire conductive path or wiring between semiconductor elements electrically connected by the through-electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Part of the steps in a method for manufacturing a semiconductor device according to one embodiment of the present invention is shown.

[0027] Figure 2 Part of the steps in a method for manufacturing a semiconductor device according to one embodiment of the present invention is shown.

[0028] Figure 3 Part of the steps in a method for manufacturing a semiconductor device according to one embodiment of the present invention is shown.

[0029] Figure 4 It is a graph showing the chain resistance measurement results of Example 1 and Comparative Example 1.

[0030] Figure 5 It is a graph showing the chain resistance measurement results of Example 2 and Comparative Example 1.

[0031] Figure 6 It is a graph showing the chain resistance measurement results of Examples 1 and 3 and Comparative Example 1.

[0032] Figure 7 It is a graph showing the chain resistance measurement results of Examples 3 and 4 and Comparative Example 1.

[0033] Explanation of symbols

[0034] W Wafer stack

[0035] 10, 20 chips

[0036] 10a Circuit formation surface

[0037] 10b Back

[0038] 12 Rewiring Layer

[0039] 12a Insulation

[0040] 12b Wiring Pattern

[0041] 20a Main surface

[0042] 20b Back

[0043] 21 Insulation film

[0044] 30 Adhesive layer

[0045] H hole

[0046] 50 Conductive materials

[0047] 51 Conductive part DETAILED DESCRIPTION

[0048] Figure 1 to Figure 3 A method for manufacturing a semiconductor device according to one embodiment of the present invention is provided. The method is a method for manufacturing a semiconductor device having a three-dimensional structure in which semiconductor elements are integrated in the thickness direction thereof. Figure 1 to Figure 3 The manufacturing process is shown using a partial cross-section view.

[0049] In the method for manufacturing a semiconductor device, first, a Figure 1 (a) Wafer stack W (preparation step) The wafer stack W has a stacked structure including a wafer 10, a wafer 20, and an adhesive layer 30 therebetween.

[0050] The wafer 10 is a wafer after a transistor forming process and a rewiring layer forming process, and has a main body 11 and a rewiring layer 12, and has a circuit forming surface 10a on the rewiring layer 12 side and a back surface 10b opposite to the circuit forming surface 10a. A plurality of semiconductor elements (not shown) are made on one side of the main body 11 of the wafer 10, and a rewiring layer 12 is formed on the elements. The rewiring layer 12 has an insulating portion 12a and a wiring pattern 12b. The circuit forming surface 10a is a surface on one side of the wafer 10 where such a rewiring layer 12 is formed. The wiring pattern 12b of the rewiring layer 12 has a portion facing the outside of the rewiring layer 12 on the circuit forming surface 10a. That is, the circuit forming surface 10a includes an exposed area of ​​the wiring pattern 12b. The thickness of such a wafer 10 is, for example, 300 to 800 μm. The wafer 10 can be thinned by grinding from the back surface 10b side later.

[0051] The wafer 20 is a wafer after a transistor forming process, and has a main surface 20a and a back surface 20b opposite to the main surface 20a. The main surface 20a of the wafer 20 is a surface on one side of the wafer 20 on which a plurality of semiconductor elements (not shown) are mounted. The thickness of the wafer 20 is 30 μm or less in the present embodiment, preferably 20 μm or less, and more preferably 15 μm or less.

[0052] Examples of semiconductor materials used to form the main bodies of the wafers 10 and 20 include silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP).

[0053] The adhesive layer 30 contains a SiOC polymer and is sandwiched between the circuit forming surface 10a of the wafer 10 and the back surface 20b of the wafer 20. The SiOC polymer refers to a polymer containing at least silicon, oxygen, and carbon as constituent elements, and also includes a SiOCH polymer further containing hydrogen. The carbon ratio in the SiOC polymer is, for example, 20 to 70% by mass, the hydrogen ratio is, for example, 2 to 20% by mass, the oxygen ratio is, for example, 10 to 40% by mass, and the silicon ratio is, for example, 3 to 40% by mass.

[0054] The adhesive layer 30 preferably contains a siloxane-based organic-inorganic hybrid adhesive, and more preferably a cured product of an adhesive composition containing a polymerizable group-containing silsesquioxane. A siloxane-based organic-inorganic hybrid adhesive is an adhesive polymer material containing a structural unit having a siloxane bond and an organic group bonded to the silicon forming the siloxane bond.

[0055] Figure 1 The chip stack W shown in (a) can be manufactured through, for example, the following process. First, the circuit forming surface 10a side of the above-mentioned chip 10 after the transistor forming process and the rewiring layer forming process is bonded to the chip (additional chip) that becomes the above-mentioned chip 20 through the adhesive layer 30. Next, a grinding device is used to grind the side of the additional chip opposite to the bonding surface of the chip 10 to thin the additional chip to a given thickness. Next, a semiconductor element is formed on the exposed surface (the side opposite to the bonding surface of the chip 10) of the thinned additional chip through a transistor forming process, etc. For example, the above-mentioned chip stack W having a stacked structure including chips 10, 20 and an adhesive layer 30 bonded to them can be manufactured as described above.

[0056] The composition for forming the above-mentioned adhesive layer 30 contains a SiOC-type material that becomes the above-mentioned SiOC-type polymer as a curable resin. Such a composition is preferred in terms of achieving high heat resistance of the adhesive layer 30. The SiOC-type material is preferably a siloxane-type organic-inorganic hybrid adhesive. As the main agent of the siloxane-type organic-inorganic hybrid adhesive, for example: polyorganosilsesquioxane containing a polymerizable group and benzocyclobutene (BCB) resin can be cited. The polymerizable functional group possessed by the polyorganosilsesquioxane containing a polymerizable group is preferably an epoxy group or a (meth)acryloyloxy group. As a BCB resin, for example: 1,3-divinyl-1,1,3,3-tetramethyldisiloxane-benzocyclobutene can be cited. As a commercially available product of the BCB resin, "CYCLOTEN" manufactured by Dow Chemical can be used.

[0057] In the present embodiment, when the adhesive layer 30 forming composition contains polymerizable group-containing polyorganosilsesquioxane, the content ratio of the polymerizable group-containing polyorganosilsesquioxane in the composition is, for example, 70 mass % or more, preferably 80 to 99.8 mass %, and more preferably 90 to 99.5 mass %.

[0058] In the present embodiment, when the adhesive layer 30-forming composition contains a polymerizable group-containing polyorganosilsesquioxane, the polymerizable group-containing polyorganosilsesquioxane includes a first structural unit [RSiO] containing at least a structural unit represented by the following formula (1): 3 / 2], and a second structural unit [RSiO 2 / 2 (OR')] (R and R' in the second structural unit may be the same or different) as a siloxane structural unit. These structural units belong to the so-called T unit in the siloxane structural unit. In this embodiment, the structural unit [RSiO 3 / 2 ] as T3 body, the structural unit [RSiO 2 / 2 (OR')] as the T2 body. In the T3 body, its silicon atom is bonded to three oxygen atoms each of which is also bonded to a silicon atom in another siloxane structural unit. In the T2 body, its silicon atom is bonded to two oxygen atoms each of which is also bonded to a silicon atom in another siloxane structural unit, and is bonded to the oxygen of an alkoxy group. Such T3 bodies and T2 bodies are both T units as siloxane structural units as described above, and are partial structures of polyorganosilsesquioxanes containing polymerizable groups that can be formed by hydrolysis of a silane compound having three hydrolyzable functional groups and a subsequent condensation reaction.

[0059] [Chemical formula 1]

[0060] [R 1 SiO 3 / 2 ] (1)

[0061] [R 1 SiO 2 / 2 (OR 2 )] (2)

[0062] R in formula (1) 1 And R in formula (2) 1 and R in formula (2) represent groups containing epoxy groups or (meth)acryloyloxy groups. 2 It represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms.

[0063] As each R in formula (1) and formula (2) 1 In the case of a group containing an epoxy group, the R 1 , for example, groups represented by the following formulae (3) to (6) are mentioned. 3 , R 4 , R 5 , R 6 Each of R and R represents a linear or branched alkylene group having 1 to 10 carbon atoms. Examples of such alkylene groups include methylene, methylmethylene, dimethylmethylene, ethylene, propylene, trimethylene, tetramethylene, pentamethylene, hexamethylene, and decamethylene. From the viewpoint of achieving high heat resistance in the formed adhesive layer 30 and suppressing shrinkage during curing, R in formula (1) 1 and R as the epoxy-containing group in formula (2)1 Preferably, they are the epoxy-containing group represented by formula (3) or the epoxy-containing group represented by formula (4), and more preferably, R 3 It is 2-(3,4-epoxycyclohexyl)ethyl which is ethylene.

[0064] [Chemical formula 2]

[0065]

[0066] In the above formula (2), R 2 As mentioned above, represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms. Therefore, OR in formula (2) 2 represents a hydroxyl group or an alkoxy group having 1 to 4 carbon atoms. Examples of the alkoxy group having 1 to 4 carbon atoms include a methoxy group, an ethoxy group, a propoxy group, an isopropoxy group, a butoxy group, and an isobutoxy group.

[0067] The polymerizable group-containing polyorganosilsesquioxane contained in the composition for forming the adhesive layer 30 may contain one or more structural units represented by the above formula (1). The polymerizable group-containing polyorganosilsesquioxane may contain one or more structural units represented by the above formula (2).

[0068] The polymerizable group-containing polyorganosilsesquioxane contained in the adhesive layer 30-forming composition may contain, as the T3 form, a structural unit represented by the following formula (7) in addition to the structural unit represented by the formula (1). 7 represents a hydrogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkenyl group, a substituted or unsubstituted cycloalkyl group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted aralkyl group. 7 It is preferably a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkenyl group, or a substituted or unsubstituted aryl group, and more preferably a phenyl group.

[0069] [Chemical formula 3]

[0070] [R 7 SiO 3 / 2 ] (7)

[0071] As R 7 Examples of the alkyl group include methyl, ethyl, propyl, n-butyl, isopropyl, isobutyl, sec-butyl, tert-butyl, and isopentyl. 7 Examples of the alkenyl group include vinyl, allyl, and isopropenyl. 7 The cycloalkyl group mentioned above includes, for example, cyclobutyl, cyclopentyl, and cyclohexyl. 7The aryl group mentioned above includes, for example, phenyl, tolyl, and naphthyl. 7 Examples of the aralkyl group include benzyl and phenethyl.

[0072] As R 7 Examples of the substituents of the alkyl, alkenyl, cycloalkyl, aryl and aralkyl groups include ether groups, ester groups, carbonyl groups, siloxane groups, halogen atoms such as fluorine atoms, acryloyl groups, methacryloyl groups, mercapto groups, amino groups and hydroxyl groups.

[0073] The polymerizable group-containing polyorganosilsesquioxane contained in the adhesive layer 30-forming composition may contain, as the T2 form, a structural unit represented by the following formula (8) in addition to the structural unit represented by the formula (2). 7 represents a hydrogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkenyl group, a substituted or unsubstituted cycloalkyl group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted aralkyl group, and specifically, is the same as R in the above formula (7): 7 Similarly, R in formula (8) 2 represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms, and is specifically the same as R in the above formula (2) 2 same.

[0074] [Chemical formula 4]

[0075] [R 7 SiO 2 / 2 (OR 2 )] (8)

[0076] The polymerizable group-containing polyorganosilsesquioxane may contain, in its siloxane structural unit, a structural unit selected from the group consisting of [RSiO 1 / 2 ], as a structural unit of the so-called D unit [R2SiO 2 / 2 ], and as a structural unit of the so-called Q unit [SiO 4 / 2 ] at least one of ].

[0077] The polymerizable group-containing polyorganosilsesquioxane may have any of a cage type, an incomplete cage type, a ladder type, and a random type silsesquioxane structure, or may have a structure in which two or more of these silsesquioxane structures are combined.

[0078] In the all-siloxane structural unit of the polyorganosilsesquioxane containing a polymerizable group in the composition for forming the adhesive layer 30, the value of the molar ratio of the T3 form to the T2 form (i.e., T3 form / T2 form) is, for example, 5 to 500, and the lower limit is preferably 10. The upper limit is preferably 100, and more preferably 50. By adjusting the value of [T3 form / T2 form] to such a range, the compatibility with the components other than the polyorganosilsesquioxane containing a polymerizable group contained in the composition for forming the adhesive layer 30 is improved, and the handling property is improved. The value of [T3 form / T2 form] of the polyorganosilsesquioxane containing a polymerizable group is 5 to 500, which means that the amount of the T2 form is relatively small compared to the T3 form, and the hydrolysis / condensation reaction of silanol is further advanced.

[0079] The value of the above molar ratio (T3 form / T2 form) in the polymerizable group-containing polyorganosilsesquioxane can be obtained, for example, by 29 It can be obtained by Si-NMR spectrum measurement. 29 In the Si-NMR spectrum, the silicon atoms in the first structural unit (T3 form) and the silicon atoms in the second structural unit (T2 form) show different chemical shift peaks or signals. The molar ratio can be obtained from the area ratio of these peaks. 29 Si-NMR spectrum can be measured, for example, using the following apparatus and conditions.

[0080] Measuring device: Trade name "JNM-ECA500NMR" (manufactured by JEOL Ltd.)

[0081] Solvent: deuterated chloroform

[0082] Cumulative times: 1800 times

[0083] Measurement temperature: 25℃

[0084] The number average molecular weight (Mn) of the polymerizable group-containing polyorganosilsesquioxane contained in the composition for forming the adhesive layer 30 is preferably 1000 to 50000, more preferably 1500 to 10000, further preferably 2000 to 8000, and particularly preferably 2000 to 7000. By setting the number average molecular weight to 1000 or more, the insulation, heat resistance, crack resistance, and adhesion of the formed cured product are improved. On the other hand, by setting the number average molecular weight to 50000 or less, the compatibility with other components in the same composition is improved, and the insulation, heat resistance, and crack resistance of the cured product are improved.

[0085] The molecular weight dispersion (Mw / Mn) of the polymerizable group-containing polyorganosilsesquioxane contained in the composition for forming the adhesive layer 30 is preferably 1.0 to 4.0, more preferably 1.1 to 3.0, and further preferably 1.2 to 2.7. By setting the molecular weight dispersion to 4.0 or less, the heat resistance, crack resistance, and adhesion of the formed cured product are further improved. On the other hand, by setting the molecular weight dispersion to 1.0 or more, the same composition is easily liquid, and there is a tendency for its handling properties to be improved.

[0086] The number average molecular weight (Mn) and weight average molecular weight (Mw) of the polymerizable group-containing polyorganosilsesquioxane are values ​​measured by gel permeation chromatography (GPC) and calculated by polystyrene conversion. The number average molecular weight (Mn) and weight average molecular weight (Mw) of the polymerizable group-containing polyorganosilsesquioxane can be measured, for example, using an HPLC apparatus (trade name "LC-20AD", manufactured by Shimadzu Corporation) under the following conditions.

[0087] Chromatographic columns: Two Shodex KF-801 (upstream side, manufactured by Showa Denko K.K.), Shodex KF-802 (manufactured by Showa Denko K.K.), and Shodex KF-803 (downstream side, manufactured by Showa Denko K.K.) were connected in series.

[0088] Measuring temperature: 40℃

[0089] Eluent: Tetrahydrofuran (THF)

[0090] Sample concentration: 0.1-0.2 mass%

[0091] Flow rate: 1mL / min

[0092] Standard sample: polystyrene

[0093] Detector: UV-VIS detector (trade name "SPD-20A", manufactured by Shimadzu Corporation)

[0094] The above-mentioned polyorganosilsesquioxane containing polymerizable groups can be produced by hydrolysis of a silane compound having three hydrolyzable functional groups and a condensation reaction after the hydrolysis. The raw materials used for its production contain at least a compound represented by the following formula (9) and, if necessary, a compound represented by the following formula (10). The compound represented by formula (9) is used to form the structural unit represented by the above formula (1) and the structural unit represented by the above formula (2). The compound represented by formula (10) is used to form the structural unit represented by the above formula (7) and the structural unit represented by the above formula (8).

[0095] [Chemical formula 5]

[0096] R1 SiX 1 3 (9)

[0097] R 7 SiX 2 3 (10)

[0098] R in formula (9) 1 represents a group containing a polymerizable group, specifically R in the above formula (1) (2) 1 Similarly, X in formula (9) 1 represents an alkoxy group or a halogen atom. Examples of the alkoxy group include alkoxy groups having 1 to 4 carbon atoms, such as methoxy, ethoxy, propoxy, isopropoxy, butoxy, and isobutoxy. 1 The halogen atom may include, for example, a fluorine atom, a chlorine atom, a bromine atom, and an iodine atom. 1 Preferably, it is an alkoxy group, more preferably a methoxy group or an ethoxy group. 1 It can be the same or different.

[0099] R in formula (10) 7 represents a substituted or unsubstituted aryl group, a substituted or unsubstituted aralkyl group, a substituted or unsubstituted cycloalkyl group, a substituted or unsubstituted alkyl group, or a substituted or unsubstituted alkenyl group, and specifically, R in the above formula (7) (8) 7 Similarly, X in formula (10) 2 represents an alkoxy group or a halogen atom, and specifically is the same as X in the above formula (9): 1 same.

[0100] The raw material for producing the above-mentioned polymerizable group-containing polyorganosilsesquioxane may further contain other hydrolyzable silane compounds. Examples of such compounds include hydrolyzable trifunctional silane compounds other than the two compounds represented by the above-mentioned formulas (9) and (10), hydrolyzable monofunctional silane compounds capable of forming M units, hydrolyzable bifunctional silane compounds capable of forming D units, and hydrolyzable tetrafunctional silane compounds capable of forming Q units.

[0101] The amount and composition of the hydrolyzable silane compound as the raw material can be appropriately adjusted according to the structure of the polymerizable group-containing polyorganosilsesquioxane as the target product. For example, the amount of the compound represented by the above formula (9) is, for example, 55 to 100 mol%, preferably 65 to 100 mol%, relative to the total amount of the hydrolyzable silane compound used. The amount of the compound represented by the above formula (10) is, for example, 0 to 70 mol%, relative to the total amount of the hydrolyzable silane compound used. The total amount of the compound represented by the formula (9) and the compound represented by the formula (10) is, for example, 60 to 100 mol%, preferably 70 to 100 mol%, and more preferably 80 to 100 mol%, relative to the total amount of the hydrolyzable silane compound used.

[0102] When two or more hydrolyzable silane compounds are used in the production of the polymerizable group-containing polyorganosilsesquioxane, the hydrolysis and condensation reactions of the respective hydrolyzable silane compounds may be performed simultaneously or sequentially.

[0103] The above-mentioned hydrolysis and condensation reaction is preferably carried out in the presence of one or more solvents. Preferred solvents include, for example, diethyl ether, dimethoxyethane, tetrahydrofuran, dimethoxyethane, The amount of the solvent used can be appropriately adjusted, for example, within a range of 2000 parts by mass or less per 100 parts by mass of the hydrolyzable silane compound depending on the reaction time and the like.

[0104] The above-mentioned hydrolysis and condensation reactions are preferably carried out in the presence of one or more catalysts and water. The catalyst may be an acid catalyst or a base catalyst. The amount of the catalyst is appropriately adjusted within the range of, for example, 0.002 to 0.2 moles per 1 mole of the hydrolyzable silane compound. The amount of water is appropriately adjusted within the range of, for example, 0.5 to 20 moles per 1 mole of the hydrolyzable silane compound.

[0105] The hydrolysis and condensation reaction of the hydrolyzable silane compound can be carried out in one stage or in two or more stages. In the case of manufacturing a polyorganosilsesquioxane containing a polymerizable group having a molar ratio value (T3 body / T2 body) of 5 or more, for example, the reaction temperature of the hydrolysis and condensation reaction in the first stage is, for example, 40 to 100°C, preferably 45 to 80°C. The reaction time of the hydrolysis and condensation reaction in the first stage is, for example, 0.1 to 10 hours, preferably 1.5 to 8 hours. The reaction temperature of the hydrolysis and condensation reaction in the second stage is preferably 5 to 200°C, more preferably 30 to 100°C. By controlling the reaction temperature to the above range, there is a tendency to more efficiently control the molar ratio value (T3 body / T2 body) and the number average molecular weight to the desired range. In addition, the reaction time of the hydrolysis and condensation reaction in the second stage is not particularly limited, and is preferably 0.5 to 1000 hours, more preferably 1 to 500 hours. The hydrolysis and condensation reactions may be carried out under normal pressure, increased pressure, or reduced pressure. The hydrolysis and condensation reactions are preferably carried out in an atmosphere of an inert gas such as nitrogen or argon.

[0106] The above-mentioned polyorganosilsesquioxane containing a polymerizable group can be obtained by the hydrolysis and condensation reaction of the hydrolyzable silane compound. After the reaction is completed, the catalyst for suppressing the ring opening of the polymerizable group is preferably neutralized. The polyorganosilsesquioxane containing a polymerizable group obtained in this way is purified as needed.

[0107] The adhesive layer 30 forming composition preferably contains at least one curing catalyst in addition to the polymerizable group-containing polyorganosilsesquioxane produced as described above.

[0108] When the adhesive layer 30 forming composition contains epoxy-containing polyorganosilsesquioxane, for example, a thermal cationic polymerization initiator may be used as a curing catalyst. When the adhesive layer 30 forming composition contains (meth)acryloyloxy-containing polyorganosilsesquioxane, for example, a thermal radical polymerization initiator may be used as a curing catalyst. The content of the curing catalyst in the adhesive layer 30 forming composition is preferably 0.1 to 3.0 parts by mass per 100 parts by mass of the polymerizable group-containing polyorganosilsesquioxane.

[0109] As the above-mentioned thermal cationic polymerization initiator, for example, aryl sulfonium salts, aluminum chelates, boron trifluoride amine complexes and the like can be cited. As aryl sulfonium salts, for example, hexafluoroantimonate can be cited. As aluminum chelates, for example, ethyl acetoacetate aluminum diisopropionate and tris(ethyl acetoacetate) aluminum can be cited. As boron trifluoride amine complexes, for example, boron trifluoride monoethylamine complexes, boron trifluoride imidazole complexes, and boron trifluoride piperidine complexes can be cited.

[0110] Examples of the thermal radical polymerization initiator include azo compounds, peroxides, and the like. Examples of the azo compound include 2,2'-azobisisobutyronitrile, 2,2'-azobis(2,4-dimethylvaleronitrile), 2,2'-azobis(4-methoxy-2,4-dimethylvaleronitrile), 2,2'-azobis(dimethyl 2-methylpropionate), 2,2'-azobis(dimethyl isobutyrate), 2,2'-azobis(diethyl 2-methylpropionate), and 2,2'-azobis(dibutyl 2-methylpropionate). Examples of the peroxide include benzoyl peroxide, tert-butyl peroxy-2-ethylhexanoate, 2,5-dimethyl-2,5-di(2-ethylhexanoyl)peroxyhexane, tert-butyl peroxybenzoate, tert-butyl peroxide, cumene hydroperoxide, dicumyl peroxide, di-tert-butyl peroxide, 2,5-dimethyl-2,5-dibutylperoxyhexane, 2,4-dichlorobenzoyl peroxide, 1,4-di(2-tert-butylperoxyisopropyl)benzene, 1,1-bis(tert-butylperoxy)-3,3,5-trimethylcyclohexane, methyl ethyl ketone peroxide, and 1,1,3,3-tetramethylbutyl 2-ethylperoxyhexanoate.

[0111] The composition for forming the adhesive layer 30 may contain one or more other curable compounds in addition to the above-mentioned polyorganosilsesquioxane containing a polymerizable group. Examples of the curable compound include epoxy compounds other than the above-mentioned polyorganosilsesquioxane containing a polymerizable group, (meth)acryloyloxy-containing compounds, vinyl-containing compounds, oxetane compounds, and vinyl ether compounds.

[0112] Examples of epoxy compounds other than the above-mentioned polymerizable group-containing polyorganosilsesquioxane include alicyclic epoxy compounds (alicyclic epoxy resins), aromatic epoxy compounds (aromatic epoxy resins), and aliphatic epoxy compounds (aliphatic epoxy resins). Examples of alicyclic epoxy compounds include 3,4,3',4'-diepoxybicyclohexane, 2,2-bis(3,4-epoxycyclohexyl)propane, 1,2-bis(3,4-epoxycyclohexyl)ethane, 2,3-bis(3,4-epoxycyclohexyl)ethylene oxide, bis(3,4-epoxycyclohexylmethyl)ether, and 1,2-epoxy-4-(2-epoxyethylene)cyclohexane adduct of 2,2-bis(hydroxymethyl)-1-butanol (e.g., trade name "EHPE3150" of Daicel Corporation).

[0113] Examples of the aromatic epoxy compound include epi-bis glycidyl ether epoxy resins and novolac-alkyl glycidyl ether epoxy resins.

[0114] Examples of the aliphatic epoxy compounds include glycidyl ethers of q-valent alcohols (q is a natural number) not having a ring structure, glycidyl esters of monocarboxylic acids or polycarboxylic acids, and epoxides of fats and oils having double bonds. Examples of epoxides of fats and oils having double bonds include epoxidized linseed oil, epoxidized soybean oil, and epoxidized castor oil.

[0115] Examples of the (meth)acryloyloxy group-containing compound include trimethylolpropane tri(meth)acrylate, di(trimethylolpropane) tetra(meth)acrylate, pentaerythritol tri(meth)acrylate, pentaerythritol tetra(meth)acrylate, dipentaerythritol penta(meth)acrylate, dipentaerythritol hexa(meth)acrylate, glycerol tri(meth)acrylate, tri(2-hydroxyethyl)isocyanurate tri(meth)acrylate, ethylene glycol di(meth)acrylate, 1,3-butanediol di(meth)acrylate, 1,3-butylene glycol di(meth)acrylate, and 1,4-diol di(meth)acrylate. 4-Butanediol di(meth)acrylate, 1,6-hexanediol di(meth)acrylate, neopentyl glycol di(meth)acrylate, diethylene glycol di(meth)acrylate, triethylene glycol di(meth)acrylate, dipropylene glycol di(meth)acrylate, bis(2-hydroxyethyl)isocyanurate di(meth)acrylate, dicyclopentanyl acrylate, epoxy acrylate, urethane acrylate, unsaturated polyester, polyester acrylate, polyether acrylate, vinyl acrylate, silicone acrylate, and polystyrene ethyl methacrylate. Examples of the (meth)acryloyloxy group-containing compounds include "DA-141" manufactured by Nagase Chemtex Co., Ltd., "Aronix M-211B" and "Aronix M-208" manufactured by Toagosei Co., Ltd., and "NK Ester", "ABE-300", "A-BPE-4", "A-BPE-10", "A-BP E-20", "A-BPE-30", "BPE-100", "BPE-200", "BPE-500", "BPE-900", and "BPE-1300N" manufactured by Shin-Nakamura Chemical Co., Ltd.

[0116] Examples of the vinyl group-containing compound include styrene and divinylbenzene.

[0117] Examples of the oxetane compound include 3,3-bis(vinyloxymethyl)oxetane, 3-ethyl-3-(hydroxymethyl)oxetane, 3-ethyl-3-(2-ethylhexyloxymethyl)oxetane, 3-ethyl-3-(hydroxymethyl)oxetane, 3-ethyl-3-[(phenoxy)methyl]oxetane, 3-ethyl-3-(hexyloxymethyl)oxetane, 3-ethyl-3-(chloromethyl)oxetane, and 3,3-bis(chloromethyl)oxetane.

[0118] Examples of the vinyl ether compound include 2-hydroxyethyl vinyl ether, 3-hydroxypropyl vinyl ether, 2-hydroxypropyl vinyl ether, 2-hydroxyisopropyl vinyl ether, 4-hydroxybutyl vinyl ether, 3-hydroxybutyl vinyl ether, 2-hydroxybutyl vinyl ether, 3-hydroxyisobutyl vinyl ether, 2-hydroxyisobutyl vinyl ether, 1-methyl-3-hydroxypropyl vinyl ether, 1-methyl-2-hydroxypropyl vinyl ether, 1-hydroxymethylpropyl vinyl ether, , 4-hydroxycyclohexyl vinyl ether, 1,6-hexanediol monovinyl ether, 1,6-hexanediol divinyl ether, 1,8-octanediol divinyl ether, p-xylene glycol monovinyl ether, p-xylene glycol divinyl ether, m-xylene glycol monovinyl ether, m-xylene glycol divinyl ether, o-xylene glycol monovinyl ether, o-xylene glycol divinyl ether, diethylene glycol monovinyl ether, diethylene glycol divinyl ether, triethylene glycol monovinyl ether, and triethylene glycol divinyl ether.

[0119] The composition for forming the adhesive layer 30 preferably contains a solvent from the viewpoint of adjusting its coating properties, etc. Examples of the solvent include propylene glycol monomethyl ether acetate, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, toluene, xylene, ethyl acetate, butyl acetate, 3-methoxybutyl acetate, methoxypropyl acetate, ethylene glycol monomethyl ether acetate, methanol, ethanol, isopropanol, 1-butanol, 1-methoxy-2-propanol, 3-methoxybutanol, ethoxyethanol, diisopropyl ether, ethylene glycol dimethyl ether, and tetrahydrofuran.

[0120] The composition for forming the adhesive layer 30 may further contain various additives such as a silane coupling agent, a defoaming agent, an antioxidant, an anti-blocking agent, a leveling agent, a surfactant, an extender, a rust preventive, an antistatic agent, and a plasticizer.

[0121] In the adhesive layer 30 or the siloxane-based organic-inorganic hybrid adhesive, the carbon ratio is preferably 20 to 70 mass%, more preferably 30 to 70 mass%, more preferably 40 to 60 mass%, the hydrogen ratio is preferably 2 to 20 mass%, more preferably 3 to 15 mass%, more preferably 4 to 10 mass%, the oxygen ratio is preferably 10 to 40 mass%, more preferably 15 to 35 mass%, more preferably 20 to 30 mass%, and the silicon ratio is preferably 3 to 40 mass%, more preferably 5 to 30 mass%, more preferably 10 to 20 mass%. Such a configuration is suitable for achieving high heat resistance in the formed adhesive layer 30 and suppressing shrinkage during curing, and also for exhibiting sufficient wafer bonding strength even when the thickness of the formed adhesive layer 30 is set to, for example, 5 μm or less. The above-mentioned ratios of each element can be identified, for example, by CHN elemental analysis, Si quantitative analysis (gravimetric method), ICP emission analysis, X-ray photoelectron spectroscopy, etc.

[0122] In the above-mentioned chip bonding using the composition for forming the adhesive layer 30 as described above, for example, first, the composition for forming the adhesive layer 30 is applied to the surface of a chip as the bonding object surface by spin coating to form an adhesive composition layer, and the composition layer is dried and cured by heating. The heating temperature at this time is, for example, 50 to 150° C., and the heating time is, for example, 5 to 120 minutes. Next, the two chips are bonded together while being pressurized through the adhesive composition layer formed on one chip, and the adhesive composition layer is cured by heating. During bonding, the pressure applied is, for example, 300 to 5000 g / cm 2 , the temperature is, for example, 30 to 200° C. The heating temperature for curing is, for example, 100 to 300° C., and the heating time is, for example, 5 to 120 minutes. When the composition for forming the adhesive layer 30 contains a polyorganosilsesquioxane containing a polymerizable group as a curable resin, it is preferred that the adhesive composition be heated at a temperature above room temperature and below 80° C. before the above-mentioned lamination, and be cured at a temperature of 100 to 200° C. after lamination.

[0123] The thickness of the adhesive layer 30 formed in this way is preferably 5 μm or less, more preferably 4 μm or less, and even more preferably 3 μm or less. The thickness of the adhesive layer 30 is, for example, 0.5 μm or more.

[0124] In the method for manufacturing the semiconductor device, next, Figure 1 As shown in (b), an insulating film 21 is formed on the main surface 20a of the wafer 20. The insulating film 21 covers the main surface 20a of the wafer 20 and has a concave portion of a predetermined pattern shape. A wiring pattern is formed on the concave portion as described later.

[0125] The insulating film 21 can be formed, for example, as described below. First, an insulating material film is formed on the main surface 20a of the wafer 20 by a thermal oxidation method or a CVD method. Examples of the insulating material film include silicon oxide films and silicon nitride films. Next, a given resist pattern is formed on the insulating material film by a lithography technique. Next, a pattern is formed on the insulating material film by etching the insulating material film using the resist pattern as an etching mask. The etching process is performed by, for example, wet etching. Then, the resist pattern is removed. For example, the insulating film 21 having a concave portion of a given pattern shape can be formed as described above.

[0126] In the method for manufacturing the semiconductor device, next, Figure 1 As shown in (c), a hole H as a through hole is formed in the wafer stack W (hole forming process). Specifically, first, a resist pattern as an etching mask is formed on the insulating film 21. The resist pattern has an opening for hole formation at a position corresponding to the hole formation position in the wafer stack W. Next, a hole H that penetrates the wafer 20 and the adhesive layer 30 to reach the wiring pattern 12b in the wafer 10 is formed in the wafer stack W by etching from the wafer 20 side through the resist pattern as an etching mask. In this etching process, reactive ion etching is performed. In the etching process for the wafer 20, reactive ion etching using the Bosh process is preferably performed, and as the etching gas, a mixed gas containing SiF6 and Ar is preferably used. As the etching gas for the subsequent etching process for the adhesive layer 30, a mixed gas containing CHF3, CF4, O2 and Ar is preferably used. In addition, the portion of the wiring pattern 12b facing the hole H becomes the bottom surface of the hole H.

[0127] In the method for manufacturing the semiconductor device, next, Figure 2 As shown in (a), an insulating film 41 is conformally formed on the inner surface of the hole H of the wafer stack W. The insulating film 41 is, for example, a silicon oxide film, and is formed by, for example, a CVD method.

[0128] Next, if Figure 2 As shown in (b), the portion on the bottom surface of the hole H in the insulating film 41 is etched and removed. Specifically, the portion on the wiring pattern 12b in the insulating film 41 in the hole H is removed by, for example, reactive ion etching. As the etching gas in the reactive ion etching, a mixed gas containing CHF3, CF4 and Ar is preferably used.

[0129] In the manufacturing method of the semiconductor device, next, the wafer stack W with the hole H formed therein is subjected to a cleaning process (cleaning process). The cleaning process in this process includes an oxygen plasma cleaning process and / or an argon sputtering cleaning process. In this process, it is preferred to perform an oxygen plasma cleaning process, followed by an argon sputtering cleaning process. In addition, in this process, a sulfuric acid cleaning process may also be performed. The sulfuric acid cleaning process is preferably performed between the oxygen plasma cleaning process and the argon sputtering cleaning process that follows.

[0130] When oxygen plasma cleaning is performed in the cleaning process, the treatment time is preferably 5 to 120 seconds, more preferably 10 to 60 seconds, and more preferably 15 to 40 seconds. When argon sputtering cleaning is performed in the cleaning process, the treatment time is preferably 0.5 to 5 minutes, and more preferably 2 to 4 minutes. When sulfuric acid cleaning is performed in the cleaning process, the treatment time is preferably 10 to 100 seconds, and more preferably 20 to 90 seconds. The concentration of sulfuric acid used in the sulfuric acid cleaning is, for example, 1 to 3 mass %.

[0131] Next, a barrier layer (not shown) is formed conformally on the wall surface of the hole H. Figure 3 As shown in (a), the conductive material 50 is deposited. As a material for forming the barrier layer, Ta can be cited, for example. As the conductive material 50, Cu is used in this embodiment. As a method for depositing the conductive material 50, electroplating can be adopted. In the case of adopting the electroplating method, after the above-mentioned barrier layer is formed, a seed layer for electroplating is conformally formed in the hole H by, for example, a sputtering film forming method. As a material for forming the seed layer, Cu can be cited, for example. In the electroplating method, Cu is grown on the seed layer.

[0132] Next, the excess accumulation portion of the conductive material 50 is Figure 3 (b) is removed. As a removal method, for example, chemical mechanical polishing (CMP) can be cited. By such removal, a conductive portion 51 is formed in the hole H of the chip stack W, and a wiring pattern 52 is formed in the recessed portion of the insulating film 21. The diameter of the conductive portion 51 is, for example, 5 to 20 μm in the present embodiment. The wiring pattern 52 is an element of the rewiring layer formed on the chip 20, and is electrically connected to a given semiconductor element mounted on the main surface 20a side of the chip 20. The conductive portion 51 is structurally and electrically connected to the wiring pattern 12b in the circuit forming surface 10a of the chip 10, and is structurally and electrically connected to the wiring pattern 52. Such a conductive portion 51 becomes a through-electrode for electrically connecting the semiconductor element from the chip 10 to the semiconductor element from the chip 20 in the manufactured semiconductor device.

[0133] Then, a series of processes including stacking a further wafer 20 on the wafer 20 having the rewiring layer formed on the main surface 20a via the adhesive layer 30 to forming the conductive portion 51 is performed a predetermined number of times depending on the number of stacked semiconductor elements of the semiconductor device to be manufactured.

[0134] In the manufacturing method of the semiconductor device, the wafer 10 can be thinned by grinding from the back side 10b thereof. The thickness of the thinned wafer 10 is, for example, 10 to 400 μm. In addition, bumps for external connection can be formed on the rewiring layer of the last stacked wafer 20. Alternatively, a through electrode can be formed that penetrates the thinned wafer 10 and is electrically connected to a given wiring pattern in the rewiring layer on the circuit forming surface 10a side of the wafer 10, and a bump for external connection electrically connected to the through electrode is formed on the back side 10b of the wafer 10.

[0135] As described above, a semiconductor device having a three-dimensional structure in which semiconductor elements are integrated in the thickness direction can be manufactured. The semiconductor device can be singulated by dicing.

[0136] In the manufacturing method of the present semiconductor device, as described above, the conductive portion 51 that becomes the through electrode for electrically connecting the semiconductor elements is structurally connected and electrically connected to the wiring pattern 12b of the circuit forming surface 10a of the chip 10. Such a bump-free structure is suitable in that a short conductive path is realized between the multilayered semiconductor elements. In the conventional WOW process, a bump electrode that is electrically connected to the through electrode that penetrates the chip is sometimes formed on the surface of the chip, and on this basis, the electrical connection between the semiconductor elements is realized through the bump electrode. In contrast, in the manufacturing method of the present semiconductor device, the conductive portion 51 that becomes the through electrode is directly connected to the wiring pattern 12b in the chip 10, and a bump-free structure is formed in the electrical connection between the semiconductor elements. Such a bump-free structure is suitable in that a short conductive path is realized between the multilayered semiconductor elements, and there is a tendency that the shorter the conductive path between the multilayered semiconductor elements, the smaller the resistance of the conductive path or wiring between the elements.

[0137] In addition, the manufacturing method of the semiconductor device is a method of multi-layering semiconductor elements by stacking semiconductor wafers with an adhesive layer 30 interposed therebetween, and the adhesive layer 30 bonded between the wafers contains a SiOC-based polymer as an adhesive. Furthermore, in the present method, in the cleaning process, a cleaning process including an oxygen plasma cleaning process and / or an argon sputtering cleaning process is performed on the wafer stack W having a hole H formed therein that penetrates the wafer 20 and the adhesive layer 30. The present invention has obtained the following insight: These structures are suitable in terms of achieving low contact resistance between the conductive portion 51 or the through electrode formed in the hole H and the wiring pattern 12b in the wafer 10. For example, as shown in the embodiments and comparative examples described later. There is a tendency that the smaller the contact resistance between the conductive portion 51 or the through electrode in the hole H and the wiring pattern 12b in the wafer 10, the smaller the resistance of the conductive path as a whole or the wiring as a whole between the semiconductor elements electrically connected by the through electrode in the manufactured semiconductor device.

[0138] As described above, the method for manufacturing a semiconductor device is suitable for realizing low wiring resistance between multilayered semiconductor elements in the manufactured semiconductor device. Such a method for manufacturing a semiconductor device is suitable in terms of suppressing high-speed signal transmission with low power consumption in the manufactured semiconductor device, and is also suitable in terms of suppressing attenuation of high-frequency signals.

[0139] As described above, the adhesive layer 30 in the present method is preferably a cured product of an adhesive composition containing a polyorganosilsesquioxane containing a polymerizable group. Such an adhesive layer 30 is suitable for achieving high heat resistance, lowering the curing temperature for forming the adhesive layer 30, and suppressing damage to the elements in the wafer as the adherend.

[0140] As described above, the thickness of the adhesive layer 30 in the present method is preferably 5 μm or less, more preferably 4 μm or less, and more preferably 3 μm or less. Such a structure is suitable for shortening the conductive portion 51 or the through-electrode formed by the present method, and therefore is suitable for reducing the resistance of the entire conductive path or the entire wiring between the semiconductor elements electrically connected through the through-electrode. In addition, the adhesive layer 30 containing the siloxane organic-inorganic hybrid adhesive is suitable for exerting sufficient wafer bonding strength even when it is as thin as this degree.

[0141] In addition, the thinner the adhesive layer 30 is, the Figure 1 (c) In each stage of the hole forming step and the subsequent cleaning step, it is easier to reduce the etching residue in the hole H. The reduction of the etching residue in the hole H contributes to the reduction of the contact resistance described above.

[0142] In addition, the thinner the adhesive layer 30 is, the Figure 1(c) In the above-mentioned hole forming step, the easier it is to suppress undercutting and side etching on the hole exposed surface of the adhesive layer 30 , the easier it is to form the conductive portion 51 corresponding to the hole H of an appropriate shape. Such a configuration helps suppress the occurrence of so-called leakage current in the conductive portion 51 .

[0143] As described above, the thickness of the wafer 20 in the present method is 30 μm or less, preferably 20 μm or less, and more preferably 15 μm or less. Such a structure is suitable for shortening the conductive portion 51 or the through-electrode formed by the present method, and therefore, is suitable for reducing the resistance of the entire conductive path or the entire wiring between the semiconductor elements electrically connected by the through-electrode.

[0144] Furthermore, when the wafer 20 and the adhesive layer 30 are thin as described above, this contributes to miniaturization and high density of the semiconductor device manufactured by the present method.

[0145] Example

[0146] [Example 1]

[0147] A total of 71 through-electrodes were formed in a given wafer stack as described below.

[0148] 〈Fabrication of Wafer Stack〉

[0149] First, prepare a first silicon wafer (300 mm in diameter) and a second silicon wafer (300 mm in diameter) with a rewiring layer on the surface. The rewiring layer of the first silicon wafer includes a Cu wiring pattern having an area exposed outside the rewiring layer. Next, the rewiring side of the first silicon wafer and the second silicon wafer are joined using the adhesive composition C described later. Specifically, first, a given amount of adhesive composition C is applied to the surface of a wafer by spin coating to form an adhesive composition layer, and the composition layer is dried and cured by heating. At this time, first, heating is performed at 80°C for 4 minutes, and then heating is performed at 100°C for 2 minutes. Next, the two wafers are laminated while being pressurized via the adhesive composition layer formed on one wafer, and then the adhesive composition layer is cured by heating. During lamination, the pressure applied is, for example, 1000 g / cm 2 , the temperature was 50°C. During curing, it was first heated at 135°C for 30 minutes and then heated at 170°C for 30 minutes. The thickness of the adhesive layer between the wafers was 2.5 μm. As described above, a wafer stack having a stacked structure including the first and second silicon wafers and the adhesive layer (thickness 2.5 μm) joining them was prepared.

[0150] 〈Process for Wafer Stack〉

[0151] Next, the second silicon wafer in the wafer stack was ground using a grinding device (trade name "DGP8761HC", manufactured by Disco Co., Ltd.) to thin the second silicon wafer to a thickness of 10 μm. Next, a silicon oxide film (insulating film) was formed on the ground surface of the second silicon wafer by a CVD method. Next, a concave portion of a given pattern shape was formed in the insulating film. The concave portion was formed by etching the insulating material film using the resist pattern as an etching mask after a given resist pattern was formed on the insulating film by lithography.

[0152] Next, after the resist pattern is removed from the insulating film, a hole (through hole) is formed in the wafer stack. Specifically, first, a resist pattern as an etching mask is formed on the insulating film. The resist pattern has an opening for hole formation at a position corresponding to the hole formation position in the wafer stack. Next, by etching from the second silicon wafer side through the resist pattern as an etching mask, a hole is formed in the wafer stack that penetrates the second silicon wafer (thickness 10μm) and the adhesive layer (thickness 2.5μm) to reach the wiring pattern in the first silicon wafer. In this etching process, first, the second silicon wafer is subjected to the first etching process, and then the adhesive layer is subjected to the second etching process. In the first etching process, an etching device (trade name "Silivia", manufactured by Applied Materials) is used to perform reactive ion etching using the Bosch process, using a mixed gas of SiF6 and Ar as an etching gas. In the second etching process, reactive ion etching is performed using an etching apparatus (trade name "e-MAX", manufactured by Applied Materials Inc.), and a mixed gas of CHF 3 , CF 4 , O 2 , and Ar is used as an etching gas.

[0153] Next, a silicon oxide film is conformally formed on the inner surface of the hole of the wafer stack by CVD. Next, the portion on the bottom surface of the hole in the silicon oxide film is etched and removed. In the etching process for this purpose, an etching device (trade name "e-MAX", manufactured by Applied Materials) is used for reactive ion etching, and a mixed gas of CHF3, CF4 and Ar is used as the etching gas.

[0154] Next, the wafer stack is subjected to a cleaning treatment. Specifically, the wafer stack with holes formed therein is subjected to an oxygen plasma cleaning treatment, and then to a sulfuric acid cleaning treatment. In the oxygen plasma cleaning treatment, a plasma device (trade name "e-MAX", manufactured by Applied Materials) is used, oxygen gas is used, the temperature condition is set to 120°C, and the plasma ashing (cleaning treatment) time is set to 15 seconds. In the sulfuric acid cleaning treatment, a cleaning device (trade name "GPTC-1") is used, 2 mass % sulfuric acid is used, and the cleaning treatment time is set to 43 seconds.

[0155] Next, a Ta barrier layer (thickness 80nm) is conformally formed on the wall of the hole after the cleaning process by CVD method, and then a Cu seed layer (thickness 1μm) for electroplating is conformally formed by sputtering film forming method. Next, Cu is deposited in the hole in the wafer stack and in the concave portion of the insulating film on the second silicon wafer by electroplating. Next, the excessive accumulation of Cu on the second silicon wafer is removed by CMP method. Thus, a through electrode is formed in the hole of the wafer stack, and a wiring pattern is formed in the concave portion of the insulating film on the second silicon wafer of the wafer stack.

[0156] <Preparation of Adhesive Composition C>

[0157] 100 parts by mass of the epoxy-containing polyorganosilsesquioxane obtained as described later, 115 parts by mass of propylene glycol monomethyl ether acetate, 0.45 parts by mass (in terms of solid content) of an antimony sulfonium salt (trade name "SI-150L", manufactured by Sanshin Chemical Industry Co., Ltd.), and 0.05 parts by mass of (4-hydroxyphenyl)dimethylsulfonium methyl sulfide (trade name "SAN-AID SI Auxiliary Agent", manufactured by Sanshin Chemical Industry Co., Ltd.) were mixed to obtain an adhesive composition C.

[0158] 〈Synthesis of polyorganosilsesquioxane〉

[0159] In a 300 mL flask equipped with a reflux condenser, a nitrogen inlet tube, a stirring device and a thermometer, 161.5 mmol (39.79 g) of 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, 9 mmol (1.69 g) of phenyltrimethoxysilane and 165.9 g of acetone as a solvent were mixed while introducing nitrogen and heated to 50°C. Next, 4.7 g (1.7 mmol in terms of potassium carbonate) of 5% aqueous solution was added to the mixture over 5 minutes, and then 1700 mmol (30.6 g) of water was added over 20 minutes. During the dropping operation, the mixture did not experience a significant temperature rise. After the dropping operation, a polycondensation reaction was carried out at 50°C for 4 hours while introducing nitrogen into the flask. As a result of analyzing the product in the reaction solution after the polycondensation reaction, the number average molecular weight was 1900 and the molecular weight dispersion was 1.5. Then, the reaction solution after standing and cooling was repeatedly washed with water until the lower liquid (aqueous phase) produced by phase separation reached neutrality, and then the upper liquid was separated and the solvent was distilled off from the upper liquid under the conditions of 1 mmHg and 40° C. until the amount of solvent reached 25% by mass, thereby obtaining a colorless and transparent liquid product (epoxy-containing polyorganosilsesquioxane).

[0160] [Example 2]

[0161] The process of Example 2 was performed on the wafer stack in the same manner as in Example 1, except that oxygen plasma cleaning was not performed in the cleaning process and argon sputtering cleaning was performed after sulfuric acid cleaning. In the argon sputtering cleaning in Example 2, a sputtering device (trade name "Producer", manufactured by Applied Materials) was used, and the Ar sputtering (cleaning) time was set to 3 minutes.

[0162] [Example 3]

[0163] In the cleaning process, the wafer stack was subjected to the process of Example 3 in the same manner as in Example 1, except that the argon sputtering cleaning process was performed after the sulfuric acid cleaning process. In the argon sputtering cleaning process in Example 3, a sputtering device (trade name "Producer", manufactured by Applied Materials) was used, and the Ar sputtering (cleaning process) time was set to 3 minutes.

[0164] [Example 4]

[0165] In the cleaning process, the time of the sulfuric acid cleaning treatment was set to 43 seconds to 86 seconds, and the argon sputtering cleaning treatment was performed after the sulfuric acid cleaning treatment. The process of Example 4 was performed on the above-mentioned wafer stack in the same manner as the process of Example 1. In the argon sputtering cleaning treatment in Example 4, a sputtering device (trade name "Producer", manufactured by Applied Materials) was used, and the Ar sputtering (cleaning treatment) time was set to 3 minutes.

[0166] [Comparative Example 1]

[0167] The process of Comparative Example 1 was performed on the wafer stack in the same manner as the process of Example 1, except that the oxygen plasma cleaning process was not performed in the cleaning step.

[0168] <Resistance measurement>

[0169] The chain resistance (daisy chain resistance) of the through-electrodes, a total of 71 in total, was measured for each wafer stack of Examples 1 to 4 and Comparative Example 1. The measurement results are shown in FIG. Figures 4 to 7 . Figure 4 It is a graph showing the chain resistance measurement results of Example 1 and Comparative Example 1. Figure 5 It is a graph showing the chain resistance measurement results of Example 2 and Comparative Example 1. Figure 6 It is a graph showing the chain resistance measurement results of Example 1, Example 3, and Comparative Example 1. Figure 7 It is a graph showing the chain resistance measurement results of Example 3, Example 4, and Comparative Example 1. In each graph, the horizontal axis represents the resistance value (Ω), and the vertical axis represents the cumulative probability (%). In addition, each point in the graph represents the contact resistance of a given through electrode (the contact resistance between the wiring pattern of the first silicon wafer and the through electrode thereon).

[0170] [evaluate]

[0171] In the above resistance value measurement, the contact resistance of 99% of the measurement points of the through electrodes formed by the methods of Examples 1 to 4 was 700Ω or less (Example 1), 450Ω or less (Example 2), 150Ω or less (Example 3), and 250Ω or less (Example 4). Figures 4 to 7 As can be seen from the graph shown, the contact resistance values ​​of the through electrodes formed by the methods of Examples 1 to 4 are significantly lower than the contact resistance value of the through electrodes formed by the method of Comparative Example 1, and the variation is significantly suppressed.

[0172] As a summary of the above, the configuration of the present invention and its modifications are described below.

[0173] [1] A method for manufacturing a semiconductor device, the method comprising:

[0174] The first step is to prepare a wafer stack having a stacked structure, the stacked structure comprising a first wafer having a circuit forming surface including a wiring pattern, a second wafer having a main surface and a back surface opposite to the main surface, and an adhesive layer containing a SiOC-based polymer and sandwiched between the circuit forming surface of the first wafer and the back surface of the second wafer.

[0175] A second step is to form a hole in the wafer stack that penetrates the second wafer and the adhesive layer and reaches the wiring pattern in the first wafer by etching the second wafer from the second wafer side through a mask pattern that masks a portion of the main surface side of the second wafer;

[0176] A third step is to form an insulating film on the inner surface of the hole;

[0177] A fourth step is to remove the portion of the insulating film on the wiring pattern in the hole by etching;

[0178] A fifth step is to perform a cleaning process including an oxygen plasma cleaning process and / or an argon sputtering cleaning process on the wafer stack after the fourth step; and

[0179] In the sixth step, a conductive portion is formed by filling the hole after the cleaning step with a conductive material.

[0180] [2] The method for manufacturing a semiconductor device according to [1], wherein:

[0181] The carbon ratio in the above-mentioned SiOC-based polymer is 20 to 70 mass%, 30 to 70 mass%, or 40 to 60 mass%, the hydrogen ratio is 2 to 20 mass%, 3 to 15 mass%, or 4 to 10 mass%, the oxygen ratio is 10 to 40 mass%, 15 to 35 mass%, or 20 to 30 mass%, and the silicon ratio is 3 to 40 mass%, 5 to 30 mass%, or 10 to 20 mass%.

[0182] [3] The method for manufacturing a semiconductor device according to [1] or [2], wherein:

[0183] The etching process is reactive ion etching.

[0184] [4] The method for manufacturing a semiconductor device according to any one of [1] to [3], wherein:

[0185] The cleaning process includes an oxygen plasma cleaning process and an argon sputtering cleaning process thereafter.

[0186] [5] The method for manufacturing a semiconductor device according to any one of [1] to [4], wherein:

[0187] The oxygen plasma cleaning treatment may be performed for 5 to 120 seconds, 10 to 60 seconds, or 15 to 40 seconds.

[0188] [6] The method for manufacturing a semiconductor device according to any one of [1] to [5], wherein:

[0189] The processing time of the argon sputtering cleaning process is 0.5 to 5 minutes, or 2 to 4 minutes.

[0190] [7] The method for manufacturing a semiconductor device according to any one of [1] to [6], wherein:

[0191] The cleaning process includes a sulfuric acid cleaning process between the oxygen plasma cleaning process and the argon sputtering cleaning process.

[0192] [8] The method for manufacturing a semiconductor device according to [7], wherein:

[0193] The treatment time of the sulfuric acid cleaning treatment is 10 to 100 seconds, or 20 to 90 seconds.

[0194] [9] The method for manufacturing a semiconductor device according to any one of [1] to [8], wherein:

[0195] The method of filling the conductive material in the sixth step is electroplating.

[0196]

[10] The method for manufacturing a semiconductor device according to any one of [1] to [9], wherein:

[0197] The adhesive layer is a cured product of an adhesive composition containing a siloxane-based organic-inorganic hybrid adhesive.

[0198]

[11] The method for manufacturing a semiconductor device according to any one of [1] to

[10] , wherein:

[0199] The adhesive layer is a cured product of an adhesive composition containing a polymerizable group-containing polyorganosilsesquioxane.

[0200]

[12] The method for manufacturing a semiconductor device according to

[11] , wherein:

[0201] The content ratio of the polymerizable group-containing polyorganosilsesquioxane in the adhesive composition is 70% by mass or more, 80 to 99.8% by mass, or 90 to 99.5% by mass.

[0202]

[13] The method for manufacturing a semiconductor device according to

[11] or

[12] , wherein:

[0203] The above-mentioned polymerizable group-containing polyorganosilsesquioxane comprises: a first structural unit [RSiO 3 / 2 ], and a second structural unit [RSiO 2 / 2 (OR')] (R and R' in the second structural unit may be the same or different) as a siloxane structural unit,

[0204] [Chemical formula 6]

[0205] [R 1 SiO 3 / 2 ] (1)

[0206] [R 1 SiO 2 / 2 (OR 2 )] (2)

[0207] (R in formula (1) 1 And R in formula (2) 1 and R in formula (2) represent groups containing epoxy groups or (meth)acryloyloxy groups. 2 represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms. ).

[0208]

[14] The method for manufacturing a semiconductor device according to any one of

[11] to

[13] , wherein:

[0209] The number average molecular weight (Mn) of the polymerizable group-containing polyorganosilsesquioxane is 1,000 to 50,000, 1,500 to 10,000, 2,000 to 8,000, or 2,000 to 7,000.

[0210]

[15] The method for manufacturing a semiconductor device according to any one of

[11] to

[14] , wherein:

[0211] The molecular weight dispersion (Mw / Mn) of the polymerizable group-containing polyorganosilsesquioxane is 1.0 to 4.0, 1.1 to 3.0, or 1.2 to 2.7.

[0212]

[16] The method for manufacturing a semiconductor device according to any one of [1] to

[15] , wherein:

[0213] The thickness of the adhesive layer is 5 μm or less, 4 μm or less, or 3 μm or less and 0.5 μm or more.

[0214]

[17] The method for manufacturing a semiconductor device according to any one of [1] to

[16] , wherein:

[0215] The second wafer has a thickness of 20 μm or less, or 15 μm or less.

[0216] Industrial Applicability

[0217] According to the method of the present invention, low wiring resistance can be achieved between semiconductor elements that are multilayered and bonded via an adhesive layer.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: In the first step, a wafer stack having a stacked structure is prepared. The stacked structure includes: a first wafer having a circuit forming surface including a wiring pattern, a second wafer having a main surface and a back surface opposite to the main surface, and an adhesive layer containing a SiOC-based polymer and sandwiched between the circuit forming surface of the first wafer and the back surface of the second wafer. A second step is to form a hole in the wafer stack that penetrates the second wafer and the adhesive layer and reaches the wiring pattern in the first wafer by etching the second wafer side through a mask pattern that masks a portion of the main surface side of the second wafer; A third step is to form an insulating film on the inner surface of the hole; A fourth step is to remove the portion of the insulating film in the hole on the wiring pattern by etching; A fifth step of performing a cleaning process including an oxygen plasma cleaning process, an argon sputtering cleaning process, and a sulfuric acid cleaning process between the oxygen plasma cleaning process and the argon sputtering cleaning process on the wafer stack after the fourth step; as well as In the sixth step, a conductive portion is formed by filling the hole after the cleaning step with a conductive material.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The cleaning process includes an oxygen plasma cleaning process and an argon sputtering cleaning process thereafter.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The oxygen plasma cleaning process may be performed for 5 to 120 seconds.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The argon sputtering cleaning process may be performed for 0.5 to 5 minutes.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The adhesive layer is a cured product of an adhesive composition containing a polymerizable group-containing polyorganosilsesquioxane.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The adhesive layer has a thickness of 5 μm or less.

7. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The second wafer has a thickness of 20 μm or less.

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