Generate error check data for error detection during data modification in a memory subsystem

Abstract

The present invention relates to generating error check data for error detection during data modification in a memory subsystem. A request to store first data is received. The first data and first error check data are received. The first error check data can be a cyclic redundancy check (CRC) operation based on the first data. Second data is generated by modifying the first data. Second error check data for the second data is generated by using the first error check data and the difference between the first data and the second data.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to memory subsystems, and more particularly, to generating error check data for error detection during data modification in a memory subsystem. Background Art

[0002] A memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory components. Summary of the Invention

[0003] One embodiment of the present invention provides a system that includes: a memory component; a processing device operatively coupled to the memory component to: receive a request to store first data; receive the first data and first error check data, the first error check data being based on a cyclic redundancy check (CRC) operation on the first data; generate second data by modifying the first data; and generate second error check data for the second data by using the first error check data and a difference between the first data and the second data.

[0004] Another embodiment of the present invention provides a method that includes: receiving a request to store first data; receiving the first data and first error check data, the first error check data being based on a cyclic redundancy check (CRC) operation on the first data; generating second data by modifying the first data; and generating, by a processing device, second error check data for the second data by using the first error check data and a difference between the first data and the second data.

[0005] Yet another embodiment of the present invention provides a method that includes: receiving, from a host system, a request to retrieve first data; retrieving second data associated with the first data and second error check data for the second data, the second data corresponding to a modification of the first data, and the second error check data being based on a cyclic redundancy check (CRC) operation on the second data; generating the first data from the second data by reversing the modification; generating first error check data based on the second error check data and a difference between the first data and the second data; determining, by a processing device, whether the first data contains an error by comparing the first error check data with error check data generated based on a CRC operation on the first data; and providing the first data to the host system in response to determining that the first data does not contain the error. Brief Description of the Drawings

[0006] The present invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the invention. However, the drawings should not be construed as limiting the invention to a particular embodiment, but are merely for explanation and understanding.

[0007] Figure 1 Illustrate an example computing environment that includes a memory subsystem in accordance with some embodiments of the present invention.

[0008] Figure 2 Is a flowchart of an example method for detecting whether an error has been introduced during data encryption.

[0009] Figure 3 Is a flowchart of an example method for detecting whether an error has been introduced during data decryption in accordance with some embodiments of the present invention.

[0010] Figure 4 Is a flowchart of an example method for generating error check data in accordance with some embodiments of the present invention.

[0011] Figure 5 Is a flowchart of an example method for detecting an error in data for a retrieval request by using error check data in accordance with some embodiments of the present invention.

[0012] Figure 6 Is a block diagram of an example computer system in which embodiments of the present invention may operate. Detailed Description

[0013] Aspects of the present invention relate to generating error check data for error detection during data modification in a memory subsystem. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in conjunction with Figure 1 Generally, a host system can utilize a memory subsystem that includes one or more memory components (also referred to hereinafter as "memory devices"). The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem can receive message data appended with a cyclic redundancy check (CRC) code from the host system to store the message data and the CRC code in one or more memory components. Later, the memory subsystem can modify the original message data in various ways, such as encrypting or compressing the original message data and / or appending metadata to the original message data. Subsequently, the memory subsystem can store the modified message data together with the original CRC code (i.e., the CRC code received from the host system).

[0015] Subsequently, the host system may request the memory subsystem to access the message data and the CRC code. In response, the memory subsystem may retrieve the modified message data and obtain the original message data from the modified message data. Then, the memory subsystem may provide the requested message data together with the original CRC code to the host system. Thus, the host system may use the original CRC code and the retrieved message data to verify whether the retrieved message data is corrupted or contains errors. For example, the host system may generate a new CRC code from the retrieved message data and may compare the new CRC code with the original CRC code. If the two CRC codes match, the host system may determine that the retrieved message data is valid (i.e., the same as the original message data requested to be stored). On the other hand, if the two CRC codes do not match, the host system may determine that the retrieved data is corrupted. In some cases, the memory subsystem (instead of the host system) may use the new CRC code and the original CRC code to verify the integrity of the original message data.

[0016] Conventionally, the memory subsystem stores the original CRC code together with the message data modified by encryption, compression, and / or additional metadata to verify the retrieved message data (i.e., the message data changed back from the modified message data). Since the memory subsystem should store the original CRC code of the host system when the message data is requested to be retrieved, the memory subsystem cannot verify whether an error has been introduced during the modification of the message data and / or the location where the error has been introduced. For example, an error may be introduced during modification (e.g., encryption) or reverse modification (or unmodification) (e.g., decryption), where the data size remains the same. To verify this error, the memory subsystem needs the CRC code corresponding to the modified or unmodified message data so that the memory subsystem can compare the corresponding CRC code with the new CRC code generated based on the modified or unmodified message data. If the two CRC codes are the same, the memory subsystem may determine that no error has been introduced during the (several) modifications. However, if the memory subsystem replaces the original CRC code with the CRC code for the modified or unmodified message data, the retrieved message data cannot be verified. Thus, the conventional memory subsystem cannot identify whether an error has been introduced and / or the location where the error has been introduced when storing and retrieving the message data of the host system.

[0017] Aspects of the present invention are addressed by a memory subsystem that generates error check data (e.g., CRC codes) upon every modification (e.g., encryption, compression, appending metadata, decryption, decompression, and / or truncation) performed on data received from a host system during storage and / or retrieval of the data. In accordance with aspects of the present invention, for storing data, the memory subsystem generates error check data using the data received from the host system, error check data corresponding to the data, and data generated from the modification (e.g., encryption, compression, and / or appending metadata to the original message data from the host system). For retrieving data, the memory subsystem generates error check data using the modified data, error check data corresponding to the modified data, and data generated from reversing the modification (e.g., decryption, decompression, and / or truncation).

[0018] Advantages of the present invention include (but are not limited to) ensuring the integrity of data during storage and retrieval by detecting when and / or if an error is introduced during storage and retrieval of the data and performing a corrective action (e.g., repeating the modification and / or reversing the modification) upon detection. Accordingly, the reliability of the memory subsystem can be improved.

[0019] Figure 1 An example computing environment 100 including a memory subsystem 110 in accordance with some embodiments of the present invention is described. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such things.

[0020] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing environment 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1An example of a host system 120 coupled to a memory subsystem 110 is described. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] The host system 120 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such a computing device that includes a memory and a processing device. The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access the memory components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0023] The memory device can include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 140) can be (but is not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Examples of the non-volatile memory device (e.g., the memory device 130) include negative-and (NAND) type flash memory. Each of the memory devices 130 can include one or more memory cell arrays, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., triple-level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component can include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of the memory cells. Each of the memory cells can store one or more data bits used by the host system 120. In addition, the memory cells of the memory device 130 can be grouped into memory pages or memory blocks, which can refer to the units of the memory components for storing data.

[0025] Although non-volatile memory components (e.g., NAND-type flash memory) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), magnetic random access memory (MRAM), negative-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point non-volatile memory cell arrays. Cross-point non-volatile memory arrays may perform bit storage based on body resistance changes in conjunction with a stacked cross-gate data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, in which non-volatile memory cells are programmed without prior erasure of the non-volatile memory cells.

[0026] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0027] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0028] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present invention, the memory subsystem 110 may not include the memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0029] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical block address and the physical block address associated with the memory device 130. The memory subsystem controller 115 can further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0030] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0031] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0032] The memory subsystem 110 includes an error detection component 113 that can be used to generate error check data or codes. In some embodiments, the memory subsystem controller 115 includes at least a portion of the error detection component 113. For example, the memory subsystem controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the error detection component 113 is part of the host system 110, an application, or an operating system.

[0033] The error detection component 113 can receive requests to store message data and corresponding error check data. The error detection component 113 can generate another message data by modifying the message data. The error detection component 113 can also generate error check data corresponding to the modified message data by using the received error check data and the difference between the message data and the modified message data. Further details regarding the operation of the error detection component 113 are described below.

[0034] Figure 2is a flow chart of an example method 200 for detecting whether an error has been introduced during data encryption according to some embodiments of the present invention. Method 200 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 200 is executed by Figure 1 the error detection component 113. Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0035] At operation 210, the processing device receives message data (e.g., M) from the host system 120. In some embodiments, the message data may include N binary data bits, such as M0, M1, etc. The processing device may receive the message data as part of a write request for storing the message data from the host system 120. In some embodiments, the processing device may receive the message data and error check data of the message data (e.g., CRC) together in a data packet. The data packet may have the error check data appended to the message data. In this case, the processing device may extract the message data and the error check data from the data packet. The error check data may include R binary data bits, such as C0, C1, etc.

[0036] In addition, at operation 210, the processing device modifies the message data. In some embodiments, the processing device encrypts the message data to produce encrypted data M'. The resulting encrypted data may also have binary digits containing the same N bits. The processing device then stores the encrypted data. This encryption process securely stores the message data in response to a write operation from the host system 120. When the host system 120 requests access to the message data M, the processing device decrypts the encrypted data to transmit the message data back to the host system 120, as will be described below with respect to Figure 3 the description. Additionally, the processing device may create a copy of the original message data for operation 215. Further, at operation 210, the processing device may generate metadata representing the type of modification performed on the original message data M. The processing device may associate the modified message data M' with the original data M for retrieval using the metadata.

[0037] After modifying the message data, at operation 215, the processing device combines the original message data M with the encrypted data M'. Before modifying the original message data M, the processing device may create a copy of the original message data M and use this copy to combine with the encrypted data M'. In some embodiments, the processing device may calculate the difference between the two data M and M' to combine the two data. Specifically, the processing device may apply an exclusive OR (XOR) logic function to the two binary data M and M'. In a further embodiment, the processing device may delete the copy of the original data M after performing operation 215.

[0038] At operation 220, the processing device applies a cyclic redundancy check (CRC) operation to the difference between the original data M and the modified data M'. As a result, the processing device generates error check data (e.g., CRC*). In some embodiments, CRC* may have R binary data bits, such as C*0, C*1, etc. The processing device may use CRC* as incremental error check data to calculate the error check data (e.g., CRC') of the modified data M', as will be described below with respect to operation 225. The incremental error check data used herein refers to error check data (e.g., CRC code calculated from a CRC operation) for incrementally updating the error check data corresponding to the original data to the error check data of the data changed from the original data.

[0039] At operation 225, the processing device receives the error check data (e.g., CRC) of the original message data M. The processing device may receive the error check data from the host system or may generate the error check data by performing a CRC operation on the received message data M. Then, the processing device updates the error check data (e.g., CRC) of the original message data with the incremental error check data (e.g., CRC*) by determining the difference between the two error check data. Similar to operation 215, the processing device may use the XOR logic function to determine the difference between the two error check data CRC and CRC*. By updating the error check data CRC corresponding to the original message data, the processing device generates the error check data (e.g., CRC') of the modified data M'. That is, the updated error check data is the error check data (e.g., CRC') corresponding to the modified data M'. Subsequently, the processing device may use CRC' to detect whether any errors are introduced during encryption, as will be described below with respect to operations 230 and 240. This error may be caused by noise or other such impairments during storing data and / or retrieving the stored data (e.g., alpha particles emitted by the encapsulation material of the memory subsystem 110, which may cause the data value or data bit stored in the memory cell to switch from a '0' value to a '1' value (or vice versa)).

[0040] At operation 230, the processing device applies a CRC operation to the encrypted data M'. In some embodiments, the resulting error check data CRC'' may have R binary data bits. Any error check data generated from the CRC operation will have the same number R of bits.

[0041] Next, at operation 240, the processing device detects whether an error has been introduced during the encryption of operation 210 based on the two error check data CRC' and CRC''. If the two error check data have the same value, the processing device may determine that the encrypted data M' is valid. Otherwise, if the two error check data do not match, the processing device may determine that the encrypted data M' is invalid due to an error introduced during the encryption of operation 210. Thus, by updating the error check data (e.g., CRC) of the original data M with incremental error check data (e.g., CRC*), the processing device can generate error check data (e.g., CRC') corresponding to the modified data M' for detecting any error introduced during the modification of operation 210.

[0042] In response to determining that the encrypted data M' is valid, the processing device may store the encrypted data M' together with its corresponding error check data CRC' in a memory component. In this case where CRC'' matches CRC', the processing device may store CRC'' (instead of CRC'). In further embodiments, the processing device may modify the received data (e.g., M) multiple times. In this case, the processing device may execute method 200 each time a modification is performed to ensure the integrity of the modified data and perform any corrective actions accordingly.

[0043] Figure 3 is a flowchart of an example method 300 for detecting whether an error has been introduced during data decryption according to some embodiments of the present invention. Method 300 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 300 is executed by Figure 1 the error detection component 113. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0044] At operation 310, the processing device receives encrypted message data. In some embodiments, the processing device may retrieve the encrypted message data M' stored in the memory component 112 from method 200. In some embodiments, the processing device may read the stored data M' in response to a request from the host system 120. The request may be associated with the request for M stored Figure 2 in the memory. That is, the host system 120 may send a read operation to the processing device to retrieve the data M that has been transmitted to the processing device for storage. The host system 120 may not be aware of the encryption performed on M. Thus, in response to the retrieval request from the host system 120, the processing device may reverse or undo the modification (i.e., decrypt) of the stored data M'. To determine how to reverse or undo the modification, the processing device may identify the type of modification performed on the original data M from the metadata associated with the modified data M'. The processing device may then determine the operation to transform the modified data M' back to the original data M. For example, if the original data M from Figure 2 the memory has been encrypted into M', the processing device may decrypt the encrypted data M' to obtain the original data M. Thus, both the encrypted data M' and the decrypted data M have the same number N of bits. Once the modified data M' has been transformed back to the original data M, the processing device provides the original data M to the host system 120 in response to the read operation (unless an error is detected during the process of reversing the modification, as will be described with respect to operation 340 below).

[0045] At operation 315, the processing device determines the difference between the encrypted data M' and the decrypted data M. Similar to operation 215, the processing device may apply the XOR logic function to the two data to determine the difference between the data.

[0046] At operation 320, the processing device performs a CRC operation on the difference determined from operation 315. As a result, the processing device generates incremental error check data (e.g., CRC^) that will be used to determine the error check data for the decrypted data M, as will be described in operation 325 below.

[0047] In operation 325, the processing device receives error check data (e.g., CRC') corresponding to the retrieved data M'. The processing device may retrieve the CRC' associated with the modified data M' that has been stored in the memory component 112. The processing device may then update the error check data (e.g., CRC') corresponding to the modified data M' by combining the error check data CRC' with the incremental error check data CRC^. Both error check data may be binary digits and have the same number R of bits. Thus, in some embodiments, the processing device may use the XOR logic function to combine the two error check data. Accordingly, the processing device generates the error check data (e.g., CRC) of the decrypted data M from the resulting product of the XOR logic function. In some embodiments, the CRC may be a binary digit having R bits. The processing device may provide the error check data of the decrypted data M to the host system 120 in response to a retrieval request.

[0048] In operation 330, the processing device applies a CRC operation to the decrypted data M and generates error check data (e.g., CRC**). In operation 340, to detect whether an error is introduced during the reverse modification or decryption in operation 310 or whether the reverse modified data M contains an error, the processing device determines whether the error check data CRC** of the reverse modified data M matches the error check data CRC determined by updating the error check data CRC' of the modified data M' with the incremental error check data CRC^. If the two error check data CRC and CRC** match, the processing device may verify that the decrypted data M does not contain an error. In this case, Figure 3 the decrypted data M in Figure 2 should be the same as the original data M received from the host system 120 in

[0049] Figure 4 is a flowchart of an example method 400 for generating error check data according to some embodiments of the present invention. Method 400 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1is performed by the error detection component 113. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more of the processes may be omitted. Accordingly, all of the processes are not required in every embodiment. Other process flows are possible.

[0050] At operation 410, the processing device receives a request to store data (e.g., Figure 2 M in). For example, the processing device may receive a request to store M as provided by the host system 120. In other embodiments, the processing device may receive the request from the memory subsystem 110.

[0051] At operation 420, the processing device receives data (e.g., M) and error check data for the data (e.g., Figure 2 CRC in). In some embodiments, the processing device may receive the data with the request. The processing device may receive the data from the host system 120 or the memory subsystem 110. The data may be in the form of binary digits. The error check data may also be in the form of binary digits. In some embodiments, the error check data may be a cyclic redundancy check (CRC) code generated by applying a CRC operation to the received data. Additionally, the error check data may be appended to the received data. In this case, the processing device may read the error check data (e.g., CRC) from a data packet containing the data (e.g., M) and the corresponding error check data (e.g., CRC). In some embodiments, the processing device may receive the error check data from the host system 120 or the memory subsystem 110. In some other embodiments, the processing device may perform a CRC operation on the received data to generate the error check data for operation 420. In a further embodiment, the processing device may create a copy of the received data to perform a correction action in case an error is detected with respect to operation 430, as will be described below.

[0052] At operation 430, the processing device generates another data (e.g., Figure 2 M’ in) by modifying the data. The processing device may modify the data while maintaining the same data size. For example, the processing device may encrypt M and generate M’, where M’ is the encrypted M having the same number of bits as M. In some embodiments, the processing device may identify the type of modification (e.g., encryption) and store, for example, using metadata, the type of modification along with M’.

[0053] At operation 440, the processing device generates error check data (e.g., CRC’) for the modified data (e.g., M’) by using the error check data (e.g., CRC) of the original data (e.g., M) and the difference between the data (e.g., M) and the modified data (e.g., M’). That is, the processing device may update the error check data (e.g., CRC) received at operation 420 to generate error check data for the modified data. The processing device may update the error check data of operation 420 based on the combination of the received data (e.g., M) and the data (e.g., M’) generated at operation 430. For example, the processing device may use incremental error check data (e.g., CRC* in Figure 2 ) generated from the combination of the original data M and the modified data M’. The incremental error check data used herein refers to the error check data (calculated from the CRC operation) for incrementally updating the error check data of the original data to reach the error check data of the modified data to verify the modified data generated from the data modification from the original data to the modified data. In some embodiments, the processing device may combine the original data and the modified data using the difference between the two data. The processing device may determine the difference using the XOR logic function. Once the processing device determines the difference between M and M’, the processing device may apply a CRC operation to the difference to generate incremental error check data CRC*. After determining the incremental error check data (e.g., CRC*), the processing device may continue to generate error check data (e.g., CRC’) for the modified data (e.g., M’) by updating the error check data (e.g., CRC) of the original data (e.g., M) with the incremental error check data (e.g., CRC*). To update the error check data (e.g., CRC) of the original data (e.g., M), the processing device may combine the error check data (e.g., CRC) of the original data (e.g., M) with the incremental error check data (e.g., CRC*). In some embodiments, the processing device may perform an XOR logic function on the two CRCs (e.g., CRC and CRC*). Thus, in some embodiments, the processing device may use the difference between CRC and CRC* determined by the XOR logic function to combine CRC and CRC*. Figure 2 In Figure 2 . That is, the processing device may update the error check data (e.g., CRC) received at operation 420 to generate error check data for the modified data. The processing device may update the error check data of operation 420 based on the combination of the received data (e.g., M) and the data (e.g., M’) generated at operation 430. For example, the processing device may use incremental error check data (e.g., CRC* in Figure 2 ) generated from the combination of the original data M and the modified data M’. The incremental error check data used herein refers to the error check data (calculated from the CRC operation) for incrementally updating the error check data of the original data to reach the error check data of the modified data to verify the modified data generated from the data modification from the original data to the modified data. In some embodiments, the processing device may combine the original data and the modified data using the difference between the two data. The processing device may determine the difference using the XOR logic function. Once the processing device determines the difference between M and M’, the processing device may apply a CRC operation to the difference to generate incremental error check data CRC*. After determining the incremental error check data (e.g., CRC*), the processing device may continue to generate error check data (e.g., CRC’) for the modified data (e.g., M’) by updating the error check data (e.g., CRC) of the original data (e.g., M) with the incremental error check data (e.g., CRC*). To update the error check data (e.g., CRC) of the original data (e.g., M), the processing device may combine the error check data (e.g., CRC) of the original data (e.g., M) with the incremental error check data (e.g., CRC*). In some embodiments, the processing device may perform an XOR logic function on the two CRCs (e.g., CRC and CRC*). Thus, in some embodiments, the processing device may use the difference between CRC and CRC* determined by the XOR logic function to combine CRC and CRC*. Figure 2 In Figure 2 . The incremental error check data used herein refers to the error check data (calculated from the CRC operation) for incrementally updating the error check data of the original data to reach the error check data of the modified data to verify the modified data generated from the data modification from the original data to the modified data. In some embodiments, the processing device may combine the original data and the modified data using the difference between the two data. The processing device may determine the difference using the XOR logic function. Once the processing device determines the difference between M and M’, the processing device may apply a CRC operation to the difference to generate incremental error check data CRC*. After determining the incremental error check data (e.g., CRC*), the processing device may continue to generate error check data (e.g., CRC’) for the modified data (e.g., M’) by updating the error check data (e.g., CRC) of the original data (e.g., M) with the incremental error check data (e.g., CRC*). To update the error check data (e.g., CRC) of the original data (e.g., M), the processing device may combine the error check data (e.g., CRC) of the original data (e.g., M) with the incremental error check data (e.g., CRC*). In some embodiments, the processing device may perform an XOR logic function on the two CRCs (e.g., CRC and CRC*). Thus, in some embodiments, the processing device may use the difference between CRC and CRC* determined by the XOR logic function to combine CRC and CRC*.

[0054] In some further embodiments, the processing device may compare the error check data (e.g., CRC’) of the modified data (e.g., M’) from operation 440 with the error check data (e.g., Figure 2("CRC" in the context) to determine whether an error has been introduced during the modification in operation 430. The error may be caused by any impairment that induces a state flip of the memory cells in the memory component 112 to the opposite state (e.g., from a '1' value to a '0' value, and vice versa). In some embodiments, the processing device may compare the error check data (e.g., CRC') updated from the error check data (e.g., CRC) of the original data (e.g., M) using incremental error check data (e.g., CRC*) with the error check data (e.g., CRC") calculated from the CRC operation of the modified data (e.g., M'). Based on the comparison, the processing device may determine whether the two error check data match. When comparing the two CRCs, the processing device may determine whether the values represented by the binary digits of each CRC are the same.

[0055] In response to determining that CRC' matches CRC", the processing device may determine that M' does not contain an error. Then, the processing device may store M' and the corresponding error check data (e.g., CRC'). When storing M', the processing device may associate M' with the received original data M. The processing device may use an identifier or metadata for the association. In this way, when the processing device receives a request to retrieve M from the host system 120, the processing device may access M' based on the association.

[0056] On the other hand, if CRC' does not match CRC", the processing device may determine that M' contains an error. Then, the processing device may perform operation 430 on a copy of the received data again as a corrective action. In some embodiments, the processing device may notify the host system 120 that M cannot be stored.

[0057] Figure 5 is a flowchart of an exemplary method 500 for detecting an error in data for a retrieval request according to some embodiments of the present invention. Method 500 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 500 is executed by Figure 1 the error detection component 113. Although shown in a particular order or sequence, unless otherwise specified, the order of the process may be modified. Thus, the described embodiments should be understood as merely examples, and the described process may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0058] In operation 510, the processing device receives retrieval data (e.g., Figure 3Request for M) in. At operation 520, the processing device retrieves another data associated with the requested data (e.g., Figure 3 M’ in) and error check data corresponding to the retrieved data. In some embodiments, the retrieved data (e.g., Figure 3 M’ in) may correspond to a modification of the data requested to be retrieved (e.g., Figure 3 M in). For example, the processing device may receive data (e.g., Figure 2 M in) from the host system 120 for storage and then receive a request to retrieve the data (e.g., Figure 3 M in) from the host system 120. However, in order to store the data (e.g., Figure 2 M in) from the host system 120, the processing device may modify (e.g., encrypt) the data (e.g., Figure 2 M in) from the host system 120 into modified data (e.g., Figure 2 M’ in) and store the modified data (e.g., Figure 2 M’ in) instead. Thus, when receiving a request to retrieve the data (e.g., Figure 3 M in) from the host system 120, the processing device first accesses the stored modified data (e.g., Figure 2 M’ in). As will be discussed below, the data received from the host system 120 (e.g., Figure 2 M in) may be different from the recovered data (e.g., Figure 3 M in) because the recovered data (e.g., Figure 3 M in) may contain errors.

[0059] In addition, at operation 520, the processing device may retrieve error check data (e.g., Figure 3 CRC’ in) for a CRC operation based on the retrieved data (e.g., M’). CRC’ may be stored together with M’ by being appended to M’. In some embodiments, both the retrieved data and the error check data may be in the form of binary data.

[0060] At operation 530, the processing device generates the requested data (e.g., Figure 3M). In some embodiments, the processing device can reverse the modification by modifying the retrieved data (e.g., M') back to the requested data (e.g., M) while maintaining the same data size. The processing device can determine how to modify the retrieved data (e.g., M') back based on the metadata associated with M'. For example, the processing device can identify the type of modification (e.g., encryption) performed on the data received from the host system 120 from the metadata M'. Then, the processing device can determine the operation (e.g., decryption) to undo or reverse the modification (e.g., encryption) based on the type of modification determined from the metadata M'.

[0061] At operation 540, the processing device generates error check data (e.g., Figure 3 CRC in) based on the retrieved error check data (e.g., CRC') and the difference between the data (e.g., M) and the retrieved data (e.g., M'). Similar to operation 440, the processing device can update the retrieved error check data (e.g., M') based on the combination of the retrieved data (e.g., M') and the data with the reversed modification for the retrieval request (e.g., M). The processing device can use incremental error check data (e.g., Figure 3 CRC^ in) to update the retrieved error check data (e.g., CRC'). For example, the processing device can generate incremental error check data (e.g., CRC^) based on the data with the reversed modification (e.g., M) and the retrieved data (e.g., M'). The processing device can use the XOR logic function to determine the difference between M and M' and apply the CRC operation to the difference to generate incremental error check data (e.g., CRC^). After determining the incremental error check data CRC^, the processing device can continue to generate the error check data (e.g., CRC) for the data with the reversed modification (e.g., M) by updating the retrieved error check data (e.g., CRC') with the incremental error check data (e.g., CRC^). For example, the processing device can combine the retrieved error check data (e.g., CRC') and the incremental error check data CRC^. The processing device can perform the XOR logic function on the two CRCs (e.g., CRC^ and CRC') for the combination. The updated error check data (e.g., CRC') will correspond to the error check data (e.g., CRC) for the data with the reversed modification (e.g., M).

[0062] At operation 550, the processing device may determine whether the inverted modified data (e.g., M) contains an error by comparing the generated error check data (e.g., CRC) with the error check data (e.g., CRC**) based on a CRC operation on the inverted modified data (e.g., M). For example, the processing device may compare the two CRCs and determine whether the two CRCs have the same value. In response to determining that CRC does not match CRC**, the processing device may determine that the inverted modified M contains an error. In some embodiments, the processing device may return to operation 530 to generate M again. In other embodiments, the processing device may notify the host system 120 of an error or failure in retrieving the requested data. On the other hand, the processing device may determine that CRC matches CRC**. In this case, the processing device determines that M does not contain an error.

[0063] At operation 560, the processing device provides the inverted modified data (e.g., M) to the host system 120 based on the request in response to determining that the inverted modified data does not contain an error.

[0064] In a further embodiment, the processing device may provide both the inverted modified data and the corresponding error check data to the host system 120. In response, the host system 120 may determine whether the received data from the processing device is the same as the data provided to the processing device for storage by comparing the received error check data with the error check data newly calculated using a CRC operation on the received data.

[0065] Figure 6 An example machine of a computer system 600 in which a set of instructions for causing a machine to execute any one or more of the methodologies discussed herein may be executed is described. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 the host system 120), which includes a memory subsystem (e.g., Figure 1 the memory subsystem 110), coupled to or utilizing the memory subsystem or available for performing operations of a controller (e.g., executing an operating system to perform operations corresponding to Figure 1 the error detection component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0066] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0067] Example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0068] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or one processor implementing another instruction set or multiple processors implementing a combination of instruction sets. The processing device 602 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 can further include a network interface device 608 to communicate over a network 620.

[0069] The data storage system 618 can include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more instruction sets 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 can also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, and the main memory 604 and the processing device 602 also constitute machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 can correspond to Figure 1 the memory subsystem 110.

[0070] In one embodiment, the instructions 626 include implementing a corresponding error detection component (e.g., Figure 1instructions for the functionality of the error detection component 113). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that is capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" should accordingly be understood to include (but not be limited to) solid-state memory, optical media, and magnetic media.

[0071] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived as a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0072] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may be described with reference to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0073] The present invention also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to the computer system bus.

[0074] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general-purpose systems may be used in conjunction with the programs in accordance with the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structure for various such systems will appear as set forth in the following description. Additionally, the present invention is not described with reference to any particular programming language. It should be understood that a variety of programming languages may be used to implement the teachings of the present invention described herein.

[0075] The present invention may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform a process according to the present invention. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read-only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0076] In the foregoing specification, embodiments of the present invention have been described with reference to specific example embodiments of the present invention. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present invention as set forth in the following claims. The specification and drawings should accordingly be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory system, comprising: A memory component; A processing device operably coupled to the memory component to: Receive a request to store first data; Receive the first data and first error check data, the first error check data being based on a cyclic redundancy check (CRC) operation on the first data; Generate second data by modifying the first data; Generate second error check data for the second data by using the first error check data and the difference between the first data and the second data; And Determine whether the second data contains an error by comparing the second error check data with error check data generated from the CRC operation on the second data.

2. The memory system according to claim 1, wherein, to generate the second error check data, the processing device: Updates the first error check data based on a combination of the first data and the second data; and Generates the second error check data by combining the first error check data and the updated first error check data.

3. The memory system according to claim 2, wherein, to update the first error check data, the processing device: Determines the difference between the first data and the second data; and Updates the first error check data by applying the CRC operation to the difference between the first data and the second data.

4. The memory system according to claim 1, wherein, to determine whether the second data contains the error, the processing device: Determines that the second data does not contain the error in response to determining that the second error check data matches the error check data generated from the CRC operation on the second data; and Determines that the second data contains the error in response to determining that the second error check data does not match the error check data generated from the CRC operation on the second data.

5. The memory system according to claim 4, the processing device further: Stores the second data in association with the second error check data in response to determining that the second data does not contain the error.

6. The memory system according to claim 1, wherein, to modify the first data, the processing device modifies the first data into the second data while maintaining the same data size.

7. A method for error detection, comprising: Receiving a request to store first data; Receiving the first data and first error check data, the first error check data being based on a cyclic redundancy check (CRC) operation on the first data; Generating second data by modifying the first data; Generating, by a processing device, second error check data for the second data by using the first error check data and the difference between the first data and the second data; And Determining whether the second data contains an error by comparing the second error check data with error check data generated from the CRC operation on the second data.

8. The method according to claim 7, wherein generating the second error check data comprises: updating the first error check data based on a combination of the first data and the second data; and generating the second error check data by combining the first error check data and the updated first error check data.

9. The method according to claim 8, wherein updating the first error check data comprises: determining the difference between the first data and the second data; and updating the first error check data by applying the CRC operation to the difference between the first data and the second data.

10. The method according to claim 7, wherein determining whether the second data contains the error comprises: determining that the second data does not contain the error in response to determining that the second error check data matches the error check data generated from the CRC operation on the second data; and determining that the second data contains the error in response to determining that the second error check data does not match the error check data generated from the CRC operation on the second data.

11. The method according to claim 10, further comprising: storing the second data in association with the second error check data in response to determining that the second data does not contain the error.

12. The method according to claim 7, wherein modifying the first data comprises modifying the first data to the second data while maintaining the same data size.

13. A method for error detection, comprising: receiving a request from a host system to retrieve first data; retrieving second data associated with the first data and second error check data of the second data, the second data corresponding to a modification of the first data, and the second error check data being based on a cyclic redundancy check (CRC) operation on the second data; generating the first data from the second data by reversing the modification; generating first error check data based on the second error check data and the difference between the first data and the second data; determining by a processing device whether the first data contains an error by comparing the first error check data with the error check data generated from the CRC operation on the first data; and providing the first data to the host system in response to determining that the first data does not contain the error.

14. The method according to claim 13, wherein generating the first error check data comprises: updating the second error check data based on a combination of the first data and the second data, the updated second error check data corresponding to the first error check data.

15. The method according to claim 14, wherein updating the second error check data comprises: determining the difference between the first data and the second data; and The second error check data is updated by combining the second error check data with error check data generated from the CRC operation on the difference between the first data and the second data.

16. The method according to claim 13, wherein determining whether the first data contains the error comprises: determining that the first data does not contain the error in response to determining that the first error check data matches the error check data generated from the CRC operation on the first data; and determining that the first data contains the error in response to determining that the first error check data does not match the error check data generated from the CRC operation on the first data.

17. The method according to claim 13, further comprising: notifying the host system of a failure to retrieve the first data in response to determining that the first data contains the error.

18. The method according to claim 13, wherein reversing the modification comprises modifying the second data back to the first data while maintaining the same data size.

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