Source driver and display device

Abstract

A source driver and a display device can be provided. The source driver includes a decoder and a buffer circuit. The decoder is configured to: receive image data and an activation signal, determine a target voltage based on the image data, and select at least one gamma line from a plurality of gamma lines for generating the target voltage. The plurality of gamma lines are configured to respectively transmit different gamma voltages. The buffer circuit includes a plurality of input terminals and is configured to be connected to the at least one selected gamma line and generate an output voltage based on at least one gamma voltage obtained from the at least one selected gamma line. The decoder can be further configured to select, according to the activation signal, a group of gamma lines including the at least one selected gamma line that will be connected to the plurality of input terminals of the buffer circuit during a conversion period of the buffer circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0082451, filed with the Korean Intellectual Property Office on Jul. 9, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a source driver and a display device, and more particularly, to a source driver for variably selecting a gamma voltage to be applied to an input terminal of a buffer circuit during a slew period of the buffer circuit and a display device including the source driver. Background art

[0004] Examples of display devices that can be used in electronic devices for displaying images, such as televisions (TVs), laptop computers, monitors, and mobile devices, include liquid crystal display (LCD) devices, organic light - emitting diode (OLED) display devices, etc. The display device may include a display panel including a plurality of pixels and a display driver for applying an electrical signal to the plurality of pixels, and the display device may implement an image according to the electrical signal. Recently, various studies have been conducted on ways to improve the performance of display devices, for example, in terms of resolution, slew rate, etc. Summary of the invention

[0005] Some example embodiments of the present inventive concept provide a source driver having improved operating characteristics.

[0006] Some example embodiments of the present inventive concept provide a display device having improved operating characteristics.

[0007] However, some example embodiments of the present inventive concept are not limited to the example embodiments set forth herein. The above and other aspects of the present inventive concept will become more apparent to those of ordinary skill in the art to which the present inventive concept pertains by referring to the detailed description of the example embodiments of the present inventive concept given below.

[0008] According to an exemplary embodiment of the present disclosure, a source driver includes a decoder and a buffer circuit. The decoder is configured to: receive image data and an activation signal, determine a target voltage based on the image data, and select at least one gamma line from a plurality of gamma lines for generating the target voltage. The plurality of gamma lines are configured to respectively transmit different gamma voltages. The buffer circuit includes a plurality of input terminals and is configured to be connected to the selected at least one gamma line. The buffer circuit is further configured to generate an output voltage based on at least one gamma voltage obtained from the selected at least one gamma line. The decoder may be further configured to select, according to the activation signal, a group of gamma lines including the selected at least one gamma line that will be connected to the plurality of input terminals of the buffer circuit during a transition period of the buffer circuit.

[0009] According to an exemplary embodiment of the present disclosure, a source driver includes a decoder and a buffer circuit. The decoder is configured to: receive image data and an activation signal, determine a target voltage based on the image data, receive a plurality of gamma voltages having different levels, and select a gamma voltage to be output from the plurality of gamma voltages based on the activation signal and the target voltage. The buffer circuit includes a plurality of input terminals to which the gamma voltage is applied and is configured to generate an output voltage based on the gamma voltage. The decoder may be further configured to: select a first voltage group during a first period from a first time point when a transition period of the buffer circuit starts to a second time point when the output voltage reaches a reference voltage. The first voltage group includes two or more gamma voltages having similar levels among the plurality of gamma voltages. And select a second voltage group during a second period from the second time point to a third time point when the output voltage reaches the target voltage. The second voltage group includes at least one gamma voltage among the plurality of gamma voltages for generating the target voltage.

[0010] According to an exemplary embodiment of the present disclosure, a display device includes: a display panel including a plurality of pixels and configured to display an image via the plurality of pixels; a source driver connected to a plurality of gamma lines that respectively transmit different gamma voltages, the source driver being configured to output a grayscale voltage to the plurality of pixels via a plurality of source lines; and a timing controller configured to output a control signal for controlling an operation of the source driver. The source driver may include a decoder and a buffer circuit. The decoder is configured to: receive image data and an activation signal from the timing controller, determine a target voltage based on the image data, and select at least one gamma line from the plurality of gamma lines for generating the target voltage. The buffer circuit includes a plurality of input terminals and is configured to be connected to the selected at least one gamma line. The buffer circuit is further configured to generate the grayscale voltage based on a target gamma voltage obtained from the selected at least one gamma line. The decoder may be further configured to select a group of gamma lines including the at least one gamma line to be connected to the plurality of input terminals during a transition period of the buffer circuit according to the activation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the inventive concept will become more apparent by describing in detail some exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the inventive concept.

[0013] Figure 2 is Figure 1 a block diagram of a data driving circuit.

[0014] Figure 3 illustrates Figure 2 a buffer circuit of

[0015] Figure 4a and Figure 4b illustrates a problem that may be caused by the resistance of a gamma line in the case of providing a plurality of inputs to the buffer circuit of Figure 2

[0016] Figure 5 illustrates a data driving circuit according to an exemplary embodiment of the inventive concept.

[0017] Figure 6 illustrates Figure 5 a structure of a decoder of

[0018] Figure 7 is a timing diagram for explaining an operation of a data driving circuit according to an exemplary embodiment of the inventive concept.​

[0019] Figure 8a and Figure 8b illustrates how to select gamma lines during a transition period of a cell buffer according to an exemplary embodiment of the inventive concept. Figure 7 during the transition period of the cell buffer of

[0020] Figure 9 illustrates regions classified according to a range of target gamma voltages according to an exemplary embodiment of the inventive concept.

[0021] Figure 10 illustrates a group of gamma lines selected for each target gamma voltage corresponding to the "Full DEC" region of Figure 9 during the transition period.

[0022] Figure 11 illustrates a group of gamma lines selected for each target gamma voltage corresponding to the "Half DEC" region of Figure 9 during the transition period.

[0023] Figure 12 illustrates a data driving circuit according to an exemplary embodiment of the inventive concept including a buffer circuit capable of receiving four input voltages.

[0024] Figures 13a to 13c illustrates the gamma lines selected during the transition period of the cell buffer of Figure 12 during the transition period.

[0025] Figure 14 illustrates a data driving circuit according to an exemplary embodiment of the inventive concept configured to receive an activation signal FS_EN generated based on an input clock signal.

[0026] Figure 15 is a timing diagram showing the operation of the data driving circuit of Figure 14 during the transition period.

[0027] Figure 16 illustrates a data driving circuit according to an exemplary embodiment of the inventive concept including an output control circuit.

[0028] Figure 17 is a timing diagram showing the operation of the data driving circuit of Figure 16 during the transition period.

[0029] Figure 18 illustrates a data driving circuit according to an exemplary embodiment of the inventive concept including a transition detection circuit.

[0030] Figure 19 is a timing diagram showing the operation of the data driving circuit of Figure 18 during the transition period. DETAILED DESCRIPTION

[0031] Although the terms "same" or "identical" are used in the description of the exemplary embodiments, it should be understood that there may be a certain degree of imprecision. Thus, when an element or a value is referred to as being the same as or similar to another element or another value, it should be understood that the element or value is the same as or similar to the other element or value within the desired manufacturing or operating tolerances (e.g., ±10%).

[0032] When the terms "about" or "substantially" are used in connection with a numerical value in this specification, the associated numerical value is intended to include manufacturing or operating tolerances around the recited numerical value (e.g., ±10%). Further, when the words "substantially" and "about" are used in connection with a geometric shape, it is intended that the precision of the geometric shape is not required, but the latitude of the shape is within the scope of the present disclosure.

[0033] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the inventive concept. Figure 2 is Figure 1 a block diagram of a data driving circuit. Figure 3 shows Figure 2 a buffer circuit of.

[0034] Referring to Figure 1 , the display device 10 may include a display panel 100, a data driving circuit 200, a gate driving circuit 300, a timing controller 400, and a memory 500.

[0035] In the display panel 100, a plurality of data lines 290 and a plurality of gate lines 310 are arranged to intersect, and pixels P are arranged in a matrix form at the intersection points between the data lines 290 and the gate lines 310. The display panel 100 may be a flat display panel, for example, a thin film transistor liquid crystal display (TFT LCD) panel, a plasma display panel (PDP), a light emitting diode (LED) display panel, or an organic LED display panel, but the inventive concept is not limited thereto.

[0036] Each pixel P is connected to one data line 290 and one gate line 310. The pixel P may be electrically connected to the data line 290 in response to a gate pulse input thereto via the gate line 310, and thus may receive a data voltage from the data line 290. The display operation of the display panel 100 may involve the operations of the data driving circuit 200 and the gate driving circuit 300 under the control of the timing controller 400.

[0037] During a display operation, the data driving circuit 200 converts digital video data RGB into a data voltage for a display image according to a data timing control signal DDC applied thereto from the timing controller 400, and supplies the data voltage to the data line 290. The data driving circuit 200 may also be referred to as a source driver 200, and the data line 290 may also be referred to as a source line 290.

[0038] During a display operation, the gate driving circuit 300 generates gate pulses for a display image according to a gate control signal GDC, and sequentially supplies the gate pulses to the gate line 310 in a line-by-line manner.

[0039] The timing controller 400 generates a data control signal DDC and a gate control signal GDC based on timing signals (e.g., a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE). The data control signal DDC is used to control the operation timing of the data driving circuit 200, and the gate control signal GDC is used to control the operation timing of the gate driving circuit 300.

[0040] During a display operation, the timing controller 400 modulates digital video data RGB for implementing an image based on data stored in the memory 500, and transmits the modulated digital video data RGB to the data driving circuit 200.

[0041] In some example embodiments, the display device 10 may display an image in units of frames. The duration of displaying a single frame may be defined as a vertical period, and the vertical period may be determined by the scanning rate of the display device 10. For example, when the scanning rate of the display device 50 is 60 Hz, the vertical period may be 1 / 60 second, i.e., approximately 16.7 milliseconds.

[0042] During a single vertical period, the gate driving circuit 300 may scan each gate line 310. The duration for which the gate driving circuit 300 scans each gate line 310 may be defined as a horizontal period. During a single horizontal period, the data driving circuit 200 may input a grayscale voltage to the pixel P. The grayscale voltage may be a voltage output by the data driving circuit 200 based on the digital video data RGB, and the brightness of the pixel P may be determined by the grayscale voltage.

[0043] Referring to Figure 2 and Figure 3 According to an example embodiment of the inventive concept, the data driving circuit 200 may include a level shifter 210, a latch circuit 220, a decoder (DEC) 230, and a buffer circuit 240. In some example embodiments, the buffer circuit 240 may include a plurality of unit buffers UB.

[0044] The level shifter 210 may receive digital video data RGB and may control the operation timing of a plurality of sampling circuits included in the latch circuit 220 in response to a timing control signal DDC. The timing control signal DDC may be a signal having a desired (or, predetermined) period.

[0045] The latch circuit 220 may sample and store the digital video data RGB according to the shift order from the level shifter 210. The latch circuit 220 may output the sampled image data DQ to the decoder 230. The decoder 230 may include: a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the decoder 230 may be a digital-to-analog converter.

[0046] In some example embodiments, the latch circuit 220 may include a sampling circuit configured to sample data and a holding latch configured to store the sampled data.

[0047] The decoder 230 may receive a plurality of gamma voltages VG, an activation signal FS_EN, and the image data DQ. In some example embodiments, the number of gamma voltages VG may be determined by the number of bits of the image data DQ. For example, if the image data DQ is 8-bit data, the number of gamma voltages VG may be 256 or less. In another example, if the image data DQ is 10-bit data, the number of gamma voltages VG may be 1024 or less. For convenience, hereinafter the image data DQ will be described as 8-bit data, and hereinafter the number of gamma voltages VG will be described as 256.

[0048] The buffer circuit 240 may include a unit buffer UB implemented as, for example, an operational amplifier, and the unit buffer UB may be connected to the data lines 290, respectively. As Figure 3As shown, each unit buffer UB may include a plurality of input terminals. The decoder 230 may select at least some of the gamma voltages VG based on the image data DQ, and may provide the selected gamma voltages VG as input voltages VL and VH to the input terminals of each unit buffer UB. Each unit buffer UB may output the average value of the input voltages VL and VH that have been provided from the decoder 230 as a grayscale voltage VOUT to the data line 290. Therefore, in the case where the image data is 8-bit data, even if the number of gamma lines to which the gamma voltage VG is input to the decoder 230 is less than 256, each unit buffer can still output one of a total of 256 grayscale voltages.

[0049] The components 210, 220, 230, and 240 included in the data driving circuit 200 are not particularly limited to Figure 2 the exemplary embodiments of, but may be changed.

[0050] Figure 4a and Figure 4b illustrates a problem that may be caused by the resistance of the gamma lines in the case of providing a plurality of inputs to Figure 2 the buffer circuit.

[0051] Referring to Figure 4a , in the case where the target voltage of the unit buffer UB1 is the output voltage VS79 corresponding to the average value of the gamma voltages VG78 and VG80, the gamma lines to which the gamma voltages VG78 and VG80 are applied are selected, and then the gamma voltages VG78 and VG80 are applied as inputs to the unit buffer UB1 via the selected gamma lines. In this case, the resistances of the plurality of gamma lines are in parallel, and thus, compared with the case of applying the input of the buffer via a single gamma line, the resistance of the plurality of gamma lines can be reduced. Therefore, the conversion delay caused by the noise from the gamma lines can be reduced.

[0052] Similarly, in the case where the target voltage of the unit buffer UB2 is the output voltage VS81 corresponding to the average value of the gamma voltage VG80 and the gamma voltage VG82, the gamma line to which the gamma voltage VG80 is applied and the gamma line to which the gamma voltage VG82 is applied are selected, and then the gamma voltages VG80 and VG82 are applied as inputs to the unit buffer UB2 via the selected gamma lines. Therefore, the conversion delay caused by the noise from the gamma lines can be reduced.

[0053] In contrast, when the target voltage of the unit buffer UB3 is the output voltage VS80 corresponding to the gamma voltage VG80, the gamma voltage VG80 is applied as multiple inputs to the unit buffer UB3 via a single gamma line to which the gamma voltage VG80 is applied. In this case, compared with the case where the gamma voltage VG80 is transmitted via multiple gamma lines, the resistance of the single gamma line increases. Therefore, due to the noise from the gamma line, conversion delay occurs. In other words, compared with the previous case where the gamma voltage VG80 is transmitted via multiple gamma lines, the conversion delay increases.

[0054] Refer to Figure 4b , when the target voltage of the unit buffer UB3 is the output voltage VS0 corresponding to the gamma voltage VG0, a gamma line for applying the same gamma voltage VG0 can be additionally provided to reduce the gamma line resistance. However, in this case, since an additional circuit is provided, the size of the entire chip increases.

[0055] Figure 5 FIG. shows a data driving circuit according to an exemplary embodiment of the inventive concept. Figure 6 FIG. shows Figure 5 the structure of the decoder of

[0056] Refer to Figure 5 , the decoder 230 may receive the image data DQ and the activation signal FS_EN, may determine a target gamma voltage corresponding to the output voltage VS of the unit buffer UB based on the image data DQ, may select a gamma line corresponding to the target gamma voltage, and may connect the selected gamma line to two input terminals of the unit buffer UB. That is, the gamma voltage applied to the gamma line selected by the decoder 230 may be input to the unit buffer UB as the input voltages VH and VL. The decoder 230 may include: a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0057] In some exemplary embodiments, the unit buffer UB may be implemented as an operational amplifier and may have a negative feedback structure in which the output terminal and the inverting input terminal of the unit buffer UB are connected. For example, as Figure 5As shown, the cell buffer UB may include two non-inverting input terminals, and input voltages VL and VH having different levels from each other may be input to the non-inverting input terminals. For example, the output voltage VS of the cell buffer UB may be determined as the average value of the input voltages VL and VH. The output voltage VS of the cell buffer UB may be a gradation voltage to be input to at least one of the plurality of data lines 290 included in the display panel 100. Unless otherwise specified, the term "input terminal of the cell buffer" as used herein may refer to a non-inverting input terminal.

[0058] Referring to Figure 6 , the decoder 230 according to an exemplary embodiment of the present disclosure may include a switch for determining whether to transmit a voltage to the gamma line. In the case where the cell buffer UB includes two gamma voltage input terminals (+) as shown in Figure 5 , the terminals for the input voltages VL and VH for the cell buffer UB may be connected to the two gamma voltage input terminals (+) of the cell buffer UB, and each gamma line may be connected to two switches. In some exemplary embodiments, the switch of the decoder 230 may be implemented as a transfer transistor that is gated according to a control signal from the timing controller 400.

[0059] The decoder 230 may select a gamma voltage to be input during the transition period of the cell buffer UB based on the activation signal FS_EN, and may turn on the switch connected to the selected gamma voltage. This will be described below with reference to Figures 7 to 8b this.

[0060] Figure 7 is a timing diagram for illustrating the operation of the data driving circuit according to an exemplary embodiment of the present inventive concept. Figure 8a and Figure 8b show how to select a gamma line during the transition period of the cell buffer in Figure 7 .

[0061] Referring to Figures 7 to 8b , the data driving circuit 200 may select a gamma line to be electrically connected to the cell buffer UB during the transition period of the cell buffer UB based on the activation signal FS_EN. In some exemplary embodiments, the activation signal FS_EN may be generated and output by the timing controller 400. Referring to Figure 7, the first target switch SW_TG1 and the second target switch SW_TG2 are defined as switches connected to the gamma lines to which the target gamma voltage VG_TG for generating the target voltage VTG is applied, and the adjacent switches SW_ADJ are defined as switches connected to the gamma lines adjacent to the gamma lines to which the target gamma voltage VG_TG is applied. In some example embodiments, the first target switch SW_TG1 and the second target switch SW_TG2 may be connected to the same gamma line or different gamma lines.

[0062] The gamma voltage may be applied to the input terminal of the cell buffer UB during a period from a first time point t1 to a fourth time point t4. That is, the period from the first time point t1 to the fourth time point t4 is defined as the output voltage generation period of the cell buffer UB. In addition, the transition period of the cell buffer UB is defined as the period from the first time point t1 to the third time point t3. The transition period (t1 to t3) of the cell buffer UB may be defined as the period from the time point when the output voltage VS of the cell buffer UB starts to increase to the time point when the output voltage VS of the cell buffer UB reaches the target voltage VTG. The output voltage generation period (t1 to t4) of the cell buffer UB may include the transition period (t1 to t3) of the cell buffer UB.

[0063] The operation of the cell buffer UB for generating the output voltage VS may start at the first time point t1. That is, at the first time point t1, the decoder 230 may select the gamma line to be connected to the cell buffer UB, thereby applying a desired (or, predetermined) voltage to the input terminal of the cell buffer UB.

[0064] The transition operation of the cell buffer UB may be performed during a period from the first time point t1 to the third time point t3. That is, at the first time point t1, a desired (or, predetermined) voltage is applied to the input terminals VL and VH of the cell buffer UB, so that the output voltage VS starts to increase, and the third time point t3 is defined as the time point when the output voltage VS reaches the target voltage VTG.

[0065] The transition period of the cell buffer UB may include a first period (t1 to t2) and a second period (t2 to t3). The first period (t1 to t2) is defined as the period from the first time point t1 when the output voltage VS starts to increase to the second time point t2 when the output voltage VS of the cell buffer UB reaches a desired (or, predefined) reference voltage VREF, and the second period (t2 to t3) is defined as the period from the second time point t2 when the output voltage VS of the cell buffer UB reaches the reference voltage VREF to the third time point t3 when the output voltage VS of the cell buffer UB reaches the target voltage VTG. For example, the reference voltage VREF may be set to up to 90% of the target voltage VTG.

[0066] During a first period (t1 to t2), the decoder 230 may turn on the first target switch SW_TG1 and the adjacent switch SW_ADJ in response to an activation signal FS_EN having a logic high level. Accordingly, the first target gamma voltage VG_TG and the adjacent gamma voltage VG_ADJ may be applied to the cell buffer UB as input voltages VH and VL.

[0067] At a second time point t2, the activation signal FS_EN may switch to a logic low level. The second time point t2 may be a time when the output voltage VS of the cell buffer UB reaches a reference voltage VREF.

[0068] During a second period (t2 to t3), the decoder 230 may turn on the first target switch SW_TG1 and the second target switch SW_TG2 in response to an activation signal FS_EN having a logic low level. Accordingly, the first target gamma voltage VG_TG and the second target gamma voltage VG_TG may be applied to the cell buffer UB as input voltages VH and VL.

[0069] The output voltage VS of the cell buffer UB reaches a target voltage VTG at a third time point t3. Then, the cell buffer UB may transmit the output voltage VS as high as the target voltage VTG to the display panel 100 via the data line 290, and the display panel 100 may display an image based on the gray scale voltage.

[0070] Since the adjacent gamma voltage VG_ADJ instead of the second target gamma voltage VG_TG is provided as an input voltage to the cell buffer UB, the gamma line resistance during the first period (t1 to t2) may be reduced. Accordingly, according to some example embodiments of the present disclosure, the conversion period of the cell buffer UB may be shortened. Since the adjacent gamma voltage VG_ADJ (instead of the gamma voltage corresponding to the target voltage VTG) is provided, an exact target voltage VTG may not be achieved. However, since the output voltage VS first rises to a reference voltage VREF close to the target voltage VTG during the first period (t1 to t2) and then rises to the target voltage VTG by applying the second target gamma voltage VG_TG during the second period (t2 to t3), an exact gray scale voltage may be generated and the conversion period of the cell buffer UB may be shortened.

[0071] Figure 7 Two gamma voltages corresponding to the target voltage VTG (e.g., the first target gamma voltage VG_TG and the second target gamma voltage VG_TG) are shown, but the inventive concept is not limited thereto. In some example embodiments, a single target gamma voltage may be applied via a single gamma line, as will be described below with reference to Figure 8a andFigure 8b described

[0072] Referring Figure 8a and Figure 8b In the first time period (t1 to t2), the decoder 230 may turn on the switches of the gamma lines to which the target gamma voltage VG_TG and the adjacent gamma voltage VG_ADJ are applied, and may apply the target gamma voltage VG_TG and the adjacent gamma voltage VG_ADJ as input voltages to the cell buffer UB. Thereafter, in the second time period (t2 to t3), the decoder 230 may control the switch of the gamma line to which the target gamma voltage VG_TG is applied, so that the two input terminals of the cell buffer UB can be connected to the gamma line to which the target gamma voltage VG_TG is applied. That is, in the first time period (t1 to t2), by turning on the first target switch SW_TG1 and the adjacent switch SW_ADJ, the target gamma voltage VG_TG and the adjacent gamma voltage VG_ADJ may be applied to the input terminals of the cell buffer UB. In the second time period (t2 to t3), by turning on the first target switch SW_TG1, the target gamma voltage VG_TG may be input to the plurality of input terminals of the cell buffer UB.

[0073] Figure 9 shows regions classified according to the range of the target gamma voltage in an exemplary embodiment according to the inventive concept. Figure 10 shows the gamma line groups selected for each target gamma voltage during the conversion period for Figure 9 the "Full DEC" region corresponding to Figure 11 shows the gamma line groups selected for each target gamma voltage during the conversion period for Figure 9 the "Half DEC" region corresponding to

[0074] Referring Figure 9, the criteria for selecting gamma rays and the configuration of gamma rays can be changed according to the desired gray-scale voltage. For example, if the target gamma voltage VG_TG is defined as the gamma voltage corresponding to the desired gray-scale voltage, the target gray-scale voltage corresponding to the target gamma voltage VG_TG ranging from gamma voltage VG0 to gamma voltage VG31 or from gamma voltage VG224 to gamma voltage VG255 can be defined as the "Full DEC" region, and all gamma rays having the target gamma voltage VG_TG included in the "Full DEC" region can be configured to be connected to the input terminal of the cell buffer UB via the decoder 230. In contrast, the target gray-scale voltage corresponding to the target gamma voltage VG_TG ranging from gamma voltage VG32 to gamma voltage VG223 can be defined as the "Half DEC" region, and gamma rays having the target gamma voltage VG_TG included in the "Half DEC" region may selectively exist. For example, among the gamma rays to which the target gamma voltage VG_TG included in the "Half DEC" region is applied, it is assumed that there are gamma rays to which the even-numbered gamma voltages VG32, VG34, …, VG220 and VG222 are applied, but there are no gamma rays to which the odd-numbered gamma voltages VG33, VG35, …, VG221 and VG223 are applied, and the interpolation method can be applied.

[0075] Refer to Figure 10 , when the target gamma voltage VG_TG is included in the "Full DEC" region, the gamma rays selected when the activation signal FS_EN has a logic high level (e.g., during the first period) may be different from the gamma rays selected when the activation signal FS_EN has a logic low level (e.g., during the second period). For example, if the target gamma voltage VG_TG is gamma voltage VG0, the gamma rays to which gamma voltages VG0 and VG1 are applied can be selected, and then gamma voltages VG0 and VG1 can be applied as inputs to the cell buffer UB during the first period, while only the gamma ray to which gamma voltage VG0 is applied can be selected during the second period. Therefore, gamma voltage VG0 can be input to the input terminal of the cell buffer UB during the first and second periods. The same method can be applied to the cases where the target gamma voltage VG_TG is gamma voltage VG1, gamma voltage VG254, or gamma voltage VG255.

[0076] Refer to Figure 11 , when the target gamma voltage VG_TG is included in the "Half DEC" region, the gamma rays selected during the first period may be the same as or different from the gamma rays selected during the second period.

[0077] For example, if the target gamma voltage VG_TG is the gamma voltage VG128 or the gamma voltage VG130 (e.g., an even-numbered gamma voltage), there are gamma lines to which an even-numbered gamma voltage is applied. Thus, the gamma voltages applied as inputs to the cell buffer UB in the first period and the second period may be different, as described above with reference to Figure 10 described.

[0078] In contrast, if the target gamma voltage VG_TG is the gamma voltage VG129 or the gamma voltage VG131 (e.g., an odd-numbered gamma voltage), there are no gamma lines to which an odd-numbered gamma voltage is applied. Thus, a gray-scale voltage is generated by interpolation. That is, by configuring the gamma voltages applied in the first period and the second period to be the same, problems (e.g., an increase in the resistance of the gamma line) that may occur when there are multiple target gamma voltages VG_TG for generating a gray-scale voltage and the multiple target gamma voltages VG_TG are to be applied via a single gamma line can be prevented.

[0079] Figure 12 A data driving circuit including a buffer circuit capable of receiving four input voltages according to an exemplary embodiment of the inventive concept is shown, Figures 13a to 13c is shown during Figure 12 the transition period of the cell buffer of.

[0080] Referring to Figures 12 to 13c , the cell buffer UB' may be configured to include three or more non-inverting input terminals. As Figure 12 shown, the cell buffer UB' may include four non-inverting input terminals configured to receive four input voltages V1, V2, V3, and V4, respectively. In this case, the adjacent gamma voltage VG_ADJ may change during the first period of the transition period of the cell buffer UB'. For example, as Figure 13a shown, the decoder 230 may select, during the first period, as many gamma lines to which the adjacent gamma voltage VG_ADJ is applied as the number of gamma lines to which the target gamma voltage VG_TG is applied, and may connect the selected gamma lines to the input terminals of the cell buffer UB'. In another example, as Figure 13b shown, the decoder 230 may select a different number of gamma lines to which the adjacent gamma voltage VG_ADJ is applied than the number of gamma lines to which the target gamma voltage VG_TG is applied, and may connect the selected gamma lines to the input terminals of the cell buffer UB'. In still another example, as Figure 13cAs shown, the decoder 230 may select multiple adjacent gamma lines during a first period. That is, the decoder 230 may select the gamma lines to which the target gamma voltage VG_TG, the first adjacent gamma voltage VG_ADJ1, and the second adjacent gamma voltage VG_ADJ2 are applied, and then may connect the selected gamma lines to the input terminals of the cell buffer UB'. In this case, the number of selected gamma lines is not particularly limited and may be changed.

[0081] Figure 14 FIG. shows a data driving circuit configured to receive an activation signal FS_EN generated based on an input clock signal according to an exemplary embodiment of the inventive concept. Figure 15 is a timing diagram showing Figure 14 the operation of the data driving circuit.

[0082] Referring to Figure 14 and Figure 15 , the data driving circuit 200 may receive a trigger signal CLK_INPUT for triggering the cell buffer UB to generate an output voltage VS, an activation signal FS_EN defining a first period and a second period, and image data DQ, may select gamma lines based on the trigger signal CLK_INPUT, the activation signal FS_EN, and the image data DQ, and may connect the selected gamma lines to the input terminals of the cell buffer UB.

[0083] In some exemplary embodiments, the trigger signal CLK_INPUT may be a signal that causes the cell buffer UB to generate an output voltage VS, and the decoder 230 may start selecting gamma lines in response to a rising edge of the trigger signal CLK_INPUT. In some exemplary embodiments, the activation signal FS_EN may be controlled based on the trigger signal CLK_INPUT. That is, the activation signal FS_EN may switch to a logic high level in response to a rising edge of the trigger signal CLK_INPUT and then may remain at the logic high level for a desired (or, predefined) duration. The subsequent operation of the data driving circuit 200 according to the activation signal FS_EN may be substantially the same as the operation described above with reference to Figure 7 FIG.

[0084] Figure 16 FIG. shows a data driving circuit including an output control circuit according to an exemplary embodiment of the inventive concept, Figure 17 is a timing diagram showing Figure 16 the operation of the data driving circuit.

[0085] Referring to Figure 16 and Figure 17, the data driving circuit 200 may further include an output control circuit "OTHZ" 250. In some example embodiments, the output control circuit 250 may be connected to an output terminal of the cell buffer UB, and may include a switch for outputting the output voltage VS of the cell buffer UB to the display panel 100. That is, the output control circuit 250 may determine whether to turn on or off the switch according to the output activation signal OTHZ_EN. For example, during a period when the output activation signal OTHZ_EN has a logic low level, the switch may be turned on so that the output voltage VS can be output to the display panel 100, and during a period when the output activation signal OTHZ_EN has a logic high level, the switch may be turned off or disconnected so that the output voltage VS is not output to the display panel 100.

[0086] In some example embodiments, the activation signal FS_EN may be activated during a period when the output activation signal OTHZ_EN has a logic high level. In this case, the output voltage VS may be maintained at its initial level during a period when the switch of the output control circuit 250 is turned off (when the activation signal FS_EN is activated) (for example, during a period from a first time point t1 to a second time point t2), and after the second time point t2 when the switch of the output control circuit 250 is turned on, a transition period may be generated. In this case, noise generated during the process of inputting the first target gamma voltage VG_TG and the adjacent gamma voltage VG_ADJ to the cell buffer UB during the period from the first time point t1 to the second time point t2 is not reflected, and the output voltage VS starts to increase after the input voltage of the cell buffer UB rises to a desired (or, predetermined) level. Therefore, the transition period (for example, the period from the second time point t2 to the time point tA when the output voltage VS reaches the target voltage VTG) can be shortened. Compared with the Figure 7 embodiment in which the length of the transition period (for example, the first transition period duration ΔT1 as shown in Figure 17 ) when the output voltage VS increases and reaches the target voltage VTG, the length of the transition period (for example, the second transition period duration ΔT2) according to the Figure 17 example embodiment when the output voltage VS starts to increase and reaches the target voltage VTG after the second time point t2 according to the output activation signal OTHZ_EN can be further shortened.

[0087] Figure 18 FIG. shows a data driving circuit including a transition detection circuit according to an example embodiment of the inventive concept. Figure 19 is a timing diagram showing the operation of the Figure 18 data driving circuit.

[0088] Referring to Figure 18 and Figure 19, According to some example embodiments of the inventive concept, the data driving circuit 200 may further include a transition detection circuit 270. The transition detection circuit may track the output voltage of the buffer circuit 240. For example, the transition detection circuit 270 may track the transition operation performed by the unit buffer UB and may output a detection signal DET based on the tracking result. In some example embodiments, the detection signal DET may include information related to the time when the output voltage VS of the unit buffer UB reaches the reference voltage VREF. For example, as Figure 19 shown, the detection signal DET may switch to a logic high level at the start of the transition operation of the unit buffer UB (e.g., when the output voltage VS of the unit buffer UB starts to increase), and then may switch to a logic low level when the output voltage VS reaches the reference voltage VREF. That is, the above operations performed according to the Figure 7 activation signal FS_EN may be performed according to the detection signal DET. In other words, the operation of the data driving circuit 200 according to the Figure 19 detection signal DET may be the same as or substantially the same as the operation of the data driving circuit 200 according to the Figure 7 activation signal FS_EN.

[0089] Although the inventive concept has been specifically shown and described with reference to some example embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, the example embodiments described above should be considered only in a descriptive sense and not for purposes of limitation.

Claims

1. A source driver, the source driver comprising: A decoder configured to: Receive image data and an activation signal, Determine a target voltage based on the image data, and Select at least one gamma line from a plurality of gamma lines for generating the target voltage, the plurality of gamma lines being configured to transmit different gamma voltages respectively; And A buffer circuit, the buffer circuit including a plurality of input terminals, the buffer circuit being configured to be connected to the selected at least one gamma line, the buffer circuit further being configured to generate an output voltage based on at least one gamma voltage obtained from the selected at least one gamma line, Wherein, the decoder is further configured to: select a group of gamma lines including the selected at least one gamma line that will be connected to the plurality of input terminals of the buffer circuit during a transition period of the buffer circuit according to the activation signal, Wherein, the transition period includes a first period and a second period, the first period being a period from a first time point when the transition period starts to a second time point when the output voltage of the buffer circuit reaches a reference voltage, and the second period being a period from the second time point to a third time point when the output voltage of the buffer circuit reaches the target voltage.

2. The source driver according to claim 1, wherein, The decoder is further configured to select the group of gamma lines including two adjacent gamma lines from the plurality of gamma lines.

3. The source driver according to claim 2, wherein, The decoder is further configured to select the group of gamma lines during the first period and select the at least one gamma line for generating the target voltage during the second period.

4. The source driver according to claim 2, wherein, The decoder is further configured to determine two or more gamma lines among the plurality of gamma lines that will be selected during the first period and two or more gamma lines among the plurality of gamma lines that will be selected during the second period based on the activation signal and the target voltage.

5. The source driver according to claim 4, wherein The decoder is further configured to: if the target voltage is higher than a first level or lower than a second level, select a target gamma line to which a target gamma voltage for generating the target voltage is applied and an adjacent gamma line adjacent to the target gamma line during the first period, and only select the target gamma line during the second period.

6. The source driver according to claim 4, wherein The decoder is further configured to: if the target voltage is between the first level and the second level, determine two or more gamma lines among the plurality of gamma lines that will be selected during the first period and two or more gamma lines among the plurality of gamma lines that will be selected during the second period based on whether there is a gamma line to which a target gamma voltage for generating the target voltage is applied among the plurality of gamma lines.

7. The source driver according to claim 6, wherein, The decoder is further configured to: if there is a gamma line to which the target gamma voltage for generating the target voltage is applied, select the gamma line as the target gamma line and adjacent gamma lines adjacent to the target gamma line during the first period, and select the target gamma line during the second period, and The decoder is further configured to: if there is no gamma line to which the target gamma voltage for generating the target voltage is applied, select the same multiple gamma lines for generating the target voltage from the multiple gamma lines during the first period and the second period.

8. The source driver according to claim 2, wherein the source driver further comprises: An output switch, the output switch is connected to the output terminal of the buffer circuit, and the output switch is configured to be turned on after the conversion period of the buffer circuit according to a switch activation signal, and output the output voltage of the buffer circuit to the outside of the source driver.

9. The source driver according to claim 2, wherein the source driver further comprises: A conversion detection circuit, the conversion detection circuit is configured to track the output voltage of the buffer circuit, wherein the decoder is further configured to receive a detection signal output by the conversion detection circuit as the activation signal.

10. A source driver, the source driver comprising: A decoder, the decoder is configured to: Receive image data and an activation signal, Determine a target voltage based on the image data, Receive a plurality of gamma voltages with different levels, and Select a gamma voltage to be output from the plurality of gamma voltages based on the activation signal and the target voltage; And A buffer circuit, the buffer circuit includes a plurality of input terminals to which the gamma voltage is applied, and the buffer circuit is configured to generate an output voltage based on the gamma voltage, wherein the decoder is further configured to: Select a first voltage group during a first period from a first time point when the conversion period of the buffer circuit starts to a second time point when the output voltage reaches a reference voltage, the first voltage group includes two or more gamma voltages with similar levels among the plurality of gamma voltages, and Select a second voltage group during a second period from the second time point to a third time point when the output voltage reaches the target voltage, the second voltage group includes at least one gamma voltage for generating the target voltage among the plurality of gamma voltages.

11. The source driver according to claim 10, wherein, The first period is defined as a period when the activation signal is at a logic high level, The second period is defined as a period when the activation signal is at a logic low level, and The decoder is further configured to select the first voltage group or the second voltage group based on the logic level of the activation signal.

12. The source driver according to claim 10, wherein, The decoder is further configured to: if the target voltage is lower than the first voltage or higher than the second voltage, receive the gamma voltage corresponding to the target voltage among the plurality of gamma voltages, and select different gamma voltages as the first voltage group and the second voltage group, and The decoder is further configured to: if the target voltage is between the first voltage and the second voltage, receive at least one gamma voltage for generating the target voltage, and select the same or different gamma voltages as the first voltage group and the second voltage group.

13. The source driver according to claim 10, wherein, The decoder is further configured to: if the target voltage is lower than the first voltage or higher than the second voltage and the gamma voltage corresponding to the target voltage is received among the plurality of gamma voltages, select different gamma voltages as the first voltage group and the second voltage group, and The decoder is further configured to: if the target voltage is between the first voltage and the second voltage and the gamma voltage corresponding to the target voltage is not received among the plurality of gamma voltages, select the same gamma voltage as the first voltage group and the second voltage group.

14. The source driver according to claim 10, the source driver further comprising: An output switch, the output switch is connected to the output terminal of the buffer circuit, and the output switch is configured to be turned on after the second period according to the switch activation signal, and output the output voltage of the buffer circuit.

15. The source driver according to claim 10, the source driver further comprising: A conversion detection circuit, the conversion detection circuit is configured to track the output voltage of the buffer circuit, wherein the decoder is further configured to receive the detection signal output by the conversion detection circuit as the activation signal.

16. A display device, the display device comprising: A display panel, the display panel includes a plurality of pixels and is configured to display an image via the plurality of pixels; A source driver, the source driver is connected to a plurality of gamma lines that respectively transmit different gamma voltages, and the source driver is configured to output a gray-scale voltage to the plurality of pixels via a plurality of source lines; And A timing controller, the timing controller is configured to output a control signal for controlling the operation of the source driver, wherein the source driver includes: A decoder, the decoder is configured to: Receive image data and an activation signal from the timing controller, Determine a target voltage based on the image data, and Select at least one gamma line for generating the target voltage from the plurality of gamma lines, and A buffer circuit, the buffer circuit includes a plurality of input terminals, the buffer circuit is configured to be connected to the selected at least one gamma line, and the buffer circuit is further configured to generate the gray-scale voltage based on the target gamma voltage obtained from the selected at least one gamma line, and Wherein, the decoder is further configured to select, according to the activation signal, a gamma line group including the at least one gamma line to be connected to the plurality of input terminals during a transition period of the buffer circuit. Wherein, the transition period includes a first period and a second period. The first period is a period from a first time point when the transition period starts to a second time point when the gray-scale voltage of the buffer circuit reaches a reference voltage. The second period is a period from the second time point to a third time point when the gray-scale voltage of the buffer circuit reaches the target voltage.

17. The display device according to claim 16, wherein, The decoder is further configured to: During the first period, select a first gamma line group including a plurality of adjacent gamma lines from the plurality of gamma lines, and During the second period, select a second gamma line group including the at least one gamma line for generating the target voltage from the plurality of gamma lines.

18. The display device according to claim 16, wherein, The decoder is further configured to: if the target voltage is higher than a first voltage or lower than a second voltage, select a target gamma line to which the target gamma voltage for generating the target voltage is applied and an adjacent gamma line adjacent to the target gamma line during the first period, and only select the target gamma line during the second period, and The decoder is further configured to: if the target voltage is between the first voltage and the second voltage, determine the gamma lines to be selected during the first period and the gamma lines to be selected during the second period from the plurality of gamma lines based on whether there is a target gamma line to which the target gamma voltage for generating the target voltage is applied.

19. The display device according to claim 18, wherein, The decoder is further configured to: if there is a target gamma line to which the target gamma voltage for generating the target voltage is applied, select the target gamma line and the adjacent gamma line during the first period and only select the target gamma line during the second period, and The decoder is further configured to: if there is no target gamma line to which the target gamma voltage for generating the target voltage is applied, select the same two or more gamma lines for generating the target voltage from the plurality of gamma lines during the first period and the second period.

20. The display device according to claim 16, wherein, The timing controller is configured to: Generate a trigger signal that triggers the output of the gray-scale voltage, and Output the activation signal, the activation signal switching to a logic high level in response to the rising edge of the trigger signal, and The decoder is further configured to select the gamma line group based on the logic level of the activation signal.

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