Semiconductor device manufacturing methods and semiconductor devices

Abstract

A method for manufacturing a semiconductor device is proposed. A silicon carbide (SiC) semiconductor body (102) is provided. Ions are introduced into the SiC semiconductor body (102) via a first surface (108) of the SiC semiconductor body (102) by at least one ion implantation process. Subsequently, a SiC device layer (110) is formed on the first surface (108) of the SiC semiconductor body (102). A semiconductor device element is formed in or on the SiC device layer (110).

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing semiconductor devices, and more specifically, to a method for manufacturing semiconductor devices in a silicon carbide semiconductor body. Background Technology

[0002] Power semiconductor devices are commonly used as switches and rectifiers in circuits for converting electrical energy, such as in DC / AC converters, AC / AC converters, or AC / DC converters, and in circuits driving heavy inductive loads, such as in motor driver circuits. Silicon carbide (SiC) has a higher dielectric breakdown field than silicon. Therefore, SiC devices can be thinner than equivalent silicon devices with the same rated blocking voltage. On the other hand, the electrical parameters of silicon carbide devices tend to degrade at a higher rate than those of equivalent silicon devices.

[0003] The long-term stability of silicon carbide device parameters needs to be improved. Summary of the Invention

[0004] Examples of this disclosure relate to a method of manufacturing a semiconductor device. The method includes providing a silicon carbide (SiC) semiconductor body. The method further includes introducing ions into the SiC semiconductor body via a first surface of the SiC semiconductor body through at least one ion implantation process. Subsequently, the method further includes forming a SiC device layer on the first surface of the SiC semiconductor body, and forming semiconductor device elements in or on the SiC device layer.

[0005] Another example of this disclosure relates to another method of manufacturing a semiconductor device. The method includes providing a silicon carbide (SiC) semiconductor body. The method further includes forming a SiC device layer on the SiC semiconductor body. The method also includes introducing ions into the SiC device layer via a first surface of the SiC device layer using at least one ion implantation process. The predominant vertically extending portion of a drift region in the SiC device layer is disposed between the range peak of the ions and the first surface of the SiC device layer. Thereafter, the method further includes forming a semiconductor device element in or on the SiC device layer.

[0006] Another example of this disclosure relates to a semiconductor device. The semiconductor device includes a SiC field stop region and / or a SiC drift region on a SiC semiconductor substrate. The Z-axis in the SiC drift region... 1 / 2 The concentration of defects is at least 1 / 3 of the SiC field-stop region and / or the SiC semiconductor substrate, or at least one order of magnitude smaller, or at least two orders of magnitude smaller, or even at least three orders of magnitude smaller.

[0007] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of methods for manufacturing silicon carbide devices and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and claims.

[0009] Figures 1A to 1E A schematic cross-sectional view is shown for illustrating a method of fabricating a SiC semiconductor device, the method comprising introducing ions into the SiC semiconductor body prior to forming a SiC device layer on the SiC semiconductor body;

[0010] Figures 2A to 2C It shows that it can be integrated into Figures 1A to 1E Exemplary process features in the method shown;

[0011] Figures 3A to 3B A schematic cross-sectional view is shown illustrating another method for manufacturing SiC semiconductor devices. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate specific examples of methods for manufacturing silicon carbide devices by way of illustration. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, a feature shown or described for one example may be used on or in combination with other examples to produce yet another example. This disclosure is intended to include such modifications and variations. Specific language is used to describe the examples, and this language should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements in different drawings are indicated by the same reference numerals.

[0013] The terms “having,” “containing,” “including,” “comprising,” etc., are open-ended and indicate the presence of the stated structure, element, or feature, but do not exclude the presence of additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0014] A given range of physical dimensions includes boundary values. For example, the range of parameter y from a to b should be expressed as a ≤ y ≤ b. The same applies to ranges with a single boundary value (such as "at most" and "at least").

[0015] The main components of a layer or structure derived from a compound or alloy are elements whose atoms form the compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0016] The term "on" should not be interpreted as simply meaning "directly on". Rather, if an element is "on" another element (e.g., a layer is "on" another layer or "on" a substrate), then another component (e.g., another layer) may be located between the two elements (e.g., if a layer is "on" the substrate, then another layer may be located between that layer and the substrate).

[0017] Examples of methods for manufacturing semiconductor devices may include providing a silicon carbide (SiC) semiconductor body. The method may further include introducing ions into the SiC semiconductor body via a first surface of the SiC semiconductor body using at least one ion implantation process. Subsequently, the method may further include forming a SiC device layer on the first surface of the SiC semiconductor body, and forming semiconductor device elements in or on the SiC device layer.

[0018] The silicon carbide semiconductor body can be a crystalline semiconductor substrate. For example, the silicon carbide crystal can have a hexagonal polytype, such as 4H or 6H. The silicon carbide semiconductor body can be homo-doped or can include different doped SiC layer portions. The silicon carbide semiconductor body can include one or more layers made of another material with a melting point close to or higher than that of crystalline silicon carbide. For example, a layer made of another material can be embedded in the crystalline silicon carbide substrate.

[0019] The silicon carbide semiconductor body may have two substantially parallel main surfaces of the same shape and size, and a lateral surface region connecting the edges of the two main surfaces. For example, the silicon carbide semiconductor body may be a rectangular prism with or without rounded edges, or a straight cylinder or a slightly inclined cylinder with or without one or more planes or notches along its outer circumference (e.g., where the sides are inclined at an angle of up to 8°, up to 5°, or up to 3°).

[0020] The silicon carbide semiconductor body can extend laterally in a plane spanned by a lateral direction (also known as the "horizontal direction").

[0021] Perpendicular to the lateral direction, the silicon carbide semiconductor body may have a smaller thickness in the vertical direction compared to its corresponding extension in the lateral direction. The lateral direction may extend parallel to the main surface, or may form an angle of up to 10°, up to 8°, or up to 5° with at least one of the main surfaces.

[0022] After ions are introduced into the SiC semiconductor body, a SiC device layer can be formed on a first surface of the SiC semiconductor body using at least one layer deposition process (e.g., epitaxial layer deposition). For example, chemical vapor deposition (CVD) can be used to form the SiC device layer. The doping concentration distribution and / or thickness of the SiC device layer can be selected considering target device parameters (e.g., voltage blocking capability and / or region-specific on-state resistance). For example, a first portion of the SiC device layer can be a drift region. For example, a second portion of the SiC device layer can be a field stop region. The field stop region can be disposed between the drift region and the back contact. For example, the doping concentration in the drift region can be greater than the doping concentration in the back contact region, for example, by one or two orders of magnitude.

[0023] Forming a semiconductor device element in or on a SiC device layer may include one or more of the following features: a semiconductor region forming, for example, p- and / or n-doped regions; an insulating layer, for example, one or more gate and / or field dielectrics and / or one or more interlayer dielectrics; a conductive layer, for example, one or more metal layers for electrical contacts and / or wiring; and one or more protective and / or passivation layers, for example, imide. For example, semiconductor regions, such as drain regions, source regions, body regions, body contact regions, current spreading regions, shielding regions, anode regions, and cathode regions, can be formed by ion implantation and / or diffusion from a diffusion source. A planar gate structure including a gate dielectric and a gate electrode, or a trench gate structure including a gate dielectric and a gate electrode in a trench, can be formed by thermal oxidation and / or layer deposition of the gate dielectric and layer deposition of a highly doped semiconductor (e.g., polysilicon and / or one or more metal layers). Therefore, a semiconductor device element can be formed in a SiC device layer after ions are introduced into the SiC semiconductor body.

[0024] In at least one operating mode of a semiconductor device (e.g., reverse conduction mode), a bipolar current consisting of holes and electrons flows through the silicon carbide semiconductor body. The bipolar current passes at least through the pn junction of the semiconductor device. Holes and electrons can recombine at a non-negligible rate, particularly near the pn junction, and further, if applicable, near the unipolar junction. Recombination can set free energy (e.g., thermal energy) and / or momentum, which can promote bipolar degradation. Bipolar degradation represents the growth of previously present crystal defects. For example, a basal dislocation (BPD) between adjacent crystal planes can transform into a stacking fault (SSF) that grows along the crystal plane in a direction primarily transverse to the vertical load current flowing through the silicon carbide body. Lattice defects can increasingly impede the flow of the vertical load current through the silicon carbide body, for example, degrading device reliability. At least one ion implantation process can be adapted to create recombination sites in the semiconductor device at locations where electron-hole recombination has a less detrimental effect on device reliability than at other locations, such as defects introduced by at least one ion implantation process. For example, recombination sites can be arranged between back-side contacts, such as the cathode contact of a power semiconductor diode, the drain contact of a power FET, or the collector contact of an IGBT. For example, the end depth of ions implanted into the SiC semiconductor body can range from, for example, 200 nm to 10 μm or 300 nm to 60 μm. Considering the temperature stability of recombination sites in SiC (e.g., defects introduced by at least one ion implantation process), recombination sites can withstand the high temperatures that may occur when, for example, semiconductor device elements are formed in or on the SiC semiconductor body. Since recombination site formation precedes the formation of semiconductor device elements, such as gate dielectric formation, in or on the SiC semiconductor body, the reliability of semiconductor device elements in or on the SiC semiconductor body can be improved because, for example, the ion implantation process associated with the recombination sites does not degrade the reliability of the semiconductor device elements.

[0025] For example, providing a SiC semiconductor body may include providing a SiC semiconductor substrate. The SiC semiconductor substrate may be a 4H-SiC semiconductor substrate. For example, after forming a SiC device layer on the SiC semiconductor substrate, the SiC semiconductor substrate or a major portion thereof may be reused by a dicing process.

[0026] For example, providing a SiC semiconductor body may include forming a SiC buffer layer on a SiC semiconductor substrate. The buffer layer can be used to generate recombination sites therein, such as defects created by introducing ions into the buffer layer of the semiconductor body. After generating recombination sites in the buffer layer, a SiC device layer can be formed. For example, the layer deposition process can be interrupted to introduce ions into the buffer layer. A first portion of the layer deposition process, for example, before introducing ions into the semiconductor body, can be used to form the buffer layer. For example, by introducing dopants therein, the buffer layer can serve as a field stop region. For example, a second portion of the layer deposition process, for example, after introducing ions into the semiconductor body, can be used to form a drift region.

[0027] For example, the thickness of the SiC buffer layer can range from 0.5 μm to 30 μm or from 1 to 10 μm. For instance, when setting the initial thickness of the SiC buffer layer, the cleaning process (e.g., hydrogen etching) prior to SiC layer deposition and the number of defects generated per implanted ion and irradiation depth range can be taken into account. This allows for the consideration of, for example, a reduction in the buffer layer thickness due to the cleaning process.

[0028] For example, the average doping concentration along the vertical extension of the SiC device layer can be less than the average doping concentration along the vertical extension of the SiC buffer layer. For example, the SiC buffer layer may include or correspond to a field stopping region having a larger doping concentration than the drift region formed in the SiC device layer. For example, the average doping concentration along the vertical extension of the SiC buffer layer can be, for example, 5 × 10⁻⁶. 16 cm -3 Up to 1×10 19 cm -3 Or 10 17 cm -3 Up to 5×10 18 cm -3 Within the range.

[0029] For example, the doping concentration of the main portion extending vertically along the SiC buffer layer can decrease gradually and / or continuously along the direction from the semiconductor substrate to the SiC device layer. The main portion can be a portion of the vertical extension of the SiC device layer that is greater than 50% (e.g., half) of the vertical extension of the SiC buffer layer. For example, this gradual and / or continuous reduction can be achieved by changing the distribution of one or more overlapping ion implantations of in-situ dopant and / or dopants during the deposition of the SiC buffer layer. In some other embodiments, the doping concentration of the main portion extending vertically along the SiC buffer layer can be constant along the direction from the semiconductor substrate to the SiC device layer.

[0030] For example, the method may also include forming an implantation mask over a first surface of the SiC semiconductor body, wherein ions for generating recombination sites are introduced through openings in the implantation mask. This can promote epitaxial growth of the SiC device layer with a high ion implantation dose pre-introduced into the SiC semiconductor body. For example, the desired crystal quality of the SiC device layer can be ensured by a lateral epitaxial overgrowth process initiated at a surface portion of the semiconductor body, where the implantation mask prevents ions from entering and damaging the lattice of the SiC semiconductor body.

[0031] For example, the minimum lateral extension of at least some openings can be in the range of 0.5 μm to 50 μm, or 2 μm to 30 μm, and the lateral distance between two adjacent openings can be in the range of 2 μm to 20 μm. This allows the desired crystal quality of the SiC device layer to be achieved by a lateral epitaxial overgrowth process initiated at a surface portion of the semiconductor body, where an implantation mask prevents ions from entering and damaging the lattice of the SiC semiconductor body.

[0032] For example, the ions include at least one of protons, He ions, Ar ions, Si ions, and C ions.

[0033] For example, forming semiconductor device elements includes forming at least one of the device elements of a pn diode or pin diode, a bipolar junction transistor, a field-effect transistor, an insulated gate bipolar transistor, and a thyristor.

[0034] The exemplary details described with reference to the methods above (e.g., details regarding the materials, functions, processes, arrangements, or dimensions of structural elements such as semiconductor regions) are correspondingly applicable to the methods further described below, and vice versa.

[0035] Another example of a method for manufacturing a semiconductor device may include providing a silicon carbide (SiC) semiconductor body. The method may also include forming a SiC device layer on the SiC semiconductor body. The method may further include introducing ions into the SiC device layer via a first surface of the SiC device layer using at least one ion implantation process. A major portion of the vertical extension of a drift region in the SiC device layer may be arranged between the range end peak of the ions and the first surface of the SiC device layer. The method may then further include forming a semiconductor device element in or on the SiC device layer. The major portion may be a portion of the vertical extension of the drift region that is greater than 50% of the vertical extension of the drift region. For example, the vertical extension of the drift region may extend from, for example, i) the pn junction between the drift region and the body region of an iF or IGBT, or between the drift region and the anode region of a diode, to ii) a highly doped contact or drain region (or emitter region) on the back side of an iF (or IGBT), or to a cathode contact on the back side of a diode. The drift region may include a buffer layer or a field stop region, wherein at least a portion or even most of the implanted range end region may be implemented.

[0036] For example, depending on the target breakdown voltage of the SiC device, the vertical distance between the range peak and the first surface can be in the range of 5 μm to 100 μm, or 6 μm to 60 μm, or 8 μm to 20 μm.

[0037] For example, the gate dielectric and gate electrode can be formed after the introduction of ions. Therefore, for example, the negative impact of processes that introduce ions to create recombination sites (e.g., defects) on the device reliability of the gate dielectric can be avoided or reduced. This is because recombination site formation precedes the formation of reliability-sensitive structural device elements, such as the gate dielectric.

[0038] For example, at least one ion implantation process may include having a range from 5 × 10 10 cm -2 Up to 5×10 13 cm -2 Or from 10 11 cm -2 Up to 5×10 12 cm -2 Proton implantation with an ion implantation dose ranging from 1 × 10⁻⁶. At least one ion implantation process may also include proton implantation with an ion implantation dose ranging from 1 × 10⁻⁶. 10 cm -2 Up to 1×10 13 cm -2 Or from 2×10 10 cm -2 Up to 1×10 12 cm -2 The implantation of helium ions at an ion implantation dose ranging from 1 × 10⁻⁶. At least one ion implantation process may also include the implantation of helium ions with a dose ranging from 1 × 10⁻⁶.9 cm -2 Up to 1×10 12 cm -2 Or from 2×10 9 cm -2 Up to 1×10 11 cm -2 Argon ion implantation dose.

[0039] Examples of semiconductor devices may include a SiC drift region above a SiC semiconductor substrate and / or a SiC field-stop region. The semiconductor device may also include a Z-region in the SiC drift region that is at least an order of magnitude smaller than the SiC field-stop region and / or the SiC semiconductor substrate. 1 / 2 Defect concentration. Z 1 / 2 Defects can be observed, for example, in deep transient spectroscopy (DLTS). Based on experimental and theoretical calculations reported in the literature, Z... 1 / 2 The defects are most likely negative U-acceptor and double-acceptor states of carbon vacancies. Due to defects generated by at least one ion implantation process, Z-type defects in the SiC field-stop region and / or the SiC semiconductor substrate... 1 / 2 The ion implantation process is used to create recombination sites in semiconductor devices where the concentration of defects is greater than that in SiC drift regions, at locations where electron-hole recombination has less detrimental effect on device reliability than at other locations.

[0040] For example, SiC drift regions can be formed from 4H-SiC.

[0041] The examples above may be examples of power semiconductor devices or examples of devices used to manufacture power semiconductor devices, such as silicon carbide power semiconductor devices. Power semiconductor devices or their electrical structures (e.g., transistors in silicon carbide devices) may have breakdown voltages or blocking voltages greater than 100V (e.g., 200V, 300V, 400V, or 500V), greater than 500V (e.g., 600V, 700V, 800V, or 1000V), or greater than 1000V (e.g., 1200V, 1500V, 1700V, 2000V, 3300V, or 6500V).

[0042] The examples and features described above and below can be combined.

[0043] Some of the above and below examples are described in conjunction with a silicon carbide substrate. Alternatively, a wide-bandgap semiconductor substrate, such as a wide-bandgap wafer, can be processed, for example, comprising a wide-bandgap semiconductor material different from silicon carbide. A wide-bandgap semiconductor wafer can have a bandgap larger than that of silicon (1.1 eV). For example, a wide-bandgap semiconductor wafer can be a silicon carbide (SiC) wafer, or a gallium arsenide (GaAs) wafer, or a gallium nitride (GaN) wafer.

[0044] Further details and aspects are mentioned in conjunction with the examples above or below. Processing a wide-bandgap semiconductor wafer may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the presented concepts or one or more examples described above or below.

[0045] The aspects and features mentioned and described together with one or more of the previously described examples and figures may also be combined with one or more other examples in order to replace similar features in other examples or to additionally introduce the feature into other examples.

[0046] The description and accompanying drawings merely illustrate the principles of this disclosure. Furthermore, all examples recorded herein are intended primarily and explicitly for illustrative purposes only to aid the reader in understanding the principles of this disclosure and the concepts contributed by the inventors(s) to the advancement of the art. All statements and specific examples of the principles, aspects, and examples of this disclosure recorded herein are intended to cover their equivalents.

[0047] It should be understood that, unless expressly or implicitly stated otherwise, such as by expressions like "hereafter," for technical reasons, the disclosure of multiple actions, processes, operations, steps, or functions in the specification or claims should not be construed as being in a particular order. Therefore, the disclosure of multiple actions or functions will not limit them to a particular order unless such actions or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may also include or be divided into multiple sub-actions, sub-functions, sub-processes, sub-operations, or sub-steps. Unless expressly excluded, such sub-actions may be included in and are part of the disclosure of this single action.

[0048] Figures 1A to 1E A method for manufacturing semiconductor devices is shown.

[0049] refer to Figure 1A The method provides a silicon carbide (SiC) semiconductor body 102. The SiC semiconductor body 102 includes a SiC semiconductor substrate 104, such as a 4H-SiC semiconductor substrate. Optionally, a buffer layer 106 may be formed on the SiC semiconductor substrate 104. The method also includes introducing ions into the SiC semiconductor body via a first surface 108 of the SiC semiconductor body 102 through at least one ion implantation process. The extent of defect-generating ions may be located in the buffer layer or in the SiC substrate. For example, implantation into the substrate may be performed before or after buffer implementation.

[0050] The details described in the above examples, such as those concerning the SiC semiconductor body or SiC semiconductor substrate or optional buffer layer or ions introduced into the SiC semiconductor body, also apply to the examples shown. At least one ion implantation process in Figure 1A The diagram is schematically illustrated by an arrow indicating an exemplary direction (e.g., non-tilted ion implantation) of ions impacting the first surface 108. Other implantation directions, such as tilted implantation directions, may also be used.

[0051] refer to Figure 1B A SiC device layer 110 is formed on the first surface of the SiC semiconductor body 102. The details described in the above example regarding the SiC device layer also apply to the example shown.

[0052] refer to Figure 1C Semiconductor device elements are formed in or on the SiC device layer 110. The details described above regarding the semiconductor device elements also apply to the illustrated example. Considering the various possibilities for semiconductor device elements formed in or on the SiC semiconductor device layer 110, a semiconductor device element formed in the SiC device layer 110 is shown in a simplified manner, for example, by a dashed box 112 indicating a portion of the SiC device layer 110 including the SiC semiconductor device element. As an example of a semiconductor device element formed on the SiC device layer 110, Figure 1D The diagram schematically illustrates a first load electrode L1 and an optional control electrode C. The first load electrode L1 (e.g., the anode electrode of a diode or thyristor, or the source electrode of a FET or IGBT) may be part of a wiring region formed on the SiC device layer 110. The optional control electrode C (e.g., the gate electrode of a FET or IGBT) may also be part of a wiring region formed on the SiC device layer 110. The wiring region may include one, two, three, or even more wiring layers, which may include patterned metal layers and interlayer dielectrics disposed between the patterned metal layers. For example, vias may electrically interconnect different wiring layers.

[0053] refer to Figure 1D The second load electrode L2 (e.g., the cathode electrode of a diode or thyristor, the drain electrode of a FET, or the collector electrode of an IGBT) can be formed on the second surface of the semiconductor body 102, for example, on the back side. As... Figure 1D Alternative Figure 1EAs illustrated in the schematic diagram, all or part of the SiC semiconductor substrate 104 can be removed. For example, all or part of the SiC semiconductor substrate 104 can be removed by mechanical polishing and / or etching. All or part of the SiC semiconductor substrate 104 can also be removed by a wafer dicing process. This allows for the reuse of that portion of the SiC semiconductor substrate 104 (e.g., a processed substrate), which, for example, is separated from the remainder of the SiC substrate or from the SiC device layer 110.

[0054] For example, Figures 2A to 2C The process features shown can be integrated into the reference. Figures 1A to 1E In the method described.

[0055] refer to Figure 2A An implantation mask 114 is formed over a first surface 108 of the SiC semiconductor body 102 (e.g., a substrate surface, a buffer surface, or a surface after drift region deposition). The implantation mask 114 includes a mask opening 116 in which ions can enter the semiconductor body 102 during ion implantation without being blocked by the mask. The details described in the above example regarding the implantation mask or opening also apply to the example shown. Figure 2B and 2C An exemplary plan view of the injection mask 114 is shown. The injection mask 114 can be strip-shaped, such as... Figure 2B The diagram is schematically shown. Alternatively or additionally, the implantation mask 114 may include multiple mask portions that are laterally spaced from each other and arranged in a regular pattern. For example, the mask portions may be circular (illustrated by solid lines), elliptical, or polygonal (e.g., square (indicated by dashed lines)). For example, when forming a SiC device layer by lateral epitaxial overgrowth, the shape and size of the mask pattern can be appropriately selected to achieve the desired crystal quality.

[0056] Figures 3A to 3B Another example of a method for manufacturing semiconductor devices is shown.

[0057] refer to Figure 3A A silicon carbide (SiC) semiconductor body 102 is provided. The SiC semiconductor body 102 includes a SiC semiconductor substrate 104, such as a 4H-SiC semiconductor substrate. A SiC device layer 110 is formed on the SiC semiconductor body 102, which may include a buffer layer between a drift region and the SiC substrate. The details described in the above examples, for example, regarding the SiC semiconductor body, SiC semiconductor substrate, or SiC device layer, also apply to the illustrated examples.

[0058] refer to Figure 3BIons are introduced into the SiC device layer 110 via a first surface 108 of the SiC device layer 110 through at least one ion implantation process. The main vertically extending portion of the drift region 118 in the SiC device layer 110 is arranged between the range end peak P of the ion and the first surface 108 of the SiC device layer 110. The details described in the above example, for example, regarding the ions introduced into the SiC device layer, also apply to the example shown.

[0059] This method continues to form semiconductor device elements in or on the SiC device layer, as shown in the reference. Figure 1C The example described above. Similar to... Figure 1D and 1E The example shown, for instance, may form a first load electrode, an optional control electrode C, and a second load electrode L2.

[0060] The exemplary method described above with reference to the accompanying drawings can be used to fabricate a semiconductor device including a SiC semiconductor substrate 104 and / or a SiC drift region 118 above the SiC field stop region. The Z-axis in the SiC drift region 104... 1 / 2 The defect concentration is at least one order of magnitude lower than that in the SiC field-stop region and / or the SiC semiconductor substrate 104. For example, the SiC field-stop region can be formed in... Figures 1A to 1E In the buffer layer 106 shown.

[0061] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used instead of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Provides a silicon carbide (SiC) semiconductor body (102); A SiC device layer (110) is formed on the SiC semiconductor body (102); Ions are introduced into the SiC device layer (110) via a first surface (108) of the SiC device layer (110) through at least one ion implantation process, wherein the main vertically extending portion of the drift region (118) in the SiC device layer (110) is arranged between the range peak (P) of the ion and the first surface (108) of the SiC device layer (110); and thereafter Semiconductor device elements are formed in or on the SiC device layer (110). A field stop region is formed between the drift region (118) and the rear contact of the semiconductor device by means of at least one ion implantation process via the first surface (108).

2. The method of claim 1, wherein providing the SiC semiconductor body (102) includes providing a SiC semiconductor substrate (104).

3. The method according to claim 2, wherein the SiC semiconductor substrate (104) is a 4H-SiC semiconductor substrate.

4. The method of claim 2, wherein providing the SiC semiconductor body (102) further includes forming a SiC buffer layer (106) on the SiC semiconductor substrate (104).

5. The method according to claim 4, wherein the thickness of the SiC buffer layer (106) is in the range of 0.5 μm to 30 μm.

6. The method according to claim 4, wherein the average doping concentration along the vertical extension of the SiC device layer (110) is less than the average doping concentration along the vertical extension of the SiC buffer layer (106).

7. The method according to claim 4, wherein the doping concentration of the main portion extending vertically along the SiC buffer layer (106) gradually and / or continuously decreases along the direction from the semiconductor substrate (104) to the SiC device layer (110).

8. The method according to claim 1, further comprising: An implantation mask (114) is formed on a first surface (108) of a SiC semiconductor body (102), wherein the ions are introduced through an opening (116) in the implantation mask (114).

9. The method of claim 8, wherein at least some of the openings (116) have a minimum lateral extension in the range of 0.5 μm to 50 μm, and the lateral distance between two adjacent openings (116) is in the range of 2 μm to 20 μm.

10. The method according to claim 1, wherein the ion comprises at least one selected from He ions, Ar ions, Si ions, and C ions.

11. The method of claim 1, wherein forming the semiconductor device element comprises forming at least one of a pn diode or pin diode, a bipolar junction transistor, a field-effect transistor, an insulated gate bipolar transistor, and a thyristor.

12. The method according to claim 1, wherein, The vertical distance between the range peak (P) and the first surface (108) is in the range of 5 μm to 100 μm.

13. The method according to claim 1, wherein, The gate dielectric and gate electrode are formed after the ions are introduced.

14. The method according to claim 1, wherein, At least one ion implantation process includes having a range from 5 × 10 10 cm -2 Up to 5×10 13 cm -2 The ion implantation dose.

15. A semiconductor device manufactured using the method of manufacturing a semiconductor device according to any one of claims 1 to 14, the semiconductor device comprising: SiC semiconductor substrate (104) and / or SiC drift region (118) above SiC field stop region, wherein Z in the SiC drift region (118) 1 / 2 The concentration of defects is at least one order of magnitude smaller than that in the SiC field stop region and / or the SiC semiconductor substrate (114).

16. The semiconductor device according to claim 15, wherein, The SiC drift region (118) is formed of 4H-SiC.

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