Semiconductor device including through-electrode

Abstract

The present invention discloses a semiconductor device including a through electrode. The semiconductor device includes: a first semiconductor chip; and a second semiconductor chip, which is stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through the first through electrode and the second through electrode. During a second test operation, the first semiconductor chip can electrically connect the first through electrode to a third test resistor. During the second test operation, the first semiconductor chip can detect a voltage level of a first internal node to test a short circuit fault between the first through electrode and the second through electrode, and the voltage level of the first internal node is determined by the third test resistor and the resistance values ​​of the first through electrode and the second through electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0082903, filed on Jul. 9, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor device and a through-electrode. Background Art

[0004] Recently, three-dimensional semiconductor devices have been developed to increase their integration density. Each three-dimensional semiconductor device can achieve maximum integration density on a limited area by vertically stacking a plurality of semiconductor chips.

[0005] Each three-dimensional semiconductor chip can be implemented using through-silicon via (TSV) technology, which uses silicon vias that vertically penetrate the semiconductor chip to electrically connect all vertically stacked semiconductor chips to each other. Therefore, compared with three-dimensional semiconductor devices manufactured using bonding wires, three-dimensional semiconductor devices manufactured using TSV can effectively reduce their packaging area.

[0006] In addition, a semiconductor device or a semiconductor package including a semiconductor device may be tested before the semiconductor package is provided to a user or customer to verify its characteristics and reliability. Therefore, various methods for testing semiconductor devices or semiconductor packages have been proposed to reduce test time and improve test efficiency. Summary of the invention

[0007] According to one embodiment, a semiconductor device may include: a first semiconductor chip; and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through a first through electrode and a second through electrode. During a second test operation, the first semiconductor chip may electrically connect the first through electrode to a third test resistor. During the second test operation, the first semiconductor chip may detect a voltage level of a first internal node to test a short circuit fault between the first through electrode and the second through electrode, the voltage level of the first internal node being determined by the third test resistor and the resistance values ​​of the first through electrode and the second through electrode.

[0008] According to one embodiment, a semiconductor device may include: a first semiconductor chip; and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip may be electrically connected to the first semiconductor chip through a first through electrode and a second through electrode. During a first test operation, the first semiconductor chip may electrically connect the first through electrode and the second through electrode to a first test resistor and a second test resistor. During the first test operation, the first semiconductor chip may detect the voltage level of the first internal node and the second internal node to test the open circuit failure of the first through electrode and the second through electrode. The voltage level of the first internal node and the second internal node may be determined by the resistance values ​​of the first test resistor and the second test resistor and the first through electrode and the second through electrode.

[0009] According to another embodiment, a semiconductor device may include: a first semiconductor chip; and a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip may be electrically connected to the first semiconductor chip through a first through electrode and a second through electrode. During a first test operation, the first semiconductor chip may be configured to electrically connect the first through electrode and the second through electrode to a first test resistor and a second test resistor, and to detect the voltage level of the first internal node and the second internal node to test the open circuit fault of the first through electrode and the second through electrode. In this case, the voltage level of the first internal node and the second internal node may be determined by the first test resistor and the second test resistor and the resistance value of the first through electrode and the second through electrode. During a second test operation, the first semiconductor chip may be configured to electrically connect the first through electrode to a third test resistor, and to detect the voltage level of the first internal node to test the short circuit fault between the first through electrode and the second through electrode. In this case, the voltage level of the first internal node may be determined by the third test resistor and the resistance value of the first through electrode and the second through electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 A block diagram of a configuration of a first test control circuit included in a semiconductor device of FIG.

[0012] Figure 3 Show Figure 2 The configuration of the first control circuit included in the first test control circuit.

[0013] Figure 4 Show Figure 2The first test control circuit includes a configuration of a first test circuit, together with Figure 1 The first through-electrode is shown together.

[0014] Figure 5 It is shown Figure 4 A circuit diagram of a configuration of a first transmitter included in a first test circuit.

[0015] Figure 6 It is shown Figure 4 A circuit diagram of a configuration of a first receiver included in a first test circuit.

[0016] Figure 7 It is shown Figure 4 A circuit diagram of a configuration of a first output circuit included in a first test circuit.

[0017] Figure 8 Show Figure 2 Configuration of a sensing circuit included in a first test control circuit.

[0018] Fig. 9 It is shown Figure 1 A block diagram of a configuration of a second test control circuit included in a semiconductor device of FIG.

[0019] Fig.10 It is shown Fig. 9 A circuit diagram of a configuration of a second control circuit included in a second test control circuit.

[0020] Fig.11 Show Fig. 9 The second test control circuit includes a configuration of the first connection circuit, together with Figure 1 The first through-electrode is shown together.

[0021] Fig.12 It is shown Fig.11 Circuit diagram of a configuration of a second transmitter included in a first connection circuit.

[0022] Fig.13 and Fig.14 A first test operation of a semiconductor device according to an embodiment of the present disclosure is shown.

[0023] Fig.15 and Fig.16 A second test operation of the semiconductor device according to the embodiment of the present disclosure is shown.

[0024] Fig.17 and Fig.18 is a timing diagram illustrating a first test operation and a second test operation of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Various embodiments of the present disclosure will be described below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0026] like Figure 1 As shown, the semiconductor device 1 according to the embodiment may include a first semiconductor chip 10 , first and second transmission through electrodes 21 and 22 , first to fourth through electrodes 23 , 24 , 25 and 26 , and a second semiconductor chip 30 .

[0027] The first semiconductor chip 10 may include a first test control circuit 11 .

[0028] When the chip identification signal CID and the open circuit test signal OPT are enabled, the first test control circuit 11 may be electrically and physically connected to the first to fourth through electrodes 23 to 26. When the chip identification signal CID and the open circuit test signal OPT are enabled, the first test control circuit 11 may sequentially test the open circuit faults of the first to fourth through electrodes 23 to 26. When the chip identification signal CID and the short circuit test signal SHT are enabled, the first test control circuit 11 may be connected to the first to fourth through electrodes 23 to 26. When the chip identification signal CID and the short circuit test signal SHT are enabled, the first test control circuit 11 may test the fault between the first through electrode 23 and the second through electrode 24, and the fault between the third through electrode 25 and the fourth through electrode 26. For example, when the chip identification signal CID and the short-circuit test signal SHT are enabled, the first test control circuit 11 can test a fault between the first through electrode 23 and the second through electrode 24 caused by a short circuit between the first through electrode 23 and the second through electrode 24. For example, when the chip identification signal CID and the short-circuit test signal SHT are enabled, the first test control circuit 11 can test a fault between the third through electrode 25 and the fourth through electrode 25 caused by a short circuit between the third through electrode 25 and the fourth through electrode 26. The chip identification signal CID can be set as a signal for activating the first semiconductor chip 10 and the second semiconductor chip 30. Although Figure 1The chip identification signal CID is shown in a single line, but the chip identification signal CID may be a signal including a plurality of bits, which is used to selectively activate a plurality of semiconductor chips. The open circuit test signal OPT may be enabled to activate the first test operation. The short circuit test signal SHT may be enabled to activate the second test operation. The first test operation may be an operation for testing an open circuit failure of the first to fourth through electrodes 23 to 26. In one embodiment, the open circuit failure refers to that at least one of the first to fourth through electrodes 23 to 26 is electrically disconnected from at least one of the first semiconductor chip 10 and the second semiconductor chip 30. The second test operation may be an operation for testing a short circuit failure between the first to fourth through electrodes 23 to 26. In one embodiment, the short circuit failure refers to that at least two adjacent electrodes of the first to fourth through electrodes 23 to 26 are electrically connected to each other. The chip identification signal CID may be transmitted from the first semiconductor chip 10 to the second semiconductor chip 30 via the first transmission through electrode 21. The open circuit test signal OPT and the short circuit test signal SHT may be transmitted from the first semiconductor chip 10 to the second semiconductor chip 30 via the second transmission electrode 22.

[0029] The first semiconductor chip 10 may sequentially test the open faults of the first to fourth through electrodes 23 to 26 during the first test operation. The first semiconductor chip 10 may test the short faults between the first through electrode 23 and the second through electrode 24 during the second test operation. The first semiconductor chip 10 may test the short faults between the third through electrode 25 and the fourth through electrode 26 during the second test operation. The first semiconductor chip 10 may test the short faults between the second through electrode 24 and the third through electrode 25 during the second test operation.

[0030] The second semiconductor chip 30 may include a second test control circuit 31 .

[0031] When the chip identification signal CID and the open test signal OPT are enabled, the second test control circuit 31 may be electrically and physically connected to the first to fourth through electrodes 23 to 26. When the chip identification signal CID and the short test signal SHT are enabled, the second test control circuit 31 may be connected to the first to fourth through electrodes 23 to 26.

[0032] As described above, the second semiconductor chip 30 may be connected to the first to fourth through electrodes 23 ˜ 26 during the first test operation and the second test operation.

[0033] The first and second transmission through electrodes 21 and 22 and the first to fourth through electrodes 23 to 26 may be implemented by using general through silicon vias (TSVs) vertically penetrating a semiconductor chip. Figure 1Six through electrodes (ie, the first transmission through electrode 21 and the second transmission through electrode 22, and the first to fourth through electrodes 23 to 26) are shown, but the number of through electrodes may be set to be less than or greater than six according to the embodiment. Figure 1 What is shown is an example in which the semiconductor device 1 includes two semiconductor chips (i.e., a first semiconductor chip 10 and a second semiconductor chip 30), wherein the two semiconductor chips are stacked and connected by a first transmission through electrode 21 and a second transmission through electrode 22 and first to fourth through electrodes 23 to 26, but the number of semiconductor chips included in the semiconductor device 1 may be set to be greater than two according to an embodiment.

[0034] See also Figure 2 The first test control circuit 11 may include a first control circuit 110 , a first test circuit 120 , a second test circuit 130 , a third test circuit 140 , a fourth test circuit 150 , and a sensing circuit 160 .

[0035] When the chip identification signal CID and the open test signal OPT (or the short test signal SHT) are enabled, the first control circuit 110 may generate a first enable signal EN_TSV. <1> And the first test data TD <1> When the chip identification signal CID is enabled to have a logic “high” level and any one of the open test signal OPT and the short test signal SHT is enabled to have a logic “high” level, the first control circuit 110 may generate the first enable signal EN_TSV enabled to have a logic “high” level. <1> When the chip identification signal CID is enabled to have a logic “high” level and any one of the open test signal OPT and the short test signal SHT is enabled to have a logic “high” level, the first control circuit 110 may generate the first test data TD enabled to have a logic “low” level. <1> .

[0036] The first control circuit 110 may generate first to fourth open switch signals OP_SW<1:4>, which are sequentially enabled when the chip identification signal CID and the open test signal OPT are enabled. The first control circuit 110 may generate first and second short switch signals SH_SW<1:2>, which are enabled when the chip identification signal CID and the short test signal SHT are enabled.

[0037] The first test circuit 120 may be configured to enable the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> And will Figure 1The first through electrode 23 shown is driven to a predetermined logic level. For example, the first test circuit 120 can be based on the first enable signal EN_TSV <1> And the first test data TD <1> A voltage is applied to the first through electrode 23 to provide a predetermined logic level on the first through electrode 23. The first test circuit 120 may receive a first open switch signal OP_SW <1> and the first short-circuit switch signal SH_SW <1> To generate a first flag signal FLAG <1> . The first test circuit 120 can be connected to the first through electrode 23. The predetermined logic level can be set to a logic "high" level or a logic "low" level according to the embodiment. The word "predetermined" (such as a predetermined logic level) as used herein with respect to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0038] The second test circuit 130 may be configured to generate a first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> Come Figure 1 The second through electrode 24 is shown to be driven to a predetermined logic level. The second test circuit 130 may be connected to the second through electrode 24. The second test circuit 130 may receive a second open switch signal OP_SW <2> and the second short-circuit switch signal SH_SW <2> To generate the second flag signal FLAG <2> .

[0039] The third test circuit 140 may be configured to detect the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> Come Figure 1 The third through electrode 25 shown is driven to a predetermined logic level. The third test circuit 140 may be connected to the third through electrode 25. The third test circuit 140 may receive a third open switch signal OP_SW <3> and the third short-circuit switch signal SH_SW <3> To generate a third flag signal FLAG <3> .

[0040] The fourth test circuit 150 may be configured based on the first enable signal EN_TSV. <1> And the first test data TD <1> Come Figure 1 The fourth through electrode 26 is shown to be driven to a predetermined logic level. The fourth test circuit 150 may be connected to the fourth through electrode 26. The fourth test circuit 150 may receive a fourth open switch signal OP_SW <4> and the fourth short-circuit switch signal SH_SW <4> To generate a fourth flag signal FLAG <4> .

[0041] When the open test signal OPT or the short test signal SHT is enabled, the sensing circuit 160 may synthesize the first to fourth flag signals FLAG<1:4> to generate the detection signal TSV_DET. The detection signal TSV_DET may be enabled when at least one of the first to fourth through electrodes 23 ˜ 26 has an open failure or a short failure occurs.

[0042] See also Figure 3 The first control circuit 110 may include a first selection signal generating circuit 111 , a logic circuit 112 and a first switch signal generating circuit 113 .

[0043] The first selection signal generation circuit 111 may generate first to fourth selection signals SEL<1:4> that are sequentially enabled when the chip identification signal CID and the open test signal OPT are enabled. The first selection signal generation circuit 111 may generate first and third selection signals SEL<1:4> that are enabled when the chip identification signal CID and the short test signal SHT are enabled. <1> and SEL <3> .

[0044] The logic circuit 112 may be configured to perform an OR logic operation and a NOR logic operation, and may include an OR gate OR11 and a NOR gate NOR11. The logic circuit 112 may generate a first enable signal EN_TSV <1> , which is enabled to have a logic “high” level when any one of the open test signal OPT and the short test signal SHT is enabled to have a logic “high” level. The logic circuit 112 may perform an OR logic operation on the open test signal OPT and the short test signal SHT to generate a first enable signal EN_TSV <1> The logic circuit 112 may generate the first test data TD <1> , which is enabled to have a logic “low” level when any one of the open test signal OPT and the short test signal SHT is enabled to have a logic “high” level. The logic circuit 112 may perform a logic OR operation on the open test signal OPT and the short test signal SHT to generate the first test data TD <1> .

[0045] The first switch signal generating circuit 113 may be configured to perform a NAND operation and may be implemented using NAND gates NAND11 and NAND12. When the open test signal OPT is enabled to have a logic "high", the first switch signal generating circuit 113 may invert and buffer the first to fourth selection signals SEL<1:4> to generate the first to fourth open switch signals OP_SW<1:4>. When the short test signal SHT is enabled to have a logic "high", the first switch signal generating circuit 113 may invert and buffer the first to third selection signals SEL<1:3> to generate the first and second short switch signals SH_SW<1:2>.

[0046] Figure 4 Show Figure 2 The configuration of the first test circuit 120 included in the first test control circuit 11, together with Figure 1 The first through-electrode 23 is shown together.

[0047] See also Figure 4 , the first test circuit 120 may include a first resistor connection circuit 121 , a first transmitter 122 , a first receiver 123 , and a first output circuit 124 .

[0048] The first resistor connection circuit 121 may be coupled between the power supply voltage VDD terminal and a first internal node nd11 connected to the first through electrode 23. When the first open switch signal OP_SW <1> When enabled to have a logic “low” level, the first resistor connecting circuit 121 may electrically connect the first through electrode 23 to the first test resistor R21. <1> When enabled to have a logic “low” level, the first resistor connecting circuit 121 may electrically connect the first through electrode 23 to the third test resistor R22 .

[0049] For example, the first resistor connection circuit 121 may include a first test resistor R21 and a first switch P21, which are coupled in series between the power supply voltage VDD terminal and the first internal node nd11 connected to the first through electrode 23. <1> When enabled to have a logic "low" level, the first switch P21 may be turned on to electrically connect the first test resistor R21 to the first through electrode 23. The first resistor connection circuit 121 may further include a third test resistor R22 and a second switch P22, which are coupled in series between the power supply voltage VDD terminal and the first internal node nd11 connected to the first through electrode 23. When the first short-circuit switch signal SH_SW <1> When enabled to have a logic "low" level, the second switch P22 may be turned on to electrically connect the third test resistor R22 to the first through electrode 23. The first test resistor R21 may be set to a replica resistor having a resistance value corresponding to the resistance value of the first through electrode 23 that is regarded as a normal through electrode without an open circuit failure. In one embodiment, if the open circuit failure of the first through electrode 23 does not occur when the first through electrode 23 has a resistance value of 100 ohms, the resistance value of the first test resistor R21 may be set to 100 ohms. The resistance value of the first test resistor R21 may be set differently according to the embodiment. The third test resistor R22 may be set to a replica resistor having a resistance value corresponding to the resistance value between the first through electrode 23 and the second through electrode 24 when a short circuit failure does not occur between the first through electrode 23 and the second through electrode 24. In one embodiment, if a short circuit failure does not occur between the first through electrode 23 and the second through electrode 24 when the resistance value between the first through electrode 23 and the second through electrode 24 is set to 100KΩ, the resistance value of the third test resistor R22 may be set to 100KΩ. The resistance value of the third test resistor R22 may be set differently according to embodiments.

[0050] The first transmitter 122 may enable the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> The level of the first through electrode 23 is driven to a predetermined logic level. <1> is enabled and the first test data TD <1> When enabled, the first transmitter 122 may drive the level of the first through electrode 23 to the predetermined logic level. The predetermined logic level may be set to a logic "low" level.

[0051] The first receiver 123 may detect a voltage level of the first internal node nd11 to generate a first internal detection signal IDET. The first receiver 123 may buffer a voltage signal of the first internal node nd11 to generate the first internal detection signal IDET.

[0052] When any one of the open test signal OPT and the short test signal SHT is enabled, the first output circuit 124 may generate the first flag signal FLAG from the first internal detection signal IDET. <1> .

[0053] Figure 2 Each of the second to fourth test circuits 130, 140, and 150 shown in FIG. 1 may be implemented to have a Figure 4 The first test circuit 120 described above is substantially the same circuit except for its input and output signals. Therefore, the description of the second to fourth test circuits 130, 140 and 150 will be omitted hereinafter. Figure 4 The second through electrode 24 is not shown in the figure, but the second through electrode 24 can be arranged adjacent to the first through electrode 23, such as Figure 1 shown.

[0054] See also Figure 5 , the first transmitter 122 may include a first pull-up / pull-down signal generating circuit 1221 and a first driving circuit 1222 .

[0055] The first pull-up / pull-down signal generating circuit 1221 may be configured to perform inversion, NAND, and NOR operations, and may be implemented to include an inverter IV31, a NAND gate NAND31, and a NOR gate NOR31. <1> When enabled to have a logic “high” level, the first pull-up / pull-down signal generating circuit 1221 may invert and buffer the first test data TD <1> To generate a first pull-up signal PU <1> When the first enable signal EN_TSV <1> When enabled to have a logic “high” level, the first pull-up / pull-down signal generating circuit 1221 may invert and buffer the first test data TD <1> To generate the first pull-down signal PD <1> When the first enable signal EN_TSV <1> is enabled to have a logic "high" level and the first test data TD <1> When enabled to have a logic “low” level, the first pull-up / pull-down signal generating circuit 1221 may generate a first pull-up signal PU having a logic “high” level. <1> and a first pull-down signal PD having a logic "high" level <1> .

[0056] The first driving circuit 1222 may be implemented to include: a PMOS transistor P31 coupled between a power supply voltage VDD terminal and a first internal node nd11 connected to the first through electrode 23; and an NMOS transistor N31 coupled between the first internal node nd11 and a ground voltage VSS terminal. <1> When the first pull-down signal PD has a logic “low” level, the first driving circuit 1222 can pull up the level of the first internal node nd11 to the power supply voltage VDD. <1> With a logic “high” level, the first driving circuit 1222 may pull down the level of the first internal node nd11 to the ground voltage VSS.

[0057] See also Figure 6 , the first receiver 123 may be configured to perform an inversion operation, and may be implemented to include inverters IV41 and IV42 connected in series.

[0058] The first receiver 123 may buffer the voltage signal of the first internal node nd11 to generate a first internal detection signal IDET.

[0059] See also Figure 7 , the first output circuit 124 may be implemented to include an inverter IV51 and a multiplexer MUX51.

[0060] When the open circuit test signal OPT is enabled, the first output circuit 124 may invert and buffer the first internal detection signal IDET to output an inverted buffer signal of the first internal detection signal IDET as the first flag signal FLAG. <1> When the short test signal SHT is enabled, the first output circuit 124 may buffer the first internal detection signal IDET to output the buffered signal of the first internal detection signal IDET as the first flag signal FLAG. <1> .

[0061] See also Figure 8 The sensing circuit 160 may include a synthetic signal generating circuit 161 , an output control signal generating circuit 162 , and a detection signal generating circuit 163 .

[0062] The synthesized signal generating circuit 161 may be configured to perform a NAND operation and a NOR operation, and may be implemented to include NAND gates NAND61 and NAND62, and a NOR gate NOR61. When all of the first to fourth flag signals FLAG<1:4> have a logic "high" level, the synthesized signal generating circuit 161 may generate a synthesized signal SUM having a logic "high" level. When at least one of the first to fourth flag signals FLAG<1:4> has a logic "low" level, the synthesized signal generating circuit 161 may generate a synthesized signal SUM having a logic "low" level.

[0063] The output control signal generation circuit 162 may be configured to perform a NOR operation and may be implemented using a NOR gate NOR62. When both the open test signal OPT and the short test signal SHT are disabled as a logic "low" level, the output control signal generation circuit 162 may generate an output control signal OUT_CON having a logic "high" level. When any one of the open test signal OPT and the short test signal SHT is enabled as a logic "high" level, the output control signal generation circuit 162 may generate an output control signal OUT_CON having a logic "low" level.

[0064] The detection signal generation circuit 163 may be implemented using a flip-flop FF61. When the output control signal OUT_CON is enabled to have a logic "high" level, the detection signal generation circuit 163 may output the synthesized signal SUM as the detection signal TSV_DET.

[0065] See also Fig. 9 The second test control circuit 31 may include a second control circuit 310 , a first connection circuit 320 , a second connection circuit 330 , a third connection circuit 340 , and a fourth connection circuit 350 .

[0066] When the chip identification signal CID is enabled and any one of the open test signal OPT and the short test signal SHT is enabled, the second control circuit 310 may generate the second enable signal EN_TSV <2> and the second test data TD <2> .

[0067] The first connection circuit 320 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> And will Figure 1 The level of the first through electrode 23 is shown to be driven to a predetermined logic level.

[0068] The second connection circuit 330 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> And will Figure 1 The level of the second through electrode 24 is shown driven to a predetermined logic level.

[0069] The third connection circuit 340 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> And will Figure 1 The level of the third through electrode 25 is shown driven to a predetermined logic level.

[0070] The fourth connection circuit 350 may be based on the second enable signal EN_TSV <2> and the second test data TD <2> And will Figure 1 The level of the fourth through-electrode 26 is shown to be driven to a predetermined logic level.

[0071] See also Fig.10The second control circuit 310 may be configured to perform inversion and NOR operations, and may be implemented to include inverters IV71 and IV72 , and NOR gates NOR71 and NOR72 .

[0072] The second control circuit 310 may generate a second enable signal EN_TSV based on the chip identification signal CID, the open test signal OPT, and the short test signal SHT. <2> and the second test data TD <2> When the chip identification signal CID is enabled to have a logic “high” level and any one of the open test signal OPT and the short test signal SHT is enabled to have a logic “high” level, the second control circuit 310 may generate the second enable signal EN_TSV enabled to have a logic “high” level. <2> When the chip identification signal CID is enabled to have a logic “high” level and any one of the open test signal OPT and the short test signal SHT is enabled to have a logic “high” level, the second control circuit 310 may generate the second test data TD enabled to have a logic “low” level. <2> .

[0073] Fig.11 Show Fig. 9 The configuration of the first connection circuit 320 included in the second test control circuit 31, together with Figure 1 The first through-electrode 23 is shown together.

[0074] See also Fig.11 , the first connection circuit 320 may include a second transmitter 321 and a second receiver 322 .

[0075] The second transmitter 321 may be enabled based on the second enable signal EN_TSV <2> and the second test data TD <2> The third internal node nd31 is driven to a predetermined logic level, and the third internal node nd31 is connected to the first through electrode 23 .

[0076] The second receiver 322 may receive and output a signal of the third internal node nd31. The second receiver 322 may receive a signal via the first through electrode 23 and may output a signal. The second receiver 322 may be implemented using a general receiver.

[0077] Fig. 9 Each of the second to fourth connection circuits 330, 340, and 350 shown in FIG. 1 may be implemented to have a Fig.11 The first connection circuit 320 is substantially the same circuit except for its input and output signals. Therefore, descriptions of the second to fourth connection circuits 330, 340 and 350 will be omitted hereinafter.

[0078] See also Fig.12, the second transmitter 321 may include a second pull-up / pull-down signal generating circuit 3211 and a second driving circuit 3212 .

[0079] The second pull-up / pull-down signal generating circuit 3211 may be configured to perform inversion, NAND, and NOR operations, and may be implemented to include an inverter IV81, a NAND gate NAND81, and a NOR gate NOR81. <2> When enabled to have a logic “high” level, the second pull-up / pull-down signal generating circuit 3211 may invert and buffer the second test data TD <2> To generate a second pull-up signal PU <2> When the second enable signal EN_TSV <2> When enabled to have a logic “high” level, the second pull-up / pull-down signal generating circuit 3211 may invert and buffer the second test data TD <2> To generate the second pull-down signal PD <2> When the second enable signal EN_TSV <2> is enabled to have a logic "high" level and the second test data TD <2> When enabled to have a logic “low” level, the second pull-up / pull-down signal generating circuit 3211 may generate a second pull-up signal PU having a logic “high” level. <2> and a second pull-down signal PD having a logic "high" level <2> .

[0080] The second driving circuit 3212 may be implemented to include: a PMOS transistor P81 coupled between the power supply voltage VDD terminal and the third internal node nd31 connected to the first through electrode 23; and an NMOS transistor N81 coupled between the third internal node nd31 and the ground voltage VSS terminal. <2> When the second pull-down signal PD has a logic “low” level, the second driving circuit 3212 can pull up the level of the third internal node nd31 to the power supply voltage VDD. <2> With a logic “high” level, the second driving circuit 3212 may pull down the level of the third internal node nd31 to the ground voltage VSS.

[0081] Fig.13 and Fig.14 A first test operation of a semiconductor device according to an embodiment of the present disclosure is shown.

[0082] In the following, reference will be made to Fig.13 The operations of the first test circuit 120 and the first connection circuit 320 connected to the first through-electrode 23 during the first test operation are described.

[0083] As reference Figure 2As described above, when the chip identification signal CID and the open circuit test signal OPT are enabled, the first control circuit 110 may generate the first enable signal EN_TSV having a logic “high” level. <1> and the first test data TD having a logic “low” level <1> When the chip identification signal CID and the open test signal OPT are enabled, the first control circuit 110 may generate the first open switch signal OP_SW enabled to have a logic “low” level. <1> .

[0084] As reference Fig. 9 As described above, when the chip identification signal CID and the open circuit test signal OPT are enabled, the second control circuit 310 may generate the second enable signal EN_TSV having a logic “high” level. <2> and the second test data TD having a logic “low” level <2> .

[0085] In the first resistor connection circuit 121, when the first open switch signal OP_SW <1> When enabled to have a logic “low” level, the first switch P21 may be turned on to electrically connect the first test resistor R21 to the first internal node nd11 connected to the first through electrode 23 .

[0086] The first transmitter 122 may be enabled based on the first enable signal EN_TSV having a logic “high” level. <1> and the first test data TD having a logic “low” level <1> , driving the level of the first through electrode 23 to a logic “low” level.

[0087] The second transmitter 321 may be enabled based on the second enable signal EN_TSV having a logic “high” level. <2> and the second test data TD having a logic “low” level <2> , the third internal node nd31 connected to the first through electrode 23 is electrically connected to the ground voltage VSS terminal. In this case, a first current path I1 may be provided between the power supply voltage VDD terminal and the ground voltage VSS terminal, and the power supply voltage VDD may be divided by the first current path I1 so as to determine the voltage level of the first internal node nd11. Fig.13 The ground voltage VSS terminal is not shown in FIG. 1 , but the ground voltage VSS terminal of the second transmitter 321 may correspond to Fig.12 The ground voltage VSS terminal is shown.

[0088] The first receiver 123 may detect a voltage level of the first internal node nd11 to generate a first internal detection signal IDET.

[0089] Because the open test signal OPT is enabled, the first output circuit 124 can generate the first flag signal FLAG from the first internal detection signal IDET. <1> .

[0090] In the following, reference will be made to Fig.14 1 and 2 are used to describe the voltage level of the first internal node nd11 for testing the open failure of the first through electrode 23 during the first test operation. Fig.14 In the figure, the abscissa represents the resistance value R of the first through-electrode 23, and the ordinate represents the voltage level of the first internal node nd11.

[0091] As described above, when the voltage level “V(nd11)” of the first internal node nd11 determined by the first current path I1 between the power voltage VDD terminal and the ground voltage VSS terminal is lower than half of the power voltage VDD, the first through-electrode 23 can be regarded as a normal through-electrode (PASS) without an open circuit failure.

[0092] In one embodiment, if the first through electrode 23 is regarded as a normal through electrode (PASS) without an open circuit fault, when the first test resistor R21 has a resistance value of 100 ohms, the first through electrode 23 may have a resistance value less than 100 ohms. Therefore, the voltage level "V(nd11)" of the first internal node nd11 may be lower than half of the power supply voltage VDD. In one embodiment, the resistance value of the first test resistor R21 may be set to correspond to the resistance value of the first through electrode 23 regarded as a normal through electrode without an open circuit fault.

[0093] On the contrary, when the voltage level “V(nd11)” of the first internal node nd11 determined by the first current path I1 between the power supply voltage VDD terminal and the ground voltage VSS terminal is higher than half of the power supply voltage VDD, the first through-electrode 23 can be regarded as an abnormal through-electrode (FAIL) having an open circuit failure.

[0094] In one embodiment, if the first through electrode 23 is regarded as an abnormal through electrode (PASS) having an open fault, when the first test resistor R21 has a resistance value of 100 ohms, the first through electrode 23 may have a resistance value greater than 100 ohms. Therefore, the voltage level "V(nd11)" of the first internal node nd11 may be higher than half of the power supply voltage VDD.

[0095] In the following, reference will be made to Fig.15 Operations of the first test circuit 120 and the second connection circuit 330 connected to corresponding ones of the first through-electrodes 23 and the second through-electrodes 24 during the second test operation are described.

[0096] As reference Figure 2As described above, when the chip identification signal CID and the short-circuit test signal SHT are enabled, the first control circuit 110 can generate a first enable signal EN_TSV having a logic “high” level. <1> and the first test data TD having a logic “low” level <1> When the chip identification signal CID and the short test signal SHT are enabled, the first control circuit 110 may generate the first short switch signal SH_SW enabled to have a logic “low” level. <1> .

[0097] As reference Fig. 9 As described above, when the chip identification signal CID and the short-circuit test signal SHT are enabled, the second control circuit 310 can generate a second enable signal EN_TSV having a logic “high” level. <2> and the second test data TD having a logic “low” level <2> .

[0098] In the first resistor connection circuit 121, when the first short-circuit switch signal SH_SW <1> When enabled to have a logic “low” level, the second switch P22 may be turned on to electrically connect the third test resistor R22 to the first internal node nd11 connected to the first through electrode 23 .

[0099] The first transmitter 122 may be enabled based on the first enable signal EN_TSV having a logic “high” level. <1> and the first test data TD having a logic “low” level <1> , driving the level of the first through electrode 23 to a logic “low” level.

[0100] The third transmitter 331 of the second connection circuit 330 may be enabled based on the second enable signal EN_TSV having a logic “high” level. <2> and the second test data TD having a logic “low” level <2> , the fourth internal node nd32 connected to the second through electrode 24 is electrically connected to the ground voltage VSS terminal. In this case, a second current path I2 may be provided between the power supply voltage VDD terminal and the ground voltage VSS terminal, and the power supply voltage VDD may be divided by the second current path I2 so as to determine the voltage level of the internal node nd11. Fig.15 The ground voltage VSS terminal is not shown in FIG. 1 , but the ground voltage VSS terminal of the third transmitter 331 may correspond to Fig.12 The ground voltage VSS terminal is shown.

[0101] The first receiver 123 may detect a voltage level of the first internal node nd11 to generate a first internal detection signal IDET.

[0102] Because the short test signal SHT is enabled, the first output circuit 124 may generate the first flag signal FLAG from the first internal detection signal IDET. <1> .

[0103] In the following, reference will be made to Fig.16 1 and 2 are used to describe the voltage level of the first internal node nd11 for testing the short circuit failure between the first through electrode 23 and the second through electrode 24 during the second test operation. Fig.16 In the figure, the abscissa represents the resistance value R between the first through-electrode 23 and the second through-electrode 24, and the ordinate represents the voltage level of the first internal node nd11.

[0104] As described above, when the voltage level “V(nd11)” of the first internal node nd11 determined by the first current path I2 between the power supply voltage VDD terminal and the ground voltage VSS terminal is lower than half of the power supply voltage VDD, the second current path I2 can be regarded as an abnormal current path (FAIL) having a short circuit fault, which is caused by a leakage current path between the first through electrode 23 and the second through electrode 24.

[0105] In one embodiment, if the second current path I2 is regarded as an abnormal current path (FAIL) with a short circuit fault, when the third test resistor R22 has a resistance value of 100 ohms, the resistance value between the first through electrode 23 and the second through electrode 24 may be equal to or less than 100 ohms. Therefore, the voltage level "V(nd11)" of the first internal node nd11 may be lower than half of the power supply voltage VDD. In one embodiment, the resistance value of the third test resistor R22 may be set to correspond to the resistance value between the first through electrode 23 and the second through electrode 24 when there is no short circuit fault between the first through electrode 23 and the second through electrode 24. In some embodiments, the third test resistor R22 has a resistance value greater than the first test resistor R21.

[0106] On the contrary, when the voltage level “V(nd11)” of the first internal node nd11 determined by the second current path I2 between the power supply voltage VDD terminal and the ground voltage VSS terminal is higher than half of the power supply voltage VDD, the second current path I2 can be regarded as a normal current path (PASS) without a short circuit fault between the first through electrode 23 and the second through electrode 24.

[0107] In one embodiment, if the second current path I2 is regarded as a normal current path (PASS) without a short-circuit fault, when the third test resistor R22 has a resistance value of 100 ohms, the resistance value between the first through electrode 23 and the second through electrode 24 may be greater than 100 ohms. Therefore, the voltage level "V(nd11)" of the first internal node nd11 may be higher than half of the power supply voltage VDD.

[0108] In the following we will refer to Fig.17, the first test operation according to the embodiment is described in conjunction with an example in which all of the first to fourth through electrodes 23 ˜ 26 have no open-circuit failure and an example in which the second through electrode 24 has an open-circuit failure.

[0109] First, an example in which all of the first to fourth through electrodes 23 to 26 have no open failure will be described hereinafter.

[0110] At a time point “ T1 ”, the open test signal OPT may be enabled to have a logic “high” level for performing a first test operation.

[0111] The first control circuit 110 may receive the chip identification signal CID and the open circuit test signal OPT to generate a first selection signal SEL enabled to have a logic “high” level. <1> , is enabled as a first enable signal EN_TSV having a logic “high” level <1> , and the first test data TD having a logic “low” level <1> The first control circuit 110 may receive the chip identification signal CID and the open test signal OPT to generate a first open switch signal OP_SW enabled to have a logic “low” level. <1> .

[0112] The second control circuit 310 may receive the chip identification signal CID and the open circuit test signal OPT to generate a second enable signal EN_TSV enabled to have a logic “high” level. <2> and the second test data TD having a logic “low” level <2> .

[0113] The first test circuit 120 may be configured to enable the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> , driving the level of the first through electrode 23 to a logic “low” level. The first test circuit 120 may respond to the first open switch signal OP_SW <1> The first test resistor R21 is electrically connected to the first through-electrode 23 .

[0114] The first connection circuit 320 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> The first through-electrode 23 is electrically connected to the ground voltage VSS terminal.

[0115] The first test circuit 120 may detect a voltage level of the first internal node nd11 to generate a first flag signal FLAG having a logic “high” level. <1> .

[0116] At time point “T2”, the first control circuit 110 may receive the chip identification signal CID and the open circuit test signal OPT to generate a second selection signal SEL enabled to a logic “high” level. <2> , a first enable signal EN_TSV enabled to a logic “high” level <1> , and the first test data TD having a logic “low” level <1> The first control circuit 110 may receive the chip identification signal CID and the open test signal OPT to generate a second open switch signal OP_SW enabled to have a logic “low” level. <2> .

[0117] The second test circuit 130 may be configured to generate a first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> , driving the level of the second through electrode 24 to a logic “low” level. The second test circuit 130 may respond to the second open switch signal OP_SW <2> And a second test resistor (not shown) is electrically connected to the second through-electrode 24 .

[0118] The second connection circuit 330 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> The second through-electrode 24 is electrically connected to the ground voltage VSS terminal.

[0119] The second test circuit 130 may detect a voltage level of a second internal node (not shown) to generate a second flag signal FLAG having a logic “high” level. <2> .

[0120] The first test operation for the third through electrode 25 may be the same as the above operation performed at the first time point "T1", and the first test operation for the fourth through electrode 26 may be the same as the above operation performed at the second time point "T2". Therefore, the first test operation for the third through electrode 25 and the fourth through electrode 26 will be omitted below.

[0121] At the time point “ T3 ”, the synthesized signal generation circuit 161 may synthesize the first to fourth flag signals FLAG<1:4> to generate a synthesized signal SUM having a logic “high” level.

[0122] At the time point “ T4 ”, since the open test signal OPT is disabled to have a logic “low” level, the output control signal generation circuit 162 may generate the output control signal OUT_CON having a logic “high” level.

[0123] Because the output control signal OUT_CON is enabled to have a logic “high” level, the detection signal generation circuit 163 may generate the detection signal TSV_DET having a logic “high” level from the synthesis signal SUM.

[0124] According to the above description, when all the first to fourth through electrodes 23 to 26 have no open failure, the detection signal TSV_DET may be generated to have a logic “high” level. Therefore, the semiconductor device 1 may regard the first to fourth through electrodes 23 to 26 as normal through electrodes without any open failure.

[0125] Next, an example in which the second through-electrode 24 has an open failure will be described hereinafter.

[0126] At a time point “ T1 ”, the open test signal OPT may be enabled to have a logic “high” level for performing a first test operation.

[0127] The first control circuit 110 may receive the chip identification signal CID and the open circuit test signal OPT to generate a first selection signal SEL enabled to have a logic “high” level. <1> , is enabled as a first enable signal EN_TSV having a logic “high” level <1> , the first test data TD having a logic “low” level <1> The first control circuit 110 may receive the chip identification signal CID and the open test signal OPT to generate a first open switch signal OP_SW enabled to have a logic “low” level. <1> .

[0128] The second control circuit 310 may receive the chip identification signal CID and the open circuit test signal OPT to generate a second enable signal EN_TSV enabled to have a logic “high” level. <2> , and a second test data TD having a logic “low” level <2> .

[0129] The first test circuit 120 may be configured to enable the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> The first test circuit 120 may respond to the first open switch signal OP_SW <1> The first test resistor R21 is electrically connected to the first through-electrode 23 .

[0130] The first connection circuit 320 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> The first through-electrode 23 is electrically connected to the ground voltage VSS terminal.

[0131] The first test circuit 120 may detect a voltage level of the first internal node nd11 to generate a first flag signal FLAG having a logic “high” level. <1> .

[0132] At the time point “T2”, the first control circuit 110 may receive the chip identification signal CID and the open circuit test signal OPT to generate a second open circuit switch signal OP_SW enabled to have a logic “low” level. <2> .

[0133] The second test circuit 130 may be configured to generate a first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> The second test circuit 130 may respond to the second open switch signal OP_SW <2> And a second test resistor (not shown) is electrically connected to the second through-electrode 24 .

[0134] The second connection circuit 330 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> The second through-electrode 24 is electrically connected to the ground voltage VSS terminal.

[0135] The second test circuit 130 may detect a voltage level of a second internal node (not shown) to generate a second flag signal FLAG having a logic “low” level. <2> .

[0136] The first test operation for the third through electrode 25 may be the same as the above operation performed at the first time point "T1", and the first test operation for the fourth through electrode 26 may be the same as the above operation performed at the second time point "T2". Therefore, the first test operation for the third through electrode 25 and the fourth through electrode 26 will be omitted below.

[0137] At the time point “ T3 ”, the synthesized signal generation circuit 161 may synthesize the first to fourth flag signals FLAG<1:4> to generate a synthesized signal SUM having a logic “low” level.

[0138] At the time point “ T4 ”, since the open test signal OPT is disabled to have a logic “low” level, the output control signal generation circuit 162 may generate the output control signal OUT_CON having a logic “high” level.

[0139] Because the output control signal OUT_CON is enabled to have a logic “high” level, the detection signal generation circuit 163 may generate the detection signal TSV_DET having a logic “low” level from the synthesis signal SUM.

[0140] According to the above description, when the second through electrode 24 among the first to fourth through electrodes 23 to 26 has an open fault, the detection signal TSV_DET may be generated to have a logic “low” level. Therefore, the semiconductor device 1 may recognize that at least one of the first to fourth through electrodes 23 to 26 has an open fault.

[0141] In the following we will refer to Fig.18 The second test operation according to the embodiment is described in conjunction with an example in which there is no short-circuit failure between the first through electrode 23 and the second through electrode 24 and an example in which there is a short-circuit failure between the first through electrode 23 and the second through electrode 24 .

[0142] First, an example in which there is no short-circuit failure between the first through electrode 23 and the second through electrode 24 will be described hereinafter.

[0143] At a time point “ T11 ”, the short test signal SHT may be enabled to have a logic “high” level for performing a second test operation.

[0144] The first control circuit 110 may receive the chip identification signal CID and the short test signal SHT to generate a first selection signal SEL enabled to have a logic “high” level. <1> , is enabled as a first enable signal EN_TSV having a logic “high” level <1> , the first test data TD having a logic “low” level <1> The first control circuit 110 may receive the chip identification signal CID and the short-circuit test signal SHT to generate a first short-circuit switch signal SH_SW enabled to have a logic “low” level. <1> .

[0145] The second control circuit 310 may receive the chip identification signal CID and the short test signal SHT to generate a second enable signal EN_TSV enabled to have a logic “high” level. <2> and the second test data TD having a logic “low” level <2> .

[0146] The first test circuit 120 may be configured to enable the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> , driving the level of the first through electrode 23 to a logic “low” level. The first test circuit 120 may respond to the first short-circuit switch signal SH_SW <1> The third test resistor R22 is electrically connected to the first through-electrode 23 .

[0147] The second connection circuit 330 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> The second through-electrode 24 is electrically connected to the ground voltage VSS terminal.

[0148] The first test circuit 120 may detect a voltage level of the first internal node nd11 to generate a first flag signal FLAG having a logic “high” level. <1> In this case, the second to fourth flag signals FLAG<2:4> may be generated to have a logic “high” level.

[0149] The synthesized signal generation circuit 161 may synthesize the first to fourth flag signals FLAG<1:4> to generate a synthesized signal SUM having a logic “high” level.

[0150] At the time point “ T12 ”, since the short test signal SHT is disabled to have a logic “low” level, the output control signal generation circuit 162 may generate the output control signal OUT_CON having a logic “high” level.

[0151] Because the output control signal OUT_CON is enabled to have a logic “high” level, the detection signal generation circuit 163 may generate the detection signal TSV_DET having a logic “high” level from the synthesis signal SUM.

[0152] According to the above description, when there is no short circuit failure between the first through electrode 23 and the second through electrode 24 , the detection signal TSV_DET may be generated to have a logic “high” level. Therefore, the semiconductor device 1 may recognize that there is no short circuit failure between the first to fourth through electrodes 23 ˜ 26 .

[0153] Next, an example in which a short-circuit failure exists between the first through-electrode 23 and the second through-electrode 24 will be described hereinafter.

[0154] At a time point “ T11 ”, the short test signal SHT may be enabled to have a logic “high” level for performing a second test operation.

[0155] The first control circuit 110 may receive the chip identification signal CID and the short test signal SHT to generate a first selection signal SEL enabled to have a logic “high” level. <1> , is enabled as a first enable signal EN_TSV having a logic “high” level <1> , and the first test data TD having a logic “low” level <1> The first control circuit 110 may receive the chip identification signal CID and the short-circuit test signal SHT to generate a first short-circuit switch signal SH_SW enabled to have a logic “low level”. <1> .

[0156] The second control circuit 310 may receive the chip identification signal CID and the short test signal SHT to generate a second enable signal EN_TSV enabled to have a logic “high” level. <2> and the second test data TD having a logic “low” level <2> .

[0157] The first test circuit 120 may be configured to enable the first enable signal EN_TSV based on the first enable signal EN_TSV. <1> And the first test data TD <1> , driving the level of the first through electrode 23 to a logic “low” level. The first test circuit 120 may respond to the first short-circuit switch signal SH_SW <1> The third test resistor R22 is electrically connected to the first through-electrode 23 .

[0158] The second connection circuit 330 may be configured based on the second enable signal EN_TSV <2> and the second test data TD <2> The second through-electrode 24 is electrically connected to the ground voltage VSS terminal.

[0159] The first test circuit 120 may detect a voltage level of the first internal node nd11 to generate a first flag signal FLAG having a logic “low” level. <1> In this case, the second to fourth flag signals FLAG<2:4> may be generated to have a logic “high” level.

[0160] The synthesized signal generation circuit 161 may synthesize the first to fourth flag signals FLAG<1:4> to generate a synthesized signal SUM having a logic “low” level.

[0161] At the time point “ T12 ”, since the short test signal SHT is disabled to have a logic “low” level, the output control signal generation circuit 162 may generate the output control signal OUT_CON having a logic “high” level.

[0162] Because the output control signal OUT_CON is enabled to have a logic “high” level, the detection signal generation circuit 163 may generate the detection signal TSV_DET having a logic “low” level from the synthesis signal SUM.

[0163] According to the above description, when a short failure occurs between the first through electrode 23 and the second through electrode 24 , the detection signal TSV_DET may be generated to have a logic “low” level. Therefore, the semiconductor device 1 may recognize that a short failure occurs between the first to fourth through electrodes 23 ˜ 26 .

[0164] As described above, according to the embodiment, the semiconductor device can electrically connect a plurality of through-electrodes to a test resistor having a resistance value corresponding to an open circuit fault or a short circuit fault, and can detect the voltage level of the internal nodes connected to the plurality of through-electrodes to test the open circuit fault or the short circuit fault of the plurality of through-electrodes.

Claims

1. A semiconductor device, comprising: a first semiconductor chip; as well as a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through the first through-electrode and the second through-electrode, wherein, during a first test operation, the first semiconductor chip electrically connects the first through-electrode and the second through-electrode to a first test resistor and a second test resistor, and During the first test operation, the first semiconductor chip detects voltage levels of a first internal node and a second internal node respectively coupled to the first through-electrode and the second through-electrode to test an open circuit failure of the first through-electrode and the second through-electrode, and the voltage levels of the first internal node and the second internal node are determined by the resistance value of the first test resistor and the resistance value of the second test resistor and the resistance value of the first through-electrode and the resistance value of the second through-electrode.

2. The semiconductor device according to claim 1, in, The resistance value of the first test resistor is set to correspond to the resistance value of the first through-electrode regarded as a normal through-electrode without an open-circuit failure; as well as The resistance value of the second test resistor is set to correspond to the resistance value of the second through-electrode which is regarded as a normal through-electrode without an open-circuit failure.

3. The semiconductor device according to claim 1, in, The first semiconductor chip is configured to include a first test control circuit; as well as Wherein, when the open circuit test signal is enabled to perform the first test operation, the first test control circuit is configured to sequentially connect the first test resistor and the second test resistor to corresponding through electrodes of the first through electrode and the second through electrode, and is configured to detect the voltage levels of the first internal node and the second internal node to sequentially test the open circuit faults of the first through electrode and the second through electrode.

4. The semiconductor device according to claim 3, wherein: The first test control circuit comprises: A first control circuit is configured to generate a first enable signal and a first test data, wherein the first enable signal and the first test data are enabled when the chip identification signal and the open circuit test signal are enabled; and configured to generate a first open circuit switch signal and a second open circuit switch signal, wherein the first open circuit switch signal and the second open circuit switch signal are sequentially enabled when the chip identification signal and the open circuit test signal are enabled; a first test circuit configured to drive the first through-electrode to a predetermined logic level based on the first enable signal and the first test data, configured to electrically connect the first test resistor to the first through-electrode when the first open switch signal is enabled, and configured to detect a voltage level of the first internal node to generate a first flag signal; a second test circuit configured to drive the second through-electrode to the predetermined logic level based on the first enable signal and the first test data, configured to electrically connect the second test resistor to the second through-electrode when the second open switch signal is enabled, and configured to detect a voltage level of the second internal node to generate a second flag signal; and The sensing circuit is configured to synthesize the first flag signal and the second flag signal to generate a detection signal when the open circuit test signal is enabled.

5. The semiconductor device according to claim 4, wherein: The first control circuit comprises: A selection signal generating circuit is configured to generate a first selection signal and a second selection signal, wherein the first selection signal and the second selection signal are sequentially enabled when the chip identification signal and the open circuit test signal are enabled; a logic circuit configured to generate the first enable signal and the first test data that are enabled when the open circuit test signal is enabled; and The first switch signal generating circuit is configured to generate the first open switch signal and the second open switch signal from the first selection signal and the second selection signal when the open test signal is enabled.

6. The semiconductor device according to claim 4, wherein: The first test circuit comprises: a first resistor connection circuit coupled between a power supply voltage terminal and the first internal node connected to the first through-electrode and configured to connect the first test resistor to the first internal node when the first open switch signal is enabled; a first transmitter configured to drive the first through-electrode to the predetermined logic level based on the first enable signal and the first test data; a first receiver configured to detect a voltage level of the first internal node to generate a first internal detection signal; and The first output circuit is configured to generate the first flag signal from the first internal detection signal when the open circuit test signal is enabled.

7. The semiconductor device according to claim 6, in, The first transmitter comprises: a first pull-up / pull-down signal generating circuit configured to: invert and buffer the first test data to generate a first pull-up signal when the first enable signal is enabled, and invert and buffer the first test data to generate a first pull-down signal when the first enable signal is enabled, and a first driving circuit configured to pull up a voltage level of the first internal node to a power supply voltage based on the first pull-up signal, and pull down a voltage level of the first internal node to a ground voltage based on the first pull-down signal, and The first receiver is configured to buffer the voltage signal of the first internal node to generate the first internal detection signal.

8. The semiconductor device according to claim 4, wherein: The second test circuit comprises: a second resistor connection circuit coupled between a power supply voltage terminal and the second internal node connected to the second through-electrode and configured to connect the second test resistor to the second internal node when the second open switch signal is enabled; a second transmitter configured to drive the second through-electrode to the predetermined logic level based on the first enable signal and the first test data; a second receiver configured to detect a voltage level of the second internal node to generate a second internal detection signal; and The second output circuit is configured to generate the second flag signal from the second internal detection signal when the open circuit test signal is enabled.

9. The semiconductor device according to claim 1, wherein: The second semiconductor chip includes a second test control circuit that electrically connects the first and second through electrodes to a ground voltage terminal when an open test signal is enabled to perform the first test operation.

10. The semiconductor device according to claim 9, wherein The second test control circuit comprises: a second control circuit configured to generate a second enable signal and a second test data, wherein the second enable signal and the second test data are enabled when the chip identification signal and the open circuit test signal are enabled; a first connection circuit configured to electrically connect the first through-electrode to the ground voltage terminal based on the second enable signal and the second test data; and A second connection circuit is configured to electrically connect the second through-electrode to the ground voltage terminal based on the second enable signal and the second test data.

11. The semiconductor device according to claim 10, wherein: The first connection circuit includes a third transmitter that electrically connects a third internal node connected to the first through-electrode to the ground voltage terminal based on the second enable signal and the second test data.

12. The semiconductor device according to claim 10, wherein: The second connection circuit includes a fourth transmitter that electrically connects a fourth internal node connected to the second through-electrode to the ground voltage terminal based on the second enable signal and the second test data.

13. The semiconductor device according to claim 1, in, During a second test operation, the first semiconductor chip electrically connects the first through-electrode to a third test resistor, and During the second test operation, the first semiconductor chip detects the voltage level of the first internal node to test a short circuit fault between the first through-electrode and the second through-electrode, and the voltage level of the first internal node is determined by the resistance value of the third test resistor and the resistance values ​​of the first through-electrode and the second through-electrode.

14. The semiconductor device according to claim 13, wherein: The resistance value of the third test resistor is set to correspond to a resistance value between the first through-electrode and the second through-electrode when a short circuit failure does not occur between the first through-electrode and the second through-electrode.

15. A semiconductor device comprising: a first semiconductor chip; as well as a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through the first through-electrode and the second through-electrode, wherein, during a first test operation, the first semiconductor chip is configured to electrically connect the first through-electrode and the second through-electrode to a first test resistor and a second test resistor, and is configured to detect voltage levels of a first internal node and a second internal node respectively connected to the first through-electrode and the second through-electrode to test an open circuit failure of the first through-electrode and the second through-electrode, the voltage levels of the first internal node and the second internal node being determined by the resistance values ​​of the first test resistor and the second test resistor and the first through-electrode and the second through-electrode, Wherein, during a second test operation, the first semiconductor chip is configured to electrically connect the first through-electrode to a third test resistor, wherein a current path is formed through the third test resistor, the first through-electrode and the second through-electrode, and is configured to detect a voltage level of the first internal node to test a short circuit fault between the first through-electrode and the second through-electrode, wherein the voltage level of the first internal node is determined by the resistance value of the third test resistor and the resistance values ​​of the first through-electrode and the second through-electrode.

16. The semiconductor device according to claim 15, in, The resistance value of the first test resistor is set to correspond to the resistance value of the first through-electrode regarded as a normal through-electrode without an open-circuit failure; as well as The resistance value of the second test resistor is set to correspond to the resistance value of the second through-electrode which is regarded as a normal through-electrode without an open-circuit failure.

17. The semiconductor device according to claim 15, wherein: The resistance value of the third test resistor is set to correspond to a resistance value between the first through-electrode and the second through-electrode when a short circuit failure does not occur between the first through-electrode and the second through-electrode.

18. The semiconductor device according to claim 15, wherein: The resistance value of the third test resistor is set to be greater than the resistance values ​​of the first test resistor and the second test resistor.

19. The semiconductor device according to claim 15, in, The first semiconductor chip is configured to include a first test control circuit; as well as wherein, when an open circuit test signal is enabled to perform the first test operation, the first test control circuit is configured to sequentially connect the first test resistor and the second test resistor to corresponding ones of the first through-electrode and the second through-electrode, and is configured to detect voltage levels of the first internal node and the second internal node to sequentially test open circuit faults of the first through-electrode and the second through-electrode; and Wherein, when the short-circuit test signal is enabled to perform the second test operation, the first test control circuit is configured to electrically connect the third test resistor to the first through-electrode, and is configured to detect the voltage level of the first internal node to test the short-circuit fault between the first through-electrode and the second through-electrode.

20. The semiconductor device according to claim 19, wherein The first test control circuit comprises: A first control circuit is configured to generate a first enable signal and a first test data, wherein the first enable signal and the first test data are enabled when the chip identification signal is enabled and any one of the open circuit test signal and the short circuit test signal is enabled; configured to generate a first open circuit switch signal and a second open circuit switch signal, wherein the first open circuit switch signal and the second open circuit switch signal are sequentially enabled when the chip identification signal and the open circuit test signal are enabled; and configured to generate a short circuit switch signal, wherein the short circuit switch signal is enabled when the chip identification signal and the short circuit test signal are enabled; a first test circuit configured to drive the first through-electrode to a predetermined logic level based on the first enable signal and the first test data, configured to electrically connect the first test resistor to the first through-electrode when the first open switch signal is enabled, configured to electrically connect the third test resistor to the first through-electrode when the short switch signal is enabled, and configured to detect a voltage level of the first internal node to generate a first flag signal; a second test circuit configured to drive the second through-electrode to the predetermined logic level based on the first enable signal and the first test data, configured to electrically connect the second test resistor to the second through-electrode when the second open switch signal is enabled, and configured to detect a voltage level of the second internal node to generate a second flag signal; and The sensing circuit is configured to synthesize the first flag signal and the second flag signal to generate a detection signal when the open test signal or the short test signal is enabled.

21. The semiconductor device according to claim 20, wherein: The first control circuit comprises: A selection signal generating circuit, configured to generate a first selection signal and a second selection signal that are sequentially enabled when the chip identification signal and the open circuit test signal are enabled; and configured to generate an enabled first selection signal when the chip identification signal and the short circuit test signal are enabled; a logic circuit configured to generate the first enable signal and the first test data that are enabled when at least one of the open test signal and the short test signal is enabled; and A first switch signal generating circuit is configured to generate the first open switch signal and the second open switch signal from the first selection signal and the second selection signal when the open test signal is enabled, and is configured to generate the short switch signal from the first selection signal when the short test signal is enabled.

22. The semiconductor device according to claim 20, wherein: The first test circuit comprises: a first resistor connecting circuit coupled between a power supply voltage terminal and the first internal node connected to the first through-electrode, configured to connect the first test resistor to the first internal node when the first open switch signal is enabled, and configured to connect the third test resistor to the first internal node when the short switch signal is enabled; a first transmitter configured to drive the first through-electrode to the predetermined logic level based on the first enable signal and the first test data; a first receiver configured to detect a voltage level of the first internal node to generate a first internal detection signal; and The first output circuit is configured to generate the first flag signal from the first internal detection signal when at least one of the open test signal and the short test signal is enabled.

23. The semiconductor device according to claim 20, wherein: The second test circuit comprises: a second resistor connection circuit coupled between a power supply voltage terminal and the second internal node connected to the second through-electrode and configured to connect the second test resistor to the second internal node when the second open switch signal is enabled; a second transmitter configured to drive the second through-electrode to the predetermined logic level based on the first enable signal and the first test data; a second receiver configured to detect a voltage level of the second internal node to generate a second internal detection signal; and The second output circuit is configured to generate the second flag signal from the second internal detection signal when the open circuit test signal is enabled.

24. The semiconductor device according to claim 15, wherein: The second semiconductor chip includes a second test control circuit, which electrically connects the first through-electrode and the second through-electrode to a ground voltage terminal when at least one of an open test signal is enabled to perform the first test operation and a short test signal is enabled to perform the second test operation.

25. The semiconductor device according to claim 24, wherein: The second test control circuit comprises: a second control circuit configured to generate a second enable signal and a second test data, wherein the second enable signal and the second test data are enabled when the chip identification signal is enabled and at least one of the open circuit test signal and the short circuit test signal is enabled; a first connection circuit configured to electrically connect the first through-electrode to the ground voltage terminal based on the second enable signal and the second test data; and A second connection circuit is configured to electrically connect the second through-electrode to the ground voltage terminal based on the second enable signal and the second test data.

26. The semiconductor device according to claim 25, wherein: The first connection circuit includes a third transmitter that electrically connects a third internal node connected to the first through-electrode to the ground voltage terminal based on the second enable signal and the second test data.

27. The semiconductor device according to claim 25, wherein: The second connection circuit includes a fourth transmitter that electrically connects a fourth internal node connected to the second through-electrode to the ground voltage terminal based on the second enable signal and the second test data.

28. A semiconductor device comprising: a first semiconductor chip; as well as a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip through the first through-electrode and the second through-electrode, wherein, during a second test operation, the first semiconductor chip electrically connects the first through-electrode to a third test resistor, wherein a current path is formed through the third test resistor, the first through-electrode, and the second through-electrode, and During the second test operation, the first semiconductor chip detects a voltage level of a first internal node connected to the first through-electrode to test a short circuit fault between the first through-electrode and the second through-electrode, and the voltage level of the first internal node is determined by the resistance value of the third test resistor and the resistance values ​​of the first through-electrode and the second through-electrode.

Images