Display device and method of manufacturing a display device

Abstract

Disclosed are a display device and a method of manufacturing the same. The display device includes a substrate including a first transmissive area, a second transmissive area, and a pixel area between the first transmissive area and the second transmissive area, a first pixel electrode in the pixel area, a first intermediate layer disposed on the first pixel electrode to emit light of a first color, and an insulating layer covering edges of the first pixel electrode and defining a first emission area by exposing a first opening of a portion of the first pixel electrode. A first partition wall is disposed on the insulating layer between the first emission area and the first transmissive area. A second partition wall is disposed on the insulating layer between the first emission area and the second transmissive area. An opposite electrode is disposed on the first intermediate layer in the pixel area and partially contacts the first partition wall and the second partition wall.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0083943, filed on July 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] One or more exemplary embodiments relate to a display apparatus, and more particularly, to a display apparatus including a transmissive region in a display region in which transmittance and distortion of a color gamut of the display region are simultaneously improved. BACKGROUND

[0004] Display apparatuses have been incorporated into a wide variety of electronic devices. Recent size and weight reductions of display apparatuses have expanded the types of electronic devices that include display apparatuses. Among the different types of display apparatuses, organic light emitting display apparatuses provide a wide viewing angle, good contrast, and a fast response speed, and thus are attracting attention as next-generation display apparatuses.

[0005] An organic light emitting display apparatus includes a plurality of pixel units having (sub)pixels, and the (sub)pixels include organic light emitting diodes. The organic light emitting diodes include an intermediate layer having an emission layer between a pixel electrode and a counter electrode. In such an organic light emitting display apparatus, emission and the degree of emission of each pixel can be controlled by using a thin film transistor electrically connected to the pixel electrode. The counter electrode is integrally formed over the plurality of (sub)pixels.

[0006] The emission layer can be patterned and deposited by using a mask (e.g., a fine metal mask (FMM)) that is open to respective subpixels. However, in existing display apparatuses, when a pattern layer is deposited by using a mask having openings corresponding to pattern regions, a shadow region can be formed due to the spread of a deposition material to a space between the uppermost layer and the mask. Accordingly, the deposition material is also deposited outside the pattern regions. SUMMARY

[0007] One or more exemplary embodiments include a display apparatus including a transmissive region in a display region in which transmittance and distortion of a color gamut of the display region are simultaneously improved. However, this is only an example, and exemplary embodiments of inventive concepts are not limited thereto.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of an implementation presented herein.

[0009] According to one or more example embodiments, a display device includes a substrate including a first transmissive area, a second transmissive area, and a pixel area between the first transmissive area and the second transmissive area. A first pixel electrode is in the pixel area. A first intermediate layer is disposed on the first pixel electrode. The first intermediate layer is configured to emit light of a first color. An insulating layer covers edges of the first pixel electrode and defines a first emission area through a first opening exposing a portion of the first pixel electrode. A first partition wall is disposed on the insulating layer between the first emission area and the first transmissive area. A second partition wall is disposed on the insulating layer between the first emission area and the second transmissive area. An opposing electrode is disposed on the first intermediate layer in the pixel area, the opposing electrode partially contacting the first partition wall and the second partition wall.

[0010] An upper surface of the first partition wall can include a first portion adjacent to the first emission area and a second portion adjacent to the first transmissive area, and the first portion can be in contact with the opposing electrode.

[0011] The second portion can not overlap the opposing electrode.

[0012] The display device can further include a material layer disposed on the opposing electrode, and the second portion can directly contact the material layer.

[0013] The display device can further include a second pixel electrode spaced apart from the first pixel electrode in a first direction in the pixel area, a second intermediate layer disposed on the second pixel electrode and emitting light of a second color, a third pixel electrode spaced apart from the second pixel electrode in the first direction in the pixel area, and a third intermediate layer disposed on the third pixel electrode and emitting light of a third color, wherein the insulating layer can cover edges of the second pixel electrode and edges of the third pixel electrode, and can define a second emission area through a second opening exposing a central portion of the second pixel electrode and a third emission area through a third opening exposing a central portion of the third pixel electrode, and the first partition wall can extend between the third emission area and the first transmissive area in the first direction.

[0014] The second partition wall can extend between the third emission area and the second transmissive area in the first direction.

[0015] A length of the first partition wall in the first direction can be the same as a length of the second partition wall in the first direction.

[0016] The length of the first partition wall and the length of the second partition wall in the first direction can be less than or equal to about 300 µm.

[0017] Widths of the first partition wall and the second partition wall in a second direction, which intersects the first direction, can be the same.

[0018] The first and second partition walls can have a width in the second direction of less than or equal to about 30 µm.

[0019] The first and second partition walls can have a height of less than or equal to about 3.5 µm.

[0020] The display device can further include a first support partition wall disposed on the insulating layer between the first and second openings in a second direction intersecting the first direction.

[0021] The display device can further include a second support partition wall disposed on the insulating layer between the second and third openings in the second direction.

[0022] The common electrode can cover the first and second support partition walls.

[0023] The first support partition wall can extend in the second direction and can be connected to the first partition wall at one side and to the second partition wall at the other side.

[0024] In the pixel area, at least one pixel portion can be disposed, and the at least one pixel portion can include a plurality of light emitting diodes emitting different colors of light, and the plurality of light emitting diodes can include a first light emitting diode including a first pixel electrode, a second light emitting diode including a second pixel electrode, and a third light emitting diode including a third pixel electrode.

[0025] The pixel portion can include a first pixel portion and a second pixel portion in the first direction, and the display device can further include a third support partition wall disposed on the insulating layer between the first and second pixel portions in the second direction.

[0026] The first and second partition walls can correspond to the first and second pixel portions, respectively.

[0027] The display device can further include a multilayer disposed between the insulating layer and the substrate and including at least one of an organic insulating layer and an inorganic insulating layer, and the multilayer can include an opening region corresponding to the first and second transmission regions, respectively.

[0028] There can be a plurality of first transmission regions and a plurality of second transmission regions in the first direction, the pixel area being between the plurality of first transmission regions and the plurality of second transmission regions, the pixel area extending in the first direction, and the common electrode can be integrally formed in the pixel area between the plurality of first transmission regions and the plurality of second transmission regions.

[0029] In an example embodiment, a method for manufacturing a display device includes forming a substrate including a first transmissive region, a second transmissive region, and a pixel region between the first transmissive region and the second transmissive region. A pixel electrode is formed in the pixel region. An intermediate layer is formed on the pixel electrode, the intermediate layer configured to emit light. An insulating layer is formed covering edges of the pixel electrode and defining an emission region through an opening exposing a portion of the pixel electrode. A first partition wall and a second partition wall having first portions and second portions are formed on the insulating layer. A mask is formed supported on the second portions of the first partition wall and the second partition wall. A counter electrode is formed on the intermediate layer by depositing a deposition material on an opening area of the mask, the opening area of the mask including the first portions of the first partition wall and the first portions of the second partition wall.

[0030] In an example embodiment, a display device includes a substrate including a first transmissive region, a second transmissive region, and a pixel region between the first transmissive region and the second transmissive region. The pixel region includes at least one pixel portion having a plurality of light emitting diodes configured to emit light of different colors. The plurality of light emitting diodes are spaced apart in a first direction. Each of the plurality of light emitting diodes includes a pixel electrode, an intermediate layer disposed on the pixel electrode, an insulating layer covering edges of the pixel electrode and defining an emission region through an opening exposing a portion of the pixel electrode, and a counter electrode disposed on the intermediate layer in the pixel region. A support partition wall is disposed on the insulating layer between the openings of the light emitting diodes adjacent in the first direction. The support partition wall extends in a second direction intersecting the first direction.

[0031] In addition to the details above, other aspects, features and advantages will become apparent from the detailed description, the claims, and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1A is a perspective view of a display device to which an embodiment of the present inventive concept is directed;

[0034] Figure 1B is a perspective view of a display device to which an embodiment of the present inventive concept is directed;

[0035] Figure 2 is a top view of a display device to which an embodiment of the present inventive concept is directed;

[0036] Figure 3 is an equivalent circuit diagram of a pixel which can be included in a display device to which an embodiment of the present inventive concept is directed;

[0037] Figure 4A and Figure 4B is a partial sectional view of a display device to which an exemplary embodiment of the inventive concept is directed;

[0038] Figure 5 is a partial plan view of a display area to which an embodiment of the inventive concept is directed;

[0039] Figure 6 is a plan view of a structure of light emitting diodes arranged in a display area of Figure 5 to which an embodiment of the inventive concept is directed;

[0040] Figure 7 is a plan view showing an enlarged portion of a display area of Figure 5 to which an embodiment of the inventive concept is directed;

[0041] Figure 8 is a partial schematic sectional view of a display area taken along line A-A' of Figure 7 to which an embodiment of the inventive concept is directed;

[0042] Figure 9 is an enlarged view of a C region of Figure 8 to which an embodiment of the inventive concept is directed;

[0043] Figure 10 is a sectional view taken along line A-A' of Figure 7 to illustrate a manufacturing process to which an embodiment of the inventive concept is directed;

[0044] Figure 11 is a partial sectional view of a display area taken along line B-B' of Figure 7 to which an embodiment of the inventive concept is directed;

[0045] Figure 12 and Figure 13 is a plan view of a display area to which an exemplary embodiment of the inventive concept is directed. DETAILED DESCRIPTION

[0046] Reference will now be made in detail to exemplary embodiments of the inventive concept, as illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout the specification. In this regard, the exemplary embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the exemplary embodiments are merely described below, by referring to the drawings, to explain aspects of the inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0047] The present disclosure will now be described more fully with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. Like reference numerals can indicate like elements throughout the drawings, and a description can be omitted herein.

[0048] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various components, these components should not be limited by these terms and the components are only used for the purpose of distinguishing between one component and another.

[0049] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] It will be further understood that the terms "comprises" and / or "comprising", as used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0051] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. For example, intervening layers, regions or components can be present.

[0052] The size of the components in the drawings can be exaggerated for the purpose of explanation and thus the example embodiments are not limited thereto. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the purpose of explanation, the example embodiments are not limited to this.

[0053] When a certain embodiment can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed at substantially the same time or in the reverse order to the described order.

[0054] In this specification, the expression "A and / or B" indicates A or B, or A and B. In addition, the expression "at least one of A and B" indicates A, or B, or A and B.

[0055] It will be understood that when a layer, region or component is referred to as being connected to another layer, region or component, it can be directly connected to the other layer, region or component and / or an intervening layer, region or component can be present. For example, when a layer, region or component is referred to as being electrically connected to another layer, region or component, it can be directly electrically connected to the other layer, region or component and / or an intervening layer, region or component can be present.

[0056] Figure 1A is a schematic perspective view of a display device 1 to which the example embodiment relates, and Figure 1B is a perspective view of a display device 1' to which the example embodiment relates.

[0057] Referring to Figure 1AThe display device 1 includes a display region DA that displays an image and a non-display region NDA that does not display an image. Pixels can be arranged in the display region DA and can emit light to provide an image to a viewer. The non-display region NDA can be outside of and surround the display region DA. For example, as shown in the embodiment of FIG. 1, the display region DA can have a rectangular shape with a longer side extending in the Y direction and a shorter side extending in the X direction. The non-display region NDA can be arranged outside of the display region (e.g., in the X and / or Y direction) and can surround the display region. For example, in the embodiment of FIG. 2, the non-display region NDA surrounds the display region DA on four sides. However, in other example embodiments, the display region DA can have a variety of other shapes, such as a circular shape, an elliptical shape, a polygonal shape, etc., and the non-display region NDA can have various different shapes and orientations relative to the display region DA. Figure 1A The display region DA can have a rectangular shape with a longer side extending in the Y direction and a shorter side extending in the X direction. The non-display region NDA can be arranged outside of the display region (e.g., in the X and / or Y direction) and can surround the display region. For example, in the embodiment of FIG. 2, the non-display region NDA surrounds the display region DA on four sides. However, in other example embodiments, the display region DA can have a variety of other shapes, such as a circular shape, an elliptical shape, a polygonal shape, etc., and the non-display region NDA can have various different shapes and orientations relative to the display region DA. Figure 1A The display region DA can have a rectangular shape with a longer side extending in the Y direction and a shorter side extending in the X direction. The non-display region NDA can be arranged outside of the display region (e.g., in the X and / or Y direction) and can surround the display region. For example, in the embodiment of FIG. 2, the non-display region NDA surrounds the display region DA on four sides. However, in other example embodiments, the display region DA can have a variety of other shapes, such as a circular shape, an elliptical shape, a polygonal shape, etc., and the non-display region NDA can have various different shapes and orientations relative to the display region DA.

[0058] The display region DA can include a pixel region PA and a transmissive region TA. For example, the display region DA can include a plurality of pixel regions PA and a plurality of transmissive regions TA arranged relative to each other. The pixel region PA is a region in which pixels are arranged and substantially emit light. In an example embodiment, the pixels in the pixel region PA can be arranged in a stripe, a pen-tile matrix, etc.

[0059] The transmissive region TA is a region in which pixels are not arranged and through which light, such as incident external light, light from components, etc., can pass through the substrate 100. The transmissive region TA can include an organic layer and / or an inorganic layer. In an example embodiment, the transmissive region TA can include the substrate 100, and a layer that can be initially formed on the substrate 100 can be removed. In another example embodiment, the substrate 100 can be disposed in the transmissive region TA, and an inorganic layer, such as a buffer layer, can be disposed only on the substrate 100.

[0060] Referring to Figure 1A , the transmissive region TA can be disposed throughout the display region DA. As described above, the transmissive region TA is a region through which light passes. The display region DA of the display device 1 displays an image and can be transparent. For example, a front surface of the display region DA of the display device 1 can be implemented as a transparent display.

[0061] In the embodiment shown in Figure 1B , the display device 1' includes a support display region SA disposed in the display region DA. The transmissive region TA can be disposed in the support display region SA. In the embodiment shown in Figure 1B , the support display region SA can be circular. However, example embodiments of the inventive concept are not limited thereto. The support display region SA can be surrounded by the display region DA.

[0062] The support display area SA can include components, such as a sensor using infrared rays, visible light, or sound, etc. disposed thereunder (e.g., in the Z direction). The transmissive area TA can be an area that allows light and / or sound emitted from the components to the outside or propagated from the outside to the components to penetrate therethrough. In an exemplary embodiment, when light such as infrared rays penetrates the support display area SA, the light transmittance can be equal to or greater than about 10%. For example, in an exemplary embodiment, the light transmittance in the support display area SA can be about 20%, 25%, 50%, 85%, or 90%.

[0063] In an exemplary embodiment, the number of pixels per unit area arranged in the support display area SA can be less than the number of pixels arranged in the display area DA.

[0064] In Figure 1B In an embodiment, the support display area SA is located at one side (e.g., the upper right side) of the display area DA. However, exemplary embodiments of the inventive concept are not limited thereto, and the location and number of the support display area SA arranged in the display area DA can vary.

[0065] Hereinafter, for the convenience of explanation, an embodiment in which the display device 1 is an organic light emitting display device is described. However, exemplary embodiments of the inventive concept are not limited thereto, and the display device can be various types of display devices including inorganic light emitting display devices (or inorganic EL display devices), quantum dot light emitting display devices, etc. For example, the emission layer of the display element of the display device 1 can include organic materials, inorganic materials, or quantum dots, or both organic materials and quantum dots, or both inorganic materials and quantum dots, etc.

[0066] Figure 2 is a schematic plan view of a display device to which an embodiment of the inventive concept is directed.

[0067] Referring to Figure 2 Various components of the display device 1 are arranged on the substrate 100. In an exemplary embodiment, the substrate 100 can include a glass material, a metal material, or a plastic material. In an embodiment in which the substrate 100 includes a plastic material, the substrate 100 can include, for example, a polymeric resin including at least one compound selected from polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate, etc. The substrate 100 including a plastic material can be flexible, rollable, or foldable.

[0068] The substrate 100 includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA can be an area in which an image is displayed. The display area DA includes a pixel area PA in which the pixels P are arranged, and a transmissive area TA which is not arranged with the pixels P and is translucent.

[0069] The pixels P are arranged in the pixel area PA of the display area DA. Each pixel P can include a display element such as a light-emitting diode. In Figure 2 In an embodiment, the display element is an organic light-emitting diode (OLED). Each pixel P can emit light of a specific color such as red, green, blue, or white from the OLED. In the specification, as described above, the pixel P can be a pixel which emits any one of red light, green light, blue light, and white light. However, exemplary embodiments of the inventive concept are not limited thereto.

[0070] The display area DA can be covered with a thin film encapsulation layer 300 to protect the display element from contaminants such as external air or moisture.

[0071] The pixels P can be electrically connected to external circuits arranged in the non-display area NDA, respectively. As Figure 2 As shown in an embodiment, the first scan driving circuit 150, the second scan driving circuit 152, the first power supply line 160, the second power supply line 170, the pad unit 180, and the data driving circuit 190 can be arranged in the non-display area NDA. However, exemplary embodiments of the inventive concept are not limited thereto, and the display device 1 can include different components in the non-display area NDA, and the arrangement of the components can be different.

[0072] The first scan driving circuit 150 can provide a scan signal to each pixel P through a scan line SL. The first scan driving circuit 150 can provide an emission control signal to each pixel P through an emission control line EL. The first scan driving circuit 150 can extend in the Y direction, and can be disposed at the left side (e.g., in the X direction) of the non-display area NDA. The second scan driving circuit 152 can extend in the Y direction, and can be disposed at the right side (e.g., in the X direction) of the non-display area NDA. The second scan driving circuit 152 can be parallel to the first scan driving circuit 150, with the display area DA between them. In an exemplary embodiment, some of the plurality of pixels P arranged in the display area DA can be electrically connected to the first scan driving circuit 150, and other pixels P can be electrically connected to the second scan driving circuit 152. In another exemplary embodiment, the scan driving circuit 152 can be omitted.

[0073] The first power line 160 can include a first sub-line 162 and a second sub-line 163, and the first and second sub-lines 162 and 163 extend in parallel to each other in the X direction and arrange the display area DA therebetween. For example, as shown in an embodiment of Figure 2 The first sub-line 162 can be arranged at a bottom side (e.g., in the Y direction) of the non-display area NDA, and the second sub-line 163 can be arranged at a top side (e.g., in the Y direction) of the non-display area NDA, as shown in an embodiment of

[0074] The pad unit 180 can be located at one side of the substrate 100. For example, as shown in an embodiment of Figure 2 The pad unit 180 can be arranged at a bottom side (e.g., in the Y direction) of the substrate. The pad unit 180 can not be covered by the insulating layer and can be electrically connected to a printed circuit board PCB. The pad unit PCB-P of the printed circuit board PCB can be electrically connected to the pad unit 180 of the display device 1. The printed circuit board PCB transmits a signal or power from a controller to the display device 1.

[0075] The control signal generated from the controller can be transmitted to the first and second scan driving circuits 150 and 152, respectively, through the printed circuit board PCB. The controller can provide the first and second power sources ELVDD and ELVSS to the first and second power lines 160 and 170, respectively, through the first and second connection lines 161 and 171 (as shown in Figure 3 The first power voltage ELVDD can be provided to each pixel P through a driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS can be provided to the opposite electrode of each pixel P connected to the second power line 170.

[0076] The data driving circuit 190 is electrically connected to the data line DL. The data signal of the data driving circuit 190 can be provided to each pixel P through a connection line 181 connected to the pad unit 180 and the data line DL connected to the connection line 181. In Figure 2 In an embodiment, the data driving circuit 190 is arranged on the printed circuit board PCB. However, in another exemplary embodiment, the data driving circuit 190 can be arranged on the substrate 100. For example, the data driving circuit 190 can be arranged between the pad unit 180 and the first power line 160 (e.g., in the Y direction).

[0077] Figure 3 is an equivalent circuit diagram of a pixel that can be included in a display device, to which an embodiment of the inventive concept is directed.

[0078] Referring to Figure 3Each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC.

[0079] The pixel circuit PC includes a drive thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to the scan line SL and the data line DL. In response to a scan signal Sn input through the scan line SL, the switching thin film transistor Ts transmits a data signal Dm input through the data line DL to the drive thin film transistor Td.

[0080] The storage capacitor Cst is connected to the switching thin film transistor Ts and the drive voltage line PL, and stores a voltage corresponding to a difference between a voltage from the switching thin film transistor Ts and a first power voltage ELVDD (or drive voltage) supplied to the drive voltage line PL.

[0081] The drive thin film transistor Td can be connected to the drive voltage line PL and the storage capacitor Cst, and can control a drive current flowing in the organic light emitting diode OLED from the drive voltage line PL according to a value of the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light having a certain brightness according to the drive current.

[0082] Figure 3 The pixel circuit PC is shown to include two thin film transistors and one storage capacitor. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the pixel circuit PC can include seven thin film transistors and one storage capacitor. In another exemplary embodiment, the pixel circuit PC can include at least two storage capacitors. Further, although the exemplary embodiments are described with respect to a single gate electrode for the switching thin film transistor Ts and the drive thin film transistor Td, in other exemplary embodiments, one or more gate electrodes can be dual gate electrodes or the like. Figure 3

[0083] Figure 4A Figure 4B is a partial schematic cross-sectional view of a display apparatus to which exemplary embodiments are directed. Figure 4A Figure 4B shows a cross-section of a pixel region PA and a transmissive region TA to which exemplary embodiments are directed.

[0084] A pixel circuit including a thin film transistor TFT and an organic light emitting diode OLED electrically connected to the pixel circuit can be arranged in the pixel region PA.

[0085] A buffer layer 111 can be arranged on the substrate 100 in the pixel region PA. For example, as shown in FIG. 1, the buffer layer 111 can be arranged on the substrate 100 in the pixel region PA and the transmissive region TA. Figure 4A ​​​In an embodiment, the buffer layer 111 can be disposed directly on the substrate 100 (e.g., in the Z direction). The buffer layer 111 can reduce or prevent penetration of impurities, moisture, or air from the bottom thereof, and can provide a flat surface on the substrate 100. In an exemplary embodiment, the buffer layer 111 can include an inorganic material such as an oxide or a nitride, an organic material, or a combination of organic / inorganic, and can have a single-layer structure or a multi-layer structure including an inorganic material and an organic material.

[0086] The semiconductor layer A can be on the buffer layer 111. For example, as Figure 4A In an embodiment, the semiconductor layer A can be disposed directly on the buffer layer 111 (e.g., in the Z direction). In an exemplary embodiment, the semiconductor layer A can include at least one compound selected from amorphous silicon (a-Si), polysilicon, an oxide semiconductor, and an organic semiconductor material. For example, the oxide semiconductor can include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), zinc (Zn), indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and / or zinc indium oxide (ZIO). For example, the polysilicon can include low temperature polysilicon (LTPS). The polysilicon material consumes a small amount of energy and has good reliability due to high electron mobility (at least 100 cm 2 / Vs), and thus the polysilicon material can be used as a semiconductor layer of a thin film transistor in a display device.

[0087] The gate electrode G can be disposed above the semiconductor layer A, with the gate insulating layer 113 therebetween (e.g., arranged in the Z direction). In an exemplary embodiment, the gate insulating layer 113 can include at least one compound selected from silicon oxide (SiO X ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), etc.

[0088] In an exemplary embodiment, the gate electrode G can include at least one compound selected from molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), etc., and can include one layer or multiple layers. The gate electrode G can include a metal having low resistance, and in an exemplary embodiment, the gate electrode G can include a single layer including Mo.

[0089] The source electrode S and / or the drain electrode D are disposed above the gate electrode G, and the interlayer insulating layer 115 is therebetween (e.g., arranged in the Z direction). In an exemplary embodiment, the source electrode S and / or the drain electrode D can include at least one compound selected from Mo, Al, Cu, and Ti, etc., and can include a single layer or multiple layers. In an exemplary embodiment, the source electrode S and / or the drain electrode D can have a multi-layer structure of, for example, Ti / Al / Ti or titanium nitride (TiN) / Al / Ti.

[0090] The planarization layer 117 can cover the upper surfaces of the source electrode S and / or the drain electrode D, and can have a flat upper surface to enable the pixel electrode 210 disposed thereon to be flat. For example, as shown in the embodiment of FIG. 1, the planarization layer 117 can be disposed directly on the source electrode S and the drain electrode D and the portions of the interlayer insulating layer 115 not covered by the electrodes (e.g., in the Z direction). The planarization layer 117 can include one layer or multiple layers including an organic material. Figure 4A

[0091] In an exemplary embodiment, the planarization layer 117 can include a general-purpose polymer such as at least one compound selected from benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), and polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a p-xylene-based polymer, or a mixture thereof.

[0092] In an exemplary embodiment, the planarization layer 117 can include an inorganic material. For example, the planarization layer 117 can include at least one compound selected from silicon oxide (SiO X ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), etc. In an embodiment in which the planarization layer 117 includes an inorganic material, chemical polishing can be performed to planarize the planarization layer. For example, in an exemplary embodiment, the planarization layer 117 can include both an organic material and an inorganic material.

[0093] The buffer layer 111, the gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117 can form a multi-layer 110 disposed between the substrate 100 and the light emitting diode OLED. However, in an exemplary embodiment, the multi-layer 110 can include other organic layers and / or inorganic layers in addition to the buffer layer 111, the gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117, and some layers can be omitted.

[0094] ​On the planarization layer 117, an organic light emitting diode (OLED) (for example, an organic light emitting diode) including a pixel electrode 210, an intermediate layer 220, and an opposite electrode 230 can be disposed as a display element.

[0095] The pixel electrode 210 can be on the planarization layer 117. For example, as shown in an embodiment of the disclosure, Figure 4A The pixel electrode 210 can be disposed directly on the planarization layer 117 (for example, in the Z direction), as shown in an embodiment of the disclosure. Figure 4A An embodiment of the disclosure includes one pixel electrode 210. However, in other exemplary embodiments, the number of OLEDs can vary, and there can be a plurality of pixel electrodes 210 spaced apart from each other and patterned according to the number of OLEDs.

[0096] In an exemplary embodiment, the pixel electrode 210 can include a (semi-)transmissive electrode or a reflective electrode. For example, the pixel electrode 210 can include a reflective layer including at least one compound selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and combinations thereof, and can include a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one compound selected from a cluster consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode 210 can have a stack structure of ITO / Ag / ITO.

[0097] An insulating layer 120 (for example, a pixel defining layer) can be disposed on the planarization layer 117. For example, as shown in an embodiment of the disclosure, Figure 4A The insulating layer 120 can be disposed directly on the planarization layer 117 (for example, in the third direction) and the side edges of the pixel electrode 210, as shown in an embodiment of the disclosure. The insulating layer 120 can cover the side edges of the pixel electrode 210 and define an emission area of a pixel by having an opening OP exposing a central portion of the pixel electrode 210. The insulating layer 120 can prevent the generation of an arc or the like at the edges of the pixel electrode 210 by increasing the distance between the edges of the pixel electrode 210 and the opposite electrode 230 located at the upper portion of the pixel electrode 210. In an exemplary embodiment, the insulating layer 120 can include an organic insulating material such as at least one compound selected from polyimide, polyamide, acryl-based resin, BCB, HMDSO, and phenol resin, and can be formed by using spin coating or the like.

[0098] The intermediate layer 220 of the OLED can include an organic emission layer. The organic emission layer can include an organic material including a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. In an exemplary embodiment, the organic emission layer can include a low molecular weight organic material or a polymer organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) can be selectively arranged above and below the organic emission layer. The organic emission layer can be arranged to correspond to the pixel electrode 210 (e.g., overlap the pixel electrode in the Z direction), respectively, and the above-described functional layers can be integrally formed above the pixel electrode 210 (e.g., in the Z direction).

[0099] The counter electrode 230 can be arranged on the intermediate layer 220. In an exemplary embodiment, the counter electrode 230 can include a light-transmissive electrode or a reflective electrode. For example, in an exemplary embodiment, the counter electrode 230 can include a metal thin film having a small work function, and the metal thin film includes at least one compound selected from Li, Ca, Al, Ag, Mg, LiF / Ca, LiF / Al, and combinations thereof.

[0100] In an exemplary embodiment, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be further arranged on the metal thin film.

[0101] In an exemplary embodiment in which the pixel electrode 210 includes a reflective electrode and the counter electrode 230 includes a light-transmissive electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and thus, the display device can be a top emission type. In an exemplary embodiment in which the pixel electrode 210 includes a transparent or semi-transparent electrode and the counter electrode 230 includes a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and thus, the display device can be a bottom emission type. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display device can be a dual emission type display device that emits light toward both a top surface and a rear surface of the display device.

[0102] The counter electrode 230 can be arranged only within the pixel area PA in the display area DA, and can not be arranged in the transmission area TA. The counter electrode 230 can be arranged on an upper portion of the intermediate layer 220 and the insulating layer 120. For example, as shown in the embodiment of FIG. 1, the counter electrode 230 can be directly arranged on the intermediate layer 220 and the insulating layer 120 (e.g., in the Z direction). The counter electrode 230 can be continuously formed above the plurality of light emitting diodes OLED (e.g., in the Y direction) and can overlap the pixel electrode 210 (e.g., in the Z direction). Figure 4A

[0103] As shown in the embodiment of FIG. 1, the counter electrode 230 can be directly arranged on the intermediate layer 220 and the insulating layer 120 (e.g., in the Z direction). The counter electrode 230 can be continuously formed above the plurality of light emitting diodes OLED (e.g., in the Y direction) and can overlap the pixel electrode 210 (e.g., in the Z direction).

[0103] As shown in the embodiment of FIG. 1, the counter electrode 230 can be directly arranged on the intermediate layer 220 and the insulating layer 120 (e.g., in the Z direction). The counter electrode 230 can be continuously formed above the plurality of light emitting diodes OLED (e.g., in the Y direction) and can overlap the pixel electrode 210 (e.g., in the Z direction).Figure 4A As shown in the embodiment of FIG. 1, the insulating layer 120 and the multi-layer 110 including the buffer layer 111, the gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117 can be completely or partially removed from the transmissive area TA. For example, the layers can be initially formed on the transmissive area TA and then removed or can not be formed at all.

[0104] Although not shown, the layers removed to form the transmissive area TA can include an opening portion for defining the transmissive area TA. The opening portion can be an opening corresponding to the shape of the transmissive area TA.

[0105] As shown in the embodiment of FIG. 1, the insulating layer 120 and the multi-layer 110 including the buffer layer 111, the gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117 can be completely or partially removed from the transmissive area TA. For example, the layers can be initially formed on the transmissive area TA and then removed or can not be formed at all. Figure 4A As shown in the embodiment of FIG. 1, the insulating layer 120 and the multi-layer 110 including the buffer layer 111, the gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117 can be completely or partially removed from the transmissive area TA. For example, the layers can be initially formed on the transmissive area TA and then removed or can not be formed at all. Figure 4B As shown in the alternative embodiment of FIG. 2, the multi-layer 110 including the buffer layer 111, the gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117 can be included in the transmissive area TA and can be arranged in the transmissive area TA similarly to the multi-layer 110. However, the insulating layer 120 can be removed and the organic light emitting diode OLED can not be formed. As described above, in the transmissive area TA, the multi-layer 110 and the insulating layer 120 can be completely or partially removed, and a conductive layer including metal (e.g., an electrode or a wire) can not be disposed. Since the conductive layer is not disposed in the transmissive area TA, the high transmissivity of the transmissive area TA can be maintained at least to some extent.

[0106] However, in order to ensure that the high transmissivity of the transmissive area TA is maintained, the counter electrode 230 can not be disposed within the transmissive area TA. For example, in a comparative example of a typical display structure, the counter electrode can be integrally formed in the entire display area and can be disposed within both the transmissive area and the pixel area. In this comparative example, the counter electrode is formed in the transmissive area, so the transmissivity of the transmissive area is reduced. Accordingly, according to the embodiment of the inventive concept, the counter electrode 230 can be disposed only in the pixel area PA, not in the transmissive area TA, to prevent a reduction in the light / acoustic transmissivity in the transmissive area.

[0107] In an embodiment, a mask including openings corresponding to the pixel areas can be used to form the counter electrode 230. However, in this embodiment, a shadow effect can occur, resulting in the deposition of a deposition material that forms the counter electrode in the transmissive area adjacent to the pixel area through a space between the insulating layer (e.g., the pixel defining layer) and the mask. The formation of the portion of the counter electrode 230 in the transmissive area TA can cause the transmissivity of the transmissive area to be reduced and the width of the transmissive area to be narrowed. Accordingly, the light transmissivity of the entire display area included in the transparent display can be reduced.

[0108] According to an embodiment of the present inventive concept, the display device 1 includes first partition walls (PW1) and second partition walls (PW2) formed on the insulating layer 120 to prevent the deposition material forming the opposite electrode 230 from being deposited within the transmissive area TA. Figure 6 Figure 6

[0109] Figure 5 is a partial schematic plan view of a display area to which an exemplary embodiment is directed. Figure 6 is a schematic plan view of a structure of light emitting diodes arranged in the display area of Figure 5

[0110] Referring to Figure 5 , the display area DA includes a first transmissive area TA1, a second transmissive area TA2, and a pixel area PA therebetween. In other words, the first transmissive area TA1, the second transmissive area TA2, and the pixel area PA can be alternately arranged by forming a certain pattern.

[0111] As shown in an embodiment of Figure 5 , the first transmissive area TA1, the pixel area PA, the second transmissive area TA2, and the pixel area PA can be arranged in the X direction. However, exemplary embodiments of the present inventive concept are not limited thereto. The first transmissive area TA1 and the second transmissive area TA2 are defined as areas arranged on one side and the other side, respectively, with respect to the pixel area PA, and can have substantially the same shape and structure. For example, as shown in an embodiment of Figure 5 , the first transmissive area TA1 can be disposed on the left side (e.g., in the X direction) of the pixel area PA, and the second transmissive area TA2 can be disposed on the right side (e.g., in the X direction) of the pixel area PA.

[0112] The display device 1 can include a plurality of first transmissive areas TA1, pixel areas PA, and second transmissive areas TA2. For example, as shown in an embodiment of Figure 5 , the plurality of first transmissive areas TA1, pixel areas PA, and second transmissive areas TA can be arranged in the Y direction. As shown in an embodiment of Figure 5 , a non-transmissive area NTA can be disposed between first transmissive areas TA1 adjacent in the Y direction. Likewise, a non-transmissive area NTA can be disposed between second transmissive areas TA2 adjacent in the Y direction.

[0113] In exemplary embodiments, lines CL supplying a signal and power to light emitting diodes arranged in the pixel area PA can be disposed in the non-transmissive area NTA. In exemplary embodiments, the lines CL can be, for example, a scan line SL, an emission control line EL, a previous scan line SL-1, and the like, which extend in the X direction. However, exemplary embodiments of the present inventive concept are not limited thereto.​​​

[0114] In a comparative embodiment, the line CL extends in a straight line (e.g., in the X direction) and extends within the first transmission region TA1 and the second transmission region TA2. In this comparative embodiment, the transmittance of the first transmission region TA1 and the second transmission region TA2 is reduced due to the line CL. However, in Figure 5 In the embodiment shown, the line CL can be arranged to bypass the first transmission region TA1 and the second transmission region TA2, and is mainly arranged in the non-transmission region NTA.

[0115] Reference Figure 6 Subpixels Pr, Pg, and Pb can be arranged in pixel region PA. In an exemplary embodiment, subpixels Pr, Pg, and Pb may each include a first subpixel Pr emitting light of a first color, a second subpixel Pg emitting light of a second color, and a third subpixel Pb emitting light of a third color. For example, the first color may be red, the second color may be green, and the third color may be blue. However, exemplary embodiments of the present invention are not limited thereto. Figure 11 As shown, the first sub-pixel Pr includes a first light-emitting diode OLED1, the second sub-pixel Pg includes a second light-emitting diode OLED2, and the third sub-pixel Pb includes a third light-emitting diode OLED3.

[0116] At least one pixel portion PX, comprising a pixel unit including adjacent first sub-pixels Pr, second sub-pixels Pg, and third sub-pixels Pb, may be arranged in the pixel region PA. For example... Figure 6 As shown in the embodiment, a plurality of pixel portions PX, such as the first pixel portion PX1 and the second pixel portion PX2, may be arranged in the pixel region PA.

[0117] The first separator wall PW1 and the second separator wall PW2 may be arranged in the pixel region PA. The first support separator wall SPW1, the second support separator wall SPW2 and the third support separator wall SPW3 may also be arranged in the pixel region PA. The first separator wall PW1, the second separator wall PW2 and the first support separator walls SPW1 to the third support separator walls SPW3 may be arranged on the insulating layer 120.

[0118] like Figure 6 As shown in the embodiment, the first partition wall PW1 and the second partition wall PW2 can be arranged in the pixel region PA between the first pixel portion PX1 and the second pixel portion PX2 and the first transmission region TA1 and the second transmission region TA2. For example, as Figure 6In an embodiment shown in FIG. 1, the first partition wall PW1 and the second partition wall PW2 can each be arranged on a side (e.g., in the X direction) of the first pixel portion PX1 and the second pixel portion PX2. The first partition wall PW1 and the second partition wall PW2 can extend in the Y direction and can be arranged in the X direction.

[0119] The first support partition wall SPW1 to the third support partition wall SPW3 are arranged between the respective ones of the sub-pixels Pr, Pg, and Pb included in the first pixel portion PX1 and the second pixel portion PX2. The first support partition wall SPW1 to the third support partition wall SPW3 can extend in the X direction and can be arranged in the Y direction.

[0120] Hereinafter, the first partition wall PW1 and the second partition wall PW2 and the first support partition wall SPW1 to the third support partition wall SPW3 will be described in detail with reference to Figure 7

[0121] Figure 7 is a schematic plan view showing an enlarged portion of a display region of Figure 5 Figure 8 is a schematic cross-sectional view of the portion of the display region taken along a line A-A' of Figure 7 Figure 9 is an enlarged view of a region C of Figure 8

[0122] With reference to FIG. 1, the first partition wall PW1 is arranged on the insulating layer 120 (e.g., in the X direction) between the pixel portion PX and the first transmission region TA1. The second partition wall PW2 is arranged on the insulating layer 120 (e.g., in the X direction) between the pixel portion PX and the second transmission region TA2. Figure 7

[0123] The first opening OPl defining the first emission region of the first sub-pixel Pr, the second opening OP2 defining the second emission region of the second sub-pixel Pg, and the third opening OP3 defining the third emission region of the third sub-pixel Pg can be defined in the insulating layer 120. With respect to the first sub-pixel Pr, the first partition wall PW1 can be located on the insulating layer 120 (e.g., in the X direction) between the first opening OPl and the first transmission region TA1.

[0124] The first partition wall PW1 and the second partition wall PW2 can extend in the Y direction. For example, the first partition wall PW1 can extend in the Y direction from the space between the third opening OP3 and the first transmission region TA1 to the space between the second opening OP2 and the first transmission region TA1. Likewise, the second partition wall PW2 can extend in the Y direction from the space between the third opening OP3 and the second transmission region TA2 to the space between the second opening OP2 and the second transmission region TA2. ​​​​​

[0125] In an exemplary embodiment, the length Ls of the first partition wall PW1 in the Y direction can be less than or equal to about 300 pm. For example, the length Ls can preferably be between about 130 pm and about 140 pm.

[0126] The length (e.g., in the Y direction) of the second partition wall PW2 can be the same as the length Ls of the first partition wall PW1. Figure 7 The length Ls of the first partition wall PW1 and the second partition wall PW2 is shown to correspond to the width of the pixel portion PX in the Y direction. However, exemplary embodiments of the inventive concept are not limited thereto. Referring to Figure 6 and Figure 7 , the first partition wall PW1 and the second partition wall PW2 can be spaced apart by a distance (e.g., in the Y direction) to respectively correspond to the length (e.g., in the Y direction) of the first pixel portion PX1 and the second pixel portion PX2, and the first partition wall PW1 and the second partition wall PW2 do not extend in the space between the first pixel portion PX1 and the second pixel portion PX2. However, in another embodiment shown in Figure 12 , the first partition wall PW1 and the second partition wall PW2 can continuously extend in the Y direction and extend between the pixel portions PX as shown in Figure 12 . However, in exemplary embodiments of the inventive concept, the first partition wall PW1, the second partition wall PW2, and the first to third support partition walls SPW1-3 can have various different numbers and arrangements.

[0127] In an exemplary embodiment, the width Ws of the first partition wall PW1 in the X direction can be less than or equal to about 30 pm. For example, in an exemplary embodiment, the width Ws of the first partition wall PW1 in the X direction can be between about 5 pm and about 10 pm. The width (e.g., in the X direction) of the second partition wall PW2 can be the same as the width Ws of the partition wall PW1.

[0128] The first support partition wall SPW1 can be disposed on the insulating layer 120 (e.g., in the Y direction) between the first opening OP1 defining the first emission area and the second opening OP2 defining the second emission area. The second support partition wall SPW2 can be disposed on the insulating layer 120 (e.g., in the Y direction) between the second opening OP2 defining the second emission area and the third opening OP3 defining the third emission area.

[0129] The third support partition wall SPW3 can be located between the pixel portions PX. For example, as shown in Figure 6 and Figure 7In the exemplary embodiment shown in FIG. 1, the third support partition wall SPW3 can be disposed between the third sub-pixel Pb included in the first pixel portion PX1 and the first sub-pixel Pr included in the second pixel portion PX2 (e.g., in the Y direction). As a result, the first support partition wall SPW1, the second support partition wall SPW2, and the third support partition wall SPW3 can be disposed between adjacent openings, such as the first opening OP1, the second opening OP2, and the third opening OP3, respectively.

[0130] In the exemplary embodiment, the first and second partition walls PW1 and PW2 disposed on the insulating layer 120 and the first to third support partition walls SPW1 to SPW3 can include an organic or inorganic material.

[0131] In the exemplary embodiment, when the first and second partition walls PW1 and PW2 and the first to third support partition walls SPW1 to SPW3 include an organic material, the organic material can be, for example, a general-purpose polymer, and the general-purpose polymer includes at least one compound selected from BCB, polyimide, HMDSO, PMMA, and PS, a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a p-xylene-based polymer, or a mixture thereof.

[0132] In the exemplary embodiment, when the first and second partition walls PW1 and PW2 and the first to third support partition walls SPW1 to SPW3 include an inorganic material, the first and second partition walls PW1 and PW2 and the support partition walls can include at least one compound selected from silicon oxide (SiO X ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), etc.

[0133] The counter electrode 230 can be disposed on the insulating layer 120 in the pixel area PA. The counter electrode 230 can overlap at least some portions of the first and second partition walls PW1 and PW2, and can not overlap other portions of the first and second partition walls PW1 and PW2. The counter electrode 230 can overlap and can cover the first to third support partition walls SPW1 to SPW3 (e.g., in the Z direction).

[0134] The first partition wall PW1 and the second partition wall PW2 can be respectively located between the first pixel part PX1 and the first transmission region TA1 and between the first pixel part PX1 and the second transmission region TA2, with respect to the first pixel part PX1. The first partition wall PW1 and the second partition wall PW2 prevent the counter electrode 230 from being formed in the first transmission region TA1 and the second transmission region TA2 due to a shadow effect, and thus prevent a decrease in transmittance of the first transmission region TA1 and the second transmission region TA1.

[0135] Experimental results of the exemplary embodiment of the inventive concept show that the area of the counter electrode 230 is reduced by about 13% due to the first partition wall PW1 and the second partition wall PW2. This indicates that a portion of the counter electrode 230 can be unnecessarily formed in the first transmission region TA1 and the second transmission region TA2 when the first partition wall PW1 and the second partition wall PW2 are not formed. However, in the exemplary embodiment of the inventive concept, the counter electrode 230 can be formed only in the pixel region PA due to the first partition wall PW1 and the second partition wall PW2.

[0136] In addition, the first support partition wall SPW1, the second support partition wall SPW2, and the third support partition wall SPW3 can prevent distortion of a color gamut that can be caused by a shadow effect of an intermediate layer (e.g., the first intermediate layer 220R, the second intermediate layer 220G, and the third intermediate layer 220B of the sub-pixel (e.g., the first sub-pixel Pr, the second sub-pixel Pg, and the third sub-pixel Pb)) being unnecessarily formed on an adjacent light emitting diode during formation of the intermediate layer. Figure 11

[0137] Referring to Figure 8 The multi-layer 110 can be disposed on the substrate 100 in the pixel region PA and the first transmission region TA1 and the second transmission region TA2, and the light emitting diode OLED can be disposed on the multi-layer 110 in the pixel region PA. The insulating layer 120 can cover an edge (e.g., a side edge in the X direction) of the pixel electrode 210, and can have a first opening OPl that defines an emission region of the light emitting diode OLED by exposing a central part of the pixel electrode 210. Figure 8 It is shown that the insulating layer 120 is not disposed in the transmission region TA. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0138] The first partition wall PW1 and the second partition wall PW2 can be arranged on the insulating layer 120.

[0139] ​In an exemplary embodiment, the height h (e.g., the length in the Z direction) of the first partition wall PW1 can be less than or equal to about 3.5 pm. For example, the height h of the first partition wall PW1 can be between about 1 pm and about 2 pm. The height (e.g., the length in the Z direction) of the second partition wall PW2 can be the same as the height h of the first partition wall PW1.

[0140] The intermediate layer 220 including the emission layer is disposed on the pixel electrode 210. Figure 8 It is shown that the intermediate layer 220 is disposed only in the first opening OP1 of the insulating layer 120, and the intermediate layer 220 is the emission layer.

[0141] The counter electrode 230 can be disposed on the intermediate layer 220. The counter electrode 230 can extend along the inner side surface of the first opening OP1 to the upper surfaces of the first partition wall PW1 and the second partition wall PW2. For example, the counter electrode 230 can be disposed on partial portions of the upper surfaces of the first partition wall PW1 and the second partition wall PW2.

[0142] The cover layer 240 and the thin film encapsulation layer 300 can be disposed on the counter electrode 230. In an exemplary embodiment, the cover layer 240 can include an organic material and / or an inorganic material. The thin film encapsulation layer 300 can include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, which are sequentially stacked. However, exemplary embodiments of the inventive concept are not limited thereto. The organic encapsulation layer 320 is sealed by the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0143] Unlike the counter electrode 230, the cover layer 240 and the thin film encapsulation layer 300 can be disposed to extend (e.g., in the X direction) over the entire display area DA. For example, the cover layer 240 and the thin film encapsulation layer 300 can extend in the pixel area PA as well as the first transmissive area TA1 and the second transmissive area TA2. Accordingly, at least some portions of the cover layer 240 can directly contact the upper surfaces of the first partition wall PW1 and the second partition wall PW2.

[0144] In an exemplary embodiment, the cover layer 240 can be omitted, and the thin film encapsulation layer 300 can be disposed directly on the counter electrode 230 (e.g., in the Z direction). In this embodiment, at least some portions of the first inorganic encapsulation layer 310 can directly contact the upper surfaces of the first partition wall PW1 and the second partition wall PW2.

[0145] As shown in more detail Figure 8 of the C region of the Figure 9In an exemplary embodiment, the upper surface PWs of the first partition wall PW1 can include a first portion PW1-1 adjacent (e.g., in the X direction) to the emission region and a second portion PW1-2 adjacent (e.g., in the X direction) to a transmissive region TA such as the first transmissive region TA1. The counter electrode 230 can directly contact the first portion PW1-1 of the upper surface PWs of the first partition wall PW1. The counter electrode 230 can not contact or overlap the second portion PW1-2 and can have a side end disposed in the first portion PW1-1. Thus, the counter electrode 230 is not formed on the second portion PW1-2. The second portion PW1-2 can be exposed to the deposition material DM during the deposition of the counter electrode 230. Figure 10 A portion of the mask M is described.

[0146] The counter electrode 230 can not be disposed on the second portion PW1-2 of the first partition wall PW1. The material layer disposed on the counter electrode 230 can also be disposed on the exposed second portion PW1-2. In an exemplary embodiment, the material layer can be the cover layer 240, and the cover layer 240 is directly disposed on the counter electrode 230 and the exposed second portion PW1-2 (e.g., in the Z direction).

[0147] In another exemplary embodiment, the cover layer 240 can be omitted, and in this embodiment, the thin film encapsulation layer 300 can be disposed on the counter electrode 230. In this embodiment, the material layer directly disposed on the counter electrode 230 and the exposed second portion PW1-2 of the first partition wall PW1 can be the first inorganic encapsulation layer 310 of the thin film encapsulation layer 300.

[0148] Figure 10 is a cross-sectional view showing one of a plurality of manufacturing processes to which an exemplary embodiment relates. Figure 10 A process of manufacturing the counter electrode 230 is shown.

[0149] Referring to Figure 10 The mask M can include an opening region OPM corresponding to the pixel region PA. The opening region OPM of the mask M can have a width (e.g., a length in the X direction) equal to or less than the pixel region PA. The deposition material DM forming the counter electrode 230 is deposited on the intermediate layer 220 through the opening region OPM of the mask M.

[0150] During the deposition of the counter electrode 230, the mask M can be supported by the first partition wall PW1 and the second partition wall PW2. For example, the mask M can be supported by the second portions PW1-2 and PW2-2 of the first and second partition walls. As Figure 10As shown in FIG. 1, a lower surface Ms of the mask M can contact upper surfaces of the second portions PW1-2 and PW2-2 of the first and second partition walls PW1 and PW2. When the lower surface Ms of the mask M contacts the upper surfaces of the first and second partition walls PW1 and PW2, the deposition material DM can be deposited only in the pixel area PA, and the counter electrode 230 can be formed only in the pixel area PA.

[0151] Figure 11 is a partial schematic cross-sectional view of a display area taken along a line B-B' of Figure 7 FIG. 1.

[0152] Referring to Figure 7 and Figure 11 , a pixel portion PX can be disposed in the pixel area PA, and the pixel portion PX can include a first sub-pixel Pr including a first organic light emitting diode OLED1, a second sub-pixel Pg including a second organic light emitting diode OLED2, and a third sub-pixel Pb including a third organic light emitting diode OLED3.

[0153] The first organic light emitting diode OLED1 emitting light of a first color can include a first pixel electrode 210R, a first intermediate layer 220R, and a first counter electrode 230R. The second organic light emitting diode OLED2 emitting light of a second color can include a second pixel electrode 210G, a second intermediate layer 220G, and a second counter electrode 230G. The third organic light emitting diode OLED3 emitting light of a third color can include a third pixel electrode 210B, a third intermediate layer 220B, and a third counter electrode 230B.

[0154] The first support partition wall SPW1 can be disposed on the insulating layer 120 (e.g., in the Y direction) between a first opening OP1 defining a first emission area of the first organic light emitting diode OLED1 and a second opening OP2 defining a second emission area of the second organic light emitting diode OLED2. The second support partition wall SPW2 can be located on the insulating layer 120 (e.g., in the Y direction) between the second opening OP2 defining the second emission area and a third opening OP3 defining a third emission area of the third organic light emitting diode OLED3.

[0155] The third support partition wall SPW3 can be located on the insulating layer 120 between the pixel portions PX. For example, as shown in the embodiment of Figure 6 and Figure 7 , the third support partition wall SPW3 can be located between the third sub-pixel Pb of the first pixel portion PX1 and the first sub-pixel Pr of the second pixel portion PX2 (e.g., in the Y direction). Accordingly, the first to third support partition walls SPW1 to SPW3 can be located between adjacent openings (e.g., the first opening OP1, the second opening OP2, and the third opening OP3), respectively.

[0156] In an embodiment, the heights h' (e.g., lengths in the Z direction) of the first to third support partition walls SPW1 to SPW3 can be the same. However, exemplary embodiments of the inventive concept are not limited thereto. The heights h' of the first to third support partition walls SPW1 to SPW3 can be formed differently according to the sizes and spaces between the respective openings (e.g., the first to third openings OP1 to OP3). The heights h' of the first to third support partition walls SPW1 to SPW3 can also be smaller than the heights h of the first and second partition walls PW1 and PW2.

[0157] The first to third support partition walls SPW1 to SPW3 can be disposed between the first to third light emitting diodes OLED1 to OLED3 and can prevent defects in which the first to third intermediate layers 220R, 220G, and 220B overlap with the emission areas of the adjacent light emitting diodes and are deposited thereon.

[0158] Figure 12 and Figure 13 are schematic plan views of display areas to which exemplary embodiments are directed. Figure 12 and 13 respectively show Figure 6 modified exemplary embodiments.

[0159] Figure 12 The structure of the partition walls PW of Figure 6 is different from that of Figure 6 The description provided with reference to Figure 6 and Figure 12 will not be repeated below, and differences between and

[0160] will be mainly described. Figure 6 Figure 12 Similarly to Figure 12 , the partition walls PW of may include the first and second partition walls PW1 and PW2 extending in the Y direction and the first to third support partition walls SPW1 to SPW3 extending in the X direction.

[0161] It is shown that the first and second partition walls PW1 and PW2 are not spaced apart from each other in the non-transmissive area NTA and can be integrally formed. The first to third support partition walls SPW1 to SPW3 can extend in the X direction and can be connected to the first and second partition walls PW1 and PW2. Figure 12The support partition wall (e.g., the third support partition wall SPW3) of the pixel region PA can include an opening SW-OP around an outer region of the respective sub-pixel (e.g., the first sub-pixel Pr, the second sub-pixel Pg, and the third sub-pixel Pb). Due to the first support partition wall SPW1 to the third support partition wall SPW3, the intermediate layer (e.g., the emission layer) included in the sub-pixel Pr, Pg, and Pb, respectively, does not unnecessarily form in the emission region of the other adjacent sub-pixel Pr, Pg, and Pb during manufacturing and thus does not overlap therewith. Further, due to the partition wall PW, the common electrode 230 does not unnecessarily form in the transmissive region TA during manufacturing and thus does not overlap therewith, thereby being formed only in the pixel region PA.

[0162] As shown in the embodiment of FIG. 1, only one pixel portion PX can be arranged in the pixel region PA between the first transmissive region TA1 and the second transmissive region TA2, compared to the embodiment of FIG. 2 in which two pixel portions PX are arranged in the pixel region PA between the first transmissive region TA1 and the second transmissive region TA2. Figure 13 Figure 6 As shown in the embodiment of FIG. 1, only one pixel portion PX can be arranged in the pixel region PA between the first transmissive region TA1 and the second transmissive region TA2, compared to the embodiment of FIG. 2 in which two pixel portions PX are arranged in the pixel region PA between the first transmissive region TA1 and the second transmissive region TA2. Figure 6 Figure 6 The pixel region PA of the embodiment of FIG. 1 includes a plurality of pixel portions such as the first pixel portion PX1 and the second pixel portion PX2.

[0163] Figure 13 The first partition wall PW1 and the second partition wall PW2 of the embodiment of FIG. 1 are adjacent (e.g., in the X direction) to the first transmissive region TA1 and the second transmissive region TA2, respectively. The width W1 of the first transmissive region TA1 in the Y direction can be the same as the length Ls1 of the first partition wall PW1 in the Y direction. Likewise, the width W2 of the second transmissive region TA2 in the Y direction can be the same as the length Ls2 of the second partition wall PW2 in the Y direction.

[0164] According to one or more exemplary embodiments of the inventive concept, the transmittance of the display region and the distortion of the color gamut are simultaneously improved in a display device including a transmissive region of the display region. However, the scope of the inventive concept is not limited to such effects.

[0165] It is to be understood that the exemplary embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other exemplary embodiments. While one or more exemplary embodiments have been described with reference to the attached drawings, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope as set forth in the following claims.​​

Claims

1. A display device comprising: a substrate including a first transmissive region, a second transmissive region, and a pixel region between the first transmissive region and the second transmissive region; a first pixel electrode in the pixel region; a first intermediate layer disposed on the first pixel electrode, the first intermediate layer configured to emit light of a first color; an insulating layer covering edges of the first pixel electrode and defining a first emission region by a first opening exposing a portion of the first pixel electrode; a first partition wall disposed on the insulating layer between the first emission region and the first transmissive region; a second partition wall disposed on the insulating layer between the first emission region and the second transmissive region; and an opposing electrode disposed on the first intermediate layer in the pixel region, at least a portion of the opposing electrode contacting the first partition wall and the second partition wall, wherein end portions of the opposing electrode terminate on upper surfaces of the first partition wall and the second partition wall, respectively. The upper surfaces of the first partition wall and the second partition wall each include a first portion adjacent to the first emission region and a second portion adjacent to the first transmissive region and the second transmissive region, the first portion contacting the opposing electrode.

2. The display device according to claim 1, wherein The second portion does not contact or overlap the opposing electrode.

3. The display device of claim 2, wherein, 4.The display device of claim 2, further comprising: a material layer disposed on the opposing electrode, wherein the material layer directly contacts the second portion. 5.The display device of claim 1, further comprising: a second pixel electrode spaced apart from the first pixel electrode in a first direction in the pixel region; a second intermediate layer disposed on the second pixel electrode, the second intermediate layer configured to emit light of a second color; a third pixel electrode spaced apart from the second pixel electrode in the first direction in the pixel region; and a third intermediate layer disposed on the third pixel electrode, the third intermediate layer configured to emit light of a third color, wherein the insulating layer covers edges of the second pixel electrode and the third pixel electrode, respectively, and defines a second emission region by a second opening exposing a portion of the second pixel electrode and a third emission region by a third opening exposing a portion of the third pixel electrode, and the first partition wall extends between the first emission region to the third emission region and the first transmissive region in the first direction. the second partition wall extends between the first emission region to the third emission region and the second transmissive region in the first direction. a length of the first partition wall in the first direction is the same as a length of the second partition wall in the first direction.

6. The display device of claim 5, wherein, ​ 7. The display device according to claim 5, wherein ​ 8. The display device according to claim 5, wherein The first partition wall and the second partition wall have the same width in a second direction intersecting the first direction.

9. The display device of claim 8, wherein, The first partition wall and the second partition wall have a length in the first direction of less than or equal to 300 pm, and the first partition wall and the second partition wall have the width in the second direction of less than or equal to 30 pm.

10. The display device of claim 8, wherein, The first partition wall and the second partition wall have a height of less than or equal to 3.5 pm.

11. The display device according to claim 5, further comprising: a first support partition wall arranged on the insulating layer between the first opening and the second opening, the first support partition wall extending in a second direction intersecting the first direction.

12. The display device according to claim 11, further comprising: a second support partition wall arranged on the insulating layer between the second opening and the third opening, the second support partition wall extending in the second direction.

13. The display device of claim 12, wherein, The common electrode covers the first support partition wall and the second support partition wall.

14. The display device of claim 11, wherein, The first support partition wall is connected to the first partition wall at a first side end and to the second partition wall at a second side end.

15. The display device according to claim 5, wherein: at least one pixel portion is arranged in the pixel region, the pixel portion including a plurality of light emitting diodes that emit light of different colors; and the plurality of light emitting diodes include a first light emitting diode including the first pixel electrode, a second light emitting diode including the second pixel electrode, and a third light emitting diode including the third pixel electrode.

16. The display device according to claim 15, wherein: the pixel portion includes a first pixel portion and a second pixel portion spaced apart in the first direction; and the display device further includes a third support partition wall arranged on the insulating layer between the first pixel portion and the second pixel portion, the third support partition wall extending in a second direction intersecting the first direction.

17. The display device according to claim 16, wherein: the first partition wall and the second partition wall are respectively arranged in correspondence with the first pixel portion and the second pixel portion, and the first partition wall and the second partition wall do not extend in the first direction to a space between the first pixel portion and the second pixel portion.

18. The display device according to claim 1, further comprising: a plurality of layers arranged between the insulating layer and the substrate, and including at least one of an organic insulating layer and an inorganic insulating layer, wherein the plurality of layers include opening regions corresponding to the first transmissive region and the second transmissive region, respectively.

19. The display device of claim 1, wherein, the substrate includes a plurality of the first transmissive regions and a plurality of the second transmissive regions spaced apart in a first direction, the pixel region is arranged between the plurality of the first transmissive regions and the plurality of the second transmissive regions, the pixel region extends in the first direction, and the first partition wall and the second partition wall are arranged in the pixel region. The counter electrode is integrally formed in the pixel region between the plurality of first transmission regions and the plurality of second transmission regions.

20. A method for manufacturing a display device, comprising: forming a substrate including a first transmission region, a second transmission region, and a pixel region between the first transmission region and the second transmission region; forming a pixel electrode in the pixel region; forming an intermediate layer on the pixel electrode, the intermediate layer configured to emit light; forming an insulating layer covering edges of the pixel electrode and defining an emission region through an opening exposing a portion of the pixel electrode; forming a first partition wall and a second partition wall each having a first portion and a second portion on the insulating layer; forming a mask supported on the second portions of the first partition wall and the second partition wall; forming a counter electrode on the intermediate layer by depositing a deposition material on an open area of the mask, the open area of the mask including the first portions of the first partition wall and the second partition wall, wherein end portions of the counter electrode terminate on upper surfaces of the first partition wall and the second partition wall, respectively.

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