Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a carrier, a conductive pillar, an adhesion layer, and a package. The conductive pillar is disposed on the carrier. The conductive pillar has a top surface facing away from the carrier. The adhesion layer is disposed on the top surface of the conductive pillar. The package is disposed on the carrier. The package has a top surface facing away from the carrier. The top surface has a first portion and a second portion. The first portion and the second portion of the top surface of the package are discontinuous.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device package, and more particularly, to a semiconductor device package including a trench. BACKGROUND

[0002] In a semiconductor device package (e.g., an optical device), a die or chip (e.g., a light emitting device) is disposed on a carrier, and a cap is attached to the carrier to cover the die. The cap can be electrically connected to the carrier by a conductive post. The conductive post is attached to the transparent cap by a conductive glue or tape. However, during the manufacturing process, there can be voids in the conductive glue or tape, which can adversely affect the electrical performance of the semiconductor device package, or even cause the semiconductor device package to break. SUMMARY

[0003] In some embodiments, a semiconductor device package includes a carrier, a conductive post, an adhesive layer, and a package. The conductive post is disposed on the carrier. The conductive post has a top surface facing away from the carrier. The adhesive layer is disposed on the top surface of the conductive post. The package is disposed on the carrier. The package has a top surface facing away from the carrier. The top surface has a first portion and a second portion. The first portion and the second portion of the top surface of the package are discontinuous.

[0004] In some embodiments, a semiconductor device package includes a carrier, a conductive post, a package, and an adhesive layer. The conductive post is disposed on the carrier. The conductive post has a top surface facing away from the carrier. The package is disposed on the carrier. The package defines a cavity for exposing a portion of the carrier and a trench connected to the cavity. The adhesive layer is disposed on the top surface of the conductive post. At least a portion of a sidewall of the adhesive layer is exposed from the trench of the package.

[0005] In some embodiments, a semiconductor device package includes a carrier, a conductive post, a package, and an adhesive layer. The conductive post is disposed on the carrier. The conductive post has a top surface facing away from the carrier. The package is disposed on the carrier. The package defines a cavity for exposing a portion of the carrier and a trench connected to the cavity. The adhesive layer is disposed on the top surface of the conductive post. At least a portion of a sidewall of the adhesive layer is exposed from the trench of the package. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that the various structures can not be drawn to scale, and that the dimensions of the various structures can be arbitrarily increased or decreased for the sake of discussion clarity.

[0007] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0008] Figure 1B A top view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0009] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0010] Figure 2B A top view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0011] Figure 2C A top view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0012] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0013] Figure 4 A cross-sectional view of a semiconductor device package according to some embodiments of the disclosure is illustrated.

[0014] Common reference numbers are used throughout the drawings and detailed description to indicate the same or similar components. The disclosure can be best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0015] Figure 1A A cross-sectional view of a semiconductor device package 1 according to some embodiments of the disclosure is illustrated. Semiconductor device package 1 includes a carrier 10, an electronic component 11, a package 12, a conductive pillar 13, a cap 14, and an adhesive layer 15. In some embodiments, the semiconductor device package can be or include an optical device. In other embodiments, the semiconductor device package can be any other electronic device other than an optical device.

[0016] Carrier 10 can include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-infused fiberglass-based copper foil laminate. Carrier 10 can include interconnect structures, such as a plurality of conductive traces or vias. In some embodiments, carrier 10 includes a ceramic material or a metal plate. In some embodiments, carrier 10 can include a substrate, such as an organic substrate or a lead frame. In some embodiments, carrier 10 can include a dual-layer substrate including a core layer and a conductive material and / or structure disposed on the upper and bottom surfaces of carrier 10. The conductive material and / or structure can include a plurality of traces.

[0017] An electronic component 11 is disposed on the carrier 10. The electronic component 11 can include an emitting die or other optical die. For example, the electronic component 11 can include a light emitting diode (LED), a laser diode, a vertical cavity surface emitting laser (VCSEL), or another device that can include one or more semiconductor layers. The semiconductor layers can include silicon, silicon carbide, gallium nitride, or any other semiconductor material. The electronic component 11 can be connected to the carrier 10 by way of flip-chip or wire bonding techniques, for example. In some embodiments, the electronic component 11 includes an LED die that is bonded to the carrier 10 via a die bonding material. The LED die includes at least one wire bonding pad. The LED die is electrically connected to the carrier 10 by a conductive wire that is bonded to the wire bonding pad of the LED die at one end and to a wire bonding pad of the carrier 10 at the other end. The electronic component 11 has an active area (or light emitting area) that faces the cover 14. In other embodiments, the electronic component 11 can include a light detector or sensor (e.g., a PIN diode, a photodiode, a phototransistor, etc.). In some embodiments, the electronic component can include any semiconductor die or chip other than an optical component.

[0018] A conductive post (e.g., a copper post or copper cylinder) 13 is disposed on the carrier 10. The conductive post 13 is disposed between the carrier 10 and the cover 14 and electrically connects the cover 14 to the carrier 10. The conductive post 13 is attached or bonded to the cover 14 by an adhesive layer 15. In some embodiments, the adhesive layer 15 includes a conductive material, such as silver paste, solder paste, etc. The conductive post 13 can be a solid cylindrical post, a solid square post, or a solid post with a suitable shape. In some embodiments, the number of conductive posts 13 can vary depending on different design requirements.

[0019] The cover 14 is disposed on the adhesive layer 15 and the encapsulant 12. For example, the cover 14 is disposed on a coplanar surface bounded by a surface 151 of the adhesive layer 15 and a surface 121 of the encapsulant 12. The cover 14 includes a patterned conductive layer (or conductive trace). The patterned conductive layer is disposed on a lower surface of the cover 14 (e.g., facing the carrier 10). The patterned conductive layer can be embedded in the lower surface of the cover 14 and exposed through the lower surface of the cover 14. The patterned conductive layer is electrically connected to the carrier 10 via the conductive post 13 and the adhesive layer 15. The cover 14 can include a transparent material. The cover 14 can include a conductive material or a dielectric material. In some embodiments, the cover 14 can include glass, a transparent metal (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)), or plastic. In some embodiments, the cover 14 can be a shield (e.g., an electromagnetic interference (EMI) shield) that is configured to protect the electronic component 11 from electromagnetic radiation / waves from outside the semiconductor device package 1.

[0020] In some embodiments, the cap 14 is also attached or bonded to the package 12 via an adhesive layer. For example, such as Figure 1B As shown in the description Figure 1A A top view of semiconductor device package 1 (for clarity, in...) Figure 1B Some components of the assembly (e.g., cap 14, carrier 10, and electronic component 11) are omitted. Adhesive layer 14h is disposed on surface 121 of package 12. Adhesive layer 14h may be disposed adjacent to the edge of surface 121 of package 12. In some embodiments, such as Figure 1B As shown, the adhesive layer 14h is positioned adjacent to edges 121a and 121c of the surface 121 of the package 12. Since the adhesive layer is not positioned adjacent to edges 121b and 121d of the surface 121 of the package 12, the gap between the cap 14 and the surface 121 of the package 12 can be defined adjacent to edges 121b and 121d. This gap can act as a vent to allow air to flow from the cavity 12c defined by the package 12 to the outside of the cavity 12c, thus avoiding the popcorn effect during the manufacturing process.

[0021] The package (or encapsulant) 12 is disposed on the carrier 10. The package 12 defines a cavity 12c for receiving the electronic component 11. The package 12 covers a portion of the conductive pillar 13 and a portion of the adhesive layer 15. The package 12 also defines trenches (or trenches) 12t to expose a portion of the sidewall 132 of the conductive pillar 13 and a portion of the sidewall 152 of the adhesive layer 15. Figure 1A As shown, the package 12 has a surface 122 that is lower than the surface 121 of the package 12. For example, the surfaces 121 and 122 of the package 12 are discontinuous. For example, the distance between the surface 122 of the package 12 and the carrier is less than the distance between the surfaces 121 of the package 12. In some embodiments, the surface 122 of the package 12 is lower than the interface between the conductive post 13 and the adhesive layer 15. The trench 12t can be formed by laser, etching, or any other suitable process. In some embodiments, the roughness of the surface 122 of the package 12 is greater than the roughness of the surface 121 of the package 12. In some embodiments, the adhesive layer 15 may be fluid before curing, and therefore a portion of the adhesive layer 15 may be disposed on a portion of the sidewall 132 of the conductive post 13 and / or the surface 122 of the package 12. In some embodiments, the package 12 comprises an epoxy resin with filler, a molding material (e.g., epoxy molding material or other molding material), a polyimide, a phenolic compound or material, a material having silicone dispersed therein, or a combination thereof.

[0022] During some processes (e.g., reflow, curing, etc.) for manufacturing a semiconductor device package, voids can be created in the adhesive layer (or adjacent to the interface between the adhesive layer and the conductive pillar), which will adversely affect the electrical performance of the semiconductor device package, or even cause the semiconductor device package to break. In some embodiments, the above problem can be mitigated by low-temperature multi-stage baking the adhesive layer and the conductive pillar. However, this can only eliminate the voids adjacent to the center of the adhesive layer, but not completely eliminate the voids adjacent to the periphery of the adhesive layer. In addition, the low-temperature multi-stage baking operation will increase the manufacturing cost and time. According to the embodiments in Figure 1A and 1B , the voids adjacent to the center or periphery of the adhesive layer 15 can be completely evacuated by the trench 12t. In some embodiments, there are no voids in the adhesive layer 15 or adjacent to the interface between the adhesive layer 15 and the conductive pillar 13 under a curing operation of up to more than 8 hours. This can strengthen the connection between the adhesive layer 15 and the conductive pillar 13 and enhance the performance of the semiconductor device package 1.

[0023] Figure 2A A cross-sectional view of a semiconductor device package 2 according to some embodiments of the disclosure is illustrated. Figure 2B A top view of the semiconductor device package 2 according to some embodiments of the disclosure in Figure 2A is illustrated (some components (e.g., the lid 14, the carrier 10, and the electronic components 11) are omitted in Figure 2B for clarity). Figure 2A The semiconductor device package 2 in 2B is similar to the semiconductor device package 1 in Figure 1A and 1B , except that in addition to the trench 12t, the package body 12 of the semiconductor device package 2 additionally defines a trench 12t1. The trench 12t and the trench 12t1 are connected to evacuate the voids in the adhesive layer 15 (or adjacent to the interface between the adhesive layer 15 and the conductive pillar 13) and the air inside the cavity 12c. Therefore, no additional gap is needed between the surface 121 of the package body 12 and the lid 14. For example, as shown in Figure 2B , the adhesive layer 14h is disposed adjacent to all edges 121a, 121b, 121c, and 121d of the surface 121 of the package body 12. This can enhance the sealing capability of the semiconductor device package 2 to prevent water and particles from entering the cavity 12c.

[0024] Figure 2C A top view of the semiconductor device package 2 according to some embodiments of the disclosure in Figure 2A is illustrated (some components (e.g., the lid 14, the carrier 10, and the electronic components 11) are omitted in Figure 2C for clarity). Figure 2C The structure illustrated in Figure 2BThe semiconductor device package 1 in Figure 2B The width of the trenches 12t and 12t1 is greater than the width of the adhesion layer 15 in Figure 2C The width of the trenches 12t and 12t1 is less than the width of the adhesion layer 15 in In some embodiments, the width of the trenches 12t and 12t1 can be the same as the width of the adhesion layer 15. In some embodiments, the shape and size of the trenches 12t (or 12t1) can be adjusted or changed depending on different design requirements.

[0025] Figure 3 A cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 3 is similar to the semiconductor device package 1 in Figure 1A , except that in Figure 3 , the surface 122 of the encapsulant 12 is substantially coplanar with the interface between the adhesion layer 15 and the conductive pillar 13. For example, the surface 122 of the encapsulant 12 is substantially coplanar with the upper surface of the conductive pillar 13. For example, the sidewall 132 of the conductive pillar 13 is completely covered by the encapsulant 12, and the sidewall 152 of the adhesion layer 15 is completely exposed from the encapsulant 12.

[0026] Figure 4 A cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure is illustrated. The semiconductor device package 4 is similar to the semiconductor device package 1 in Figure 1A , except that in Figure 4 , the surface 122 of the encapsulant 12 is higher than the interface between the adhesion layer 15 and the conductive pillar 13. For example, the surface 122 of the encapsulant 12 is higher than the upper surface of the conductive pillar 13. For example, the sidewall 132 of the conductive pillar 13 is completely covered by the encapsulant 12, a portion of the sidewall 152 of the adhesion layer 15 is covered by the encapsulant 12, and another portion of the sidewall 152 of the adhesion layer 15 is exposed from the encapsulant 12.

[0027] In the description of some embodiments, a component provided "on" another component can encompass cases where the former component is directly on the latter component (e.g., in physical contact with the latter component), as well as cases where one or more intervening components are present between the former component and the latter component.

[0028] In descriptions of some embodiments, components characterized as "light transmissive" or "transparent" can refer to such components having a light transmittance of at least 80%, e.g., at least 85% or at least 90%, at the relevant wavelength or relevant range of wavelengths, e.g., the peak infrared wavelength or infrared wavelength range emitted by the light emitter. In descriptions of some embodiments, components characterized as "light shielding," "light blocking," or "opaque" can refer to such components having a light transmittance of no greater than 20%, e.g., no greater than 15% or no greater than 10%, at the relevant wavelength or relevant range of wavelengths, e.g., the peak infrared wavelength or infrared wavelength range emitted by the light emitter.

[0029] Additionally, quantities, ratios and other numerical values are sometimes presented in range format. It is to be understood that such range format is used only for convenience and brevity and should be taken as a literal description of a range meant to encompass each and every value within the range.

[0030] As used herein, the terms "substantially," "essentially," "approximately," and "about" are used to describe and account for small variations in, e.g., measurements, temperatures, etc. When used in connection with a description of an event or circumstance, the terms can refer to instances in which the event or circumstance is explicitly encountered, as well as instances in which the event or circumstance is not explicitly encountered, but is closely approximated. For example, when used in connection with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0031] Although the present disclosure has been described and illustrated with a certain degree of particularity, the description and illustration are intended to be illustrative, rather than restrictive, of the disclosure. Changes in implementations could be made by persons skilled in the art without departing from the spirit or scope of the disclosure as defined by the appended claims. The drawings are not necessarily to scale. Distinctions between the techniques in the disclosure can exist due to manufacturing variations, etc. Other embodiments of the disclosure can exist which are not specifically described. The specification and drawings are, accordingly, to be regarded in an illustrative, rather than a restrictive, sense. Modifications can be made that come within the scope of the disclosure. The disclosed methods can be implemented in any number of ways, using hardware, software or a combination thereof. The details of one or more implementations are set forth in the specification, which is to be taken in a generic and descriptive sense, and not a restrictive sense. Although the disclosed methods have been described with reference to particular operations performed in a particular order, it will be understood that the operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated otherwise, the order and grouping of operations is not a limitation of the present disclosure.

Claims

1. A semiconductor device package comprising: a carrier; a conductive stud disposed on the carrier, the conductive stud having a top surface facing away from the carrier; a solder paste layer disposed on the top surface of the conductive stud; and a package disposed on the carrier, the package having a top surface facing away from the carrier, the top surface having a first portion and a second portion, and the package defining an air cavity and an air trench connected to the air cavity, wherein the first portion and the second portion of the top surface of the package are discontinuous, and the solder paste layer, an interface of the conductive stud with the solder paste layer, and at least a portion of the conductive stud are exposed from the air trench of the package.

2. The semiconductor device package of claim 1, wherein a distance between the first portion of the top surface of the package and the carrier is greater than a distance between the second portion of the top surface of the package and the carrier, and the second portion of the top surface of the package is exposed from the air trench of the package.

3. The semiconductor device package of claim 1, wherein the first portion of the top surface of the package is substantially coplanar with a top surface of the solder paste layer.

4. The semiconductor device package of claim 1, wherein a distance between the second portion of the top surface of the package and the carrier is less than a distance between the top surface of the conductive stud and the carrier.

5. The semiconductor device package of claim 1, wherein a width of the air trench is less than a width of the solder paste layer from a top view.

6. The semiconductor device package of claim 1, wherein a roughness of the second portion of the top surface of the package is greater than a roughness of the first portion of the top surface of the package.

7. The semiconductor device package of claim 1, further comprising a light emitting device disposed on the carrier, wherein the air cavity of the package is for housing the light emitting device.

8. The semiconductor device package of claim 1, further comprising a transparent conductive cap and an adhesive layer joining the transparent conductive cap to a surface of the package, wherein the adhesive layer is disposed adjacent to a first edge and a second edge relative to the first edge of the surface of the package, and the adhesive layer is disposed non-adjacent to a third edge and a fourth edge relative to the third edge of the surface of the package to define a gap that allows air within the air cavity to flow outside of the air cavity.

9. A semiconductor device package comprising: a carrier; a conductive stud disposed on the carrier, the conductive stud having a top surface facing away from the carrier; a package disposed on the carrier, the package defining an air cavity for exposing a portion of the carrier and an air trench connected to the air cavity; a solder paste layer disposed on the top surface of the conductive stud; a transparent conductive cap disposed on the solder paste layer and the package; and a transparent conductive cap disposed on the solder paste layer and the package. ​ an adhesion layer joining the transparent conductive cap to a surface of the package and defining a gap between the transparent conductive cap and the surface of the package, wherein at least a portion of a sidewall of the solder paste layer and an interface of the conductive pillar with the solder paste layer are exposed from the air trench of the package, and the gap acts as a vent to allow air flow within the air trench and the air cavity to outside of the air cavity.

10. The semiconductor device package of claim 9, wherein the solder paste layer has a first sidewall facing the air cavity and a second sidewall facing away from the air cavity, and the first sidewall of the solder paste layer is exposed from the air trench of the package.

11. The semiconductor device package of claim 10, wherein the package comprises an epoxy with fillers, a molding compound, a polyimide, a phenolic compound, or a combination thereof, the second sidewall of the solder paste layer is covered by the package.

12. The semiconductor device package of claim 9, wherein the conductive pillar has a first sidewall facing the air cavity and a second sidewall facing away from the air cavity; and a portion of the first sidewall is exposed from the air trench of the package; and the second sidewall is covered by the package.

13. The semiconductor device package of claim 9, wherein a width of the air trench of the package is less than, equal to a width of the solder paste layer.

14. The semiconductor device package of claim 9, wherein the transparent conductive cap comprises a patterned conductive layer embedded in and exposed through a lower surface of the transparent conductive cap.

15. The semiconductor device package of claim 14, wherein the patterned conductive layer of the transparent conductive cap is electrically connected to the carrier through the solder paste layer and the conductive pillar.

16. The semiconductor device package of claim 9, further comprising a light emitting device disposed on the carrier and within the air cavity of the package.

17. The semiconductor device package of claim 9, wherein the solder paste layer directly contacts the transparent conductive cap.

18. A semiconductor device package comprising: a carrier; a conductive pillar disposed on the carrier, the conductive pillar having a top surface facing away from the carrier; a package disposed on the carrier, the package defining an air cavity exposing a portion of the carrier, a first air trench connected to the air cavity, and a second air trench connected to an exterior of the semiconductor device package; and a solder paste layer disposed on the top surface of the conductive pillar and between the first air trench and the second air trench, wherein the first air trench and the second air trench are connected to evacuate an air gap in the solder paste layer and air within the air cavity.

19. The semiconductor device package of claim 18, further comprising a cap and an adhesion layer joining the cap to a surface of the package, wherein the adhesion layer is disposed adjacent to all edges of the surface of the package.

20. The semiconductor device package of claim 18, wherein the layer of solder paste has a first sidewall facing the air cavity and a second sidewall facing away from the air cavity, and the first sidewall of the layer of solder paste is exposed from the first air trench, the second sidewall of the layer of solder paste is exposed from the second air trench.

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