PFM of a dc-dc regulator with intermittent vout sensing and adjustable minimum input power consumption

Abstract

Embodiments of the present disclosure generally relate to PFM of a DC-DC regulator with intermittent output VOUT sensing and adjustable minimum input power consumption. Embodiments relate to methods and apparatus for controlling a DC-DC converter, for example, a PFM control method for a DC-DC regulator using intermittent VOUT sensing. In these and other embodiments, PIN_MIN can be adjusted by external components already in use in typical applications, thus no additional pins or components are required.

Description

TECHNICAL FIELD

[0001] The present embodiments relate generally to power supplies, and more particularly to methods and apparatus for controlling a DC-DC converter. BACKGROUND

[0002] DC-DC converters sometimes use discontinuous output voltage sensing (VOUT). Examples include "high-side" buck and "primary-sensed" flyback topologies. These topologies can be used with universal AC input voltages (85VAC to 265VAC), where low "standby" and "no-load" input power consumption (PIN_MIN) is a key parameter regulated and adjusted by many national and international standards. PFM improves light-load efficiency, which makes low PIN_MIN possible. Discontinuous VOUT sensing affects PFM operation, because methods used with continuous VOUT sensing cannot be used with discontinuous VOUT sensing. SUMMARY

[0003] The present embodiments relate to methods and apparatus for controlling a DC-DC converter, such as a PFM control method for a DC-DC regulator using discontinuous VOUT sensing. In these and other embodiments, PIN_MIN can be adjusted by external components already in use in typical applications, so no additional pins or components are needed. BRIEF DESCRIPTION OF DRAWINGS

[0004] These and other aspects and features of the present embodiments will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a schematic diagram illustrating an example high-side buck regulator.

[0006] Figure 2 is a simplified schematic diagram illustrating a buck regulator with a typical implementation of PFM.

[0007] Figure 3 is a plot illustrating characteristic signals of the buck regulator illustrated in Figure 2

[0008] Figure 4 is a plot illustrating burst mode operation.

[0009] Figure 5 is a schematic diagram of an example DC-DC regulator, illustrated in accordance with an embodiment.

[0010] Figure 6 is a plot illustrating operation of PFM for discontinuous VOUT sensing in an example of Figure 5 ​​

[0011] Figure 7 is a schematic diagram illustrating an exemplary application of the present embodiments.

[0012] Figure 8 and Figure 9 is a schematic diagram illustrating an example of a low power offline regulator with flyback topology.

[0013] Figure 10 and Figure 11 is a schematic diagram illustrating an example of a low power offline regulator with flyback topology. DETAILED DESCRIPTION

[0014] The present embodiments will now be described in detail with reference to the accompanying drawings, provided by way of illustration of the embodiments described and the exemplary examples provided, in order to enable those skilled in the art to practice the embodiments and alternatives falling within the scope of the present embodiments. Notably, the following drawings and examples are not meant to limit the scope of the present embodiments to a single embodiment, but other embodiments are possible with the exchange of some or all of the elements described or illustrated. Moreover, where certain elements of the present embodiments can be implemented in part using known components, only those portions of such known components that are necessary for an understanding of the present embodiments will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the present embodiments. Embodiments described as being implemented in software should not be limited thereto, but can encompass embodiments implemented in hardware, or combinations of software and hardware, as will be apparent to one of ordinary skill in the art, unless otherwise specified herein. In this description, embodiments showing a single component should not be considered limiting; rather, the present disclosure is intended to encompass other embodiments including multiple identical components, and vice versa, unless otherwise expressly stated herein. Furthermore, Applicant does not intend to be bound by any term in the specification or claims other than as set forth in the following claims unless explicitly recited herein. Moreover, the present embodiments encompass presently known equivalents as well as future known equivalents in addition to the materials, designs, manufactures, and processes referred to herein which are presently known or which are hereafter devised.

[0015] The present embodiments relate to methods and apparatus for controlling a DC-DC converter, for example, a PFM control method for a DC-DC regulator using intermittent VOUT sensing. In these and other embodiments, PIN_MIN can be adjusted by external components already in use in typical applications, thus not requiring additional pins or components.

[0016] There are techniques for controlling DC-DC control methods, including: intermittent VOUT sensing (high-side buck converter given as an example); pulse frequency modulation (PFM) with continuous VOUT sensing; and burst mode with intermittent VOUT sensing.

[0017] Figure 1 This is a schematic diagram illustrating an example high-side step-down regulator.

[0018] As shown in the figure, the regulator is "floating," and the control circuit system references the switching node—not ground. Therefore, V OUT It is not continuously monitored; that is, the regulation is based on being charged to V during the conduction period of D2 and D1. OUT C SAMPLE Voltage. The PFM operates in intermittent conduction mode (DCM), therefore when V OUT When not being monitored, the control block should begin pulsating. This is consistent with the use of continuous V. OUT Typical PFM methods for sensing are incompatible.

[0019] Figure 2 This is a simplified schematic diagram illustrating a typical implementation of a buck regulator with PFM.

[0020] Figure 3 It is shown in Figure 2 The graph shows the characteristic signal of the buck regulator.

[0021] onceV OUT Voltage drops below V TRIGGER A certain level generates a pulse. The result is V. OUT The load current slowly discharges the output capacitor, causing V to rise. OUT Attenuation, which creates the condition for the next pulse. V TRIGGER Voltage level is defined by the following formula:

[0022]

[0023] The output current is given by the following formula:

[0024]

[0025] Pulses are generated only when needed, and the switching frequency is proportional to the output current. Note that this scheme requires continuous monitoring of V. OUT Therefore, the PFM scheme described herein is incompatible with topologies that have intermittent VOUT sensing topologies (e.g., "high-side" buck and "primary sensing" buck).

[0026] To overcome this problem, "burst mode" operation is usually used to achieve low P. IN_MIN . Figure 4 This is a graph illustrating the operation in burst mode.

[0027] onceV OUT Exceeding the planned V OUT_PEAK The voltage regulator then stops generating the preset T. OFF_FIXEDa pulse of time. During this time period, the output voltage decays, and after the timer expires, the regulator resumes operation. The modulation is achieved by varying the length of the "burst" period T BURST If I OUT is high, the output voltage will drop more during the fixed T OFF_FIXED time period and many pulses are needed to reach V OUT_PEAK ; if I OUT is low, a few pulses will recharge C OUT to V OUT_PEAK level, as V OUT drops almost nothing during T OFF_FIXED .

[0028] For integrated regulators, the burst mode has a clear disadvantage; the internal T OFF_FIXED timer produces a fixed P IN_MIN . If an adjustable P IN_MIN is needed, T OFF-FIXED should be adjustable, which requires a pin on the IC.

[0029] Figure 5 is a schematic diagram of an example DC-DC regulator according to an embodiment.

[0030] The regulation is based on the C SAMPLE ripple voltage. As long as D2 is on, D1 should also be on, so C SAMPLE should be charged to (approximately) V OUT level. Once D2 stops conducting, D1 is off and U1 sees the voltage drop present on C SAMPLE . During this time, C SAMPLE discharges slowly through R1 and R2. Once the non-inverting input of U1 becomes lower than the reference voltage VREF, it sets the RS flip-flop (assuming the timer expired) and the power MOSFET turns on. The drain current ramps up, and when the output of the current sense amplifier U3 reaches the VREF voltage, the comparator U2 resets the RS flip-flop. The power MOSFET is turned off, which forces D2 to conduct. At the same time, the timer block starts, which blocks the AND gate for a predetermined time period. When the timer re- enables the AND gate, the power MOSFET is not turned on until the time expires. The regulator is then ready for the next pulse.

[0031] Figure 6 is a graph showing the operation of the PFM for intermittent V OUT sensing in the example of Figure 5 .

[0032] Obviously, the voltage on C SAMPLE should decay faster than V OUT . Otherwise, the sampling will not capture the actual VOUT Because if C SAMPLE Voltage greater than V OUT If this happens, D1 will not be turned on. Therefore, we can write:

[0033]

[0034] C SAMPLE The ripple ΔV on the capacitor is:

[0035] ΔV=V OUT -V TRIGGER Eq.(2)

[0036] The trigger level V TRIGGER It is given by the following formula:

[0037]

[0038] Output current I OUT It can be represented as:

[0039]

[0040] For P IN_MIN We need I OUT_MIN In this case, the switching period T becomes T MAX Therefore, we can rewrite Eq.(4):

[0041]

[0042] The peak current of the inductor can be expressed as:

[0043]

[0044] TMAX is:

[0045]

[0046] By combining Eq.(5), Eq.(6), and Eq.(7), we obtain:

[0047]

[0048] because

[0049]

[0050] We ultimately obtained:

[0051]

[0052] Based on Eq.(10), it is possible to increase C OUT To reduce P at the costIN_MIN In other words, C IN_MIN may be determined for a desired P OUT , and then C SAMPLE , R1 and R2 can be determined from Eq. (1).

[0053] Figure 7 are schematic diagrams showing exemplary applications of the present embodiments. RAA223011 is a low power offline regulator that accepts a rectified universal AC input (85VAC to 265VAC) and converts it to a (typically) 12VDC output. As shown, the regulator uses a floating topology where the chip ground is connected to the switch node.

[0054] Regulators of this type are produced by many vendors. Figure 8 and Figure 9 are schematic diagrams showing examples of low power offline regulators with a floating topology.

[0055] Such products can also be used in different topologies. Figure 10 and Figure 11 are schematic diagrams showing examples of low power offline regulators with a flyback topology.

[0056] An important parameter of such products is the low input power PIN_MIN, which is specified and regulated by many national and international standards. Some competitors achieve low PIN_MIN without being simultaneously regulated (Power Integrations Link-Zero, as shown above). Other competitors specify low input power when the output is in regulation. This is more difficult to achieve, and RAA223011 is a member of this class of products.

[0057] Low PIN can only be achieved by low switching frequency (fSW) operation, which requires large output capacitors (COUT). As an example, in Figure 11 The part in the 1721A / B / D / F has 4 versions of the part: 1721A / B / D / F with 4 different burst frequencies 420Hz / 885Hz / 1260Hz / 1750Hz, as shown in Table 2 below:

[0058] Table 2 f burst As a function of C out and P IN(no-load)

[0059]

[0060] The version with f burst = 1750Hz is intended for applications with high requirements on load step behavior

[0061] We can see that lower pin P IN(no-load) requires large C​OUT More P IN Other parts require much smaller C OUT = 100 μF. In short, there are two parts available today: one can achieve low P IN But must have large C OUT Operation (optimized for low P IN Only) ; snf part cannot achieve low P IN But uses small C OU (optimized for low total BOM cost only). There does not appear to be an available part that covers both ends of the spectrum. RAA223011 uses P IN_MIN Modulation described herein, externally, without additional pin(s) and without additional part(s).

[0062] While the present embodiments have been particularly described with reference to the preferences of the application, it will be readily apparent to those of ordinary skill in the art that changes and modifications in form, substance and details can be made therein without departing from the spirit and scope of the disclosure. It is therefore intended that the appended claims cover all such changes and modifications that fall within the scope of the disclosure.

Claims

1. An electronic device comprising: A switching transistor, wherein the first terminal of the switching transistor is coupled to the input node (V) of the electronic device. DD ); Inductor (L) OUT The inductor is coupled to the second terminal of the switching transistor and to the output node (V) of the electronic device. OUT ); A controller is coupled to the control terminal of the switching transistor, wherein the controller includes a timer; Sampling capacitor (C) SAMPLE The first terminal of the sampling capacitor is coupled to the output node, and the second terminal of the sampling capacitor is coupled to the inductor; The voltage divider circuit (R1, R2) is coupled in parallel to the sampling capacitor; A first comparator (U1) has its first input terminal coupled to the voltage divider node of the voltage divider circuit, and its second input terminal coupled to the reference voltage (V). REF The output terminal of the first comparator is coupled to the controller; A current sensor is coupled between the switching transistor and the inductor; as well as The second comparator (U2) has its first input terminal coupled to the output terminal of the current sensor, its second input terminal coupled to the second input terminal of the first comparator, and its output terminal coupled to the controller.

2. The electronic device according to claim 1, wherein the controller comprises a first logic device and a second logic device. in, The first logic device is an AND gate, and the second logic device is an RS flip-flop. Wherein, the first input terminal of the first logic device is coupled to the output terminal of the timer, and the second input terminal of the first logic device is coupled to the output terminal of the first comparator; and Wherein, the first input terminal of the second logic device is coupled to the output terminal of the first logic device, the second input terminal of the second logic device is coupled to the output terminal of the second comparator, and the output terminal of the second logic device is coupled to the input terminal of the timer and the control terminal of the switching transistor.

3. The electronic device of claim 1, wherein the sampling capacitor, the voltage divider circuit, the first comparator, and the second comparator comprise sensors.

4. The electronic device of claim 1, wherein the current sensor includes a current sensing amplifier (U3), wherein the output terminal of the current sensing amplifier is coupled to a first input terminal of the second comparator as the output terminal of the current sensor.

5. The electronic device of claim 1, wherein the electronic device is configured to control a DC-DC converter.

6. The electronic device of claim 5, wherein the electronic device is configured to detect whether a discharge threshold of the DC-DC converter is met based on the voltage at the sampling capacitor.

7. The electronic device of claim 6, wherein the discharge threshold includes a voltage based on the output of the voltage divider circuit.

8. The electronic device of claim 5, wherein the electronic device is configured to detect whether a charging threshold of the DC-DC converter is met based on the current at the inductor.

9. A DC-DC converter, comprising an electronic device according to any one of claims 1 to 8 for controlling the DC-DC converter.

10. A method for operating an electronic device according to any one of claims 1 to 8, comprising: The voltage at the sampling capacitor is detected to be lower than a discharge threshold, which is based on the output of a voltage divider circuit coupled in parallel with the sampling capacitor; Apply a charging pulse current to the output capacitor; The current at the inductor coupled to the sampling capacitor and the voltage divider circuit exceeds the charging threshold. The charging pulse current is terminated in response to the detection that the charging threshold has been exceeded; as well as The sampling capacitor is discharged in response to the detection that the charging threshold has been exceeded.

11. The method of claim 10, further comprising: In response to the detection that the charging threshold has been exceeded, a timer configured with a delay threshold is started.

12. The method of claim 11, further comprising: The second condition is satisfied: the voltage at the sampling capacitor is lower than the discharge threshold. as well as In response to detecting a second satisfaction below the discharge threshold, a second charging pulse current is applied to the output capacitor.

13. The method of claim 11, wherein the charging threshold includes a maximum current threshold.

14. The method of claim 12, further comprising: Detect whether the delay threshold is met; Applying the second charging pulse current further includes applying the second charging pulse current to the output capacitor in response to detecting a second satisfaction below the discharge threshold and detecting the satisfaction of the delay threshold.

15. The method of claim 14, wherein the discharge threshold includes a minimum voltage threshold, and the delay threshold represents a predetermined time period.

Images