A stress isolation packaging structure for MEMS devices

Abstract

The invention relates to a stress isolation packaging structure of a MEMS device, belonging to the field of chip packaging, and specifically: a step is made on a packaging bottom plate of a packaging tube shell, a fixed area of ​​a stress isolation substrate is fixed on the step, a suspended area of ​​the stress isolation substrate is suspended above the packaging bottom plate to form a gap area with the packaging bottom plate, the fixed area and the suspended area are connected through a rigid substrate neck, a substrate isolation groove is made between the suspended area and the fixed area, the substrate isolation groove is outside the step and does not contact the step, a MEMS chip is fixed in the suspended area and does not directly contact the packaging tube shell, the mechanical stress transmitted to the MEMS chip by the packaging tube shell is isolated through the substrate isolation groove, and at the same time, it is ensured that the isolation system does not introduce other external interference factors that affect the performance of the MEMS chip, so that the performance of the MEMS chip will not be affected by environmental stress and deteriorated.

Description

Technical Field

[0001] The present invention relates to chip packaging, and in particular to a stress isolation packaging structure suitable for MEMS devices which are easily affected by stress and may cause performance changes or even failure. Background Art

[0002] The packaging of electronic components usually involves interconnecting electronic signals of one or more electronic chips and encapsulating them in a protective structure to provide mechanical protection or chemical corrosion protection, and to achieve electrical signal connection between the electronic chip and the outside of the package. Some electronic products, such as gyroscopes, accelerometers, oscillators, and bulk acoustic wave filters in MEMS devices, are very sensitive to stress, and their industrial-grade products need to be airtightly packaged with ceramic shells, metal shells, preformed plastic shells, etc. The usual method is to fix the back of the MEMS chip to the packaging base plate of the packaging shell through adhesive, and then interconnect the front leads to form a functional circuit, and finally add a packaging cover to seal it to form a MEMS sensor or actuator component that can be used in electronic products. Only the back of the MEMS chip is in contact with the shell through adhesive, and the front is not in contact with any solid. The stress caused by the package is introduced from the back of the MEMS chip.

[0003] The mechanical stress introduced by the package mainly comes from the unequal volume changes between the MEMS chip and the packaging material caused by temperature changes, as well as the mechanical deformation of the PCB board during use. The most commonly used material for MEMS chips is silicon, and its thermal expansion coefficient is 2.6ppm / K (2.6 parts per million / degree) at room temperature, which is difficult to find the same material; among the commonly used packaging shell materials, the alumina ceramic (thermal expansion coefficient ~7ppm / k) that is closest to the thermal expansion coefficient of silicon is also much larger than silicon; because the thermal expansion coefficient of the adhesive and the packaging shell material is different from that of the MEMS chip material (mainly silicon), during the packaging processing and subsequent high-temperature processes, such as adhesive curing, capping, SMT and daily use by end users, temperature changes cause inconsistent volume changes between the MEMS chip and the packaging shell and adhesive, thereby generating mechanical stress. In addition to temperature changes, PCB deformation caused by the assembly process, PCB deformation caused by mechanical vibration and mechanical shock during use by end users will also be transmitted to the MEMS chip through the packaging shell, causing abnormal deformation of the stress-sensitive MEMS structure. In severe cases, it will cause the MEMS structure to stick, the MEMS chip to fall off, or even break, which will be manifested in the output signal of the MEMS sensor as a drift of the zero point and sensitivity, and the output signal will be saturated or there will be no output signal.

[0004] Therefore, considering that the device performance and reliability may change due to the influence of external stress during the packaging and use process, we need to fully consider the packaging structure to reduce or eliminate the impact and influence of external stress on the micromechanical structure of the MEMS chip, while at the same time completely lead the electrical signals generated by the MEMS to the outside through the package body.

[0005] When packaging MEMS devices, reducing or isolating packaging stress is an important consideration. Existing methods for reducing or isolating packaging stress generally include the following: (1) Adding an isolation layer between the MEMS chip and the package body or using a soft adhesive with low hardness to stick the MEMS chip. The disadvantage is that the soft adhesive is easy to deform and has weak resistance to mechanical impact. In addition, for some MEMS devices, such as MEMS actuators and MEMS gyroscopes, the soft adhesive will also reduce the performance of the device. (2) Reducing the contact area between the MEMS chip and the packaging tube shell. The disadvantage is that the mechanical strength of the connection between the chip and the tube shell is low and the resistance to mechanical impact is weak. In addition, the small contact area between the two will cause unbalanced deformation of the MEMS chip, and the performance will be worse. (3) The MEMS chip is installed in the tube shell through an elastic packaging liner. The disadvantage is that the liner cost is high, the packaging process is complicated, the resistance to mechanical impact is weak, and it may also cause signal delays.

[0006] In the prior art, the patent number CN110723713A shows a method of using 3D printing stress buffer layer on the package substrate, adding an array of alternating overlapping stress isolation layers of a certain thickness between the package substrate and the MEMS mounting layer to relieve the stress transmitted by the substrate. The criss-cross columnar strips can effectively eliminate the strain from the package tube shell substrate through layer-by-layer buffering. However, the bonding between the MEMS and the isolation layer causes serious unevenness between the mounting glue and the MEMS bonding surface due to the depression between the strips, artificially causing the imbalance of the MEMS chip when the top column strip itself generates stress. The MEMS chip is subjected to a large tensile force along the strip direction of the topmost isolation layer, while in the vertical direction, due to the existence of the gap between the strips, no or less stress is generated. In this way, for the MEMS chip, the tensile deformation is unbalanced, and the impact on the device with symmetrical MEMS structure is obvious. In addition, under normal circumstances, the height and size of our package cavity are limited, so the thickness of the isolation layer is very limited, and 3D printing is also challenging for cost and mass production.

[0007] The patent (CN201911000389.9) adopts a spring-type flexible connection. The MEMS carrier uses silicon wafer etching to form a planar corrugated spring mechanism, and the two ends are stretched and suspended on the support frame. This structure is similar to a carrier suspended by springs at both ends. The MEMS chip is installed on the MEMS carrier. The stress transmitted by the package is completely relieved through the micro-deformation of the planar corrugated elastic mechanism. The MEMS chip installed on the carrier is basically not affected by the stress of the package. This patent has a significant effect in alleviating the stress of the packaging shell, but the disadvantages of this method are also obvious and it is difficult to implement in practice for the following reasons: 1) The corrugated spring structure formed by etching itself has limited stiffness. It is difficult to ensure that the planar corrugated mechanism will not be damaged when the MEMS is subsequently assembled on the carrier. If the stiffness of the planar corrugated spring is increased, it is difficult to ensure that the stress transmitted from the packaging shell will not be transmitted to the MEMS carrier; 2) Since the MEMS carrier suspension mechanism adopts a flexible connection, external vibrations can easily be transmitted to the MEMS carrier mechanism through the corrugated spring structure. The resonance between the MEMS and the carrier will overlap with the MEMS signal, causing great interference to the MEMS signal, seriously affecting the stability of the MEMS signal output, and it is difficult to ensure the linear output of the MEMS signal; 3) The inherent resonance characteristics of the spring structure will also have a hysteresis effect on the frequency response of certain types of sensors.

[0008] The US patent (US 20180230005A1) describes various types of three-dimensional vibration and stress isolation bases, which are also made by making an independent bearing platform, and the bearing platform and the periphery of the structure are connected by local elastic suspension to achieve a flexible connection between the MEMS chip bearing platform and the package. It is similar to the plane corrugation connection in the patent (CN201911000389.9). In addition to being stronger than the plane corrugation spring mechanism, it also has the disadvantages of resonance and resonance of the plane corrugation connection.

[0009] Patent US 10278281B1 shows a packaging method that uses a rigid stress isolation plate to avoid direct contact between MEMS and the package shell. The stress isolation plate is made into a stepped boss shape, the upper boss is used to support the MEMS, and the lower step is directly connected to the package shell. The upper boss of the stress isolation mechanism uses a plane smaller than the MEMS chip to support the MEMS chip, in order to reduce the contact area between the MEMS chip and the mounting surface, so as to reduce the stress on the MEMS. The stress isolation mechanism digs a pit at the bottom of the step, in order to reduce the contact surface between the entire isolation system and the package shell, and reduce the stress of the stress isolation mechanism from the package shell. At the same time, a certain isolation groove is dug on the front of the lower part of the step to weaken the transmission of stress between the two parts of the step. This rigid stress isolation plate reduces the stress transmitted from the outside to the MEMS chip by gradually reducing the strain of the package shell. Structurally, since the area of ​​the boss on the top of the step is smaller than the area of ​​the MEMS chip, it is difficult to achieve absolute symmetry in the installation of the MEMS chip on the boss, and the supporting surface of the boss itself with a certain area will also produce strain with changes in external conditions. This causes the stress of the boss on the MEMS chip to be local. The local stress changes the local characteristics of the MEMS chip, making it difficult for the MEMS chip to achieve the design expectations or causing instability in the device operation.

[0010] Patent US 8698292B2 adopts a method of preparing bumps on a glass plane to reduce the contact area between the MEMS chip and the substrate. The smaller the bumps, the smaller the bump stress on the MEMS chip. Similar to the principle in patent US 10278281B1, it is difficult to achieve symmetrical installation of the MEMS chip on the supporting surface on the contact bumps, and the possibility of unbalanced stress on the MEMS still exists. Summary of the invention

[0011] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a stress isolation packaging structure for a MEMS device, which isolates the mechanical stress transmitted to the MEMS chip by the packaging shell through a stress isolation substrate, while ensuring that the isolation system does not introduce other external interference factors that affect the performance of the MEMS chip.

[0012] In order to solve the above technical problems, the present invention provides a stress isolation packaging structure of a MEMS device, comprising a packaging tube shell, a stress isolation substrate and a packaging cover plate;

[0013] The package tube shell is composed of a package bottom plate and a first step layer, a second step layer, and a third step layer, which enclose a cavity. The first step is provided with a first step and a gap area. The package tube shell also has an inner pad inside and an outer pad outside. The inner pad and the outer pad are electrically connected through an internal circuit of the package tube shell.

[0014] The stress isolation substrate is composed of three parts: a suspended area, a substrate neck and a fixed area. The suspended area and the fixed area are connected through the substrate neck, and a substrate isolation groove is made between the suspended area and the fixed area.

[0015] The fixed area is fixed on the first step, the suspended area is suspended on the gap area, and the substrate isolation groove is outside the first step and does not contact the first step;

[0016] The MEMS chip is fixed on the suspended area, and the ASIC chip is fixed on the suspended area or fixed area of ​​the stress isolation substrate. Both the ASIC chip and the MEMS chip are connected to the inner pads of the packaging shell through metal wires, and the ASIC chip and the MEMS chip are also interconnected through metal wires. The packaging cover plate is welded on the packaging shell, and together with the packaging shell, it forms a sealed cavity to protect the MEMS chip and the ASIC chip.

[0017] The present invention also provides another stress isolation packaging structure, including a packaging tube shell, a stress isolation substrate and a packaging cover plate;

[0018] The package tube shell comprises a package bottom plate, a pad is fixed on the package bottom plate, an inner pad is provided inside the package tube shell, an outer pad is provided outside the package tube shell, and the inner pad and the outer pad are electrically connected through an internal circuit of the package tube shell;

[0019] The stress isolation substrate is composed of three parts: a suspended area, a substrate neck and a fixed area. The suspended area and the fixed area are connected through the substrate neck, and a substrate isolation groove is made between the suspended area and the fixed area.

[0020] The fixed area is fixed on the pad, the suspended area is suspended above the package bottom plate to form a gap area with the package bottom plate, and the substrate isolation groove is outside the pad and does not contact the pad;

[0021] The MEMS chip is fixed on the suspended area, and the ASIC chip is fixed on the suspended area or fixed area of ​​the stress isolation substrate. Both the ASIC chip and the MEMS chip are connected to the inner pads of the packaging shell through metal wires, and the ASIC chip and the MEMS chip are also interconnected through metal wires. The packaging cover plate is welded on the packaging shell, and together with the packaging shell, it forms a sealed cavity to protect the MEMS chip and the ASIC chip.

[0022] The stress isolation packaging structure of the present invention uses a rigid stress isolation substrate as a packaging substrate for a MEMS chip, wherein a fixed area of ​​the stress isolation substrate is fixed on a packaging shell, and a suspended area is suspended from the packaging shell, a substrate isolation groove is made between the fixed area and the suspended area, and the fixed area and the suspended area are connected via a rigid substrate neck; the MEMS chip is mounted in the suspended area and is not in direct contact with the packaging shell, and the mechanical stress conducted by the packaging shell is isolated by the substrate isolation groove, so that the performance of the MEMS chip will not be degraded by environmental stress.

[0023] As an embodiment of the present invention, there is only one substrate neck, and the width of the substrate neck is 1 / 10 to 1 / 2 of the width of the stress isolation substrate. The width of the substrate neck is determined according to the packaging requirements. The larger the width, the stronger the mechanical impact resistance of the packaged product, but the worse the stress isolation effect; conversely, the smaller the width, the worse the mechanical impact resistance of the packaged product, but the better the stress isolation effect.

[0024] As another embodiment of the present invention, there may be at least two substrate necks, which divide the substrate isolation groove into an edge substrate isolation groove and an intermediate substrate isolation groove. The intermediate substrate isolation groove is located between two adjacent substrate necks. The width of the substrate neck does not exceed 1 / 3 of the width of the stress isolation substrate. Although the ability to resist mechanical impact is improved compared with having only one substrate neck, the stress isolation performance is reduced to a certain extent.

[0025] In one embodiment of the present invention, a thin film heating resistor and a thin film temperature sensor are also fabricated on the suspended area of ​​the stress isolation substrate, and the temperature of the MEMS chip is kept constant through an external temperature control circuit to eliminate the influence of temperature changes on the performance of the MEMS chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 1 is a top view of the stress isolation packaging structure of the first embodiment.

[0027] Figure 2 yes Figure 1 AB section view.

[0028] Figure 3 is a cross-sectional view of the packaging tube shell of the first embodiment.

[0029] Figure 4 FIG. 1 is a top view of the stress isolation substrate of the first embodiment.

[0030] Figure 5 is a cross-sectional view of the stress isolation packaging structure of the second embodiment.

[0031] Figure 6 is a cross-sectional view of the stress isolation packaging structure of the third embodiment.

[0032] Figure 7 FIG. 4 is a top view of the stress isolation substrate of the fourth embodiment. DETAILED DESCRIPTION

[0033] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0034] Embodiment 1

[0035] A stress isolation packaging structure of a MEMS device Figure 1 , Figure 2 As shown, the package tube shell 10 has a first step 13a, the fixed area 43 of the stress isolation substrate 40 is fixed on the first step 13a of the package tube shell by the die bonding glue 31, and the suspended area 41 of the stress isolation substrate 40 is suspended above the gap area 13b of the package tube shell 10; a substrate isolation groove 47 is made between the fixed area 43 and the suspended area 41 of the stress isolation substrate 40 for isolating stress, the fixed area 43 of the stress isolation substrate 40 is connected to the suspended area 41 through the substrate neck 45, and the substrate isolation groove 47 is outside the first step 13a of the package tube shell 10 and does not contact the first step 13a;

[0036] The MEMS chip 25 is fixed on the suspended area 41 of the stress isolation substrate 40 by the die bonding glue 31, and the ASIC chip 27 is fixed on the fixed area 43 of the stress isolation substrate 40 by the die bonding glue 31. The ASIC chip 27 and the MEMS chip 25 are interconnected by the metal wire 35. The ASIC chip 27 and the MEMS chip 25 can also be connected to the inner pad 19 of the package shell 10 by the metal wire 35. The inner pad 19 leads the electrical signal to the outer pad of the package shell 10 through the circuit inside the package shell 10; similarly, if electronic components such as heaters, resistors, inductors, capacitors, etc. are also made on the stress isolation substrate, the substrate pad 49 of the stress isolation substrate 40 can also be connected to the ASIC chip or the inner pad 19 through the metal wire 35. The package cover plate 37 and the package shell 10 are welded by solder 33 to form a sealed cavity 39, and the MEMS chip 25 and the ASIC chip 27 are well protected. Since the MEMS chip 25 is mounted on the suspended area 41 of the stress isolation substrate 40 and is not in direct contact with the packaging shell 10, the mechanical stress transmitted by the packaging shell 10 is isolated by the substrate isolation groove 47, so that the performance of the MEMS chip 25 will not be degraded by environmental stress; the substrate neck 45 is a part of the stress isolation substrate 40, and is made of the same material and is a rigid structure that can withstand mechanical impact, so the metal wire 35 can be bonded to the MEMS chip 25 through an ordinary bonding process to achieve signal connection; at the same time, the substrate neck 45 can promptly transmit the mechanical motion signal transmitted by the packaging shell 10 to the MEMS chip 25, and will not cause signal delay or interference like the elastic stress isolation structure in the prior art.

[0037] The package tube shell 10 of the present invention provides a sealed cavity for protecting the chip and leading out the electrical signal for the system. The material of the package tube shell 10 can be a ceramic package tube shell, a metal tube shell, a PCB board tube shell, or a preformed plastic package tube shell; the ceramic tube shell is used as an example for explanation. Figure 3 As shown, the package tube shell 10 is composed of a package base plate 11 and a first step layer 13, a second step layer 15, and a third step layer 17, which enclose a cavity 38; a first step 13a and a gap area 13b are made on the first step layer 13, the first step 13a is used to install a stress isolation substrate 40, and the gap area 13b prevents the stress isolation substrate 40 from contacting the package base plate 11, and the thickness of the first step layer 13 is usually between 0.1mm and 5mm; the inner pad 19 is made on the second step layer 15, and the thickness of the second step layer 15 is usually between 0.1mm and 5mm. 5mm, (in an extreme example, the second step layer is eliminated and the inner pad 19 is directly made on the first step layer 13, but this method has a large tube shell area and low strength.) The thickness of the third step layer 17 is usually between 0.1mm and 5mm, and a metallized pattern can be made on the surface for metal melting sealing with the alloy solder of the packaging cover 37, or a Kovar alloy ring can be made for parallel sealing with the packaging cover 37, or nothing can be done and the ceramic material can be directly used and bonded and sealed with the packaging cover 37 by a sealant (such as epoxy glue).

[0038] In order to avoid the stress isolation substrate 40 introducing additional mechanical stress, the stress isolation substrate 40 is made of a material with similar properties to the material of the MEMS chip 25, especially a material with a similar thermal expansion coefficient, preferably the same material. Usually, the material of the MEMS chip 25 is Si, and the stress isolation substrate 40 should also be made of Si material. Here, Si material is used as an example. Figure 4 As shown, the stress isolation substrate 40 of Si material is divided into three parts, namely, a suspended area 41, a substrate neck 45 and a fixed area 43, by a substrate isolation groove 47, on which a heating resistor 51, a thermistor 53, a metal lead 55 and a substrate pad 49 are made, wherein the heating resistor 51 and the thermistor 53 are made on the suspended area 41, and the substrate pad 49 is made on the fixed area 43. The heating resistor 51 is connected to the substrate pads 49a and 49c through the metal lead 55, and the thermistor 53 is connected to the substrate pads 49b and 49d through the metal lead 55; the thickness of the stress isolation substrate 40 is 0.1mm to 2mm, and it is made of ordinary Si wafers in the semiconductor industry, and can be single crystal Si or polycrystalline Si material, without any requirements on doping concentration, and even scrapped wafers in the semiconductor industry can be used, which is low in cost.

[0039] The manufacturing method of the stress isolation substrate 40 is briefly as follows: an insulating layer and a heating resistor 51, a thermistor 53, a metal lead 55 and a substrate pad 49 are manufactured on a Si material wafer. The manufacturing method can be a semiconductor processing technology such as deposition, photolithography, and etching, or a screen printing process; the heating resistor 51, the thermistor 53, the metal lead 55 and the substrate pad 49 can be made of different materials or the same material, such as Pt; the power of the heating resistor 51 is controlled by an external circuit according to the temperature signal represented by the thermistor 53, and the substrate isolation groove 47 also plays a role in reducing heat loss. Under the condition of consuming lower power, the suspended area 41 and the ME mounted thereon are kept The temperature of the MEMS chip 25 is constant, eliminating the influence of temperature changes on the performance of the MEMS chip 25; the substrate isolation groove 47 is formed by laser cutting, sandblasting or semiconductor processing technology, among which laser processing is simpler and cheaper, and the material disc can be cut into small pieces of stress isolation substrate 40 while forming the substrate isolation groove 47; the width of the substrate neck 45 is determined according to the packaging requirements. The larger the width, the stronger the mechanical impact resistance of the packaged product, but the worse the stress isolation effect. On the contrary, the smaller the width, the worse the mechanical impact resistance of the packaged product, but the better the stress isolation effect. Generally, the width of the substrate neck 45 is 1 / 10 to 1 / 2 of the width of the stress isolation substrate 40. The substrate neck 45 can be located at the center of the stress isolation substrate 40 along the Y direction, or at a non-center of the stress isolation substrate 40 along the Y direction.

[0040] In some applications, in order to reduce costs or power consumption, heating resistors and temperature control are not required, and the stress isolation substrate 40 can be divided into three parts: a suspended area 41, a substrate neck 45 and a fixed area 43. There is a substrate isolation groove 47 between the suspended area 41 and the fixed area 43, which is used to isolate the mechanical stress transmitted from the fixed area 43 to the suspended area 41; the substrate isolation groove 47 is formed by laser cutting, sandblasting or semiconductor processing technology, wherein laser processing does not require a mask template, which is simpler and more convenient. While forming the substrate isolation groove 47, the material wafer can be cut into small pieces of stress isolation substrate 40; the width of the substrate neck 45 is determined according to the packaging requirements. The larger the width, the stronger the mechanical impact resistance of the packaged product, but the worse the stress isolation effect. Conversely, the smaller the width, the worse the mechanical impact resistance of the packaged product, but the better the stress isolation effect. Generally, the width of the substrate neck 45 is 1 / 10 to 1 / 2 of the width of the stress isolation substrate 40.

[0041] The assembly method includes the following steps:

[0042] (1) Stress isolation substrate 40 loading and curing:

[0043] Using a chip mounter, firstly, a chip mount glue 31 is applied on the first step 13a of the package tube shell 10. The chip mount glue 31 is made of silver paste or epoxy glue with high hardness. The suction nozzle of the chip mounter selects the fixed area 43 as the suction position for the stress isolation substrate 40. During the chip mount process, ensure that the substrate isolation groove 47 is outside the first step 13a, and ensure that the chip mount glue 31 does not flow through the substrate isolation groove 47 and contact the suspended area 41;

[0044] The package tube shell 10 with the stress isolation substrate 40 installed is put into an oven for curing. The thickness of the stress isolation substrate adhesive after curing is 20-30 μm. In this way, a suspended structure with the stress isolation substrate 40 is obtained.

[0045] (2) ASIC chip installation:

[0046] Glue is applied to the ASIC chip 27 mounting area. The ASIC chip mounting area is selected in the fixed area 43 of the stress isolation substrate 40. There is no special restriction on the selection of ASIC mounting glue, which can be the same as the stress isolation substrate mounting glue. The thickness of the ASIC mounting glue after curing is 20-30 μm.

[0047] (3)MEMS chip curing:

[0048] Glue is applied to the suspended area 41 of the stress isolation substrate to install the MEMS chip 25. There are many options for MEMS mounting glue. This embodiment takes the same mounting glue as the stress isolation substrate 40 as an example. The thickness of the MEMS mounting glue is between 10 and 150 μm. After the mounting process is completed, the mounting glue is cured according to the curing curve to fix the AISC chip and the MEMS chip at the same time.

[0049] (4) Wire bonding:

[0050] Wire bonding is performed according to the package design; the pads 19 in the package shell, the ASIC chip 27, the MEMS chip 25, and the stress isolation substrate 40 are connected according to the assembly drawing for wire interconnection; the height of each arc and the wire pull force of each line are monitored to meet the design requirements and SPC quality monitoring;

[0051] (5) Capping:

[0052] Select the sealing method according to the packaging needs, such as flat sealing, alloy solder melting sealing or epoxy sealing;

[0053] (6) Finished product inspection:

[0054] Inspect products according to product performance or quality control specifications and perform performance tests or quality inspections on products.

[0055] Embodiment 2:

[0056] The stress isolation packaging structure of this embodiment is as follows Figure 5 As shown, compared with the packaging structure of the first embodiment, the only difference is that: no steps are made on the packaging tube shell 10, but the pad 80 is fixed to the packaging base plate 11 by the die bonding glue 31, the fixed area 43 of the stress isolation substrate 40 is fixed to the pad 80 by the die bonding glue 31, and the suspended area 41 of the stress isolation substrate 40 is suspended above the packaging base plate 11, and a gap area 11b is formed between the suspended area 41 and the packaging base plate 11; the material of the pad 80 is made of a material with similar properties to the material of the MEMS chip 25, especially a material with a similar thermal expansion coefficient, preferably the same material, usually the material of the MEMS chip 25 is Si, preferably, the pad 80 is also made of Si material; the size of the pad 80 is preferably not larger than the size of the fixed area 43; a substrate isolation groove 47 is made between the fixed area 43 and the suspended area 41 for isolating stress, the fixed area 43 is connected to the suspended area 41 through the substrate neck 45, and the substrate isolation groove 47 is outside the pad 80 and has no contact with the pad 80.

[0057] Embodiment three:

[0058] The stress isolation packaging structure of this embodiment is as follows Figure 6 As shown, compared with the packaging structure of the first embodiment, the only difference is that: the MEMS chip 25 and the ASIC chip 27 are both mounted on the suspended area 41 of the stress isolation substrate 40, wherein the MEMS chip 25 is fixed on the suspended area 41 by the die bonding glue 31, and the ASIC chip 27 is fixed on the MEMS chip 25 by the die bonding glue 31 (it can also be: the ASIC chip 27 and the MEMS chip 25 are fixed side by side on the suspended area 41 or the ASIC chip 27 is fixed on the suspended area 41 by the die bonding glue 31, and the MEMS chip 25 is fixed on the ASIC chip by the die bonding glue 31). The ASIC chip 27 and the MEMS chip 25 are interconnected through metal wires 35, and the ASIC chip 27 and the MEMS chip 25 are also connected to the inner pads 19 of the package shell 10 through the metal wires 35, and the inner pads 19 lead out the electrical signals through the circuit inside the package shell 10.

[0059] Embodiment 4:

[0060] In order to enhance the ability to resist mechanical shock, the stress isolation substrate 40 is divided into four parts: a suspended area 41, two substrate necks 45 and a fixed area 43. Figure 7As shown, there are edge substrate isolation grooves 47a and intermediate substrate isolation grooves 47b between the suspended area 41 and the fixed area 43, wherein the intermediate substrate isolation groove 47b is located between the two substrate necks 45, and its size is determined according to product requirements, and generally does not exceed 1 / 3 of the width of the stress isolation substrate 40; compared with embodiments 1 to 3, the materials and processing methods are the same, the mechanical impact resistance is higher, but the stress isolation performance is reduced to a certain extent.

[0061] The above is only the best embodiment of the present invention. It should be pointed out that, for ordinary technicians in this field, without departing from the principle of the present invention, the technical solution of the present invention can be modified or replaced by equivalents, which can also achieve the technical effect of the present invention and should also be regarded as belonging to the protection scope of the present invention.

Claims

1. A stress isolation packaging structure of a MEMS device, comprising a packaging tube shell, a stress isolation substrate and a packaging cover plate; Features: The package shell comprises a package bottom plate and a first step, an inner pad is provided inside the package shell, and an outer pad is provided outside the package shell, and the inner pad and the outer pad are electrically connected through an internal circuit of the package shell; The stress isolation substrate is composed of three parts: a suspended area, a substrate neck and a fixed area. The suspended area and the fixed area are connected through the substrate neck, and a substrate isolation groove is made between the suspended area and the fixed area. The fixed area is fixed on the first step, the suspended area is suspended on the package bottom plate, and a gap area is formed between the package bottom plate, and the substrate isolation groove is outside the first step and does not contact the first step; The MEMS chip is fixed on the suspended area, and the ASIC chip is fixed on the suspended area or fixed area of ​​the stress isolation substrate. The ASIC chip and the MEMS chip are connected to the inner pad of the package shell through metal wires, and the ASIC chip and the MEMS chip are also interconnected through metal wires. The package cover plate is welded on the package shell, and together with the package shell, forms a sealed cavity for protecting the MEMS chip and the ASIC chip.

2. A stress isolation packaging structure of a MEMS device, comprising a packaging tube shell, a stress isolation substrate and a packaging cover plate; Features: The package tube shell comprises a package bottom plate, a pad is fixed on the package bottom plate, an inner pad is provided inside the package tube shell, an outer pad is provided outside the package tube shell, and the inner pad and the outer pad are electrically connected through an internal circuit of the package tube shell; The stress isolation substrate is composed of three parts: a suspended area, a substrate neck and a fixed area. The suspended area and the fixed area are connected through the substrate neck, and a substrate isolation groove is made between the suspended area and the fixed area. The fixed area is fixed on the pad, the suspended area is suspended above the package bottom plate to form a gap area with the package bottom plate, and the substrate isolation groove is outside the pad and does not contact the pad; The MEMS chip is fixed on the suspended area, and the ASIC chip is fixed on the suspended area or fixed area of ​​the stress isolation substrate. The ASIC chip and the MEMS chip are connected to the inner pad of the package shell through metal wires, and the ASIC chip and the MEMS chip are also interconnected through metal wires. The package cover plate is welded on the package shell, and together with the package shell, forms a sealed cavity for protecting the MEMS chip and the ASIC chip.

3. The stress isolation packaging structure of a MEMS device as claimed in claim 1 or 2, characterized in that: There is only one substrate neck, and the width of the substrate neck is 1 / 10 to 1 / 2 of the thickness of the stress isolation substrate.

4. The stress isolation packaging structure of a MEMS device as claimed in claim 1 or 2, characterized in that: There are at least two substrate necks, which divide the substrate isolation groove into an edge substrate isolation groove and an intermediate substrate isolation groove. The intermediate substrate isolation groove is located between two adjacent substrate necks, and the width of the substrate neck does not exceed 1 / 3 of the width of the stress isolation substrate.

5. The stress isolation packaging structure of a MEMS device as claimed in claim 1 or 2, characterized in that: The material of the stress isolation substrate is Si, and the thickness is 0.1 mm to 2 mm.

6. The stress isolation packaging structure of a MEMS device as claimed in claim 2, characterized in that: The material of the pad is Si, and the size of the pad is not larger than the size of the fixing area.

7. The stress isolation packaging structure of a MEMS device as claimed in claim 1 or 2, characterized in that: Electronic components, metal leads and substrate pads are made on the stress isolation substrate. The electronic components are interconnected through metal leads and connected to the substrate pads. The substrate pads are electrically connected to the ASIC chip or internal pads through metal wires. The electronic components include heaters, resistors, inductors or capacitors.

8. The stress isolation packaging structure of a MEMS device as claimed in claim 7, characterized in that: The electronic components are a thin film heating resistor and a thin film temperature sensor, which are located on a suspended area of ​​a stress isolation substrate and are externally connected to a temperature control circuit.

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