A tail current biasing circuit for a signal amplifier in SiGe technology

Abstract

A tail current bias circuit for a SiGe process signal amplifier, the port of the bias current source for outputting the bias current is connected to the collector of transistor Q1, the emitter of the transistor Q1 is grounded after passing through resistor R1, the base of the transistor Q1 is connected to the base of transistor Q2, the emitter of the transistor Q2 is grounded together with the ground terminal of resistor R2 and resistor R1 after passing through resistor R2, and the base of the transistor Q1 is also grounded together with the ground terminals of resistor R2 and resistor R1 after passing through capacitor C1; the collector of the transistor Q2 is respectively connected to the emitters of two transistors Q3 and Q4, the collector of the transistor Q3 is connected to the power supply after passing through resistor R3, the collector of the transistor Q4 is connected to the power supply after passing through resistor R4, and the bases of the transistors Q3 and Q4 are respectively connected to a differential signal input; the collector of the transistor Q1 is connected to the base of the transistor Q1 through a DNW CMOS module.

Description

Technical Field

[0001] The present invention relates to the field of bias circuits, and particularly to a tail current bias circuit for a signal amplifier in SiGe technology. Background Art

[0002] TSAO402 is a high-speed optical communication chip designed using SiGe HBT technology. To ensure the high-speed channel bandwidth and the quality of the transmitted signal, a large current drive is required. Therefore, it is necessary to reduce the power supply voltage of the high-speed signal channel to reduce the overall power consumption of the chip, making it more competitive in the market.

[0003] Reducing the power supply voltage will result in a limited voltage space available for the internal circuits of the chip. At the same time, due to the large current inside the chip, a significant voltage drop will be formed with the resistance of the power supply metal layer and vias. Therefore, the internal power supply voltage is often further reduced compared to the external power supply voltage, which further compresses the voltage space of the internal circuits of the chip.

[0004] In such a situation, for the high-speed signal channel, if the traditional design is adopted, the CMOS transistor of the current source that supplies power to the bias circuit for the tail current of the high-speed signal amplifier cannot operate normally in the saturation region due to insufficient voltage space, resulting in the current of the current source supplied to the bias circuit being less than expected. Moreover, there are significant deviations under different process corners, greatly degrading the quality of the output signal of this stage of the high-speed amplifier and the consistency of various indicators.

[0005] When designing using SiGe HBT technology, in order to save power consumption, chip design engineers usually reduce the traditional 3.3V to 1.8V. The following lists three traditional designs for the tail current source bias circuit of high-speed signal amplifiers:

[0006] The first traditional design uses a single CMOS transistor for the tail current source and bias circuit design, which can avoid problems such as Figure 1 the current source of the bias circuit not being able to operate normally due to the large voltage space required by the B-type current source. However, since CMOS devices will introduce large parasitic capacitances and the tail current source has a low impedance, it will also affect the quality of the output large-signal eye diagram. Therefore, it is not suitable for circuit designs that require high-speed signal quality under the current process, such as high-speed signal transmission circuits with a transmission rate exceeding 10 Gbps.

[0007] The second traditional design is as shown in Figure 2, a tail current source and bias circuit design using stacked CMOS is adopted. This structure realizes the problem of avoiding low impedance of the tail current source on the basis of sacrificing the voltage space of the tail current bias circuit. For the stacked Cascode NMOS, it can also reduce a certain parasitic capacitance of the tail current source at the same time, but its parasitic capacitance is still relatively large compared with the BJT NPN transistor. In addition, the voltage space of the bias circuit is also relatively tight in the case of the Cascode current source.

[0008] The third traditional design is as Figure 3 , a tail current source and bias circuit design using BJT NPN transistors is adopted. This design takes advantage of the small parasitic capacitance of BJT transistors. This design can meet the circuit design requirements with certain signal quality. For this type of circuit, in order to ensure the accuracy of current mirror matching, a feedback BJT triode and an emitter resistor are usually added as auxiliary components. This structure is called Beta Helper. This circuit structure has the advantages of high current mirror matching accuracy, small parasitic capacitance of the tail current source, and high impedance of the tail current source. However, since the bias circuit wastes a large amount of voltage space on the feedback BJT, the voltage drop generated by two Vbe plus a resistor for improving accuracy makes it difficult for the PMOS of the current source above the bias circuit to work properly even when only a single transistor is used. Therefore, it is not suitable for circuit designs with low-voltage power supply. Summary of the Invention

[0009] The object of the present invention is to provide a tail current bias circuit for a SiGe process signal amplifier, which modifies the traditional Beta Helper based on the above third design, can meet demanding current source structures such as stacked PMOS current sources, and provides high current mirror matching accuracy, low parasitic capacitance of the tail current source, and high impedance of the tail current source. It can avoid the problem of large variation in the tail current source current caused by insufficient voltage space under all process corners, and solve the above problems.

[0010] The technical solution adopted by the present invention is as follows:

[0011] A tail current bias circuit for a SiGe process signal amplifier, the port of the bias current source for outputting the bias current is connected to the collector of transistor Q1. The emitter of transistor Q1 is grounded through resistor R1. The base of transistor Q1 is connected to the base of transistor Q2. The emitter of transistor Q2 is grounded through resistor R2 and shares the ground with the ground terminal of resistor R1. The base of transistor Q1 is also grounded through capacitor C1 and shares the ground with resistor R2 and the ground terminal of resistor R1. The collector of transistor Q2 is respectively connected to the emitters of two transistors Q3 and Q4. The collector of transistor Q3 is connected to the power supply through resistor R3. The collector of transistor Q4 is connected to the power supply through resistor R4. The bases of transistors Q3 and Q4 are respectively connected to a differential signal input;

[0012] The collector of the triode Q1 is connected to the base of the triode Q1 through a DNW CMOS module. The circuit structure of the DNW CMOS module is as follows:

[0013] The collector of the triode Q1 is connected to the gate of the NMOS transistor NM1. The drain of the NMOS transistor NM1 is connected to the power supply. The source and body terminal of the NMOS transistor NM1 are connected. The source of the NMOS transistor NM1 is connected to the power supply after passing through the diode D1. The source of the NMOS transistor NM1 is also grounded after passing through a reverse diode D2. The source of the NMOS transistor NM1 is also connected to the base of the triode Q1.

[0014] To better implement this solution, further, a Level Shifter module is also provided between the collector of the triode Q1 and the DNW CMOS module. The circuit structure of the Level Shifter module is as follows:

[0015] The drains of the PMOS transistor PM1 and the PMOS transistor PM2 are connected to the power supply. The gates of the PMOS transistor PM1 and the PMOS transistor PM2 are connected. The source and gate of the PMOS transistor PM1 are connected. The source of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2. The drain and gate of the NMOS transistor NM2 are connected;

[0016] The source of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM5. The gates of the NMOS transistor NM3, the NMOS transistor NM4, and the NMOS transistor NM5 are connected. The drain and gate of the NMOS transistor NM3 are connected and connected to a current source that supplies power downward at one end. The sources of the NMOS transistor NM3, the NMOS transistor NM4, and the NMOS transistor NM5 are grounded together;

[0017] Taking the source of the PMOS transistor PM2 as the input terminal and connecting it to the DNW CMOS module, and taking the source of the NMOS transistor NM2 as the output terminal and connecting it to the collector of the triode Q1.

[0018] To better implement this solution, further, the connection line between the Level Shifter module and the DNW CMOS module is also connected to the base of the triode Q1, and a resistor R5 is also connected in series on the branch of the capacitor C1.

[0019] To better implement this solution, further, the circuit structure of the bias current source is as follows:

[0020] The drains of PMOS transistor PM3, PMOS transistor PM4, and PMOS transistor PM5 are connected to the power supply. The gates of PMOS transistor PM3 and PMOS transistor PM4 are connected. The gates of PMOS transistor PM5, PMOS transistor PM6, and PMOS transistor PM7 are connected together. The source of PMOS transistor PM3 is connected to the drain of PMOS transistor PM6. The gate of PMOS transistor PM3 is connected to the source of PMOS transistor PM6. The source of PMOS transistor PM7 serves as the port for outputting the bias current. The sources of PMOS transistor PM5 and PMOS transistor PM6 are connected to a current source that pulls down to ground.

[0021] To better implement this solution, further, all the grounds are connected to the hot ground that returns to the power supply, i.e., the negative pole of the power supply.

[0022] Some bias current sources (i.e., cascoded current source) such as the structure of the above-mentioned bias current source consume a relatively large voltage margin. Therefore, in a low-voltage and high-speed circuit, it may cause the following tail current bias circuit not to work properly, thus affecting the reliability and signal quality of the high-speed amplifier. So, changes are made to the tail current bias circuit to enable the circuit to work properly under all circumstances.

[0023] Due to the low threshold voltage Vth of the low-voltage NMOS transistor, the feedback voltage can be greatly reduced through reasonable circuit design for the Vgs voltage of the feedback. To reduce the threshold voltage, the width-to-length ratio of the device channel of the feedback NMOS transistor needs to be increased. At the same time, the base and the source are connected together to reduce the increase in the threshold voltage Vth caused by the body effect. Here, we use a deep well DNW connection for NMOS transistor NM1. Usually, there is no LVT and Native CMOS in the SiGe process. Therefore, this connection method is required to reduce Vth. As a result, the feedback voltage can be reduced to about 0.5V - 0.6V, generally saving about 0.2V of voltage space compared with using NPN transistors.

[0024] And we also add a Level Shifter module to the bias circuit to reduce the feedback voltage of the bias circuit. Its basic principle is to connect a voltage source with a suitable voltage between two current sources with equal currents. For the Level Shifter, theoretically, a low-impedance voltage source is required to achieve voltage conversion without affecting the stability of the feedback loop. If the upper and lower current sources are mismatched, the excess current will flow into or out of the NPN transistor of the bias circuit, resulting in an increase or decrease in the tail current. Therefore, the currents of the upper and lower current sources are smaller than the bias current. For example, they are much smaller than 1 / 10 of the bias current, which can reduce the deviation of the current mirror caused by the current mismatch of the upper and lower current sources of the Level Shifter module.

[0025] In this solution, a voltage conversion is achieved by using a diode-connected NMOS transistor. The upper end of the diode is connected to the gate of the feedback NMOS transistor, and the lower end of the diode is connected to the collector of the NPN transistor in the bias circuit to form a feedback. Therefore, the feedback voltage of the new BetaHelper is theoretically Vgs - Vgs = 0V, which leaves enough voltage space for the current source in the bias circuit. However, due to the non-ideality of the Level Shifter module, additional poles will be introduced into the loop. Therefore, it is necessary to ensure the stability of the loop and make appropriate compensation during the design. Here, a series of resistor and capacitor is used to compensate for a left zero. Compensating at a higher impedance can reduce the capacitance size and avoid more area consumption.

[0026] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows:

[0027] 1. For the tail current bias circuit of the SiGe process signal amplifier described in the present invention, the deep well DNW is used to connect the NMOS transistor NM1 and the Level Shifter module is connected, so that the high-speed amplifier can work normally and have good performance at low voltages under all process corners;

[0028] 2. For the tail current bias circuit of the SiGe process signal amplifier described in the present invention, the deep well DNW is used to connect the NMOS transistor NM1 and the Level Shifter module is connected. The bias circuit has a low structural complexity, is convenient to construct and use, and has a high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution, the drawings required for the embodiments will be briefly introduced below. It should be understood that for those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts, where:

[0030] Figure 1 is the circuit diagram of the first traditional design in the background technology of the present invention;

[0031] Figure 2 is the circuit diagram of the second traditional design in the background technology of the present invention;

[0032] Figure 3 is the circuit diagram of the third traditional design in the background technology of the present invention;

[0033] Figure 4 is the circuit diagram of the technical solution of Embodiment 1 of the present invention;

[0034] Figure 5 is the circuit diagram of the Level Shifter module of the present invention;

[0035] Figure 6 It is the circuit diagram of the technical solution of Embodiment 3 of the present invention;

[0036] Figure 7 It is the eye diagram under the second traditional design CMOS type tail current source of the present invention;

[0037] Figure 8 It is the eye diagram under the third traditional design NPN type tail current source of the present invention;

[0038] Figure 9 is Figure 8 and Figure 7 overlapped eye diagram;

[0039] Figure 10 It is the superimposed large-signal eye diagram of the third traditional design under multiple process corners in the background art of the present invention;

[0040] Figure 11 It is the superimposed large-signal eye diagram of the technical solution of Embodiment 1 of the present invention under multiple process corners;

[0041] Figure 12 It is the superimposed large-signal eye diagram of the technical solution of Embodiment 3 of the present invention under multiple process corners. Detailed implementation manners

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will, in conjunction with the accompanying drawings in the embodiments of the present invention, clearly and completely describe the technical solutions in the embodiments of the present invention. It should be understood that the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, and thus should not be regarded as a limitation on the protection scope. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0043] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "arranged", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can also be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0044] The following will, in conjunction with Figures 1 to 12 make a detailed description of the present invention.

[0045] As we know, under large-signal conditions, even if the -3dB small-signal bandwidth of two compared CML amplifiers remains basically unchanged in terms of small signals, the size of the virtual ground capacitance of the CML amplifier will affect the rise and fall times of the large signal by influencing the charging and discharging time (slew rate) of the output signal, thereby affecting the speed of the output large signal and reducing the margin between the output signal eye diagram and the eye mask. When we use the structure of the second traditional design as shown in Figure 2 and the eye diagram under the second traditional design CMOS-type tail current source of the present invention is as shown in Figure 7 When using the circuit diagram of the third traditional design as shown in Figure 3 the eye diagram under the third traditional design NPN-type tail current source of the present invention is as shown in Figure 8 and Figure 9 is Figure 8 and Figure 7 's overlapping eye diagram. From the rise and fall times of the eye diagram when the typical power supply voltage is 1.8V, the typical temperature is 50°C, and the typical process is TT, it can be determined that using an NPN-type tail current source under large signals has a certain speed advantage.

[0046] By further simulating the changes in the key indicators of the eye diagram of several NPN-type tail current source bias circuit structures (the third traditional Beta Helper structure, the Beta Helper structure with DNW CMOS, and the Beta Helper structure with both DNW CMOS and Level Shifter) at multiple process corners, it can be evaluated that the new high-speed amplifier tail current bias circuit (especially the structure with both DNW CMOS and Level Shifter) has a significant advantage in the low power supply voltage mode. The superimposed eye diagram of the third traditional structure at all process corners is as shown in Figure 10 It can be seen that at some low power supply corners (below 1.8V), the amplitude of the eye diagram output by the CML amplifier is greatly reduced, and some eye diagrams are completely closed and unable to drive the next stage. Therefore, it shows that this structure cannot guarantee performance in a low power supply voltage circuit at all.

[0047] The process corner simulation settings are as follows:

[0048] Signal rate: PRBS31, 10Gbps

[0049] Power supply range: 1.6V ~ 1.9V

[0050] Temperature range: -40°C ~ 120°C

[0051] Process corners: FF, TT, SS (NPN, NMOS, PMOS, RESISTOR)

[0052] The current is the Bandgap Current

[0053] Embodiment 1

[0054] A tail current bias circuit for a SiGe process signal amplifier, as Figure 4 , the port of the bias current source for outputting the bias current is connected to the collector of transistor Q1, the emitter of the transistor Q1 is grounded after passing through resistor R1, the base of the transistor Q1 is connected to the base of transistor Q2, the emitter of transistor Q2 is grounded together with the grounding end of resistor R2 after passing through resistor R2, and the base of the transistor Q1 is also grounded together with the grounding ends of resistor R2 and resistor R1 after passing through capacitor C1; the collector of transistor Q2 is respectively connected to the emitters of two transistors Q3 and Q4, the collector of the transistor Q3 is connected to the power supply after passing through resistor R3, the collector of the transistor Q4 is connected to the power supply after passing through resistor R4, and the bases of transistors Q3 and Q4 are respectively connected to a differential signal input;

[0055] The collector of the transistor Q1 is connected to the base of the transistor Q1 through a DNW CMOS module, and the circuit structure of the DNW CMOS module is:

[0056] The collector of transistor Q1 is connected to the gate of NMOS transistor NM1, the drain of the NMOS transistor NM1 is connected to the power supply, the source and the substrate terminal of the NMOS transistor NM1 are connected, the source of the NMOS transistor NM1 is connected to the power supply after passing through diode D1, the source of the NMOS transistor NM1 is also grounded after passing through a reverse diode D2, and the source of the NMOS transistor NM1 is also connected to the base of the transistor Q1.

[0057] Working principle: Since the threshold voltage Vth of the low-voltage NMOS transistor is low, the feedback voltage can be greatly reduced through reasonable circuit design for the feedback Vgs voltage. In order to reduce the threshold voltage, the aspect ratio of the device channel needs to be increased for the feedback NMOS transistor, and at the same time, the base and the source are connected to reduce the increase in the threshold voltage Vth caused by the body effect. Here, we use a deep well DNW connection for the NMOS transistor NM1. Usually, there is no LVT and Native CMOS in the SiGe process, so this connection method is required to reduce Vth. Therefore, the feedback voltage can be reduced to about 0.5V - 0.6V, and generally, it can save about 0.2V of voltage space compared with using NPN transistors.

[0058] In this solution, that is, the bias circuit structure with a DNW CMOS module, the eye diagram superposition at all process corners is as Figure 11This structure has a large eye height variation at low supply voltages (below 1.8V), and the variation rate of the amplitude reaches plus or minus 24% under all process corners. Therefore, this type of bias still has some impact on the performance when used at low voltages, but the impact is much less than that of the existing traditional structures.

[0059] Embodiment 2

[0060] Based on Embodiment 1, a Level Shifter module is further provided between the collector of the triode Q1 and the DNW CMOS module, as Figure 5 The circuit structure of the Level Shifter module is as follows:

[0061] The drains of the PMOS transistor PM1 and the PMOS transistor PM2 are connected to the power supply. The gates of the PMOS transistor PM1 and the PMOS transistor PM2 are connected. The source of the PMOS transistor PM1 is connected to its gate. The source of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2. The drain and the gate of the NMOS transistor NM2 are connected.

[0062] The source of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM5. The gates of the NMOS transistor NM3, the NMOS transistor NM4, and the NMOS transistor NM5 are connected. The drain and the gate of the NMOS transistor NM3 are connected and then connected to a current source that is connected to the power supply and supplies power downward. The sources of the NMOS transistor NM3, the NMOS transistor NM4, and the NMOS transistor NM5 are grounded together.

[0063] The source of the PMOS transistor PM2 is used as the input end and connected to the DNW CMOS module. The source of the NMOS transistor NM2 is used as the output end and connected to the collector of the triode Q1.

[0064] Furthermore, the circuit structure of the bias current source is as follows:

[0065] The drains of the PMOS transistor PM3, the PMOS transistor PM4, and the PMOS transistor PM5 are connected to the power supply. The gates of the PMOS transistor PM3 and the PMOS transistor PM4 are connected. The gates of the PMOS transistor PM5, the PMOS transistor PM6, and the PMOS transistor PM7 are connected together. The source of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM6. The gate of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM6. The source of the PMOS transistor PM7 is used as the port for outputting the bias current. The sources of the PMOS transistor PM5 and the PMOS transistor PM6 are connected to a current source that pulls down and grounds.

[0066] Working principle: Some bias current sources (i.e., cascoded current sources), such as the structure of the bias current source described in this embodiment, consume a relatively large voltage margin, so in a low-voltage high-speed circuit, it may cause the following tail current bias circuit to malfunction, thereby affecting the reliability and signal quality of the high-speed amplifier. Therefore, modifications have been made to the tail current bias circuit to enable the circuit to work properly under all circumstances.

[0067] And we also added a Level Shifter module to the bias circuit to reduce the feedback voltage of the bias circuit. The basic principle is to connect a voltage source with an appropriate voltage between two current sources with equal currents. For the Level Shifter, theoretically, a low-impedance voltage source is required to achieve voltage conversion without affecting the stability of the feedback loop. If the upper and lower current sources are mismatched, the excess current will flow into or out of the NPN transistor of the bias circuit, resulting in an increase or decrease in the tail current. Therefore, the currents of the upper and lower current sources are smaller than the bias current. For example, they are much less than 1 / 10 of the bias current, which can reduce the deviation of the current mirror caused by the current mismatch of the upper and lower current sources of the Level Shifter module.

[0068] Other parts of this embodiment are the same as those of the above-mentioned Embodiment 1, so they will not be elaborated here.

[0069] Embodiment 3

[0070] Based on Embodiment 1 or 2, in this embodiment, as Figure 6 , the connection line between the Level Shifter module and the DNW CMOS module is also connected to the base of the triode Q1, and a resistor R5 is also connected in series on the branch of the capacitor C1.

[0071] Furthermore, all the groundings are connected to the hot ground of the power supply, that is, the negative pole of the power supply.

[0072] Working principle: This embodiment uses a diode-connected NMOS transistor to achieve voltage conversion. The upper end of the diode is connected to the gate of the feedback NMOS transistor, and the lower end of the diode is connected to the collector of the NPN transistor of the bias circuit to form feedback. Therefore, the theoretically feedback voltage of the new Beta Helper is Vgs - Vgs = 0V, which leaves enough voltage space for the current source of the bias circuit. However, due to the non-ideality of the Level Shifter module, additional poles will be introduced into the loop. Therefore, when designing, it is necessary to ensure the stability of the loop and make appropriate compensation. Here, a series connection of a resistor and a capacitor is used to compensate for a left zero point. Making compensation at a place with a higher impedance can reduce the capacitance size and avoid more area consumption.

[0073] The eye diagram superposition diagram of the bias circuit structure with both DNW CMOS and Level Shifter at all process corners is as follows Figure 12 . This structure has a small change in eye height, and the change rate of the amplitude at all process corners is only plus or minus 7%. Using this structure, there is no need to worry about the driving ability of the amplifier in the high-speed channel at all process corners, and it can ensure good consistency of the output signal.

[0074] Other parts of this embodiment are the same as those of the above Embodiment 1 or 2, so they will not be described in detail.

[0075] It can be seen that for the above embodiments, the novel high-speed amplifier tail current bias circuit for SiGe HBT process and low-voltage power supply is applied in TSAO402. Through simulation verification of various process corners, it can ensure that the key indicators such as the tail current of the high-speed signal amplifier and the eye diagram of the output signal have a small change range. It can meet the design requirements during the final laboratory test and mass production test, and ensure the consistency of the output signal quality and various indicators.

[0076] The above are only the preferred embodiments of the present invention, and do not limit the present invention in any form. Any simple modification or equivalent change made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A tail current biasing circuit for a SiGe process signal amplifier, Characterized in that: The port of the bias current source for outputting the bias current is connected to the collector of transistor Q1. The emitter of transistor Q1 is grounded after passing through resistor R1. The base of transistor Q1 is connected to the base of transistor Q2. The emitter of transistor Q2 is grounded together with the grounding end of resistor R2 and resistor R1 after passing through resistor R2. The base of transistor Q1 is also grounded together with the grounding ends of resistor R2 and resistor R1 after passing through capacitor C1. The collector of transistor Q2 is respectively connected to the emitters of two transistors Q3 and Q4. The collector of transistor Q3 is connected to the power supply after passing through resistor R3. The collector of transistor Q4 is connected to the power supply after passing through resistor R4. The bases of transistors Q3 and Q4 are respectively connected to a differential signal input; The collector of transistor Q1 is connected to the base of transistor Q1 through a DNW CMOS module. The circuit structure of the DNW CMOS module is: The collector of transistor Q1 is connected to the gate of NMOS transistor NM1. The drain of NMOS transistor NM1 is connected to the power supply. The source and substrate terminal of NMOS transistor NM1 are connected. The source of NMOS transistor NM1 is connected to the power supply after passing through diode D1. The source of NMOS transistor NM1 is also grounded after passing through a reverse diode D2. The source of NMOS transistor NM1 is also connected to the base of transistor Q1; A Level Shifter module is also provided between the collector of transistor Q1 and the DNW CMOS module. The circuit structure of the Level Shifter module is: The drains of PMOS transistor PM1 and PMOS transistor PM2 are connected to the power supply. The gates of PMOS transistor PM1 and PMOS transistor PM2 are connected. The source and gate of PMOS transistor PM1 are connected. The source of PMOS transistor PM2 is connected to the drain of NMOS transistor NM2. The drain and gate of NMOS transistor NM2 are connected; The source of PMOS transistor PM1 is connected to the drain of NMOS transistor NM4. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM5. The gates of NMOS transistor NM3, NMOS transistor NM4 and NMOS transistor NM5 are connected. The drain and gate of NMOS transistor NM3 are connected and connected to a current source that supplies power downward with one end connected to the power supply. The sources of NMOS transistor NM3, NMOS transistor NM4 and NMOS transistor NM5 are grounded together; Taking the source of PMOS transistor PM2 as the input end and connecting it to the DNW CMOS module, and taking the source of NMOS transistor NM2 as the output end and connecting it to the collector of transistor Q1; The circuit structure of the bias current source is: The drains of PMOS transistor PM3, PMOS transistor PM4, and PMOS transistor PM5 are connected to the power supply. The gates of PMOS transistor PM3 and PMOS transistor PM4 are connected. The gates of PMOS transistor PM5, PMOS transistor PM6, and PMOS transistor PM7 are connected together. The source of PMOS transistor PM3 is connected to the drain of PMOS transistor PM6. The gate of PMOS transistor PM3 is connected to the source of PMOS transistor PM6. The source of PMOS transistor PM7 serves as the port for outputting the bias current. The sources of PMOS transistor PM5 and PMOS transistor PM6 are connected to a current source that pulls down to ground.

2. A SiGe process signal amplifier tail current bias circuit according to claim 1, characterized in that: The connection line between the Level Shifter module and the DNW CMOS module is also connected to the base of transistor Q1, and a resistor R5 is also connected in series on the branch of capacitor C1.

3. A SiGe process signal amplifier tail current bias circuit according to any one of claims 1-2, characterized in that: All grounds are connected to the hot ground that returns to the power supply, that is, the negative pole of the power supply.

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