Hardware-based state collector acceleration engine for memory subsystem operations

Abstract

The present application is directed to a hardware-based state collector acceleration engine for memory subsystem operations. The acceleration engine may execute one or more verification procedures on one or more codewords of a management unit. The acceleration engine may collect verification data for the management unit based on executing the verification procedures. The acceleration engine may aggregate the verification data into group verification data associated with a management unit set. The acceleration engine may transmit the group verification data to a firmware of a memory subsystem or a host device.

Description

[0001] Cross-references

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 62 / 874,456, filed by ZHU et al. on July 15, 2019, entitled “HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-SYSTEM OPERATIONS,” and U.S. Non-Provisional Patent Application No. 16 / 916,934, filed by ZHU et al. on June 30, 2020, entitled “HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-SYSTEM OPERATIONS,” each of which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates generally to memory subsystems, and more specifically, to a hardware-based state collector acceleration engine for memory subsystem operations. Background Art

[0004] The memory subsystem may be a storage device, a memory module, and a mixture of a storage device and a memory module. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0005] A method is described. The method may include performing a set of one or more verification operations on one or more codewords of management units of a memory subsystem; collecting verification data for the management units based at least in part on performing the set of one or more verification operations; aggregating the verification data for the management units into group verification data associated with a set of management units based at least in part on collecting the verification data; and transmitting the group verification data to firmware of the memory subsystem.

[0006] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: perform a set of one or more verification operations on one or more codewords of a management unit of a memory subsystem; collect verification data for the management unit based on performing the set of one or more verification operations; aggregate the verification data of the management unit into group verification data associated with a set of management units based on collecting the verification data; and transmit the group verification data to firmware of the memory subsystem.

[0007] A system is described. The system may include a memory subsystem configured to: perform a set of one or more verification operations on one or more codewords of management units of the memory subsystem; collect verification data for the management units based on performing the set of one or more verification operations; aggregate the verification data of the management units into group verification data associated with a set of management units based on collecting the verification data; and transmit the group verification data to firmware of the memory subsystem.

[0008] A method is described. The method may include receiving a first command to perform an operation to identify defective memory cells of a management unit set; dividing the first command into a set of one or more second commands for management units in the management unit set based on receiving the first command, each management unit being associated with at least one second command; performing the operation on each management unit in the management unit set based on dividing the first command into the set of one or more second commands; determining one or more statistics for identifying defective memory cells of one or more management units in the management unit set based on performing the operation on each management unit; and transmitting the one or more statistics of the defective memory cells of the management unit to firmware of a memory subsystem.

[0009] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: receive a first command to perform an operation to identify defective memory cells of a management unit set; based on receiving the first command, divide the first command into a set of one or more second commands for management units in the management unit set, each management unit being associated with at least one second command; based on dividing the first command into the set of one or more second commands, perform the operation on each management unit in the management unit set; based on performing the operation on each management unit, determine one or more statistics for identifying defective memory cells of one or more management units in the management unit set; and transmit the one or more statistics of the defective memory cells of the management unit to firmware of a memory subsystem.

[0010] A system is described. The system may include a memory subsystem configured to receive a first command to perform an operation to identify defective memory cells of a management unit set; divide the first command into a set of one or more second commands for management units in the management unit set based on receiving the first command, each management unit being associated with at least one second command; perform the operation on each management unit in the management unit set based on dividing the first command into the set of one or more second commands; determine one or more statistics for identifying defective memory cells of one or more management units in the management unit set based on performing the operation on each management unit; and transmit the one or more statistics of the defective memory cells of the management unit to firmware of the memory subsystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a computing environment according to examples as disclosed herein is described.

[0012] Figure 2 An example of a memory subsystem supporting an acceleration engine for memory subsystem operations according to aspects of the present disclosure is described.

[0013] Figure 3 An example of a data structure supporting an acceleration engine for memory subsystem operations according to aspects of the present disclosure is described.

[0014] Figure 4 An example of a memory subsystem supporting an acceleration engine for memory subsystem operations according to aspects of the present disclosure is described.

[0015] Figure 5 and 6 Flowcharts illustrating one or more methods for performing operations according to examples as disclosed herein are shown.

[0016] Figure 7 An example machine of a computer system 700 supporting an acceleration engine for memory subsystem operations according to examples as disclosed herein is illustrated. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure are directed to a hardware-based state collector acceleration engine for memory subsystem operations. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0018] The host system may send access requests to the memory subsystem to store data at the memory subsystem and read data from the memory subsystem. The data to be read and written is referred to as "user data" hereinafter. The host request may include a logical address (e.g., a logical block address (LBA)) of the user data, which is a location of the host system associated with the user data. The logical address (e.g., LBA) may be part of the metadata of the user data.

[0019] Memory components may include nonvolatile and volatile memory devices. A nonvolatile memory device is a package of one or more dies. The dies in a package may be assigned one or more channels for communication with a memory subsystem controller. A nonvolatile memory device includes cells (i.e., electronic circuits that store information) that are grouped into pages to store data bits.

[0020] The non-volatile memory device may include a three-dimensional cross-point ("3D cross-point") memory device as a cross-point array of non-volatile memory, which may be combined with a stackable crossbar grid data access array to perform bit storage based on changes in bulk resistance.

[0021] Such non-volatile memory devices may group pages across dies and channels to form management units (MUs). MUs may include user data and corresponding metadata. A memory subsystem controller may send and receive user data and corresponding metadata to and from a memory device as a management unit. A super management unit (SMU) may be a group of one or more MUs that are managed together. For example, a memory subsystem controller may perform media management operations (e.g., wear leveling operations, refresh operations, etc.) on a SMU.

[0022] The memory subsystem may perform operations such as initialization operations (e.g., formatting) and media management operations (e.g., defect scanning, wear leveling, refreshing) on ​​the non-volatile memory devices. For example, the memory subsystem may perform a defect scan to determine the failure rate of memory cells of the memory device. Additionally or alternatively, the memory subsystem may perform a formatting procedure (i.e., a formatting operation) that writes a fixed data pattern to the non-volatile media to reset, erase, or preset data on the memory device. In some examples, the memory subsystem may perform a wear leveling procedure (i.e., a wear leveling operation) to distribute write operations throughout the memory device, thereby mitigating performance reduction due to wear of the memory device of the memory subsystem.

[0023] Conventionally, the memory subsystem includes firmware that manages initialization operations and media management operations, and monitors the status of the memory devices. Such conventional firmware management can take a relatively long time to execute (eg, hours, days).

[0024] Aspects of the present disclosure address the above and other deficiencies by including a hardware-designed memory subsystem of one or more acceleration engines for performing memory subsystem operations. The hardware-based acceleration engine of the memory subsystem and the described techniques can enable operations such as (and not limited to) initialization operations (e.g., formatting operations), media management operations (e.g., defect scanning, wear leveling procedures), etc. to be performed relatively faster, and also achieve other advantages such as higher reliability of memory devices, reduced processing overhead, etc.

[0025] The hardware may include digital circuitry with dedicated (ie, hard-coded) logic to perform the operations described herein.

[0026] In some embodiments, the hardware is part of a controller of a memory subsystem. The memory device may include a state collector acceleration engine. The state collector acceleration engine may enable the hardware of the subsystem controller to determine memory device statistics and send them to, for example, firmware of the memory subsystem. The state collector acceleration engine may collect, aggregate, analyze, or otherwise determine statistics about the media of the memory subsystem (e.g., as part of a defect scanning program). In some instances, the statistics may be associated with a MU, SMU, page, die, or stack of the memory subsystem (e.g., a memory device of the memory subsystem). Assigning such processes or operations to the hardware of the memory subsystem controller may achieve reduced communication bandwidth (e.g., compared to transmitting each MU level data), less processing overhead at the central processing unit (CPU) (e.g., processing device) of the memory subsystem, lower power requirements of the CPU, faster memory device operations (e.g., defect scanning, formatting operations, wear leveling operations), and other advantages.

[0027] First, in reference Figure 1 Features of the present disclosure are described in the context of the described computing environment. Figure 2-4 Features of the present disclosure are described in the context of a memory subsystem and a memory format described herein. Figure 5-7 These and other features of the present disclosure are further illustrated and described with reference to a computer diagram and flow chart of an acceleration engine for memory subsystem operations.

[0028] Figure 1 An example of a computing environment 100 is illustrated according to examples as disclosed herein. The computing environment can include a host system 105 and a memory subsystem 110. The memory subsystem 110 can include media such as one or more non-volatile memory devices (e.g., memory device 130), one or more volatile memory devices (e.g., storage device 140), or a combination thereof.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing environment 100 can include a host system 105 coupled to a memory system. The memory system can be one or more memory subsystems 110. In some examples, the host system 105 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 105 coupled to a memory subsystem 110 is illustrated. The host system 105 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0031] The host system 105 may be a computing device such as a desktop computer, a portable computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an embedded system, an Internet of Things (IoT) device, or such computing devices including a memory and a processing device. The host system 105 may be coupled to the memory subsystem 110 using a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), and the like. The physical host interface may be used to transmit data between the host system 105 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 105 via a PCIe interface, the host system 105 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 105.

[0032] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Examples of non-volatile memory devices (e.g., memory device 130) include three-dimensional (3D) cross-point ("3D cross-point") type flash memory, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells.

[0034] Although a non-volatile memory component such as a 3D cross-point type memory is described, the memory device 130 can be based on any other type of non-volatile memory, such as "NAND" (NAND), read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), "NOR" (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or a combination thereof. In some examples, a particular memory component may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. Each of the memory cells may store one or more data bits for use by the host system 105.

[0036] In addition, the memory cells of the memory device 130 may be grouped into memory pages or sets of memory cells, which may refer to cells used to store data. Pages may be grouped across dies and channels to form management units (MUs). MUs may include user data and corresponding metadata. A super management unit (SMU) is a group of one or more MUs that are managed together. For example, the memory subsystem controller may perform media management operations (e.g., wear leveling operations, refresh operations, etc.) on the SMUs. The memory subsystem controller may also perform media management operations (e.g., wear leveling operations, refresh operations, etc.) on the MUs.

[0037] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0038] The memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the illustrated example, the local memory 125 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines to control the operation of the memory subsystem 110, including controlling communications between the memory subsystem 110 and the host system 105.

[0039] In some examples, local memory 125 may include memory registers that store memory pointers, fetched data, etc. Local memory 125 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another example of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0040] In general, the memory subsystem controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses (e.g., logical block addresses (LBA)) and physical addresses. The memory subsystem controller 115 may additionally include a host interface circuit system to communicate with the host system 105 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 105.

[0041] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some examples, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0042] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory units of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the media device externally (e.g., perform media management operations on the media device 130). In some embodiments, the memory device 130 may be a locally managed memory device, which is a raw memory device combined with a local media controller 135 that performs memory management operations on the memory device 130 within the same memory device package.

[0043] The memory subsystem 110 includes an acceleration engine 150 that converts commands for the SMU into commands for the MU to perform operations related to the memory subsystem operation as described herein. "Conversion" includes generating one or more MU level commands for corresponding SMU level commands. The acceleration engine 150 can enable operations (e.g., formatting operations, scans such as defect scans, wear leveling operations, etc.) to be performed relatively faster, and also achieve other advantages such as higher reliability of memory devices, reduced processing overhead (e.g., of the processor 120 or the host system 105), and reduced processing power usage. In some embodiments, the memory subsystem controller 115 may include multiple acceleration engines 150. In some instances, the memory subsystem controller 115 includes at least a portion of the acceleration engine 150. In some embodiments, the acceleration engine 150 is part of the hardware of the host system 105.

[0044] The acceleration engine 150 may be hardware of the memory subsystem controller 115, the local media controller 135, or a combination thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic for performing the operations described herein. The acceleration engine 150 may be configured to receive SMU-level commands. The SMU-level commands may be received from, for example, firmware of the memory subsystem 110, another component of the memory subsystem controller 115, or the host system 105. The acceleration engine 150 (e.g., a command queue acceleration engine) may generate one or more MU-level commands based on the SMU-level commands. Additionally or alternatively, the acceleration engine 150 may generate or otherwise determine statistics for one or more MUs, SMUs, dies, pages, channels, or a combination thereof for the memory device 130. Additional details about the operation of the acceleration engine 150 are described below.

[0045] Figure 2 An example of a memory subsystem 200 supporting an acceleration engine for memory subsystem operations according to aspects of the present disclosure is described. In some examples, the memory subsystem 200 may implement aspects of the computing environment 100. The memory subsystem 200 may include one or more memory devices 205. Some non-volatile memory devices may group pages across dies and channels to form management units (MUs). The MUs may include user data and corresponding metadata. The memory subsystem controller may send and receive user data and corresponding metadata to and from the memory devices 205 as management units. In some embodiments, the MU 215 may be a group of dies, channels, pages, codewords, parity bits, memory cells, or a combination thereof. The MU 215 may enable the memory subsystem controller to manage (e.g., execute operations, programs, etc.) on portions of the memory devices 205 in an allocated group or segment of the media.

[0046] A super management unit (SMU) is a group of one or more MUs. For example, SMU 210-a may include MU 215-a and MU 215-b. The MUs in the SMU are managed together. For example, the memory subsystem controller may perform initialization and media management operations (e.g., wear leveling operations, refresh operations, etc.) on the SMU.

[0047] In some examples, various memory subsystem operations may be performed on the memory device 205. In some examples, the memory subsystem operations may include defect scans to identify defective portions of the memory device 205, formatting procedures for resetting or writing data patterns (e.g., configured patterns of all 0s, all 1s, 0s and 1s, and other patterns) to the memory device 205, wear leveling procedures to move data between SMUs 210, MUs 215, or both (e.g., to distribute data based on the performance of various portions of the memory device 205 to mitigate the effects of poor performance in certain portions, such as "bad" dies, MUs, SMUs, stacks, pages, channels, or combinations thereof), and other such operations.

[0048] For example, a hardware-based accelerator (e.g., acceleration engine 150) may perform a defect scan on memory device 205. As part of a verification operation to determine the functionality or performance of each MU 215 (e.g., gathering verification information or statistics, failed bit counts (FBCs) of codewords of MU 215-a and MU 215-b), the acceleration engine 150 may write and / or read to memory device 205. Additionally or alternatively, the acceleration engine may process the statistics or data to mark or otherwise determine the performance of each MU 215. For example, the acceleration engine may mark the codewords of MU 215-a as "bad" codewords if the statistics (e.g., average FBC or maximum FBC) meet a threshold. In some cases, MU 215-a may be marked as a "bad" MU if the number of codewords marked as "bad" for MU 215-a meets a threshold. Additionally or alternatively, a die, channel, SMU, etc. may be marked as "bad" based on the determined statistics meeting the threshold.

[0049] An acceleration engine (e.g., a command queue acceleration engine) may receive commands for SMU 210, for example, from firmware (not shown) of memory subsystem 200. For example, a memory subsystem controller may receive a write command associated with a formatting operation for SMU 210-a. The acceleration engine may generate commands for one or more MUs 215 based on the commands for the SMUs. For example, the acceleration engine may generate write commands for MU 215-a and MU 215-b based on the received write command for SMU 210-a. In addition, the acceleration engine may generate or otherwise determine statistics for one or more MUs 215, SMU 210, die, page, channel, or a combination thereof of memory device 205 (e.g., as part of a defect scan operation).

[0050] Figure 3An example of a management unit data structure 300 supporting an acceleration engine for memory subsystem operations according to aspects of the present disclosure is illustrated. In some examples, the data structure 300 can implement aspects of the computing environment 100 or the memory subsystem 200. Figure 3 Describes the MU used to verify the operation (e.g., reference Figure 2 An example data structure of MU 215) described above.

[0051] Some non-volatile memory devices may group pages across dies and channels to form management units (MUs). MUs may include user data and corresponding metadata. Data structure 300 may illustrate an example layout of MUs across multiple dies 305 and channels 310. For example, MUs may include pages of memory devices across die 305-a and channels 310-a, 310-b, 310-c, and 310-d. The pages may include information about verification operations such as error detection procedures, which may also be referred to as error correction code (ECC) processes, ECC operations, ECC techniques, or in some cases, simply ECC. In some examples, ECC (e.g., block codes, convolutional codes, Hamming codes, low-density parity-check codes, vortex codes, polar codes) may be used in error detection procedures. For example, the ECC codeword payload 315 - a and the ECC parity bits 320 - a may be located at the die 305 - a and the lane 310 - a and may be used to determine the performance of the MU (eg, average FBC, maximum FBC, etc.).

[0052] In some examples, such codewords and ECCs may be used in error detection or correction procedures to determine and / or output error detection information for a memory device. For example, a read operation may utilize the ECC codeword payload 315-a and the ECC parity bits 320-a to determine whether one or more bits or memory cells of a codeword associated with the ECC codeword payload 315-a are performing as expected (e.g., whether the state of the memory cell contains the expected state). In some cases, error detection information for a codeword may be aggregated or otherwise merged into information for a die, channel, page, MU, SMU, or stack of a memory device as discussed herein (e.g., the results of one or more verification operations).

[0053] In some cases, the memory subsystem controller or memory device may be configured to register a MU (e.g., a Figure 3 MUs of the format described in ) perform various memory subsystem operations (e.g., ECC operations). In some cases, the hardware of the memory subsystem controller may generate or execute write commands, move commands, read commands, etc. to one or more MUs (e.g., as part of defect scans, format operations, wear leveling operations, or combinations thereof).

[0054] A memory subsystem controller (e.g., a memory subsystem controller such as memory subsystem controller 115, local media controller 135, or a combination thereof) or a memory device (e.g., memory device 205) may include one or more acceleration engines (e.g., hardware of a memory device or memory subsystem controller) configured to perform such operations or commands. For example, the memory subsystem controller may include an acceleration engine (e.g., a command queue acceleration engine) configured to receive commands for the SMU from firmware of the memory device. The memory subsystem controller may receive a read command associated with an ECC operation for the SMU. The acceleration engine may generate commands for one or more MUs based on the command for the SMU. For example, the acceleration engine may generate commands for Figure 3 305, pages, channels 310, or a combination thereof. In addition or alternatively, the memory subsystem controller or memory device may include an acceleration engine configured to generate or otherwise determine statistics for one or more MUs, SMUs, dies 305, pages, channels 310, or a combination thereof of the memory device. For example, the acceleration engine may generate or receive statistics based on data determined by ECC operations for each MU of the SMUs, and aggregate the statistics into group statistics for the SMUs.

[0055] Figure 4 An example of a memory subsystem 400 supporting an acceleration engine for memory subsystem operations according to aspects of the present disclosure is illustrated. In some examples, the memory subsystem 400 may implement aspects of the computing environment 100, the memory subsystem 200, the data structure 300, or a combination thereof. Figure 4 An example memory subsystem is illustrated having an acceleration engine 410 that can enable the memory subsystem to perform memory subsystem operations relatively faster, more efficiently, and with less processing overhead by offloading various processes to memory devices or subsystem hardware (eg, acceleration engine 410).

[0056] The memory subsystem 400 may be referenced Figure 1 1. The memory subsystem 400 may include a memory controller 405. The memory controller 405 may be a reference Figure 1 1 and 135. The memory controller 405 may include one or more acceleration engines 410 (e.g., see Figure 1The memory controller 405 may also include a buffer 415, which may be an example of a memory storage device that is locally accessible to the memory controller 405. In some cases, the buffer 415 may be a reference Figure 1 An example of the depicted local memory 125. The memory controller 405 may also include an ECC engine 425, which may be an example of a hardware engine (eg, a decoder) configured to collect ECC information (eg, verification data and / or failure data) for codewords of the MU.

[0057] Memory subsystem 400 may include media 420. Media 420 may include reference Figure 1 The memory device 130 or storage device 140 and / or reference Figure 2 Aspects of the memory device 205 described. For example, the medium 420 may include an SMU (e.g., SMU 210) and an MU (e.g., MU 215). The medium 420 may communicate with the memory controller 405 and other various components of the memory subsystem 400.

[0058] In some examples, memory subsystem operations may be performed in the memory subsystem 400. For example, the memory subsystem operations may be performed on a portion of the media 420 (e.g., a SMU of the media 420). In some examples, the memory subsystem operations may include a defect scan to identify defective portions of the media 420. Additionally or alternatively, the memory subsystem operations may include format operations to reset or write data patterns (e.g., all 0s, all 1s, configured patterns of 0s and 1s, and other patterns) of the portion of the media 420. Additionally or alternatively, the memory subsystem operations may include wear leveling operations that move data between portions of the media 420, such as distributing data based on the performance of the SMUs or MUs of the media 420 in order to mitigate the effects of SMUs or MUs with relatively poor FBC statistics (e.g., "bad" dies, MUs, SMUs, stacks, pages, channels, or combinations thereof).

[0059] The memory subsystem 400 may include an acceleration engine 410. The acceleration engine 410 may be hardware of the memory subsystem (eg, hardware of a memory device or memory controller 405). In some examples, the acceleration engine 410 may be a reference Figure 14. The acceleration engine 410 may be configured to perform aspects of memory subsystem operations, which may enable relatively faster execution, less processing overhead (e.g., by executing a process instead of firmware processed at the processing unit 430), and other advantages. In some examples, the acceleration engines may be implemented individually in the memory subsystem 400. In some examples, the acceleration engines may be implemented together in the memory subsystem 400. In some other examples, the functions of the acceleration engines 410 may be implemented by a single acceleration engine 410. In any case, the various functions of each acceleration engine 410 as described herein may be implemented in a different order or by different components of the memory subsystem 400.

[0060] The acceleration engine 410-a may be an example of a command queue acceleration engine. The acceleration engine 410-a may, for example, receive, read, write, or move SMU commands associated with memory subsystem operations from the firmware of the memory subsystem (e.g., the firmware of the processing unit 430). For example, the acceleration engine 410-a may receive a command for the SMU of the media 420. The acceleration engine 410-a may generate one or more corresponding commands for one or more MUs of the SMU. For example, the acceleration engine 410-a may generate and / or issue commands for one or more codewords or memory units of the MU based on the command for the SMU. In some cases, the acceleration engine 410-a may generate such commands for some or all of the MUs of the SMU.

[0061] As part of the formatting operation, the firmware of the memory subsystem may send a write command for the SMU of the media 420. The command may include an instruction to format the data of the SMU into a fixed pattern. For example, the data may be formatted as all 0s, all 1s, or a configured pattern of 0s and 1s. The acceleration engine 410-a may generate one or more write commands for the MU based on the write command for the SMU. For example, the acceleration engine 410-a may send a write command to each MU of the SMU to format the data of each MU into a fixed pattern. In some instances, the write information may specify a mode or data state to be written. For example, the acceleration engine 410-a may retrieve write information indicating that the data of the MU is written as one or more states (e.g., all 0s). In some cases, the write information may be sent from the firmware to the acceleration engine 410-a. In some other cases, the acceleration engine 410-a may receive or retrieve the write information from the memory component 435 (e.g., the write information may be stored on the memory component 435). In some cases, memory component 435 may be an example of an on-chip static RAM or DRAM (OnChip SRAM-or-DRAM) component. Additionally or alternatively, the write information may be stored on buffer 415. Storing the write information on buffer 415 may reduce the time required to format the SMU (e.g., when the data or data pattern to be written to each MU of the SMU is the same). For example, because buffer 415 may be a locally accessible memory (i.e., located in memory controller 405), storing and retrieving write information from buffer 415 may be relatively faster than retrieving write information for each MU from memory component 435.

[0062] In some examples, the firmware may send a read command for the SMU of the media 420. In such examples, the acceleration engine 410-a may generate one or more read commands for the MUs based on the read command for the SMUs. For example, the acceleration engine 410-a may send a read command to each MU of the SMU to obtain read data for each MU of the SMU. The read data may be sent to the buffer 415 and / or the memory component 435. Additionally or alternatively, the hardware of the memory subsystem (e.g., the acceleration engine 410-b) may generate statistics (e.g., FBC statistics) based on the read data and transmit the statistics to the firmware, for example, as part of a validation operation.

[0063] The acceleration engine 410-a can process multiple SMU-level or MU-level commands simultaneously. For example, the acceleration engine 410-a can receive read, write, or move commands for multiple SMUs. The acceleration engine 410-a can simultaneously generate and / or issue a corresponding command set for each SMU-level command. The set can include one or more commands. Additionally or alternatively, the acceleration engine 410-a can simultaneously process multiple commands for the SMU in the command set. That is, the acceleration engine 410-a can simultaneously generate and / or issue multiple commands for each MU of the SMU. In some instances, the number of parallel MU-level commands can be programmable, for example to adjust the speed of the memory subsystem operation, dynamically respond to the bandwidth requirements of the hardware, and other advantages.

[0064] In some examples, the acceleration engine 410-b may be an example of a status collector acceleration engine. For example, the acceleration engine 410-b may be hardware configured to receive status information from one or more ECC engines 425. The status information may be based on read data of a read command (e.g., an access operation), read statistics, verification information or statistics (e.g., error detection information or statistics from one or more ECC programs as described herein), etc. The acceleration engine 410-b may determine statistics for a MU, SMU, die, stack, or a combination thereof based on the status information from the ECC engine 425. Performing such functions by, for example, hardware (e.g., rather than firmware) of a memory subsystem controller may achieve faster operation times.

[0065] For example, the acceleration engine 410-b may receive verification information from the ECC engine 425. That is, the ECC engine 425 may output codeword information for the codewords of the MU. For example, the ECC engine 425-a may perform one or more verification operations (e.g., ECC operations) to obtain codeword information (e.g., statistics for the codewords of the MU). In some instances, the codeword information may include one or more FBCs of the codeword (e.g., 0 to 1 FBC, 1 to 0 FBC, or both), the number of 1s of the codeword, the number of 0s of the codeword, or other such metrics. In some cases, for example, as part of a defect scan operation, the acceleration engine 410-b may receive the codeword information.

[0066] The acceleration engine 410-b may process information from the ECC engine 425. For example, the acceleration engine 410-b may merge codeword information (e.g., codeword statistics of MUs including SMUs) into group statistics. The group statistics may be statistics corresponding to MUs, SMUs, dies, stacks, or combinations thereof of a memory device. For example, the group statistics may include an average FBC of one or more MUs, a maximum FBC of one or more MUs, or other such statistics determined from the codeword information (e.g., read data or statistics associated with the codewords of each MU in the SMU). In some examples, the group statistics may include a die or stack level histogram based on the merged codeword information (e.g., a 0 to 1 FBC, a 1 to 0 FBC, a number of 1s or 0s, or a combination of such metrics for all codewords of a die or stack). The acceleration engine 410-b may discard information or data used to aggregate group statistics (e.g., codeword information of MUs and other read data), for example, to reduce communication bandwidth for sending large amounts of MU-level data to firmware. The acceleration engine 410-b may send group statistics to the firmware. In some cases, the firmware may determine and mark the performance of the MU, SMU, die, or stack based on the group statistics. In some other cases, the acceleration engine 410-b may determine and mark the performance and send an indication of the performance to the firmware.

[0067] The acceleration engine 410-b may use such information or statistics (e.g., group statistics, codeword information from the ECC engine 425, or other read data associated with one or more MUs) as parameters for one or more memory subsystem operations. For example, a media management algorithm may use the statistics as input to adjust one or more parameters of a memory subsystem, memory device, algorithm, or operation. For example, an algorithm used to determine data allocation as part of a wear leveling operation may use the statistics to determine which portions of the media 420 are relatively "worn" (e.g., marked as "bad"). The algorithm may accordingly determine to move data from one SMU or MU to another SMU or MU. For example, the firmware may issue an SMU move command to transfer data from a "bad" SMU to a relatively "good" SMU. In some instances, the acceleration engine 410-a may decompose the SMU move command into one or more MU move commands.

[0068] In some cases, the memory subsystem 400 may include both acceleration engines 410-a and 410-b. For example, a defect scan of the medium 420 may include both a write command and a read command. The firmware may issue a write command for the SMU to the acceleration engine 410-a. The acceleration engine 410-a may divide the write command for the SMU into one or more write commands for one or more MUs of the SMU. As an example, the write command may be a 0 to 1 write command, a 1 to 0 write command, or both. The firmware may also issue a read command, for example to verify that the data or data pattern written to the SMU is correctly written and / or read. The acceleration engine 410-a may divide the read command for the SMU into one or more read commands for one or more MUs of the SMU. The hardware of the memory controller (e.g., the ECC engine 425) may perform a verification operation based on the MU-level write command and the MU-level read command to output data to the acceleration engine 410-b. The acceleration engine 410-b may merge the data into group statistics and transmit the group statistics to the firmware.

[0069] Figure 5 A flowchart illustrating one or more methods 500 for performing operations on a management unit set according to aspects of the present disclosure is shown. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The hardware-based acceleration engine 150 is executed. The hardware may include processing logic to perform the operations described herein, such as a digital circuit system with dedicated (ie, hard-coded) logic.

[0070] Although shown in a particular order or sequence, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in a different order, and some operations may be performed in parallel. In addition, one or more operations may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other operation flows are possible.

[0071] At 505, processing logic may perform a set of one or more verification operations on one or more codewords of a management unit of a memory subsystem. In some examples, processing logic may generate a command to collect verification data for the management unit, wherein performing the set of one or more verification operations is based at least in part on generating the command. In some examples, the management unit includes pages associated with one or more dies and channels of the memory subsystem. In some examples, the memory subsystem may be a 3-dimensional (3D) crosspoint subsystem.

[0072] At 510, processing logic may collect verification data for managing the unit based on performing the set of one or more verification operations. In some examples, the set of one or more verification operations includes one or more FBC operations, one or more read operations, or a combination thereof. In some examples, the set of one or more verification operations may be performed by one or more ECC engines.

[0073] At 515, the processing logic may aggregate the verification data of the management units into group verification data associated with the management unit set based on the collected verification data by the hardware of the memory subsystem. The aggregation may be done by the hardware of the memory subsystem or another component of the memory subsystem controller (e.g., an acceleration engine of the memory subsystem).

[0074] In some examples, the processing logic may generate statistics based on the verification data, wherein the aggregate verification data may be based on generating the statistics. The generating may be done by hardware of the memory subsystem controller or another component of the memory subsystem. In some examples, the statistics include a histogram, a maximum FBC, an average FBC of a management unit, a number of subsets of memory cells corresponding to a codeword of a state, or a combination thereof. In some examples, the statistics correspond to a die of a memory subsystem, a stack of a memory subsystem, a management unit of a memory subsystem, a set of management units of a memory subsystem, or a combination thereof.

[0075] In some examples, processing logic may store verification data in a buffer of the memory subsystem based on collecting verification data, the verification data including results of the set of one or more verification operations, wherein aggregating the verification data may be based on storing the verification data in the buffer.

[0076] At 520, processing logic may transmit the group verification data to the firmware of the memory subsystem. In some examples, processing logic may transmit the statistical data to the firmware of the memory subsystem.

[0077] Figure 6 A flowchart illustrating one or more methods 600 for performing operations on a management unit set according to aspects of the present disclosure is shown. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1 The hardware-based acceleration engine 150 is executed. The hardware may include processing logic to perform the operations described herein, such as a digital circuit system with dedicated (ie, hard-coded) logic.

[0078] Although shown in a particular order or sequence, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in a different order, and some operations may be performed in parallel. In addition, one or more operations may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other operation flows are possible.

[0079] Processing logic may receive a first command to be performed to identify defective memory cells of a management unit set at 605. The command may be received from firmware of the memory subsystem or another component of the memory subsystem controller.

[0080] At 610, processing logic may divide the first command into a set of one or more second commands for management units in a management unit set based on receiving the first command, each management unit being associated with at least one second command. In some examples, the first command for the management unit set includes a read command and the set of one or more second commands for each management unit includes a read command set.

[0081] At 615, processing logic may perform an operation on each management unit in the set of management units based on dividing the first command into a set of one or more second commands. In some examples, performing the operation on each management unit includes performing one or more verification operations for one or more codewords of each management unit, and obtaining verification data for each management unit based on performing the one or more verification operations.

[0082] At 620, processing logic may determine one or more statistics for identifying defective memory cells of one or more management units in the management unit set based on performing the operations on each management unit. In some examples, processing logic may compile verification data for each management unit into group verification data for a management unit set, a stack of memory subsystems, a die of a memory subsystem, or a combination thereof, wherein determining the one or more statistics may be based on the group verification data.

[0083] At 625, processing logic may transmit one or more statistics of defective memory cells of the management unit to firmware of the memory subsystem.

[0084] In some examples, the one or more statistics include a histogram, a maximum FBC, an average FBC for a management unit, a number of states determined, or a combination thereof. In some examples, the memory subsystem can be a 3D crosspoint subsystem.

[0085] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, parts of two or more of the methods may be combined.

[0086] In some examples, an apparatus as described herein may perform one or more methods, such as method 500 or 600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing one or more of the operations described herein.

[0087] Figure 7 An example machine of a computer system 700 supporting an acceleration engine for memory subsystem operations according to examples as disclosed herein is illustrated. The computer system 700 may include an instruction set for causing the machine to perform any one or more of the techniques described herein. In some examples, the computer system 700 may correspond to a host system (e.g., a reference Figure 1 host system 105) that includes, is coupled to, or uses a memory subsystem (e.g., reference Figure 1 The memory subsystem 110 described above may be used to perform operations of the controller (e.g., to execute an operating system to perform operations corresponding to the reference Figure 1 In some examples, the machine may be connected (e.g., via a network) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a cloud computing infrastructure or environment.

[0088] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0089] The example computer system 700 includes a processing device 705, a main memory 710 (e.g., read-only memory (ROM), flash memory, DRAM, such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 715 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 725, which communicate with each other via a bus 745.

[0090] The processing device 705 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 705 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 705 is configured to execute instructions 735 for performing the operations and steps discussed herein. The computer system 700 may additionally include a network interface device 720 to communicate on a network 740.

[0091] The data storage system 725 may include a machine-readable storage medium 730 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 735 or software embodying any one or more of the methods or functions described herein. The instructions 735 may also reside, completely or at least partially, within the main memory 710 and / or within the processing device 705 during execution by the computer system 700, the main memory 710 and the processing device 705 also constituting machine-readable storage media. The machine-readable storage medium 730, the data storage system 725, and / or the main memory 710 may correspond to a memory subsystem.

[0092] In one example, instructions 735 include implementing instructions corresponding to acceleration engine 750 (eg, reference Figure 1 The machine-readable storage medium 730 is a storage medium that stores instructions for the functionality of the acceleration engine 150 described herein. Although the machine-readable storage medium 730 is shown as a single medium, the term "machine-readable storage medium" may include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" may also include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0093] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0094] As used herein, the term "virtual ground" refers to a circuit node that is maintained at a voltage of approximately zero volts (0V) without being directly coupled to ground. Thus, the voltage of the virtual ground may fluctuate over time and return to approximately 0V in a steady state. Virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" refers to a connection to approximately 0V.

[0095] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (conductive contact or connection or coupling) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are electronically connected to each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, for example, one or more intermediate components such as switches or transistors may be used to interrupt the flow of signals between the connected components for a period of time.

[0096] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components, in which signals are able to communicate between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0097] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0098] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0099] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as a metal. The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "started up". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "unstarted".

[0100] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The specific implementation includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0101] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dashed line and a second label that distinguishes among similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0102] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0103] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items with a phrase such as "at least one of" or "one or more of"), "or" indicates a list containing endpoints, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed conditional set. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0104] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special computer or a general or special processor. And, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0105] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory subsystem, comprising: performing a verify operation on one or more codewords of a management unit of the memory subsystem, wherein the management unit includes pages associated with one or more dies and channels of the memory subsystem; collecting authentication data for the management unit based at least in part on performing the authentication operation; Aggregating the verification data for each administrative unit in a set of administrative units into group verification data associated with the set of administrative units based at least in part on collecting the verification data; and The group verification data is sent to firmware of the memory subsystem.

2. The method according to claim 1, further comprising: Statistics are generated based at least in part on the verification data, wherein aggregating the verification data is based at least in part on the generated statistics.

3. The method of claim 2, wherein the statistical data comprises a histogram, a maximum failed bit count (FBC), an average FBC of the management unit, and / or a number of a subset of memory cells corresponding to a codeword of a state. 4 . The method of claim 2 , wherein the statistical data corresponds to a die of the memory subsystem, a stack of the memory subsystem, a management unit of the memory subsystem, and / or the set of management units of the memory subsystem.

5. The method of claim 2, wherein sending the group verification data to the firmware of the memory subsystem further comprises: The statistical data is sent to the firmware of the memory subsystem.

6. The method of claim 1, further comprising: The verification data is stored in a buffer of the memory subsystem based at least in part on collecting the verification data, the verification data comprising a result of the verification operation, wherein aggregating the verification data is based at least in part on storing the verification data in the buffer. 7 . The method of claim 1 , wherein the verify operation comprises one or more Failed Bit Count (FBC) operations and / or one or more read operations.

8. The method of claim 1, further comprising: A command is generated to collect the verification data of the management unit, wherein performing the verification operation is based at least in part on generating the command.

9. The method of claim 1, wherein the management unit further comprises a codeword, a parity bit, and / or a group of memory cells.

10. The method of claim 1, wherein the memory subsystem is a 3-dimensional cross-point subsystem.

11. The method according to claim 1, wherein: Aggregating the verification data is performed by an acceleration engine unit of the memory subsystem.

12. The method of claim 1, wherein: The verification operation is performed by one or more ECC engine units.

13. A method for operating a memory subsystem, comprising: receiving a first command to be performed to identify defective memory cells of a set of management cells, wherein respective management cells in the set of management cells include pages associated with one or more dies and channels of the memory subsystem; dividing the first command into a set of one or more second commands for management units in the set of management units based at least in part on receiving the first command, each management unit being associated with at least one second command; performing the operation on each management unit in the set of management units based at least in part on dividing the first command into the set of one or more second commands; determining one or more statistics identifying the defective memory cells of one or more management units in the set of management units based at least in part on performing the operations for each management unit; and The one or more statistical data of the defective memory cells of the management unit are sent to firmware of the memory subsystem.

14. The method of claim 13, wherein performing the operation on each management unit further comprises: performing a verification operation for one or more codewords for each management unit; and Authentication data is obtained for each management unit based at least in part on performing the authentication operation.

15. The method of claim 14, further comprising: The verification data for each management unit is compiled into group verification data for the set of management units, the stack of memory subsystems, and / or the die of the memory subsystems, wherein determining the one or more statistics is based at least in part on the group verification data.

16. The method of claim 13, wherein the first command for the set of management units comprises a read command and the set of one or more second commands for each management unit comprises a set of read commands.

17. The method of claim 13, wherein the one or more statistical data comprises a histogram, a maximum failed bit count (FBC), an average FBC of the one or more management units, and / or a number of determined states.

18. The method of claim 13, wherein the memory subsystem is a 3-dimensional cross-point subsystem.

19. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to cause a memory subsystem to: performing a verify operation on one or more codewords of a management unit of the memory subsystem, wherein the management unit includes pages associated with one or more dies and channels of the memory subsystem; collecting authentication data for the management unit based at least in part on performing the authentication operation; Aggregating the verification data for each administrative unit in a set of administrative units into group verification data associated with the set of administrative units based at least in part on collecting the verification data; and The group verification data is sent to firmware of the memory subsystem.

20. The non-transitory computer-readable medium of claim 19, wherein the code is further operable to cause the processor to: Statistics are generated based at least in part on the verification data, wherein aggregating the verification data is based at least in part on the generated statistics.

21. The non-transitory computer-readable medium of claim 20, wherein the statistical data comprises a histogram, a maximum failed bit count (FBC), an average FBC of the management unit, and / or a number of a subset of memory cells corresponding to a codeword of a state.

22. The non-transitory computer-readable medium of claim 20, wherein the statistical data corresponds to a die of the memory subsystem, a stack of the memory subsystem, a management unit of the memory subsystem, and / or the set of management units of the memory subsystem.

23. The non-transitory computer-readable medium of claim 20, wherein the code is further operable to cause the processor to: The statistical data is sent to the firmware of the memory subsystem.

24. The non-transitory computer-readable medium of claim 19, wherein the code is further operable to cause the processor to: The verification data is stored in a buffer of the memory subsystem based at least in part on collecting the verification data, the verification data comprising a result of the verification operation, wherein aggregating the verification data is based at least in part on storing the verification data in the buffer.

25. A memory system comprising: A memory subsystem configured to: performing a verify operation on one or more codewords of a management unit of the memory subsystem, wherein the management unit includes pages associated with one or more dies and channels of the memory subsystem; collecting authentication data for the management unit based at least in part on performing the authentication operation; Aggregating the verification data for each administrative unit in a set of administrative units into group verification data associated with the set of administrative units based at least in part on collecting the verification data; and The group verification data is sent to firmware of the memory subsystem.

26. A memory system comprising: A memory subsystem configured to: receiving a first command to be performed to identify defective memory cells of a set of management cells, wherein respective management cells in the set of management cells include pages associated with one or more dies and channels of the memory subsystem; dividing the first command into a set of one or more second commands for management units in the set of management units based at least in part on receiving the first command, each management unit being associated with at least one second command; performing the operation on each management unit in the set of management units based at least in part on dividing the first command into the set of one or more second commands; determining one or more statistics identifying the defective memory cells of one or more management units in the set of management units based at least in part on performing the operations for each management unit; and The one or more statistical data of the defective memory cells of the management unit are sent to firmware of a memory subsystem.

Images