Edge Modulation Transmitter and Digital Isolator

Abstract

The present application provides an edge modulation transmitter and a digital isolator, which relate to the field of digital circuit technologies. The input signal of the edge modulation transmitter is a digital signal, and the rising edge and the falling edge appear alternately; the edge modulation transmitter includes a detection module; when the time interval between two adjacent edges of the input signal detected by the detection module is less than a preset duration, the edge modulator outputs a first number of pulses at the specified edge moment of the input signal; when the time interval between two adjacent edges of the input signal detected by the detection module is greater than or equal to the preset duration, the edge modulator outputs a second number of pulses at the specified edge moment of the input signal, and the second number is greater than the first number. When the transmitter detects common-mode noise in the system, it performs adaptive edge modulation based on the data rate of the input signal, ensuring the accuracy of signal output.

Description

Technical Field

[0001] This application relates to the field of digital circuit technologies, and more particularly, to an edge modulation transmitter and a digital isolator. Background Art

[0002] As digital isolators are mainly used for transmitting digital signals between circuit modules with a large voltage difference, there is a lot of noise interference in their working environment, especially common mode transient (CMT). This poses a significant threat to the transmission reliability of digital isolator signals. The existing pulse-based edge encoding and decoding technologies can achieve a relatively small anti-CMT interference range, and cannot perform targeted modulation of different modes on the input signal according to the data rate of the input signal, resulting in poor accuracy of digital signal modulation. Summary of the Invention

[0003] In view of this, the purpose of the embodiments of this application is to provide an edge modulation transmitter and a digital isolator to improve the problem in the existing technology that it is impossible to perform targeted modulation of different modes on the input signal according to the data rate of the input signal, resulting in poor accuracy of digital signal modulation.

[0004] The embodiments of this application provide an edge modulation transmitter. The input signal of the edge modulation transmitter is a digital signal, and the rising edge and the falling edge appear alternately;

[0005] The edge modulation transmitter includes a detection module;

[0006] When the detection module of the edge modulation transmitter detects that the time interval between two adjacent edges of the input signal is less than a preset duration, a first number of pulses are output at the specified edge moment of the input signal;

[0007] When the detection module of the edge modulation transmitter detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset duration, a second number of pulses are output at the specified edge moment of the input signal, and the second number is greater than the first number.

[0008] In the above implementation, the data rate of the input signal is detected through the detection module, and different adaptive edge modulations are performed on the input signal under different data rates, so as to make the edge modulations of different data rates more accurate, thereby improving the data transmission stability of the edge modulation transmitter.

[0009] Optionally, the edge modulation transmitter further includes an edge modulation module, and the detection module includes an edge trigger module and a counting module. The edge trigger module and the counting module are connected in parallel between the input end of the edge modulation module and the signal input end of the edge modulation transmitter. The output end of the edge trigger module is connected to the reset end of the counting module;

[0010] When the period of the input signal is greater than a preset duration, the edge trigger module outputs a first pulse signal, and the first pulse signal is a reset signal for the counting module. The counting module outputs based on the first pulse signal indicating that the time interval between two adjacent edges of the input signal detected by the detection module is less than the preset duration. The edge modulation module is used to drive the output of the first number of pulses at the specified edge moment of the input signal when the time interval between two adjacent edges of the input signal detected by the detection module is less than the preset duration, and to output the second number of pulses at the specified edge moment of the input signal when the time interval between two adjacent edges of the input signal detected by the detection module is greater than or equal to the preset duration.

[0011] In the above implementation, the data rate of the input signal is detected in real time by an edge trigger and a timer, and is represented by the first pulse signal, so as to clear the counting module, and the data rate of the input signal is transmitted to the edge modulation module through the counting module.

[0012] Optionally, the edge trigger module includes an edge trigger and a timer. The input end of the edge trigger is connected to the signal input end, the output end of the edge trigger is connected to the reset end of the timer, and the output end of the timer is respectively connected to the reset end of the timer, the first input end of the edge modulation module, and the reset end of the counting module;

[0013] When the edge trigger detects the specified edge of the input signal, it transmits a first reset signal to the timer to clear the timer, and outputs the first pulse signal through the output end of the timer when the timing of the timer reaches the preset duration.

[0014] In the above implementation, through the logical setting of the edge trigger and the timer, the timer outputs a pulse signal when the period of the input signal is greater than the preset duration, and does not output a pulse signal when the period of the input signal is less than or equal to the preset duration, realizing threshold detection of the period of the input signal.

[0015] Optionally, the counting module is an asynchronous counter with an overflow protection function.

[0016] In the above implementation, the overflow protection function can keep the value of the counting module at a fixed value, so as to facilitate subsequent edge modulation based on this fixed value.

[0017] Optionally, the counting module includes a first D flip - flop, a second D flip - flop, a NOT gate, and a NOR gate. The clock input terminal of the first D flip - flop is connected to the signal input terminal. The clear terminals of the first D flip - flop and the second D flip - flop are both connected to the output terminal of the timer. The D terminal, Q terminal, and terminal of the first D flip - flop are connected to the input terminal of the NOT gate. The output terminal of the NOT gate is connected to the first input terminal of the NOR gate. The output terminal of the NOR gate is connected to the clock input terminal of the second D flip - flop. The D terminal of the second D flip - flop is connected to the terminal of the second flip - flop. The second input terminal of the NOR gate and the Q terminal of the second D flip - flop are both connected to the second input terminal of the edge modulation module.

[0018] In the above implementation, a two - bit counting module is implemented by two D flip - flops, which has a low cost and a simple component structure.

[0019] Optionally, when the time interval between two adjacent edges of the input signal detected by the detection module is greater than or equal to the preset duration, the edge modulator outputs a second number of pulses at the specified edge moment of the input signal, and the spacing between the second number of pulses is a first spacing.

[0020] In the above implementation, the edge modulation module increases the pulse spacing for high - data - rate input signals, so that the pulse signals that cannot be received by the receiver when the CMT event occurs are transmitted to the receiver after the CMT event, thus ensuring data transmission stability.

[0021] An embodiment of the present application provides a digital isolator. The digital isolator includes an edge modulation transmitter, a driver, and a receiver as described above. The receiver includes a comparator circuit and a latch. The output terminal of the driver is connected to the input terminal of the comparator circuit. The output terminal of the comparator circuit is connected to the input terminal of the latch. The output terminal of the latch is the output terminal of the digital isolator;

[0022] The comparator circuit compares the output signal of the driver. When the output signal of the driver is a pulse of the first polarity, the latch is set to the first logical latch state, and the output terminal of the latch outputs the first logic. When the output signal of the driver is a pulse of the second polarity, the latch is set to the second logical latch state, and the output terminal of the latch outputs the second logic.

[0023] In the above implementation, the latch that can be triggered by a single pulse is used to switch the logic latch state, realizing the stable output of digital signals against CMT interference.

[0024] Optionally, the driver is a six-terminal transformer composed of two mutually coupled coils.

[0025] In the above implementation, the input signal is converted and output through the driver, reducing signal interference and transmission distortion.

[0026] Optionally, the receiver further includes a resistor-capacitor circuit connected in series between the driver and the comparator.

[0027] In the above implementation, the waveform of the output signal of the driver is adjusted through the resistor-capacitor circuit, improving the output accuracy of the digital signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0029] Figure 1 A schematic structural diagram of a digital isolator provided by an embodiment of the present application.

[0030] Figure 2 A schematic structural diagram of an edge modulation transmitter provided by an embodiment of the present application.

[0031] Figure 3 A schematic structural diagram of a counting module provided by an embodiment of the present application.

[0032] Figure 4 A signal schematic diagram of increasing the number of pulses for a low data rate input signal provided by an embodiment of the present application.

[0033] Figure 5 A signal schematic diagram of increasing the pulse spacing for a high data rate input signal provided by an embodiment of the present application.

[0034] Figure 6 A schematic structural diagram of the driver provided by an embodiment of the present application.

[0035] Icons: 10 - Digital isolator; 11 - Edge modulation transmitter; 111 - Detection module; 1111 - Edge trigger module; 1112 - Counting module; 112 - Edge modulation module; 12 - Driver; 13 - Receiver; 131 - Comparator circuit; 132 - Latch; 133 - Resistor-capacitor circuit. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0037] First, start with the digital isolator. A digital isolator is a chip in an electronic system that, when digital signals and analog signals are transmitted, enables the electronic system to have high withstand voltage isolation characteristics to achieve isolation between electronic systems. Common-mode noise has a greater impact on the transmission reliability of the digital isolator signal. The digital isolators in the prior art have a small anti-CMT interference range and cannot perform targeted edge modulation on input signals with different transmission rates, and cannot guarantee the signal transmission quality in some environments. Therefore, this embodiment provides a digital isolator 10 to solve the above problems.

[0038] The input signal of the edge modulation transmitter 11 provided in the embodiment of the present application is a digital signal, and the rising edge and the falling edge appear alternately. The edge modulation transmitter 11 includes a detection module 111. The detection module 111 is used to detect the magnitude relationship between the time interval between two adjacent edges of the input signal and a preset duration, so that when the time interval between two adjacent edges of the input signal is less than the preset duration, the edge modulation transmitter 11 outputs a first number of pulses at the specified edge moment of the input signal, and when the time interval between two adjacent edges of the input signal is greater than or equal to the preset duration, the edge modulation transmitter 11 outputs a second number of pulses at the specified edge moment of the input signal.

[0039] Optionally, the second number is greater than the first number. In this embodiment, when giving an example, the second number can be 2 and the first number can be 1. It should be understood that in other embodiments, the first number and the second number can be selected as any other values.

[0040] Optionally, the above-mentioned specified edge can be the rising edge or the falling edge.

[0041] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a digital isolator provided in the embodiment of the present application.

[0042] The digital isolator 10 includes an edge modulation transmitter 11, a driver 12, and a receiver 13. The edge modulation transmitter 11 is electrically connected to the receiver 13 through the driver 12.

[0043] Please refer toFigure 2 , Figure 2 This is a schematic structural diagram of an edge modulation transmitter provided by an embodiment of the present application.

[0044] The edge modulation transmitter 11 includes a detection module 111 and an edge modulation module 112. The detection module 111 includes an edge trigger module 1111 and a counting module 1112 connected in parallel between the input end of the edge modulation module 112 and the signal input end of the edge modulation transmitter 11. The output end of the edge trigger module 1111 is connected to the reset end of the counting module 1112.

[0045] When the period of the input signal at the signal input end is greater than a preset duration, the edge trigger module 1111 outputs a first pulse signal. The first pulse signal is the reset signal of the counting module 1112. The counting module 1112 outputs a data rate determination signal representing the input signal based on the first pulse signal. The edge modulation module 112 is used to perform adaptive edge modulation on the input signal in different modes when the data rate determination signals are different, and transmits it to the receiver 13 through at least one multi-stage buffer and driver 12.

[0046] Specifically, the edge trigger module 1111 includes an edge trigger T1 and a timer T2. The input end of the edge trigger T1 is connected to the signal input end. The output end of the edge trigger T1 is connected to the reset end of the timer T2. The output end of the timer T2 is respectively connected to the reset end of the timer T2, the first input end of the edge modulation module 112, and the reset end of the counting module 1112.

[0047] The output signal of the edge trigger T1 when detecting the rising edge or falling edge of the input signal is used as the reset and clear signal (the first reset signal) of the timer T2, and the first reset signal is transmitted to the timer T2 to clear it. That is, each edge of the input signal will clear the timing of the timer T2, and the timer T2 does not output the first pulse signal. When the timing of the timer T2 reaches the preset duration, the timing of the timer T2 is not cleared, and the first pulse signal is output through its own output end.

[0048] Optionally, the counting module 1112 in this embodiment is an asynchronous counter with an overflow protection function. There are many implementation methods for the asynchronous counter, such as forming a 2-bit counter through D flip-flops.

[0049] A method for implementing overflow protection is proposed below. Those skilled in the art can use other methods to achieve similar functions. The specific implementation method is not a limitation to the present application.

[0050] Specifically, please refer to Figure 3 , Figure 3 This is a schematic structural diagram of a counting module provided by an embodiment of the present application.

[0051] The counting module 1112 includes a first D flip-flop D1, a second D flip-flop D2, a NOT gate, and a NOR gate. The clock input terminal of the first D flip-flop D1 is connected to the signal input terminal D. The clear terminals CLR of the first D flip-flop D1 and the second D flip-flop D2 are both connected to the output terminal of the timer T2. The D terminal, Q terminal, and terminal of the first D flip-flop D1 are connected to the input terminal of the NOT gate. The output terminal of the NOT gate is connected to the first input terminal of the NOR gate. The output terminal of the NOR gate is connected to the clock input terminal of the second D flip-flop D2. The D terminal of the second D flip-flop D2 is connected to the terminal of the second flip-flop. The second input terminal of the NOR gate and the Q terminal of the second D flip-flop D2 are both connected to the second input terminal of the edge modulation module 112. Among them, the first input terminal of the edge modulation module 112 is connected to the output terminal of the timer T2, and the third input terminal of the edge modulation module 112 is connected to the signal input terminal of the edge modulation transmitter 11.

[0052] For the first D flip-flop D1 and the second D flip-flop D2, when the second D flip-flop D2 of the second stage outputs a second logic through the D terminal, the output of the first D flip-flop D1 can be directly transmitted to the second D flip-flop D2 of the second stage. When the second D flip-flop D2 of the second stage switches to output the first logic through the D terminal, the clock input of the second D flip-flop D2 of the second stage switches to the second logic, maintaining the latch state. And the first pulse signal of the timer T2 can clear the D-terminal outputs of the first D flip-flop D1 and the second D flip-flop D2 simultaneously.

[0053] Then the working principle of the above counting module 1112 is as follows: The signal output from the Q terminal of the second D flip-flop D2 is the highest-bit signal, and the signal output from the Q terminal of the first D flip-flop D1 is the lowest-bit signal. When the data rate of the input signal input to the signal input terminal of the edge modulation transmitter 11 is low, that is, when the period of the input signal input to the signal input terminal of the edge modulation transmitter 11 is greater than the preset timing duration of the timer T2, the timer T2 outputs a first pulse signal, and the counting module 1112 is continuously cleared and cannot count up. Then the highest-bit signal remains the second logic (the second logic can be selected from 1 and 0 according to specific requirements. In this embodiment, the second logic is exemplified as 0).

[0054] When the data rate of the input signal at the signal input terminal of the edge modulation transmitter 11 is high, that is, when the period of the input signal at the signal input terminal of the edge modulation transmitter 11 is less than or equal to the preset timing duration of the timer T2, the clock of the timer T2 is frequently cleared and does not output the first pulse signal. Then the counting module 1112 continuously counts, and due to the overflow protection mechanism, the highest-bit signal is the first logic (in this embodiment, the first logic is exemplified as 1).

[0055] Therefore, when the highest bit signal of the counting module 1112 is the second logic, it can be determined that the input signal input to the signal input end of the edge modulation transmitter 11 is a low data rate. When the highest bit signal of the counting module 1112 is the first logic, it can be determined that the input signal input to the signal input end of the edge modulation transmitter 11 is a high data rate.

[0056] It should be understood that the pre-designed time duration in this embodiment can be flexibly adjusted according to the specific structure and requirements of the digital isolator 10.

[0057] In this embodiment, the edge modulation module 112 adaptively edge-modulates the input signal of the low data rate edge modulation transmitter 11 based on the data rate determination signal. The specific steps may include:

[0058] (1) When the highest bit signal is the first logic, the edge modulation module 112 outputs a first number of pulse signals for the first edge signal and a second number of pulse signals for the second edge signal.

[0059] (2) When the highest bit signal is the second logic, the edge modulation module 112 outputs a third number of pulse signals for the first edge signal and a fourth number of pulse signals for the second edge signal;

[0060] (3) The third number is greater than the first number, the fourth number is greater than the second number, and the first edge signal and the second edge signal are complementary edge signals of edge rising or edge falling.

[0061] Among them, in this embodiment, taking the first signal edge as the rising edge, the first number as 1, the second number as 1, the third number as 2, and the fourth number as 2 as an example, please refer to Figure 4 , Figure 4 is a signal schematic diagram for increasing the number of pulses of a low data rate input signal provided by an embodiment of the present application. Among them, the waveform of the first output end refers to the waveform output by the upper output end of the edge modulation module 112, the waveform of the second output end refers to the waveform output by the lower output end of the edge modulation module 112, and the output waveform is the final output waveform of the digital isolator 10, and t1 is the pre-designed time duration.

[0062] The technical advantage of this embodiment is that since a certain number of additional pulse signals are transmitted for the corresponding edge at a low data rate, even if the initial signal is damaged due to interference, such as a CMT event and cannot be normally received, the subsequent additional transmitted pulse signals can still be received, thus ensuring the accuracy of signal transmission.

[0063] In this embodiment, the edge modulation module 112 adaptively edge-modulates the input signal of the high data rate edge modulation transmitter 11 based on the data rate determination signal. The specific steps may include:

[0064] (1) When the highest bit signal is the first logic, the edge modulation module 112 outputs a pulse signal with a fifth number of pulse intervals equal to the first interval for the first edge signal, and outputs a pulse signal with a sixth number of pulse intervals equal to the second interval for the second edge signal;

[0065] (2) When the highest bit signal is the second logic, the edge modulation module 112 outputs a pulse signal with a fifth number of pulse intervals equal to the third interval for the first edge signal, and outputs a pulse signal with a sixth number of pulse intervals equal to the third interval for the second edge signal;

[0066] (3) The third interval is greater than the first interval, the fourth interval is greater than the second interval, and the first edge signal and the second edge signal are complementary edge signals with rising or falling edges.

[0067] Among them, in this embodiment, taking the first signal edge as the rising edge as an example, please refer to Figure 5 , Figure 5 which is a signal schematic diagram of increasing the pulse interval of a high data rate input signal provided by an embodiment of the present application. Among them, the waveform of the first output terminal refers to the waveform output by the upper output terminal of the edge modulation module 112, the waveform of the second output terminal refers to the waveform output by the lower output terminal of the edge modulation module 112, the output waveform is the final output waveform of the digital isolator 10, and t1 is the pre-designed time duration.

[0068] The technical advantage of this embodiment is that since the pulse interval corresponding to the lower edge at low data rate is larger, it can withstand interference for a longer time, such as CMT events, and can continue to transmit and receive signals after the CMT ends, thus ensuring the accuracy of signal transmission.

[0069] It should be understood that as long as the signals of the counting module 1112 are used to make the high-speed and low-speed signals have different pulse numbers or intervals, so as to adaptively edge-modulate the input signal, the specific method of this embodiment is not limited.

[0070] Optionally, the drive buffer of the driver 12 can also provide a feedback signal to the edge modulation module 112. Different embodiments can depend on the logic design of the edge modulation module 112 and its cooperation with the feedback signal of the drive buffer of the driver 12.

[0071] Next, the driver 12 and the receiver 13 of the digital isolator 10 will be specifically described.

[0072] Please refer to Figure 6, Figure 6 It is a schematic structural diagram of the driver provided by the embodiment of the present application. Optionally, in this embodiment, the driver 12 is a six-terminal transformer composed of two mutually coupled coils. The first input terminal and the second input terminal of the driver 12 are respectively connected to the first output terminal and the second output terminal of the edge modulation module 112 through a multi-stage buffer, and the first output terminal and the second output terminal of the driver 12 are connected to the receiver 13.

[0073] Further, the driver 12 also has a third output terminal connected to the receiver 13 between the first output terminal and the second output terminal, and a third access terminal grounded between the first input terminal and the second input terminal.

[0074] Please continue to refer to Figure 1 , the receiver 13 includes a comparator circuit 131 and a latch 132. The output terminal of the driver 12 is connected to the input terminal of the comparator circuit 131. The output terminal of the comparator circuit 131 is connected to the input terminal of the latch 132. The output terminal of the latch 132 is the output terminal of the digital isolator 10.

[0075] Optionally, the receiver 13 may further include a resistor-capacitor (RS) circuit 133 connected in series between the driver 12 and the comparator circuit 131 for adjusting the received waveform. The specific adjustment method is not the key point of the present invention, so it will not be elaborated.

[0076] Specifically, the comparator circuit 131 includes a first comparator C1 and a second comparator C2. The non-inverting input terminal of the first comparator C1 is respectively connected to the inverting input terminal of the second comparator C2 and the first output terminal of the resistor-capacitor circuit 133. The inverting input terminal of the first comparator C1 is respectively connected to the non-inverting input terminal of the second comparator C2 and the second output terminal of the resistor-capacitor circuit 133.

[0077] The latch 132 can be an R-S latch. The output terminal of the fifth comparator C5 is connected to the S terminal of the latch 132. The output terminal of the sixth comparator C6 is connected to the R terminal of the latch 132. The Q terminal of the latch 132 is the signal output terminal of the digital isolator 10.

[0078] In summary, the embodiments of the present application provide an edge modulation transmitter and a digital isolator. The input signal of the edge modulation transmitter is a digital signal, and the rising edge and the falling edge appear alternately. The edge modulation transmitter includes a detection module. When the time interval between two adjacent edges of the input signal detected by the detection module is less than a preset duration, the edge modulator outputs a first number of pulses at the specified edge moment of the input signal. When the time interval between two adjacent edges of the input signal detected by the detection module is greater than or equal to the preset duration, the edge modulator outputs a second number of pulses at the specified edge moment of the input signal, and the second number is greater than the first number.

[0079] In the above implementation, the data rate of the input signal is detected through the detection module, and different adaptive edge modulations are performed on the input signal under different data rates, so that the edge modulations of different data rates are more accurate, thereby improving the data transmission stability of the edge modulation transmitter.

[0080] In several embodiments provided by the present application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the block diagrams in the drawings show the possible architectures, functions, and operations of the devices according to multiple embodiments of the present application.

[0081] In addition, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0082] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered within the protection scope of the present application.

[0083] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

Claims

1. An edge-modulated transmitter, characterized in that: The input signal of the edge modulation transmitter is a digital signal, and the rising edge and the falling edge appear alternately; The edge-modulated transmitter includes a detection module; The edge modulation transmitter outputs a first number of pulses at a specified edge time of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is less than a preset time length; The edge modulation transmitter outputs a second number of pulses at the designated edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length, and the second number is greater than the first number; The edge modulation transmitter further includes an edge modulation module, the detection module includes an edge trigger module and a counting module, the edge trigger module and the counting module are connected in parallel between the input end of the edge modulation module and the signal input end of the edge modulation transmitter, and the output end of the edge trigger module is connected to the reset end of the counting module; The edge trigger module outputs a first pulse signal when the period of the input signal is greater than a preset duration, the first pulse signal being a reset signal for the counting module, and the counting module being configured to output a data rate determination signal representing the input signal based on the first pulse signal; The edge modulation module is used to perform adaptive edge modulation of different modes on the input signal when the data rate determination signal is different, and transmit the signal to the receiver through at least one multi-stage buffer and a driver.

2. The edge-modulated transmitter according to claim 1, wherein The counting module also outputs, based on the first pulse signal, an indication that the detection module detects that the time interval between two adjacent edges of the input signal is less than the preset duration. The edge modulation module is used to drive the output of the first number of pulses at the specified edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is less than the preset duration, and to output the second number of pulses at the specified edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset duration.

3. The edge-modulated transmitter according to claim 1, wherein: The edge trigger module includes an edge trigger and a timer, the input end of the edge trigger is connected to the signal input end, the output end of the edge trigger is connected to the reset end of the timer, and the output end of the timer is respectively connected to the reset end of the timer, the first input end of the edge modulation module, and the reset end of the counting module; When the edge trigger detects the specified edge of the input signal, it transmits a first reset signal to the timer to clear the timer, and outputs the first pulse signal through the output end of the timer when the timing of the timer reaches the preset time length.

4. The edge-modulated transmitter according to claim 1, wherein: The counting module is an asynchronous counter with overflow protection function.

5. The edge-modulated transmitter according to claim 3, wherein: The counting module includes a first D flip-flop, a second D flip-flop, a NOT gate, and a NOR gate. The clock input terminal of the first D flip-flop is connected to the signal input terminal. The clear terminal of the first D flip-flop and the clear terminal of the second D flip-flop are both connected to the output terminal of the timer. The D terminal, Q terminal, and The output end of the NOT gate is connected to the first input end of the NOR gate, the output end of the NOR gate is connected to the clock input end of the second D flip-flop, and the D end of the second D flip-flop is connected to the clock input end of the second D flip-flop. The second input end of the NOR gate and the Q end of the second D flip-flop are both connected to the second input end of the edge modulation module.

6. The edge-modulated transmitter according to claim 1, wherein: When the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset duration, the edge-modulated transmitter outputs the second number of pulses at the specified edge moment of the input signal, and the spacing between the second number of pulses is the first spacing.

7. A digital isolator, characterized in that: The digital isolator comprises an edge-modulated transmitter, a driver, and a receiver according to any one of claims 2 to 6, wherein the receiver comprises a comparator circuit and a latch, an output end of the driver is connected to an input end of the comparator circuit, an output end of the comparator circuit is connected to an input end of the latch, and an output end of the latch is an output end of the digital isolator; The comparator circuit compares the output signal of the driver. When the output signal of the driver is a pulse of a first polarity, the latch is set to a first logical latch state, and the output end of the latch outputs a first logic. When the output signal of the driver is a pulse of a second polarity, the latch is set to a second logical latch state, and the output end of the latch outputs a second logic.

8. The digital isolator according to claim 7, wherein: The driver is a six-terminal transformer consisting of two mutually coupled coils.

9. The digital isolator according to claim 8, wherein: The receiver further includes a resistor-capacitor circuit connected in series between the driver and the comparator.

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