A circuit board with an asymmetric structure and a manufacturing method thereof

Abstract

The present invention discloses a circuit board with an asymmetric structure and a manufacturing method thereof, and relates to the field of circuit board manufacturing. The method comprises a pre-stage step, a layer-adding step and an outer layer patterning step. The asymmetric circuit board prepared by the pre-stage step, the layer-adding step and the outer layer patterning step of the present invention comprises a total number of three circuit layers (inner patterned circuit, bottom patterned circuit and top patterned circuit), so the asymmetric circuit board can have a relatively low overall board thickness and a relatively low manufacturing cost.

Description

Technical Field

[0001] The invention relates to the field of circuit board manufacturing, and in particular to a circuit board with an asymmetric structure and a manufacturing method thereof. Background Art

[0002] Generally speaking, the number of circuit layers contained in the circuit board manufactured by the existing manufacturing method is usually designed to be an even number of layers. For example, the number of circuit layers of the existing circuit board is usually four layers, six layers, or eight layers. However, the circuit board manufactured by the existing circuit board manufacturing method has the problem of high manufacturing cost and the overall board thickness cannot be effectively reduced.

[0003] Therefore, how to provide a method for manufacturing a circuit board with an asymmetric structure by improving the structural design to reduce the manufacturing cost and overall board thickness of the circuit board and overcome the above-mentioned defects has become one of the important issues that this business wants to solve. Summary of the invention

[0004] In view of the defects existing in the prior art, the technical problem solved by the present invention is: how to reduce the manufacturing cost and overall board thickness of the circuit board.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a circuit board with an asymmetric structure, comprising the following steps:

[0006] S110: a pre-step, providing a substrate, defining two opposite side surfaces of the substrate as a first surface and a second surface, and forming an inner patterned circuit on the first surface;

[0007] S120: a layer-building step, forming a dielectric layer on the first surface, the dielectric layer entirely covers the inner patterned circuit, and defining a surface of the dielectric layer away from the substrate as a third surface; the substrate has a first thickness T1, and the dielectric layer has a second thickness T2, T1 being 1.2 to 2.0 times of T2, so as to form an asymmetric structure;

[0008] S130: an outer layer patterning step, forming a top surface patterned circuit on the third surface of the dielectric layer, and forming a bottom surface patterned circuit on the second surface of the substrate to form an asymmetric circuit board; the inner layer patterned circuit, the bottom surface patterned circuit and the top surface patterned circuit all include a plurality of metal conductors; the substrate, the inner layer patterned circuit and the bottom surface patterned circuit are collectively defined as a core substrate structure, and the dielectric layer and the top surface patterned circuit are collectively defined as a circuit build-up structure.

[0009] On the basis of the above technical solution, after S120 and before S130, the following steps are also included:

[0010] S121: a debonding step of debonding the second surface of the substrate;

[0011] S122: a drilling step of drilling the circuit build-up layer structure and the core substrate structure together to form a through hole, the through hole passing through the core substrate structure and the circuit build-up layer structure;

[0012] S123: Electroplating step, electroplating the circuit build-up layer structure and the core substrate structure together to form a metal conductive layer on the inner side wall of the through hole; the through hole and the metal conductive layer are jointly defined as a plated through-hole structure, and the plated through-hole structure electrically connects multiple metal conductors of the inner patterned circuit, the bottom patterned circuit and the top patterned circuit through the metal conductive layer, thereby electrically connecting the inner patterned circuit, the bottom patterned circuit and the top patterned circuit to each other.

[0013] Based on the above technical solution, S130 also includes the following steps: forming a bottom surface stress buffer structure on the second surface of the substrate, the bottom surface stress buffer structure surrounds the bottom surface patterned circuit; the bottom surface stress buffer structure includes a plurality of bottom surface stress buffer protrusions that are spaced apart from each other and arranged in an alternating or matrix arrangement; a bottom surface fixed gap is formed between adjacent bottom surface stress buffer protrusions, and the second surface portion of the substrate is exposed to the bottom surface fixed gap; the bottom surface fixed gap has a first width W1, and each bottom surface stress buffer protrusion has a second width W2, W2 is 5.0 to 15 times that of W1; each bottom surface stress buffer protrusion is surrounded by at least five other adjacent bottom surface stress buffer protrusions.

[0014] Based on the above technical solution, S130 also includes the following steps: forming a top surface stress buffer structure on the third surface of the dielectric layer, the top surface stress buffer structure surrounds the top surface patterned circuit; the top surface stress buffer structure includes a plurality of top surface stress buffer protrusions that are spaced apart from each other and arranged in an alternating or matrix arrangement; a top surface fixed gap is formed between adjacent top surface stress buffer protrusions, and the third surface portion of the dielectric layer is exposed to the top surface fixed gap; the top surface fixed gap has a third width W3, and each top surface stress buffer protrusion has a fourth width W4, W4 is 5.0 to 15 times that of W3; each top surface stress buffer protrusion is surrounded by at least five other adjacent top surface stress buffer protrusions.

[0015] On the basis of the above technical scheme, the middle part of the asymmetric circuit board is defined as the critical area A, and the part surrounding the critical area A is defined as the non-critical area B; in the core substrate structure, the inner layer patterned circuit and the bottom surface patterned circuit are both located in the critical area A, and the bottom surface stress buffer structure is located in the non-critical area B; in the circuit build-up layer structure, the top surface patterned circuit is located in the critical area A, and the top surface stress buffer structure is located in the non-critical area B; the coverage rate of the bottom surface stress buffer structure and the top surface stress buffer structure in the non-critical area B is both 10-15%.

[0016] The present invention provides a circuit board with an asymmetric structure, which includes a core substrate structure, the core substrate structure includes a substrate, and two opposite side surfaces of the substrate are defined as a first surface and a second surface, and the core substrate structure includes an inner layer patterned circuit located on the first surface, and a bottom surface patterned circuit located on the second surface; the circuit board also includes a circuit build-up layer structure, and the circuit build-up layer structure includes a dielectric layer and a top surface patterned circuit; the dielectric layer is located on the first surface and covers the inner layer patterned circuit, and a side surface of the dielectric layer away from the substrate is defined as a third surface, and the top surface patterned circuit is located on the third surface;

[0017] The substrate has a first thickness T1, the dielectric layer has a second thickness T2, T1 is 1.2 to 2.0 times of T2, so as to form an asymmetric structure; the inner layer patterned circuit, the bottom surface patterned circuit and the top surface patterned circuit all include a plurality of metal conductors.

[0018] Based on the above technical solution, the circuit board includes a plated through-hole structure, which includes a through-hole penetrating the circuit build-up layer structure and the core substrate structure, and a metal conductive layer plated on the inner wall of the through-hole; the metal conductive layer electrically connects multiple metal conductors of the inner patterned circuit, the bottom patterned circuit and the top patterned circuit, thereby electrically connecting the inner patterned circuit, the bottom patterned circuit and the top patterned circuit to each other.

[0019] On the basis of the above technical solution, the circuit board also includes a bottom surface stress buffer structure located on the second surface of the substrate, and the bottom surface stress buffer structure surrounds the bottom surface patterned circuit; the bottom surface stress buffer structure includes a plurality of bottom surface stress buffer protrusions that are spaced apart from each other and arranged in an alternating or matrix arrangement; a bottom surface fixed gap is formed between adjacent bottom surface stress buffer protrusions, and the second surface portion of the substrate is exposed to the bottom surface fixed gap; the bottom surface fixed gap has a first width W1, and each bottom surface stress buffer protrusion has a second width W2, and W2 is 5.0 to 15 times of W1; each bottom surface stress buffer protrusion is surrounded by at least five other adjacent bottom surface stress buffer protrusions.

[0020] On the basis of the above technical solution, the circuit board also includes a top surface stress buffer structure located on the third surface of the dielectric layer, and the top surface stress buffer structure surrounds the top surface patterned circuit; the top surface stress buffer structure includes a plurality of top surface stress buffer protrusions that are spaced apart from each other and arranged in an alternating or matrix arrangement; a top surface fixed gap is formed between adjacent top surface stress buffer protrusions, and the third surface portion of the dielectric layer is exposed to the top surface fixed gap; the top surface fixed gap has a third width W3, and each top surface stress buffer protrusion has a fourth width W4, W4 is 5.0 to 15 times of W3; each top surface stress buffer protrusion is surrounded by at least five other adjacent top surface stress buffer protrusions.

[0021] On the basis of the above technical scheme, the middle part of the asymmetric circuit board is defined as the critical area A, and the part surrounding the critical area A is defined as the non-critical area B; in the core substrate structure, the inner layer patterned circuit and the bottom surface patterned circuit are both located in the critical area A, and the bottom surface stress buffer structure is located in the non-critical area B; in the circuit build-up layer structure, the top surface patterned circuit is located in the critical area A, and the top surface stress buffer structure is located in the non-critical area B; the coverage rate of the bottom surface stress buffer structure and the top surface stress buffer structure in the non-critical area B is both 10-15%.

[0022] Compared with the prior art, the advantages of the present invention are:

[0023] (1) Compared with the circuit board with an even number of layers of at least four layers in the prior art, the asymmetric circuit board of the present invention comprises a total of three circuit layers (inner patterned circuit, bottom patterned circuit and top patterned circuit), so the asymmetric circuit board can have a relatively low overall board thickness and a relatively low manufacturing cost.

[0024] At the same time, since the circuit board in the prior art has a large number of layers, the pressing process in the manufacturing process specifically includes browning (that is, allowing the core board to react with the browning solution to form a dense organic browning film on the copper surface of the core board to enhance the bonding force between the core board and the PP sheet), combination and stacking; while the circuit board of the present invention has only three circuit layers, and does not require a combination process during pressing, thereby further reducing the manufacturing cost.

[0025] (2) The bottom surface stress buffer structure and the top surface stress buffer structure of the present invention can resist the stress generated by the asymmetric circuit board bending in different directions. By matching the bottom surface stress buffer structure and the top surface stress buffer structure, the warpage of the asymmetric circuit board is reduced to less than 0.75%;

[0026] Furthermore, the coverage of the bottom surface stress buffer structure and the top surface stress buffer structure in the non-critical area B of the present invention is 10-15%, so that the bottom surface stress buffer structure 14 and the top surface stress buffer structure 23 can provide an effective stress buffering effect, thereby further reducing the warping of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a flow chart of a method for manufacturing a circuit board with an asymmetric structure according to an embodiment of the present invention;

[0028] Figure 2 Schematic diagram of the pre-steps in an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of a layer-adding step in an embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of an outer layer patterning step in an embodiment of the present invention;

[0031] Figure 5 A schematic diagram of a drilling step in an embodiment of the present invention;

[0032] Figure 6 Schematic diagram of the electroplating step in an embodiment of the present invention;

[0033] Figure 7 A schematic diagram of an asymmetric circuit board having a bottom surface stress buffer structure and a top surface stress buffer structure according to an embodiment of the present invention;

[0034] Figure 8 An enlarged schematic diagram of the bottom surface stress buffer structure in an embodiment of the present invention;

[0035] Fig. 9 An enlarged schematic diagram of a top surface stress buffer structure in an embodiment of the present invention;

[0036] Fig.10 FIG. 4 is an overall schematic diagram of an asymmetric circuit board in an embodiment of the present invention.

[0037] In the figure:

[0038] 1-core substrate structure, 11-substrate, 111-first surface, 112-second surface, 12-inner patterned circuit, 13-bottom patterned circuit, 14-bottom stress buffer structure, 141-bottom stress buffer bump, 141a-bottom fixed gap;

[0039] 2-line build-up structure, 21-dielectric layer, 211-third surface, 22-top patterned line, 23-top stress buffer structure, 231-top stress buffer bump, 231a-top fixed gap;

[0040] 3- electroplated through hole structure, 31- through hole, 32- metal conductive layer. DETAILED DESCRIPTION

[0041] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0042] See also Figure 1 As shown, the method for manufacturing a circuit board with an asymmetric structure in an embodiment of the present invention comprises the following steps:

[0043] S110: Preliminary steps, see Figure 2 As shown, a substrate 11 is provided, and two opposite side surfaces of the substrate 11 are defined as a first surface 111 and a second surface 112 , and an inner patterned circuit 12 is formed on the first surface 111 .

[0044] S120: Layer adding step, see Figure 3 As shown, a dielectric layer 21 is formed on the first surface 111 of the substrate 11, and the dielectric layer 21 entirely covers the inner patterned circuit 12. A side surface of the dielectric layer 21 away from the substrate 11 is defined as a third surface 211.

[0045] S130: Outer layer patterning step, see Figure 4 As shown, a top patterned circuit 22 is formed on the third surface 211 of the dielectric layer 21, and a bottom patterned circuit 13 is formed on the second surface 112 of the substrate 11 to form a circuit board with an asymmetric structure (hereinafter referred to as an asymmetric circuit board).

[0046] See also Figure 4 As shown, the substrate 11 , the inner layer patterned circuit 12 and the bottom surface patterned circuit 13 are collectively defined as a core substrate structure 1 , and the dielectric layer 21 and the top surface patterned circuit 22 are collectively defined as a circuit build-up layer structure 2 .

[0047] It should be noted that the inner patterned circuit 12, the bottom patterned circuit 13 and the top patterned circuit 22 may include a plurality of metal conductors (not shown in the figure), and the plurality of metal conductors are arranged at intervals from each other; the size of the plurality of metal conductors and the distance between any two adjacent metal conductors may vary according to requirements. In other words, the size and distance of the metal conductors are not limited to being the same or different. The metal conductor may be a metal pad or a metal pattern, but the present invention is not limited thereto.

[0048] It can be seen that the asymmetric circuit board manufactured by the above method contains a total of three circuit layers (inner patterned circuit 12, bottom patterned circuit 13 and top patterned circuit 22), so the asymmetric circuit board can have a relatively low overall board thickness and relatively low manufacturing cost.

[0049] For further information, see Figure 3 or Figure 4 As shown, the substrate 11 has a first thickness T1, and the dielectric layer 21 has a second thickness T2, and the first thickness T1 is greater than the second thickness T2 to form an asymmetric structure. The first thickness T1 can be 1.2 to 2.0 times (1.5 times in this embodiment) the second thickness T2. Specifically, the first thickness T1 can be 50 to 80 microns, and the second thickness T2 can be 25 to 55 microns, but the present invention is not limited thereto. In addition, the material of the dielectric layer 21 can be epoxy resin or epoxy resin containing glass fiber, but the present invention is not limited thereto.

[0050] Preferably, see Figure 1 As shown, after S120 and before S130, the following steps are also included:

[0051] S121: a debonding step, in which the second surface 112 of the substrate 11 is debonded to remove dust generated when performing S120. The debonding method may be debonding residue liquid, ultraviolet light or plasma. The principle is that since no other circuit build-up layer structure is formed on the second surface 112 of the substrate 11, after performing S120, dust generated when performing S120 may remain on the second surface 112, so the second surface 112 needs to be debonded to avoid the dust from negatively affecting the subsequent process.

[0052] Preferably, see Figure 1 As shown, after S121 and before S130, the following steps are also included:

[0053] S122: Drilling steps, see Figure 5 As shown, the circuit build-up layer structure 2 and the core substrate structure 1 are drilled together to form a through hole 31 , and the through hole 31 passes through the core substrate structure 1 and the circuit build-up layer structure 2 .

[0054] S123: Electroplating step, see Figure 6 As shown, the circuit build-up layer structure 2 and the core substrate structure 1 are electroplated together to form a metal conductive layer 32 on the inner side wall of the through hole 31. The through hole 31 and the metal conductive layer 32 are collectively defined as a plated-through hole structure 3 (PTH). The plated-through hole structure 3 electrically connects the inner patterned circuit 12, the bottom patterned circuit 13 and the top patterned circuit 22 through the metal conductive layer 32, thereby electrically connecting the inner patterned circuit 12, the bottom patterned circuit 13 and the top patterned circuit 22 to each other.

[0055] Preferably, since the first thickness T1 of the substrate 11 is greater than the second thickness T2 of the dielectric layer 21, the asymmetric circuit board will generate a corresponding stress, and the stress causes the asymmetric circuit board to bend toward the core substrate structure 1. In order to avoid bending of the asymmetric circuit board due to stress, S130 also includes the following steps:

[0056] See also Figure 7 As shown, a bottom stress buffer structure 14 is formed on the second surface 112 of the substrate 11, and the bottom stress buffer structure 14 surrounds the bottom patterned circuit 13. The bottom stress buffer structure 14 can resist the stress of the asymmetric circuit board bending toward the core substrate structure 1.

[0057] For further information, see Figure 7 As shown, the bottom stress buffer structure 14 includes a plurality of bottom stress buffer bumps 141, and the plurality of bottom stress buffer bumps 141 are arranged at intervals from each other and in a staggered arrangement or a matrix arrangement; each bottom stress buffer bump 141 has a height H1 between 20 and 40 microns, but the present invention is not limited thereto. Figure 8 As shown, each bottom surface stress buffering protrusion 141 is a non-circular geometric figure, and a bottom surface fixed gap 141a is formed between adjacent bottom surface stress buffering protrusions 141 (that is, the distance between any two adjacent bottom surface stress buffering protrusions 141 is fixed). Each bottom surface stress buffering protrusion 141 can be, for example, a metal (such as copper) formed on the second surface 112 of the substrate 11 by electroplating, but the present invention is not limited thereto. In addition, at least a portion of the second surface 112 of the substrate 11 is exposed to the bottom surface fixed gap 141a.

[0058] For further information, see Figure 8 As shown, the bottom fixed gap 141a has a first width W1, and each bottom stress buffering protrusion 141 has a second width W2, the second width W2 is greater than the first width W1, and the second width W2 is 5.0 to 15 times (7.0 times in this embodiment) the first width W1. The first width W1 is 0.1 to 0.3 mm (0.2 mm in this embodiment), and the second width W2 is 1.0 to 1.8 mm (1.4 mm in this embodiment).

[0059] In addition, see Figure 8As shown, each bottom surface stress buffering protrusion 141 can be a pentagonal or hexagonal geometric figure, and multiple bottom surface stress buffering protrusions 141 are arranged at intervals from each other and in a staggered arrangement, and each bottom surface stress buffering protrusion 141 is surrounded by at least five other adjacent bottom surface stress buffering protrusions 141, but the present invention is not limited thereto. In this embodiment, each bottom surface stress buffering protrusion 141 is hexagonal, and each bottom surface stress buffering protrusion is surrounded by six adjacent bottom surface stress buffering protrusions 141, but the present invention is not limited thereto.

[0060] Preferably, in order to better avoid bending of the asymmetric circuit board, see Figure 7 As shown, S130 also includes the following steps: forming a top surface stress buffer structure 23 on the third surface 211 of the dielectric layer 21, the top surface stress buffer structure 23 surrounding the top surface patterned circuit 22. The top surface stress buffer structure 23 can resist the stress of the asymmetric circuit board bending toward the circuit build-up structure 2.

[0061] For further information, see Figure 7 As shown, the top surface stress buffer structure 23 includes a plurality of top surface stress buffer bumps 231, and the plurality of top surface stress buffer bumps 231 are arranged at intervals from each other and in a staggered arrangement or a matrix arrangement; each top surface stress buffer bump 231 has a height H2 between 20 and 40 microns, but the present invention is not limited thereto. Fig. 9 As shown, each top surface stress buffering protrusion 231 is a non-circular geometric figure, and a top surface fixed gap 231a is formed between adjacent top surface stress buffering protrusions 231 (that is, the distance between any two adjacent top surface stress buffering protrusions 2311 is fixed). In addition, at least a portion of the third surface 211 of the dielectric layer 21 is exposed to the top surface fixed gap 231a.

[0062] For further information, see Fig. 9 As shown, the top surface fixed gap 231a has a third width W3, and each top surface stress buffering protrusion 231 has a fourth width W4, the fourth width W4 is greater than the third width W3, and the fourth width W4 is 5.0 to 15 times (7.0 times in this embodiment) the third width W3. In this embodiment, the third width W3 is between 0.1 and 0.3 mm (0.2 mm in this embodiment), and the fourth width W4 is between 1.0 and 1.8 mm (1.4 mm in this embodiment).

[0063] In addition, see Fig. 9As shown, each top surface stress buffering protrusion 231 can be a pentagonal or hexagonal geometric figure, and multiple top surface stress buffering protrusions 231 are arranged at intervals from each other and in a staggered arrangement, and each top surface stress buffering protrusion 231 is surrounded by at least five other adjacent top surface stress buffering protrusions 231, but the present invention is not limited thereto. In this embodiment, each top surface stress buffering protrusion 231 is hexagonal, and each top surface stress buffering protrusion is surrounded by six adjacent top surface stress buffering protrusions 231, but the present invention is not limited thereto.

[0064] It is worth mentioning that the bottom stress buffer structure 14 is not electrically connected to the bottom patterned circuit 13, nor is it electrically connected to the plated through hole structure 3, and the top stress buffer structure 23 is not electrically connected to the top patterned circuit 22, nor is it electrically connected to the plated through hole structure 3. The bottom stress buffer structure 14 can be matched with the top stress buffer structure 23 to make the warpage of the asymmetric circuit board below 0.75%.

[0065] In addition, see Fig.10 As shown, the asymmetric circuit board is defined with at least one critical area A and one non-critical area B, wherein the critical area A is located in the middle part of the asymmetric circuit board, and the non-critical area B surrounds the critical area A. In the core substrate structure 1, the inner patterned circuit 12 and the bottom patterned circuit 13 are both located in the critical area A, and the bottom stress buffer structure 14 is located in the non-critical area B. In the circuit build-up structure 2, the top patterned circuit 22 is located in the critical area A, and the top stress buffer structure 23 is located in the non-critical area B.

[0066] It can be seen that the critical area A can be regarded as the area where any circuit is formed on the asymmetric circuit board (such as the inner layer patterned circuit 12, the bottom surface patterned circuit 13, or the top surface patterned circuit 22), and the non-critical area B can be regarded as the area where no circuit is formed on the asymmetric circuit board. When the asymmetric circuit board is finally formed, the critical area A of the asymmetric circuit board will be retained, and the non-critical area B of the asymmetric circuit board will be removed.

[0067] Furthermore, the multiple bottom surface stress buffer bumps 141 of the bottom surface stress buffer structure 14 have a coverage rate of 10 to 15% (the coverage rate in this embodiment is 12%) in the non-critical area B of the second surface 112 of the substrate 11, and the multiple top surface stress buffer bumps 231 of the top surface stress buffer structure 23 have a coverage rate of 10 to 15% (the coverage rate in this embodiment is 12%) in the non-critical area B of the third surface 211 of the dielectric layer 21, so that the bottom surface stress buffer structure 14 and the top surface stress buffer structure 23 can provide an effective stress buffering effect, thereby reducing the warping of the circuit board.

[0068] See also Fig. 9As shown, the circuit board with an asymmetric structure manufactured by the above method in the embodiment of the present invention includes a core substrate structure 1 and a circuit build-up layer structure 2. The core substrate structure 1 includes a substrate 11, an inner layer patterned circuit 12 and a bottom surface patterned circuit 13. The substrate 11 has a first surface 111 and a second surface 112 located on opposite sides, the inner layer patterned circuit 12 is formed on the first surface 111, and the bottom surface patterned circuit 13 is formed on the second surface 112.

[0069] The circuit build-up structure 2 includes a dielectric layer 21 and a top patterned circuit 22. The dielectric layer 21 is formed on the first surface 111 of the substrate 11 and covers the inner patterned circuit 12; a side surface of the dielectric layer 21 away from the substrate 11 is defined as a third surface 211, and the top patterned circuit 22 is formed on the third surface 211.

[0070] Preferably, the circuit board also includes a plated-through hole structure 3 (PTH), which runs through the core substrate structure 1 and the circuit build-up layer structure 2, and the inner layer patterned circuit 12, the bottom surface patterned circuit 13 and the top surface patterned circuit 22 are electrically connected to each other through the plated through hole structure 3.

[0071] Preferably, the circuit board also includes a bottom surface stress buffer structure 14 and / or a top surface stress buffer structure 23, the bottom surface stress buffer structure 14 is formed on the second surface 112 of the substrate 11, and the top surface stress buffer structure 23 is formed on the third surface 211 of the dielectric layer 21, so as to effectively reduce the warping of the asymmetric circuit board.

[0072] See also Figure 6 As shown, the circuit board with an asymmetric structure in the embodiment of the present invention (hereinafter referred to as the asymmetric circuit board) includes a core substrate structure 1 and a circuit build-up structure 2. The core substrate structure 1 includes a substrate 11, an inner patterned circuit 12 and a bottom patterned circuit 13; the two opposite side surfaces of the substrate 11 are defined as a first surface 111 and a second surface 112, the inner patterned circuit 12 is located on the first surface 111, and the bottom patterned circuit 13 is located on the second surface 112. The circuit build-up structure 2 includes a dielectric layer 21 and a top patterned circuit 22; the dielectric layer 21 is located on the first surface 111 and covers the inner patterned circuit 12, and the side surface of the dielectric layer 21 away from the substrate 11 is defined as a third surface 211, and the top patterned circuit 22 is located on the third surface 211.

[0073] It should be noted that the inner patterned circuit 12, the bottom patterned circuit 13 and the top patterned circuit 22 may include a plurality of metal conductors (not shown in the figure), and the plurality of metal conductors are arranged at intervals from each other; the size of the plurality of metal conductors and the distance between any two adjacent metal conductors may vary according to requirements. In other words, the size and distance of the metal conductors are not limited to being the same or different. The metal conductor may be a metal pad or a metal pattern, but the present invention is not limited thereto.

[0074] See also Figure 6 As shown, the substrate 11 has a first thickness T1, and the dielectric layer 21 has a second thickness T2, and the first thickness T1 is greater than the second thickness T2 to form an asymmetric structure. The first thickness T1 can be 1.2 to 2.0 times (1.5 times in this embodiment) the second thickness T2. Specifically, the first thickness T1 can be 50 to 80 microns, and the second thickness T2 can be 25 to 55 microns, but the present invention is not limited thereto. In addition, the material of the dielectric layer 21 can be epoxy resin or epoxy resin containing glass fiber, but the present invention is not limited thereto.

[0075] It can be seen that the asymmetric circuit board of the present invention comprises three circuit layers in total (inner patterned circuit 12, bottom patterned circuit 13 and top patterned circuit 22), so the asymmetric circuit board can have a relatively low overall board thickness and relatively low manufacturing cost.

[0076] Preferably, the asymmetric circuit board in this embodiment also includes a plated-through hole structure 3 (PTH), the plated-through hole structure 3 includes a through hole 31 penetrating the circuit build-up layer structure 2 and the core substrate structure 1, and a metal conductive layer 32 electroplated on the inner wall of the through hole 31; the metal conductive layer 32 electrically connects multiple metal conductors of the inner patterned circuit 12, the bottom patterned circuit 13 and the top patterned circuit 22, thereby making the inner patterned circuit 12, the bottom patterned circuit 13 and the top patterned circuit 22 electrically connected to each other.

[0077] Furthermore, since the first thickness T1 of the substrate 11 is greater than the second thickness T2 of the dielectric layer 21 , the asymmetric circuit board will generate a corresponding stress, and the stress causes the asymmetric circuit board to bend toward the core substrate structure 1 .

[0078] Therefore, to avoid stress-induced bending of asymmetrical circuit boards, see Figure 7As shown, the asymmetric circuit board in this embodiment further includes a bottom stress buffer structure 14 formed on the second surface 112 of the substrate 11, and the bottom stress buffer structure 14 surrounds the bottom patterned circuit 13. The bottom stress buffer structure 14 can resist the stress of the asymmetric circuit board bending toward the core substrate structure 1.

[0079] See also Figure 7 As shown, the bottom stress buffer structure 14 includes a plurality of bottom stress buffer bumps 141, and the plurality of bottom stress buffer bumps 141 are arranged at intervals from each other and in a staggered arrangement or a matrix arrangement; each bottom stress buffer bump 141 has a height H1 between 20 and 40 microns, but the present invention is not limited thereto. Figure 8 As shown, each bottom surface stress buffering protrusion 141 is a non-circular geometric figure, and a bottom surface fixed gap 141a is formed between adjacent bottom surface stress buffering protrusions 141 (that is, the distance between any two adjacent bottom surface stress buffering protrusions 141 is fixed). Each bottom surface stress buffering protrusion 141 can be, for example, a metal (such as copper) formed on the second surface 112 of the substrate 11 by electroplating, but the present invention is not limited thereto. In addition, at least a portion of the second surface 112 of the substrate 11 is exposed to the bottom surface fixed gap 141a.

[0080] For further information, see Figure 8 As shown, the bottom fixed gap 141a has a first width W1, and each bottom stress buffering protrusion 141 has a second width W2, the second width W2 is greater than the first width W1, and the second width W2 is 5.0 to 15 times (7.0 times in this embodiment) the first width W1. The first width W1 is 0.1 to 0.3 mm (0.2 mm in this embodiment), and the second width W2 is 1.0 to 1.8 mm (1.4 mm in this embodiment).

[0081] In addition, see Figure 8 As shown, each bottom surface stress buffering protrusion 141 can be a pentagonal or hexagonal geometric figure, and multiple bottom surface stress buffering protrusions 141 are arranged at intervals from each other and in a staggered arrangement, and each bottom surface stress buffering protrusion 141 is surrounded by at least five other adjacent bottom surface stress buffering protrusions 141, but the present invention is not limited thereto. In this embodiment, each bottom surface stress buffering protrusion 141 is hexagonal, and each bottom surface stress buffering protrusion is surrounded by six adjacent bottom surface stress buffering protrusions 141, but the present invention is not limited thereto.

[0082] Preferably, in order to better avoid bending of the asymmetric circuit board, see Figure 7As shown, the asymmetric circuit board in this embodiment further includes a top surface stress buffer structure 23 formed on the third surface 211 of the dielectric layer 21, and the top surface stress buffer structure 23 surrounds the top surface patterned circuit 22. The top surface stress buffer structure 23 can resist the stress of the asymmetric circuit board bending toward the circuit build-up structure 2.

[0083] For further information, see Figure 7 As shown, the top surface stress buffer structure 23 includes a plurality of top surface stress buffer bumps 231, and the plurality of top surface stress buffer bumps 231 are arranged at intervals from each other and in a staggered arrangement or a matrix arrangement; each top surface stress buffer bump 231 has a height H2 between 20 and 40 microns, but the present invention is not limited thereto. Fig. 9 As shown, each top surface stress buffering protrusion 231 is a non-circular geometric figure, and a top surface fixed gap 231a is formed between adjacent top surface stress buffering protrusions 231 (that is, the distance between any two adjacent top surface stress buffering protrusions 2311 is fixed). In addition, at least a portion of the third surface 211 of the dielectric layer 21 is exposed to the top surface fixed gap 231a.

[0084] For further information, see Fig. 9 As shown, the top surface fixed gap 231a has a third width W3, and each top surface stress buffering protrusion 231 has a fourth width W4, the fourth width W4 is greater than the third width W3, and the fourth width W4 is 5.0 to 15 times (7.0 times in this embodiment) the third width W3. In this embodiment, the third width W3 is between 0.1 and 0.3 mm (0.2 mm in this embodiment), and the fourth width W4 is between 1.0 and 1.8 mm (1.4 mm in this embodiment).

[0085] In addition, see Fig. 9 As shown, each top surface stress buffering protrusion 231 can be a pentagonal or hexagonal geometric figure, and multiple top surface stress buffering protrusions 231 are arranged at intervals from each other and in a staggered arrangement, and each top surface stress buffering protrusion 231 is surrounded by at least five other adjacent top surface stress buffering protrusions 231, but the present invention is not limited thereto. In this embodiment, each top surface stress buffering protrusion 231 is hexagonal, and each top surface stress buffering protrusion is surrounded by six adjacent top surface stress buffering protrusions 231, but the present invention is not limited thereto.

[0086] It is worth mentioning that the bottom stress buffer structure 14 is not electrically connected to the bottom patterned circuit 13, nor is it electrically connected to the plated through hole structure 3, and the top stress buffer structure 23 is not electrically connected to the top patterned circuit 22, nor is it electrically connected to the plated through hole structure 3. The bottom stress buffer structure 14 can be matched with the top stress buffer structure 23 to make the warpage of the asymmetric circuit board below 0.75%.

[0087] In addition, see Fig.10 As shown, the asymmetric circuit board in this embodiment is defined with at least one critical area A and one non-critical area B, wherein the critical area A is located in the middle part of the asymmetric circuit board, and the non-critical area B surrounds the critical area A. In the core substrate structure 1, the inner patterned circuit 12 and the bottom patterned circuit 13 are both located in the critical area A, and the bottom stress buffer structure 14 is located in the non-critical area B. In the circuit build-up structure 2, the top patterned circuit 22 is located in the critical area A, and the top stress buffer structure 23 is located in the non-critical area B.

[0088] It can be seen that the critical area A can be regarded as the area where any circuit is formed on the asymmetric circuit board (such as the inner layer patterned circuit 12, the bottom surface patterned circuit 13, or the top surface patterned circuit 22), and the non-critical area B can be regarded as the area where no circuit is formed on the asymmetric circuit board. When the asymmetric circuit board is finally formed, the critical area A of the asymmetric circuit board will be retained, and the non-critical area B of the asymmetric circuit board will be removed.

[0089] Furthermore, the multiple bottom surface stress buffer bumps 141 of the bottom surface stress buffer structure 14 have a coverage rate of 10 to 15% (the coverage rate in this embodiment is 12%) in the non-critical area B of the second surface 112 of the substrate 11, and the multiple top surface stress buffer bumps 231 of the top surface stress buffer structure 23 have a coverage rate of 10 to 15% (the coverage rate in this embodiment is 12%) in the non-critical area B of the third surface 211 of the dielectric layer 21, so that the bottom surface stress buffer structure 14 and the top surface stress buffer structure 23 can provide an effective stress buffering effect, thereby reducing the warping of the circuit board.

[0090] Furthermore, the present invention is not limited to the above-mentioned embodiments. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention. Contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

Claims

1. A method for manufacturing a circuit board with an asymmetric structure, characterized in that: The method comprises the following steps: S110: a pre-step, providing a substrate (11), defining two opposite side surfaces of the substrate (11) as a first surface (111) and a second surface (112), and forming an inner patterned circuit (12) on the first surface (111); S120: a layer-building step, forming a dielectric layer (21) on the first surface (111), the dielectric layer (21) entirely covering the inner patterned circuit (12), and defining a side surface of the dielectric layer (21) away from the substrate (11) as a third surface (211); the substrate (11) has a first thickness T1, and the dielectric layer (21) has a second thickness T2, T1 being 1.2 to 2.0 times of T2, so as to form an asymmetric structure; S130: an outer layer patterning step, forming a top surface patterned circuit (22) on the third surface (211) of the dielectric layer (21), and forming a bottom surface patterned circuit (13) on the second surface (112) of the substrate (11), so as to form an asymmetric circuit board; the inner layer patterned circuit (12), the bottom surface patterned circuit (13) and the top surface patterned circuit (22) all include a plurality of metal conductors; the substrate (11), the inner layer patterned circuit (12) and the bottom surface patterned circuit (13) are collectively defined as a core substrate structure (1), and the dielectric layer (21) and the top surface patterned circuit (22) are collectively defined as a circuit build-up layer structure (2); Wherein, S130 also includes the following steps: forming a bottom surface stress buffer structure (14) on the second surface (112) of the substrate (11), the bottom surface stress buffer structure (14) surrounding the bottom surface patterned circuit (13); the bottom surface stress buffer structure (14) comprising a plurality of bottom surface stress buffer protrusions (141) arranged at intervals from each other and arranged in a staggered or matrix arrangement; a bottom surface fixed gap (141a) is formed between adjacent bottom surface stress buffer protrusions (141), and the second surface (112) of the substrate (11) is partially exposed to the bottom surface fixed gap (141a); the bottom surface fixed gap (141a) has a first width W1, and each bottom surface stress buffer protrusion (141) has a second width W2, W2 being 5.0 to 15 times of W1; each bottom surface stress buffer protrusion (141) is surrounded by at least five other adjacent bottom surface stress buffer protrusions (141); Wherein, S130 also includes the following steps: forming a top surface stress buffer structure (23) on the third surface (211) of the dielectric layer (21), the top surface stress buffer structure (23) surrounding the top surface patterned circuit (22); the top surface stress buffer structure (23) comprising a plurality of top surface stress buffer protrusions (231) arranged at intervals from each other and arranged in a staggered or matrix arrangement; a top surface fixed gap (231a) is formed between adjacent top surface stress buffer protrusions (231), and the third surface (211) of the dielectric layer (21) is partially exposed to the top surface fixed gap (231a); the top surface fixed gap (231a) has a third width W3, and each top surface stress buffer protrusion (231) has a fourth width W4, W4 being 5.0 to 15 times of W3; and each top surface stress buffer protrusion (231) is surrounded by at least five other adjacent top surface stress buffer protrusions (231).

2. The method for manufacturing a circuit board with an asymmetric structure according to claim 1, characterized in that: After S120 and before S130, the following steps are also included: S121: a debonding step, performing debonding on the second surface (112) of the substrate (11); S122: a drilling step, drilling the circuit build-up layer structure (2) and the core substrate structure (1) together to form a through hole (31), wherein the through hole (31) penetrates the core substrate structure (1) and the circuit build-up layer structure (2); S123: an electroplating step, wherein the circuit build-up layer structure (2) and the core substrate structure (1) are electroplated together to form a metal conductive layer (32) on the inner side wall of the through hole (31); the through hole (31) and the metal conductive layer (32) are collectively defined as an electroplated through hole structure (3); the electroplated through hole structure (3) is electrically connected to a plurality of metal conductors of the inner layer patterned circuit (12), the bottom surface patterned circuit (13) and the top surface patterned circuit (22) through the metal conductive layer (32), thereby electrically connecting the inner layer patterned circuit (12), the bottom surface patterned circuit (13) and the top surface patterned circuit (22) to each other.

3. The method for manufacturing a circuit board with an asymmetric structure according to claim 1, wherein: The middle part of the asymmetric circuit board is defined as a critical area A, and the part surrounding the critical area A is defined as a non-critical area B; in the core substrate structure (1), the inner layer patterned circuit (12) and the bottom surface patterned circuit (13) are both located in the critical area A, and the bottom surface stress buffer structure (14) is located in the non-critical area B; in the circuit layer structure (2), the top surface patterned circuit (22) is located in the critical area A, and the top surface stress buffer structure (23) is located in the non-critical area B; the coverage of the bottom surface stress buffer structure (14) and the top surface stress buffer structure (23) in the non-critical area B is both 10-15%.

4. A circuit board with an asymmetric structure, the circuit board comprising a core substrate structure (1), the core substrate structure (1) comprising a substrate (11), two opposite side surfaces of the substrate (11) being defined as a first surface (111) and a second surface (112), characterized in that: The core substrate structure (1) comprises an inner patterned circuit (12) located on a first surface (111), and a bottom patterned circuit (13) located on a second surface (112); the circuit board also comprises a circuit build-up structure (2), the circuit build-up structure (2) comprising a dielectric layer (21) and a top patterned circuit (22); the dielectric layer (21) is located on the first surface (111) and covers the inner patterned circuit (12), a side surface of the dielectric layer (21) away from the substrate (11) is defined as a third surface (211), and the top patterned circuit (22) is located on the third surface (211); The substrate (11) has a first thickness T1, the dielectric layer (21) has a second thickness T2, T1 is 1.2 to 2.0 times of T2, so as to form an asymmetric structure; the inner layer patterned circuit (12), the bottom surface patterned circuit (13) and the top surface patterned circuit (22) all include a plurality of metal conductors; The circuit board comprises a plated through-hole structure (3), the plated through-hole structure (3) comprising a through-hole (31) penetrating the circuit build-up layer structure (2) and the core substrate structure (1), and a metal conductive layer (32) plated on the inner wall of the through-hole (31); the metal conductive layer (32) electrically connects a plurality of metal conductors of an inner patterned circuit (12), a bottom patterned circuit (13), and a top patterned circuit (22), thereby electrically connecting the inner patterned circuit (12), the bottom patterned circuit (13), and the top patterned circuit (22) to each other; The circuit board further comprises a bottom surface stress buffer structure (14) located on the second surface (112) of the substrate (11), the bottom surface stress buffer structure (14) surrounding the bottom surface patterned circuit (13); the bottom surface stress buffer structure (14) comprises a plurality of bottom surface stress buffer protrusions (141) arranged at intervals from each other and arranged in a staggered or matrix arrangement; a bottom surface fixed gap (141a) is formed between adjacent bottom surface stress buffer protrusions (141), and the second surface (112) of the substrate (11) is partially exposed to the bottom surface fixed gap (141a); the bottom surface fixed gap (141a) has a first width W1, and each bottom surface stress buffer protrusion (141) has a second width W2, W2 being 5.0 to 15 times of W1; each bottom surface stress buffer protrusion (141) is surrounded by at least five other adjacent bottom surface stress buffer protrusions (141); The circuit board further comprises a top surface stress buffer structure (23) located on the third surface (211) of the dielectric layer (21), the top surface stress buffer structure (23) surrounding the top surface patterned circuit (22); the top surface stress buffer structure (23) comprises a plurality of top surface stress buffer protrusions (231) arranged at intervals from each other and arranged in a staggered or matrix arrangement; a top surface fixed gap (231a) is formed between adjacent top surface stress buffer protrusions (231), and the third surface (211) of the dielectric layer (21) is partially exposed to the top surface fixed gap (231a); the top surface fixed gap (231a) has a third width W3, and each top surface stress buffer protrusion (231) has a fourth width W4, W4 being 5.0 to 15 times of W3; and each top surface stress buffer protrusion (231) is surrounded by at least five other adjacent top surface stress buffer protrusions (231).

5. The circuit board with an asymmetric structure as claimed in claim 4, characterized in that: The middle part of the circuit board with the asymmetric structure is defined as the critical area A, and the part surrounding the critical area A is defined as the non-critical area B; in the core substrate structure (1), the inner layer patterned circuit (12) and the bottom surface patterned circuit (13) are both located in the critical area A, and the bottom surface stress buffer structure (14) is located in the non-critical area B; in the circuit layer structure (2), the top surface patterned circuit (22) is located in the critical area A, and the top surface stress buffer structure (23) is located in the non-critical area B; the coverage of the bottom surface stress buffer structure (14) and the top surface stress buffer structure (23) in the non-critical area B is 10-15%.

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