Mask design methods and methods for manufacturing semiconductor devices using them

Abstract

A method of manufacturing a semiconductor device includes the steps of: forming a lower structure including a first repeating pattern; and forming an upper structure, the step of forming a second repeating pattern to correspond to each of the first repeating patterns on the lower structure, and the step of forming the second repeating pattern includes: preparing a design layout for the second repeating pattern; forming a first corrected layout including the corrected second repeating pattern by performing optical proximity correction (OPC) on the design layout; forming a second corrected layout by performing position correction on the first corrected layout to move the position of the corrected second repeating pattern to correspond to the changed position of the first repeating pattern according to the physical deformation of the lower structure; using the second corrected layout to manufacture a mask; and using the mask to pattern a photoresist layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0087692, filed on July 19, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a mask design method and a method for manufacturing a semiconductor device using the mask design method. Background Technology

[0004] In integrated circuit design, to form circuits on a semiconductor substrate, a circuit layout is prepared, and this layout can be transferred to the wafer surface using a mask, such as a photomask. As semiconductor devices become increasingly integrated, integrated circuit design becomes more complex. Therefore, accurately realizing the layout according to the initially intended design on the mask required for photolithography becomes increasingly important. In particular, when the wavelength of the light source used in the exposure equipment is close to the feature size of the semiconductor device, pattern distortion may occur due to diffraction, interference, etc., of the beam. Thus, on the wafer, optical proximity effect (OPE) may occur, where an image with a shape different from the original shape is formed, or the influence of adjacent patterns causes distortion of the pattern shape. To prevent problems such as dimensional changes due to optical proximity effect, an optical proximity correction (OPC) process is performed. The OPC process is provided to predict dimensional changes in advance during pattern transfer and to pre-deform the design pattern so that the pattern shape according to the layout is obtained after pattern transfer. Summary of the Invention

[0005] One aspect of the present invention is to provide a mask design method with improved accuracy and efficiency, and a method for manufacturing a semiconductor device using the mask design method.

[0006] According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a lower structure including a first repeating pattern; and forming an upper structure, the upper structure including forming a second repeating pattern to correspond to each of the first repeating patterns on the lower structure, and forming the second repeating pattern including: preparing a design layout for the second repeating pattern; forming a first corrected layout including the corrected second repeating pattern by performing optical proximity correction (OPC) on the design layout; forming a second corrected layout by performing position correction on the first corrected layout to move the position of the corrected second repeating pattern to correspond to the changed position of the first repeating pattern according to the physical deformation of the lower structure; using the second corrected layout to manufacture a mask; and using the mask to pattern a photoresist layer.

[0007] According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: preparing a design layout including repeating patterns and non-repeating patterns; forming a first corrected layout including corrected repeating patterns by performing a first optical proximity correction (OPC) on the repeating patterns; forming a second corrected layout by performing a first position correction on the first corrected layout to move the position of the corrected repeating patterns; performing a second optical proximity correction (OPC) on the non-repeating patterns using a method different from the first optical proximity correction; and performing a second position correction on the non-repeating patterns to move the position of the non-repeating patterns.

[0008] According to one aspect of the present invention, a mask design method includes: preparing a design layout, the design layout including a second repeating pattern formed to match a first repeating pattern; forming a first corrected layout including the corrected second repeating pattern by performing optical proximity correction (OPC) on the design layout; forming a second corrected layout by performing position correction on the first corrected layout to move the position of the corrected second repeating pattern to correspond to a positional change of the first repeating pattern; and providing the second corrected layout to an exposure apparatus. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example embodiment;

[0011] Figure 2 This is a flowchart illustrating a mask design method according to an example embodiment;

[0012] Figure 3A and Figure 3BThis is a diagram illustrating a mask design method according to an example embodiment;

[0013] Figure 4 and Figure 5 This is a diagram illustrating a mask design method according to an example embodiment;

[0014] Figure 6 This is a flowchart illustrating a mask design method according to an example embodiment;

[0015] Figure 7A and Figure 7B This is a diagram illustrating a mask design method according to an example embodiment;

[0016] Figure 8 This is a schematic plan view of a semiconductor device according to an example embodiment;

[0017] Figure 9 This is a schematic cross-sectional view illustrating a semiconductor device according to an example embodiment;

[0018] Figures 10A to 10F This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment; and

[0019] Figure 11A and Figure 11B This is a schematic diagram illustrating the deformation that occurs in the lower structure during the manufacture of a semiconductor device according to an example embodiment. Detailed Implementation

[0020] In the following, exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0022] Reference Figure 1 The method of manufacturing a semiconductor device may include: designing a design layout for the semiconductor device (S100), performing optical proximity correction (OPC) and position correction on the design layout (S200), manufacturing a mask using the corrected design layout (S300), and manufacturing the semiconductor device using the mask (S400).

[0023] In the design layout (S100) of the semiconductor device, a design layout corresponding to the circuit pattern of the semiconductor device to be formed on the wafer can be provided from a host computer, a server of a semiconductor manufacturing facility, or other suitable methods. Specifically, the layout is a physical instruction in which the circuit designed for the semiconductor device can be transferred onto the wafer, and the layout can include multiple patterns. For example, the design layout can be provided based on the coordinate values ​​of the outline of the pattern formed from a CAD system. Specifically, the pattern can include repeating patterns with the same shape repeated, and can be provided in the form of combinations of polygons such as triangles and / or quadrilaterals.

[0024] Performing optical proximity correction (OPC) and position correction (S200) on the design layout can include optical proximity correction and position correction performed in separate operations, respectively.

[0025] First, optical proximity correction refers to correcting altered patterns in a design layout by reflecting errors based on the optical proximity effect (OPE). As patterns become more refined, optical proximity can occur due to the influence between adjacent patterns during the exposure process. Therefore, by performing optical proximity correction to correct the design layout, the occurrence of the optical proximity effect can be suppressed. For example, optical proximity correction may include enlarging the overall size of the patterns forming the design layout and processing corners. For example, optical proximity correction may include moving the edges of each pattern or adding additional polygons. Due to optical proximity correction, distortions in the pattern caused by diffraction, interference, etc., of the beam generated during exposure are corrected, and errors caused by pattern density can also be corrected. After optical proximity correction, further optical proximity correction verification can be performed.

[0026] Position correction can include moving the position of the pattern to which optical proximity correction has been performed, taking into account the physical transformations and changes to the underlying structure to which the pattern is to be aligned. Deformation of the underlying structure occurs due to factors during the manufacturing process of the semiconductor device. As a result, gradual misalignment may occur, where the actual pattern position of the pattern on the underlying structure changes from the original layout. Position correction can move the position of the pattern to which optical proximity correction has been performed without changing its shape.

[0027] The final design layout data, corrected by optical proximity correction and position correction, can be transferred to exposure equipment used to manufacture masks (e.g., photomasks and electron beam masks) for photolithography processes.

[0028] Manufacturing a mask using the corrected design layout (S300) can be performed based on the corrected design layout data. An exposure process is executed on a mask substrate using the corrected design layout data to manufacture the mask. After the exposure process, for example, a series of processes such as development, etching, cleaning, baking, etc., can be further performed to form the mask. According to an example embodiment, verification of the corrected design layout data can be further performed before transmitting the corrected design layout data.

[0029] Fabricating a semiconductor device using a mask (S400) may include performing a photolithography process using a mask. The semiconductor device may include volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM), or non-volatile memory such as flash memory, and may include logic semiconductor devices such as microprocessors (e.g., central processing unit (CPU), controllers, or application-specific integrated circuits (ASICs)). Specifically, the semiconductor device may be fabricated by forming a second repeating pattern on a lower structure including a first repeating pattern. The second repeating pattern can be aligned with the first repeating pattern with high precision using a mask. In addition to the photolithography process, the semiconductor device may be ultimately fabricated by further performing deposition processes, etching processes, ion implantation processes, cleaning processes, etc.

[0030] Figure 2 This is a flowchart illustrating a mask design method according to an example embodiment. Figure 2 The text is a detailed description of the process. Figure 1 This is part of a method for manufacturing a semiconductor device. Specifically, mask design methods are shown in some example embodiments, where the design layout includes repeating patterns.

[0031] Reference Figure 2 The mask design method may include: designing a design layout including a repeating pattern (S110); forming a first correction layout including the corrected repeating pattern by performing optical proximity correction on the design layout (S210); forming a second correction layout by performing position correction to move the position of the corrected repeating pattern relative to the first correction layout (S220); and providing the second correction layout to an exposure apparatus (S230). Thereafter, the previously referenced process is performed in the same manner as in the manufacture of a semiconductor device. Figure 1 The fabrication of the mask is described (S300). In the following text, references are omitted. Figure 1 The description is a repetitive description.

[0032] Previous reference Figure 1The description of the design layout (S100) can also be applied to a design layout (S110) that includes repeating patterns. However, in some example embodiments, the design layout includes regularly arranged repeating patterns. As an example, the repeating pattern may be a pattern of configuration for forming memory cells of a semiconductor device. More specifically, the repeating pattern may be a vertical channel pattern or a contact plug pattern of the memory cell. In particular, the repeating pattern may be a pattern that corresponds one-to-one with the repeating pattern of the underlying structure, but is not limited thereto.

[0033] As described above, forming a first corrected layout including a corrected repeating pattern by performing optical proximity correction on the design layout (S210) can be an operation in which the pattern included in the design layout is changed by reflecting the error according to the optical proximity effect (OPE).

[0034] Forming a second corrected layout by performing position correction to move the position of the corrected repeating pattern relative to the first corrected layout (S220) may include: determining a position correction value considering misalignment caused by the lower structure (S222), and forming the second corrected layout by moving the position of the corrected repeating pattern of the first corrected layout according to the position correction value (S224). The position correction value may be determined by considering physical changes occurring in the lower structure in which the repeating pattern is formed (e.g., expansion, contraction, warping, etc. of the lower structure). The position correction value may be determined by considering the temperature of the process forming the lower structure and the coefficient of thermal expansion of the material forming the lower structure, and may also be determined by simulation based on actual data. The second corrected layout is obtained by moving only the position of the corrected repeating pattern of the first corrected layout; therefore, the shape of each of the corrected repeating patterns in the second corrected layout may be the same as the shape of each of the corrected repeating patterns in the first corrected layout.

[0035] Providing a second corrected layout to the exposure equipment (S230) can ultimately transmit the corrected design layout data to the exposure equipment for mask fabrication.

[0036] Figure 3A and Figure 3B This is a diagram illustrating a mask design method according to an example embodiment.

[0037] Reference Figure 3A and Figure 3B This will schematically illustrate the mask design methods based on each of the examples and comparative examples. First, as... Figure 3A As shown, regarding this example, optical proximity correction can first be performed on the repeating pattern x. This can correspond to Figure 2The formation of the first correction layout (S210) is achieved. Pattern x has a regularly repeating form. Therefore, optical proximity correction can be repeatedly performed on most patterns (e.g., more than half of the patterns) except for those in the edge regions. Thus, some patterns, including those in the central region, are corrected equally to form a first pattern y with the same shape. During optical proximity correction, the patterns in the edge regions can be corrected slightly differently depending on the surrounding environment. Thus, the patterns in the edge regions can be corrected to be different from the first pattern y, thereby forming the second to ninth patterns w, w', z, z', v1, v2, v3, and v4. In this operation, optical proximity correction is repeatedly performed on most patterns, including those in the central region, in a similar manner, thus significantly reducing the time spent on optical proximity correction and obtaining uniform results.

[0038] Next, positional corrections considering the alignment of the substructure can be performed. This can correspond to... Figure 2 The second correction layout is formed (S220). Regarding position correction, a grid is defined for dividing the design layout including the pattern into a predetermined size (e.g., about 0.01 nm to about 1 nm), and position correction can be continuously performed on the grid. Alternatively, a region can be divided into multiple regions, and position correction can be performed on each region. Position correction values ​​can be applied differently depending on the position of the pattern, where the position correction value refers to the direction and amount of position correction.

[0039] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, they mean that the associated numerical value includes a tolerance of ±10% above or below said value. When a range is specified, the range includes all values ​​in between, such as an increment of 0.1%.

[0040] like Figure 3B As shown, regarding the comparative example, firstly, a region of pattern x, which will be the target of optical proximity correction, is divided, and position correction can be performed. Considering alignment with the lower structure, position correction can be performed on pattern x before optical proximity correction has been performed. Then, optical proximity correction can be performed on pattern x after position correction has been performed. In some example embodiments, the repeatability of pattern x is compromised due to the initially performed positional movement. In some example embodiments, repeatability cannot be identified during optical proximity correction. Therefore, optical proximity correction is performed on randomly divided regions (a, b, c…). Therefore, compared with the previously referenced… Figure 3A The different methods of optical proximity correction for repeating patterns described above can be used to perform optical proximity correction when each element in the pattern is set as an independent target.

[0041] In some example embodiments, performing optical proximity correction takes a relatively long time, resulting in... Figure 3A The uniformity is reduced compared to the example. Specifically, in some example embodiments, optical proximity correction is performed after defining a grid for dividing the design layout, including the position-corrected pattern, into grids of predetermined sizes, and optical proximity correction is performed continuously on the grids. Here, the numerical error caused by the size of the aforementioned grid is greater than the error allowed in actual semiconductor processes. Furthermore, it is confirmed that this numerical error is greater than that based on... Figure 3A The numerical error of the position correction method in the example embodiment. Therefore, according to the comparative example, when manufacturing a semiconductor device, the dispersion of the critical dimensions of the photoresist pattern may increase. Conversely, according to Figure 3A The above example uses pattern repeatability to perform optical proximity correction on repeating patterns, thus preventing the aforementioned problems. Therefore, improvements to misalignment caused by position correction can be effectively obtained.

[0042] Figure 4 and Figure 5 This is a diagram illustrating a mask design method according to an example embodiment.

[0043] Reference Figure 4 and Figure 5 This will be shown schematically in Figure 2 An example embodiment of the method for forming the position of the moving repeating pattern in the second correction layout (S220). First, as... Figure 4 As shown, the repeating pattern P1 of the first correction layout is set with continuous coordinates, and position correction values ​​can be assigned to each coordinate. For example, the coordinates can be determined in units of the grid size of the first correction layout data, and the position correction values ​​can be given as vectors with direction and magnitude. Based on the position correction values ​​for each coordinate, the edges of each repeating pattern P1 are moved to form the final pattern P2. In some example embodiments, the positions of the edges can be moved substantially continuously. In the final pattern P2, the position correction value v1 for the first pattern can be different from the position correction value v2 for the second pattern. As described above, position correction can be performed continuously when moving the edges, thus improving accuracy. However, in some example embodiments, the first correction layout can be divided into multiple regions, and position correction can be performed continuously in each region as described above.

[0044] like Figure 5As shown, according to an example embodiment, a repeating pattern P1 is grouped into multiple groups G1 and G2 in regularly repeating units. Representative coordinates are determined for each of the multiple groups G1 and G2, and position correction values ​​v1' and v2' are assigned to these representative coordinates. The edges of the repeating pattern P1 can be moved based on the position correction values ​​v1' and v2' of the multiple groups G1 and G2. The multiple groups G1 and G2 can be set as repeating units with predetermined sizes, and do not necessarily have to be the smallest repeating unit. Furthermore, these groups can be selected differently considering the size, category, etc., of the pattern P1. The representative coordinates of each of the multiple groups G1 and G2 can be the center coordinates of each of the groups G1 and G2, but are not limited to this.

[0045] As described above, when using a method that moves the edges continuously or in groups, position correction can be performed continuously compared to some example embodiments where each polygon of pattern P1 is cut and moved, thus improving accuracy. For example, errors, such as violations that occur during verification of whether a mask can be patternizable, can be significantly reduced.

[0046] Figure 6 This is a flowchart illustrating a mask design method according to an example embodiment. Figure 6 Specifically, a mask design method considering some example embodiments is shown, in which the design layout includes non-repeating patterns in addition to repeating patterns.

[0047] Figure 7A and Figure 7B This is a diagram illustrating a mask design method according to an example embodiment. Figure 7A and Figure 7B The diagram schematically illustrates the regions of a semiconductor device that include repeating and non-repeating patterns.

[0048] First, refer to Figure 6 The mask design method may include: determining whether the design layout includes non-repeating patterns other than repeating patterns (S202). When the design layout does not include non-repeating patterns, refer to the above. Figure 2 The process involves performing optical proximity correction (S210) on the repeating pattern and position correction (S220) on the corrected repeating pattern. When the design layout includes non-repeating patterns, mask design can be performed according to two options, as described below.

[0049] First, according to the first option, optical proximity correction (S212) can be performed on the entire pattern, including repeating and non-repeating patterns, and position correction (S222) can be performed on the corrected entire pattern. Figure 7A and Figure 7BAs shown, a semiconductor device may include a memory cell region MCA containing a repeating pattern, a row decoder region ROW DEC containing a non-repeating pattern, and a peripheral circuit region PERI containing a non-repeating pattern. Figure 7A and Figure 7B In the diagram, the shadow indication for the area performs optical proximity correction, and the arrow indicates position correction. For example... Figure 7A As shown, according to the first option, optical proximity correction can first be performed on the entire pattern. Optical proximity correction can be performed on each of the repeating and non-repeating patterns, and then these repeating and non-repeating patterns can be merged. For the repeating pattern, refer to the above... Figure 3A The first optical proximity correction, which repeatedly applies optical proximity correction to the pattern, can be performed. For non-repeating patterns, each pattern is set as the target in a manner different from some example embodiments of repetitive patterns, and a second optical proximity correction can be performed, as referred to above. Figure 3B Next, positional correction can be performed on the entire pattern for which optical proximity correction has been performed.

[0050] Next, according to the second option, optical proximity correction can be performed on the repeating pattern (S214), position correction can be performed on the corrected repeating and non-repeating patterns (S224), and optical proximity correction can be performed on the non-repeating pattern (S226). Figure 7B As shown, firstly, optical proximity correction can be performed on the repeating pattern of the memory cell region MCA. For the repeating pattern, refer to the above... Figure 3A The process involves performing a first optical proximity correction on the pattern repeatedly. Then, position correction is performed on the corrected repeating pattern along with non-repeating patterns for which optical proximity correction has not been performed. Finally, optical proximity correction is performed on the non-repeating patterns for which position correction has been performed. For the non-repeating patterns, refer to the above... Figure 3B Each pattern is set as a target and a second optical proximity correction can be performed.

[0051] Subsequently, the above references were executed in the same manner. Figure 2 The description of providing the final layout to the exposure equipment (S230) and Figure 1 The subsequent operations are used to manufacture semiconductor devices.

[0052] Figure 8 This is a schematic plan view of a semiconductor device according to an example embodiment.

[0053] Figure 9 This is a schematic cross-sectional view illustrating a semiconductor device according to an example embodiment. Figure 9 It shows Figure 8 A cross-sectional view of the semiconductor device taken along line I-I'. For ease of illustration, in Figure 8 and Figure 9 Only the main components of the semiconductor device are shown.

[0054] Reference Figure 8 and Figure 9 The semiconductor device 100 may include a substrate 101, a first stacked structure GS1 and a second stacked structure GS2 disposed on the substrate 101 and including a gate electrode 130, a channel structure CH extending in a direction perpendicular to the upper surface of the substrate 101, and a separation region 170 extending through the first stacked structure GS1 and the second stacked structure GS2. The channel structure CH passes through the first stacked structure GS1 and the second stacked structure GS2 and has a channel layer 140 disposed therein. Furthermore, the semiconductor device 100 may also include a first insulating layer 125 on the uppermost portion of the first stacked structure GS1, a second insulating layer 127 on the second stacked structure GS2, and a contact plug 190 passing through the second insulating layer 127 and connected to the channel structure CH. In addition to the channel layer 140, each of the channel structures CH may include a gate dielectric layer 145 disposed between the channel layer 140 and the gate electrode 130, a channel insulating layer 150 disposed inside the channel layer 140, and a channel pad 155 in the upper end of the channel structure CH.

[0055] In the semiconductor device 100, a single memory cell string can be provided around each channel structure CH, and multiple memory cell strings can be arranged in rows and columns in the x and y directions.

[0056] The substrate 101 may contain a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

[0057] The channel structures CH can be spaced apart from each other in rows and columns on the substrate 101. The channel structures CH can be in the form of a first channel structure CH1 of a first stacked structure GS1 and a second channel structure CH2 of a second stacked structure GS2 connected to each other, and can have curved portions due to width differences in the connection regions. In the channel structures CH, the channel layer 140 can have an annular form surrounding the channel insulating layer 150 formed therein. However, according to some example embodiments, the channel layer can have a cylindrical shape, such as a cylinder or prism, without the channel insulating layer 150. According to example embodiments, the channel layer 140 can be directly connected to the substrate 101 in the lower portion, or can be electrically connected to the substrate 101 via a separate epitaxial layer disposed below. The channel layer 140 can contain a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material can be an undoped material or a material containing p-type or n-type impurities. The channel structures CH arranged linearly in the x-direction can be connected to different bit lines through an arrangement of upper wiring structures connected to the channel pads 155. A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. The gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially disposed from the channel layer 140. A channel pad 155 is disposed on the upper portion of the channel layer 140 and may be configured to be electrically connected to the channel layer 140 while covering the upper surface of the channel insulating layer 150. The channel pad 155 may include, for example, doped polysilicon. The channel structure CH may correspond to the repeating and / or non-repeating patterns discussed above.

[0058] Gate electrodes 130 may be spaced apart from each other along the side surface of each of the channel structures CH in a direction perpendicular to the substrate 101. Each gate electrode 130 may form the gate electrode of a ground select transistor, the gate electrode of a plurality of memory cells, and the gate electrode of a string select transistor. The gate electrodes 130 may form ground select lines, word lines, and string select lines as they extend, and the word lines may be connected together to adjacent strings of memory cells arranged in predetermined units in the x and y directions.

[0059] The separation region 170 may extend in one direction while passing through the first stack structure GS1 and the second stack structure GS2. The separation region 170 may consist only of insulating material, or it may include both insulating and conductive material.

[0060] In the semiconductor device 100, the above reference can be used. Figures 2 to 7B The mask design method described herein manufactures a mask to form a second channel structure CH2 disposed on a first channel structure CH1 in the lower portion and / or a contact plug 190 disposed on the second channel structure CH2. This will be referred to below. Figures 10A to 11B To describe in more detail.

[0061] Figures 10A to 10F This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment. Figures 10A to 10F It shows the relationship with Figure 9 The corresponding cross-section.

[0062] Figure 11A and Figure 11B This is a schematic diagram illustrating the deformation that occurs in the lower structure during the manufacture of a semiconductor device according to an example embodiment.

[0063] Reference Figure 10A A sacrificial layer 180 and an interlayer insulating layer 120 are alternately stacked on a substrate 101 to form a first stack structure GS1, a first channel via CHH1 is formed through the first stack structure GS1, and a channel sacrificial layer 185 is formed by filling the first channel via CHH1.

[0064] The sacrificial layer 180 may be a layer that will be replaced by the gate electrode 130 by a subsequent process. The sacrificial layer 180 may be formed of a material to be etched, which has etch selectivity relative to the interlayer insulating layer 120 and the first insulating layer 125. The first insulating layer 125 may be formed on the uppermost portion. However, according to an example embodiment, the first insulating layer 125 may be disposed in the lower portion of the second stacked structure GS2. The thicknesses of the interlayer insulating layer 120 and the sacrificial layer 180, as well as the number of films forming them, may vary from those shown in the figures. The channel sacrificial layer 185 may be formed of a material to be etched, which has etch selectivity relative to the sacrificial layer 180 and the interlayer insulating layer 120. For example, the channel sacrificial layer 185 may comprise silicon (Si).

[0065] Reference Figure 10B A sacrificial layer 180 and an interlayer insulating layer 120 are alternately stacked on the first stacked structure GS1 to form a second stacked structure GS2.

[0066] The second stack structure GS2 can be formed by stacking the sacrificial layer 180 and the interlayer insulating layer 120 on the first insulating layer 125 and the channel sacrificial layer 185 in a manner similar to the first stack structure GS1.

[0067] Reference Figure 10C A second channel hole CHH2 is formed through the second stacked structure GS2, and the channel sacrificial layer 185 in the first channel hole CHH1 can be removed from the second channel hole CHH2.

[0068] First, the second channel via CHH2 can be formed to align with the first channel via CHH1. Specifically, a photoresist layer on the second stacked structure GS2 is patterned to expose a portion of the second stacked structure GS2, and then the second stacked structure GS2 is etched to form the second channel via CHH2 in the exposed area. In this operation, for example, it can be achieved by using the above reference... Figures 2 to 7B The mask design method described describes a mask that is manufactured using a photolithography process to form a photoresist layer.

[0069] like Figure 11A and Figure 11B As shown, when the first stacked structure GS1 undergoes multiple operations, expansion or contraction, twisting, warping, etc., occur due to the processing temperature and the difference in the coefficients of thermal expansion between the different materials forming the first stacked structure GS1. Therefore, the first stacked structure GS1 can be deformed into a first stacked structure GS1'. In some example embodiments, it may be difficult to align the second channel hole CHH2 to correspond to the first channel hole CHH1 respectively during this operation. However, as described above, in the mask manufactured according to the example embodiment, not only optical proximity correction but also position correction is performed for the pattern used to form the second channel hole CHH2. Therefore, the second channel hole CHH2 can be aligned with the first channel hole CHH1 of the deformed stacked structure GS1' as described above with high precision.

[0070] Then, the channel sacrificial layer 185 exposed by the second channel hole CHH2 is removed to form a channel hole CHH in which the first channel hole CHH1 and the second channel hole CHH2 are connected.

[0071] Reference Figure 10D It can form a channel structure CH that includes a first channel structure CH1 and a second channel structure CH2.

[0072] The channel structure CH can be configured such that each of the first channel structure CH1 and the second channel structure CH2 is connected to each other to form a single structure. The channel structure CH can be formed by forming at least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pad 155 in the channel via CHH.

[0073] The gate dielectric layer 145 may have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this operation, the gate dielectric layer 145 may be formed wholly or partially, and a portion of the gate dielectric layer may be formed extending perpendicularly to the substrate 101 along the channel via CHH. A channel layer 140 may be formed on the gate dielectric layer 145 within the channel via CHH. An insulating layer 150 may be formed to fill the channel via CHH and may be an insulating material. The channel pad 155 may be formed of a conductive material (e.g., polysilicon).

[0074] Reference Figure 10E An opening OP is formed through the first stacked structure GS1 and the second stacked structure GS2, and the sacrificial layer 180 can be removed through the opening OP.

[0075] First, before forming the opening OP, a second insulating layer 127 can be further formed to protect the channel structure CH. The opening OP can be formed by forming a mask layer using a photolithography process and anisotropically etching the first stacked structure GS1 and the second stacked structure GS2. The opening OP can be provided in the form of a trench extending in the y-direction. The substrate 101 can be exposed in the lower part of the opening OP.

[0076] For example, wet etching can be used to selectively remove the sacrificial layer 180 relative to the interlayer insulating layer 120. Therefore, multiple side openings can be formed between the interlayer insulating layers 120, and a portion of the sidewalls of the channel structure CH can be exposed through these side openings.

[0077] Reference Figure 10F The gate electrode 130 is formed by filling the area where the sacrificial layer 180 has been removed with a conductive material, and the separation region 170 is formed by filling the opening OP.

[0078] The gate electrode 130 may comprise a metal, polysilicon, or a metal silicide material. The opening OP provides a transport path for the material used to form the gate electrode 130. After the gate electrode 130 is formed, the material deposited in the opening OP to form the gate electrode 130 can be removed by an additional process.

[0079] The separation region 170 can be formed by filling the opening OP with at least one of an insulating material and a conductive material.

[0080] Next, let's refer to... Figure 9 A contact hole is formed through the second insulating layer 127, and conductive material is embedded in the contact hole to form a contact plug 190.

[0081] Contact plugs 190 can be formed to align with the channel structure CH. Specifically, a photoresist layer on the second insulating layer 127 is patterned to expose a portion of the second insulating layer 127, and then the second insulating layer 127 is etched to form contact holes in the exposed areas. In this operation, for example, it can be achieved by using the above reference... Figures 2 to 7B The mask design method described describes a mask that is manufactured using a photolithography process to form a photoresist layer.

[0082] As described above, according to the exemplary embodiments of the present invention, position correction is performed after optical proximity correction is performed on the repeating pattern, thus providing a mask design method with improved accuracy and efficiency, as well as a method for manufacturing a semiconductor device using the mask design method.

[0083] Although described with reference to specific examples and accompanying drawings, those skilled in the art can make various modifications, additions, and substitutions to the exemplary embodiments based on the description. For example, the described techniques may be performed in a different order than the described methods, and / or components such as the described circuit layout may be connected or combined differently from the methods described above, or the results may be appropriately achieved by other components or equivalents.

[0084] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure as defined by the appended claims. Rather, the language used in the specification is descriptive rather than restrictive, and it should be understood that various changes can be made without departing from the spirit and scope of the inventive concept of this disclosure. Furthermore, features of various embodiments can be combined to form other embodiments of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: Forming a lower structure including the first repeating pattern; as well as Forming the upper structure includes forming a second repeating pattern to correspond to each of the first repeating patterns on the lower structure. The formation of the second repeating pattern includes: Prepare the design layout for the second repeating pattern; A first corrected layout, including a corrected second repeating pattern, is formed by performing optical proximity correction on the design layout. The second corrected layout is formed by performing position correction on the first corrected layout to move the position of the corrected second repeating pattern to correspond to the changed position of the first repeating pattern according to the physical deformation of the lower structure. The mask is fabricated using the second correction layout; and The mask is used to pattern the photoresist layer.

2. The manufacturing method according to claim 1, wherein, The formation of the second correction layout includes: Assign position correction values ​​to the coordinates of the first corrected layout; and The corresponding edge of the corrected second repeating pattern is moved according to the position correction value.

3. The manufacturing method according to claim 1, wherein, The formation of the second correction layout includes: Multiple groups are defined by grouping the corrected second repeating pattern in repeating units; Determine representative coordinates for each of the plurality of groups; Assign position correction values ​​to the representative coordinates of each of the plurality of groups; and For each of the plurality of groups, the edges of each of the corrected second repeating patterns are moved according to the position correction value.

4. The manufacturing method according to claim 3, wherein, The representative coordinates are the center coordinates of each of the plurality of groups.

5. The manufacturing method according to claim 1, wherein, Forming the first corrected layout includes: equally correcting at least a portion of the second repeating pattern that forms the design layout.

6. The manufacturing method according to claim 5, wherein, Equally correcting at least a portion of the second repeating pattern forming the design layout includes: correcting a portion of the second repeating pattern, excluding the second repeating pattern in the edge region, to the same shape through the optical proximity correction.

7. The manufacturing method according to claim 1, wherein, Forming the second corrected layout includes determining the altered position of the first repeating pattern by taking into account the process temperature of the process forming the lower structure and the coefficient of thermal expansion of the material forming the lower structure.

8. The manufacturing method according to claim 7, wherein, The expansion, contraction, or warping of the lower structure changes the initial position of the first repeating pattern to the changed position of the first repeating pattern.

9. The manufacturing method according to claim 1, wherein, The substructure includes: Alternatingly stacking a first interlayer insulating layer and a first sacrificial layer on a substrate; and A first channel hole is formed through the first interlayer insulating layer and the first sacrificial layer and extends vertically on the substrate, the first repeating pattern being the first channel hole.

10. The manufacturing method according to claim 9, wherein, The superstructure includes: A second interlayer insulating layer and a second sacrificial layer are alternately stacked on the lower structure; and A second channel hole is formed, which passes through the second interlayer insulation layer and the second sacrificial layer and extends vertically to connect to the first channel hole, and the second repeating pattern is the second channel hole.

11. A method for manufacturing a semiconductor device, comprising: Prepare a design layout that includes repeating and non-repeating patterns; A first corrected layout comprising the corrected repeating pattern is formed by performing a first optical proximity correction on the repeating pattern. A second corrected layout is formed by performing a first position correction on the first corrected layout to move the position of the corrected repeating pattern to correspond to the position change of the first repeating pattern below the repeating pattern; A second optical proximity correction is performed on the non-repeating pattern using a method different from the first optical proximity correction; and A second position correction is performed on the non-repeating pattern to move the position of the non-repeating pattern.

12. The manufacturing method according to claim 11, wherein, After performing the second optical proximity correction on the non-repeating pattern, the second position correction is performed on the non-repeating pattern.

13. The manufacturing method according to claim 12, wherein, The first position correction is performed together with the second position correction.

14. The manufacturing method according to claim 11, wherein, After performing the second position correction on the non-repeating pattern, the second optical proximity correction is performed on the non-repeating pattern.

15. The manufacturing method according to claim 14, wherein, The first position correction is performed together with the second position correction.

16. The manufacturing method according to claim 11, wherein The repeating pattern forms a memory cell region including memory cells, and The non-repeating pattern forms a peripheral circuit region, which includes circuitry electrically connected to the memory cell.

17. A mask design method, comprising: Prepare a design layout, the design layout including a second repeating pattern of an upper structure formed to match a first repeating pattern of a lower structure; A first corrected layout, including a corrected second repeating pattern, is formed by performing optical proximity correction on the design layout. The second corrected layout is formed by performing position correction on the first corrected layout to move the position of the corrected second repeating pattern to correspond to the position change of the first repeating pattern; as well as The second correction layout is provided to the exposure equipment.

18. The mask design method according to claim 17, wherein, The formation of the second correction layout includes: The corresponding edges of the corrected second repeating pattern are moved according to the position correction value.

19. The mask design method according to claim 17, wherein, Forming the first correction layout includes: equally correcting more than half of the second repeating pattern.

20. The mask design method according to claim 17, wherein, The shape of each of the corrected second repeating patterns in the second corrected layout is the same as the shape of each of the corrected second repeating patterns in the first corrected layout.

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