Non-volatile storage device for mitigating interference and method of operating the same

Abstract

The present application discloses a non-volatile memory device for mitigating interference and an operation method thereof. The non-volatile memory device may include a write circuit and a sense amplifier. The write circuit may perform a preselection operation on a selected memory cell. When a snapback occurs in the selected memory cell, the write circuit may selectively perform a reset write operation and a set write operation on the selected memory cell according to the write data. When a snapback does not occur in the selected memory cell, the write circuit may not apply a voltage and a current to the selected memory cell. The sense amplifier may sense whether a snapback occurs in the selected memory cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0085653 filed on July 16, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments generally relate to an integrated circuit technology, and more particularly, to a nonvolatile memory device and a system utilizing the same. Background Art

[0004] An electronic device may include many electronic components. For example, a computer system may include a large number of electronic components composed of semiconductors. A computer system may include a storage device. Since DRAM (dynamic random access memory) can store and output data at a high speed and constant speed and perform random access, DRAM is widely used as a common storage device. However, since DRAM includes storage cells each composed of capacitors, DRAM has a volatile characteristic, that is, the data stored therein is lost when the power is interrupted. In order to eliminate this disadvantage of DRAM, a flash memory has been developed. The flash memory includes storage cells each composed of floating gates, so even if the power is interrupted, the flash memory has a non-volatile characteristic of retaining the data stored therein. However, the flash memory stores and outputs data at a lower speed than DRAM, so it is difficult to perform random access.

[0005] Recently, a next generation memory device having a high operating speed and a non-volatile characteristic has been developed. Examples of the next generation memory device may include: phase change RAM, magnetic RAM, resistive RAM, and ferroelectric RAM. The next generation memory device may operate at a high speed with a non-volatile characteristic. Specifically, a PRAM may include a memory cell formed of a chalcogenide, and may store data by changing the resistance value of the memory cell. Summary of the invention

[0006] In one embodiment, a nonvolatile memory device may include a write circuit and a sense amplifier. The write circuit may be configured to apply a preselected voltage to a selected memory cell based on a write signal; when snapback occurs in the selected memory cell, apply one of a reset write voltage and a set write voltage to the selected memory cell based on write data; and when snapback does not occur in the selected memory cell, interrupt the voltage and current applied to the selected memory cell. The sense amplifier may be configured to sense whether snapback occurs in the selected memory cell.

[0007] In one embodiment, a method for operating a nonvolatile memory device may include: applying a preselected voltage to a selected memory cell. The preselected voltage may have a voltage corresponding to a maximum voltage of a reset distribution. The operating method may also include sensing whether snapback occurs in the selected memory cell. The operating method may also include: selectively performing a reset write operation and a set write operation on the selected memory cell based on write data and whether snapback occurs in the selected memory cell; and interrupting the preselected voltage applied to the selected memory cell.

[0008] In one embodiment, a nonvolatile memory device may include: a write control circuit, a sense amplifier, and a write driver. The write control circuit may be configured to generate a preselection signal based on a write signal; generate one of a reset write signal and a set write signal when a sense signal is enabled; and disable the preselection signal and do not generate the reset write signal and the set write signal when the sense signal is disabled. The sense amplifier may be configured to sense whether a snapback occurs in a memory cell and generate the sense signal. The write driver may be configured to perform a preselection operation on the selected memory cell based on the preselection signal; perform a reset write operation on the selected memory cell based on the reset write signal, and perform a set write operation on the selected memory cell based on the set write signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a configuration of a nonvolatile memory device according to an embodiment.

[0010] Figure 2 It's a picture. Figure 1 A diagram of the configuration of the write control circuit shown in .

[0011] Figure 3 It's a picture. Figure 2 0 is a timing diagram of the operation of the write control circuit shown in .

[0012] Figure 4 It's a picture. Figure 1 Schematic diagram of the configuration of the first global control circuit shown in .

[0013] Figure 5 It's a picture. Figure 1 Schematic diagram of the configuration of the second global control circuit shown in .

[0014] Figure 6 is a graph illustrating threshold voltage distribution depending on the resistance state of a memory cell.

[0015] Figure 7is a flowchart illustrating an operating method of a nonvolatile memory device according to one embodiment.

[0016] Fig. 8A , Figure 8B and Figure 8C is a timing diagram illustrating the operation of the nonvolatile memory device according to the embodiment.

[0017] Fig. 9 is a block diagram illustrating an electronic device including a semiconductor memory device according to an embodiment.

[0018] Fig.10 is a block diagram illustrating a data storage apparatus including a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0019] Various embodiments of the present disclosure are directed to a nonvolatile memory device and an operating method thereof, which can perform a preselection operation during a write operation, perform a write operation on a memory cell that has snapped back according to write data, and prevent a voltage and / or current from being applied to a memory cell that has not snapped back.

[0020] The nonvolatile memory device and the method of operating the same according to the present embodiment can mitigate disturbances that may occur in memory cells during a write operation of the nonvolatile memory device, thereby improving the reliability of the nonvolatile memory device.

[0021] Figure 1 is a diagram illustrating a configuration of a nonvolatile memory device 100 according to an embodiment. Figure 1 In the present invention, the nonvolatile memory device 100 may include a memory array 110. The memory array 110 may include a plurality of bit lines BL arranged in a column direction and a plurality of word lines WL arranged in a row direction. A plurality of memory cells MC may be coupled to respective intersections between the plurality of bit lines BL and the plurality of word lines WL. Each memory cell MC may be coupled between the bit line BL and the word line WL corresponding thereto. The memory cell MC may be configured as a variable resistance element and, for example, include a phase change material. The nonvolatile memory device 100 may be a resistive memory device or a phase change memory device. The memory array 110 may be configured as a cross point array.

[0022] The nonvolatile memory device 100 may include a column selection circuit 120 and a row selection circuit 130. The column selection circuit 120 may be coupled between a first global electrode GBL and a plurality of bit lines BL. The column selection circuit 120 may couple a bit line selected among a plurality of bit lines BL to the first global electrode GBL. The column selection circuit 120 may select a specific bit line among a plurality of bit lines BL based on a column address signal CADD, and couple the selected bit line to the first global electrode GBL. The row selection circuit 130 may be coupled between a second global electrode GWL and a plurality of word lines WL. The row selection circuit 130 may couple a word line selected among a plurality of word lines WL to the second global electrode GWL. The row selection circuit 130 may select a specific word line among a plurality of word lines WL based on a row address signal RADD, and couple the selected word line to the second global electrode GWL. Since a specific bit line and a specific word line are selected, a specific memory cell may be selected.

[0023] The nonvolatile memory device 100 may perform a write operation on a selected memory cell. When performing a write operation, the selected memory cell may be set to a low or high resistance state. When the memory cell is set to a low resistance state, the memory cell may become a set cell in which cell data is stored. When the memory cell is set to a high resistance state, the memory cell may become a reset cell in which reset data is stored. When performing a write operation, the nonvolatile memory device 100 may first perform a preselection operation. According to the result of the preselection operation, the nonvolatile memory device 100 may selectively perform a write operation on the selected memory cell. The preselection operation may indicate an operation of causing a selected memory cell to snap back and / or turn on the selected memory cell. The nonvolatile memory device 100 may perform a preselection operation to cause a selected memory cell to snap back and / or turn on the selected memory cell, regardless of the resistance state of the selected memory cell. Therefore, when the selected memory cell is in a low resistance state or a high resistance state, the selected memory cell may snap back through the preselection operation. When the selected memory cell is a defective cell, the selected memory cell may not snap back through the pre-selection operation. The defective cell may be an open cell having a higher resistance than in a standard high resistance state. Because the open cell is usually in an over-reset state, the open cell cannot be set to a low resistance state or a high resistance state through a write operation. The non-volatile memory device 100 can prevent voltage and current from being applied to the defective cell. When the selected memory cell does not snap back, the non-volatile memory device 100 can interrupt the voltage and current applied to the selected memory cell. Therefore, the non-volatile memory device 100 can reduce unnecessary current consumed by the write operation and reduce interference with memory cells adjacent to the selected memory cell.

[0024] Figure 1A selected memory cell T is illustrated, and memory cells adjacent to the selected memory cell T may be half-selected memory cells A and B. The half-selected memory cell A may be a memory cell coupled to the same bit line as the selected memory cell T and to a different word line than the selected memory cell T. The half-selected memory cell B may be a memory cell coupled to a different bit line than the selected memory cell T and to the same word line as the selected memory cell T. When an inhibition voltage is continuously applied to the half-selected memory cells A and B, interference may be generated in causing snapback of the half-selected memory cells A and B and / or turning on the half-selected memory cells A and B. Specifically, when the half-selected memory cells A and B have a threshold voltage lower than the threshold voltage of a standard memory cell, the possibility of interference may further increase. In the prior art, when the selected memory cell T is a defective cell, the operation of determining whether the selected memory cell T is a defective cell is not performed, and during the write operation of the nonvolatile memory device 100, the voltage and current for the preselection operation are continuously applied to the selected memory cell T. Because the voltage and current for the preselection operation may have a voltage level corresponding to the inhibition voltage, unnecessary current consumption may continuously occur, and the possibility of interference of the half-selected memory cells A and B is inevitably increased. The nonvolatile memory device 100 according to the present embodiment can determine whether the selected memory cell T is a defective cell, and when the selected memory cell T is a defective cell, the voltage and current applied to the selected memory cell T are interrupted, thereby reducing the power consumed by the write operation and alleviating the interference of the adjacent memory cells.

[0025] exist Figure 1In the present invention, the nonvolatile memory device 100 may include write circuits 140 and 150 and a sense amplifier (SA) 160. The write circuits 140 and 150 may perform one of a preselection operation, a reset write operation, and a set write operation on a selected memory cell during a write operation of the nonvolatile memory device 100. The write circuits 140 and 150 may apply a preselection voltage to the selected memory cell based on a write signal WT so as to perform a preselection operation on the selected memory cell. The write signal WT enabled when the nonvolatile memory device 100 performs a write operation may be generated based on a command signal. The write circuits 140 and 150 may selectively perform a reset write operation and a set write operation based on whether the selected memory cell snaps back via the preselection operation. When snapback occurs in the selected memory cell, the write circuits 140 and 150 may perform a reset write operation and a set write operation based on the write data WDT. When snapback occurs in the selected storage cell and the write data WDT is reset data, the write circuits 140 and 150 may apply a reset write voltage to the selected storage cell so as to perform a reset write operation on the selected storage cell. When snapback occurs in the selected storage cell and the write data WDT is set data, the write circuits 140 and 150 may apply a set write voltage to the selected storage cell so as to perform a set write operation on the selected storage cell. When snapback does not occur in the selected storage cell, the write circuits 140 and 150 may not apply voltage and current to the selected storage cell. The write circuits 140 and 150 may interrupt the voltage and current applied to the selected storage cell until the write operation is terminated after the preselection operation is completed. The write circuits 140 and 150 may determine whether snapback has occurred in the selected storage cell based on the sensing signal DOUT.

[0026] SA 160 may sense whether a snapback occurs in a selected memory cell. SA 160 may generate a sensing signal DOUT by sensing whether a snapback occurs in a selected memory cell. When a snapback occurs in a selected memory cell, SA 160 may enable the sensing signal DOUT. When a snapback does not occur in a selected memory cell, SA 160 may keep the sensing signal DOUT in a disabled state. SA 160 may be coupled to a second global electrode GWL and generate a sensing signal DOUT by sensing a change in a voltage level of the second global electrode GWL. When a snapback occurs in a selected memory cell, the amount of current flowing through the selected memory cell may increase rapidly. Therefore, the voltage level of the first global electrode GBL may drop, and the voltage level of the second global electrode GWL may increase. SA 160 may generate a sensing signal DOUT by sensing a rise in the voltage level of the second global electrode GWL or an amount of current flowing through the second global electrode GWL. In one embodiment, SA 160 may be coupled to a first global electrode GBL and generate a sensing signal DOUT by sensing a change in the voltage level of the first global electrode GBL. The SA 160 may be modified to generate the sensing signal DOUT by sensing a drop in the voltage level of the first global electrode GBL or an amount of current flowing through the first global electrode GBL.

[0027] The write circuits 140 and 150 may include a write control circuit 140 and a write driver 150. The write control circuit 140 may generate a control signal for controlling the write driver 150 to perform various operations. The write control circuit 140 may generate a preselection signal PRESEL, a reset write signal RSTWT, and a set write signal SETWT during a write operation of the nonvolatile memory device 100. When performing a write operation, the write control circuit 140 may first generate a preselection signal PRESEL. The write control circuit 140 may generate a preselection signal PRESEL to perform a preselection operation. The write control circuit 140 may selectively perform a write operation according to whether a selected memory cell undergoes snapback through a preselection operation. When snapback occurs in the selected memory cell, the write control circuit 140 may generate one of a reset write signal RSTWT and a set write signal SETWT. When snapback does not occur in the selected memory cell, the write control circuit 140 may disable the preselection signal PRESEL and does not generate a reset write signal RSTWT and a set write signal SETWT.

[0028] The write control circuit 140 may generate a preselection signal PRESEL based on the write signal WT. When a snapback occurs in the selected memory cell, the write control circuit 140 may generate one of a reset write signal RSTWT and a set write signal SETWT based on the write data WDT. An operation of determining whether a snapback occurs in the selected memory cell may be performed based on the sense signal DOUT.

[0029] The write control circuit 140 may enable one of the reset write signal RSTWT and the set write signal SETWT based on the sense signal DOUT and the write data WDT. When the sense signal DOUT is enabled and the write data WDT is reset data, the write control circuit 140 may enable the reset write signal RSTWT. When the sense signal DOUT is enabled and the write data WDT is set data, the write control circuit 140 may enable the set write signal SETWT. When the sense signal DOUT is disabled, the write control circuit 140 may keep both the reset write signal RSTWT and the set write signal SETWT in a disabled state regardless of the write data WDT.

[0030] The write driver 150 may receive a control signal from the write control circuit 140, and may perform a preselection operation, a reset write operation, and a set write operation on the selected memory cell. The write driver 150 may perform a preselection operation on the selected memory cell based on the preselection signal PRESEL. The write driver 150 may perform a preselection operation on the selected memory cell by applying a preselection voltage and a first current to the selected memory cell based on the preselection signal PRESEL. The write driver 150 may perform a reset write operation on the selected memory cell based on the reset write signal RSTWT. The write driver 150 may perform a reset write operation on the selected memory cell by applying a reset write voltage and a second current to the selected memory cell based on the reset write signal PRTWT. The write driver 150 may perform a set write operation on the selected memory cell based on the set write signal SETWT. The write driver 150 may perform a set write operation on the selected memory cell by applying a set write voltage and a third current to the selected memory cell based on the set write signal SETWT. The preselect voltage may have a voltage level lower than the reset write voltage and higher than the set write voltage. An amount of the third current may be greater than an amount of the first current and less than an amount of the second current.

[0031] The write driver 150 may include a first global control circuit 151 and a second global control circuit 152. The first global control circuit 151 may be coupled to the first global electrode GBL and receive a first high power supply voltage VH1 and a second high power supply voltage VH2. The first high power supply voltage VH1 may have a voltage level higher than the second high power supply voltage VH2. The first global control circuit 151 may selectively apply a first high voltage, a second high voltage, and a third high voltage to the first global electrode GBL based on a preselection signal PRESEL, a reset write signal RSTWT, and a set write signal SETWT. The first global control circuit 151 may apply a first high voltage to the first global electrode GBL based on the preselection signal PRESEL. The first global control circuit 151 may apply a second high voltage to the first global electrode GBL based on the reset write signal RSTWT. The first global control circuit 151 may apply a third high voltage to the first global electrode GBL based on the set write signal SETWT. The first high voltage may have a voltage level higher than the third high voltage and lower than the second high voltage. The first high voltage may be generated by clamping the first high power supply voltage VH1, and the second high voltage may have substantially the same voltage level as the first high power supply voltage VH1. The third high voltage may have substantially the same voltage level as the second high power supply voltage VH2.

[0032] The second global control circuit 152 may be coupled to the second global electrode GWL and receive a first low power supply voltage VL1 and a second low power supply voltage VL2. The first low power supply voltage VL1 may have a voltage level higher than the second low power supply voltage VL2 and lower than the second high power supply voltage VH2. The second global control circuit 152 may selectively apply the first low voltage, the second low voltage, and the third low voltage to the second global electrode GWL based on the preselection signal PRESEL, the reset write signal RSTWT, and the set write signal SETWT. The second global control circuit 152 may apply the first low voltage to the second global electrode GWL based on the preselection signal PRESEL. The second global control circuit 152 may apply the second low voltage to the second global electrode GWL based on the reset write signal RSTWT. The second global control circuit 152 may apply the third low voltage to the second global electrode GWL based on the set write signal SETWT. The first low voltage may have a voltage level higher than the second low voltage and the third low voltage. The second low voltage and the third low voltage may have substantially the same voltage level. In one embodiment, the second low voltage may have a voltage level lower than the third low voltage. The second global control circuit 152 may control the first current to the third current to selectively flow through the second global electrode GWL based on the preselection signal PRESEL, the reset write signal RSTWT, and the set write signal SETWT. The second global control circuit 152 may control the first current to flow through the second global electrode GWL based on the preselection signal PRESEL. The second global control circuit 152 may control the second current to flow through the second global electrode GWL based on the reset write signal RSTWT. The second global control circuit 152 may control the third current to flow through the second global electrode GWL based on the set write signal SETWT. The first current may be a parasitic current corresponding to the minimum current, and when a snapback occurs in the selected memory cell, the minimum current may maintain the on-state of the selected memory cell. The second current may be a reset write current for programming the resistance state of the selected memory cell to a high resistance state. The third current may be a set write current for programming the resistance state of the selected memory cell to a low resistance state.

[0033] refer to Figure 2, the write control circuit 140 may include: a write pulse generator 210, a reset write signal generator 220, a set write signal generator 230, and a preselection signal generator 240. The write pulse generator 210 may receive a write signal WT. The write pulse generator 210 may generate a reset pulse signal RSTP and a set pulse signal SETP based on the write signal WT. The reset pulse signal RSTP may have a pulse width that defines the time for performing a reset write operation, and the set pulse signal SETP may have a pulse width that defines the time for performing a set write operation. The set pulse signal SETP may have a pulse width longer than the reset pulse signal RSTP. When the time for performing a preselection operation has passed after the write signal WT is enabled, the write pulse generator 210 may generate a reset pulse signal RSTP and a set pulse signal SETP. The time for performing a preselection operation may include at least the time required until a preselection voltage and a first current are applied to a selected memory cell to cause a snapback to the selected memory cell, and the SA 160 generates a sensing signal DOUT.

[0034] The reset write signal generator 220 may receive a reset pulse signal RSTP, write data WDT, and a sense signal DOUT, and may generate a reset write signal RSTWT. When the write data WDT is reset data, the write data WDT may have a logic low level. When the write data WDT is set data, the write data WDT may have a logic high level. When the write data WDT is at a logic low level and the sense signal DOUT is enabled as a logic high level, the reset write signal generator 220 may output a reset pulse signal RSTP as a reset write signal RSTWT, and enable the reset write signal RSTWT. The set write signal generator 230 may receive a set pulse signal SETP, write data WDT, and a sense signal DOUT, and generate a set write signal SETWT. When the write data WDT is at a logic high level and the sense signal DOUT is enabled as a logic high level, the set write signal generator 230 may output a set pulse signal SETP as a set write signal SETWT, and enable the set write signal SETWT. The preselection signal generator 240 can receive the write signal WT and the set pulse signal SETP, and generate the preselection signal PRESEL. The preselection signal generator 240 can enable the preselection signal PRESEL based on the write signal WT. When the set pulse signal SETP is enabled, the preselection signal generator 240 can disable the preselection signal PRESEL. Because the set pulse signal SETP is enabled when the time of performing the preselection operation passes after the write signal WT is enabled, the set pulse signal SETP can be used to determine the time point when the preselection signal PRESEL is disabled. In one embodiment, the preselection signal generator 240 can disable the preselection signal PRESEL based on the reset pulse signal RSTP instead of the set pulse signal SETP. The preselection signal generator 240 can be changed to generate the preselection signal PRESEL based on one or more of the write signal WT, the set pulse signal SETP and the reset pulse signal RSTP.

[0035] The reset write signal generator 220 may include: a first inverter 221, a first NAND gate 222, and a second inverter 223. The first inverter 221 may invert the write data WDT and output the inverted signal. The first NAND gate 222 may receive the reset pulse signal RSTP, the output of the first inverter 221, and the sensing signal. The second inverter 223 may invert the output of the first NAND gate 222 and output the inverted signal as the reset write signal RSTWT. The set write signal generator 230 may include a second NAND gate 231 and a third inverter 232. The second NAND gate 231 may receive the set write pulse SETP, the write data WDT, and the sensing signal DOUT. The third inverter 232 may invert the output of the second NAND gate 231 and output the inverted signal as the set write signal SETWT. The preselect signal generator 240 may include: a fourth inverter 241, a third NAND gate 242, and a fifth inverter 243. The fourth inverter 241 may invert the set write pulse SETUP. The third NAND gate 242 may receive the output of the fourth inverter 241 and the write signal WT. The fifth inverter 243 may invert the output of the third NAND gate 242 and output the inverted signal as the preselection signal PRESEL.

[0036] Figure 3 It's a picture. Figure 2 . When the write operation of the nonvolatile memory device 100 is performed, the write signal WT may be enabled. When the write signal WT is enabled, the preselection signal generator 240 may enable the preselection signal PRESEL. When the preselection operation is performed based on the preselection signal PRESEL so that the selected memory cell undergoes snapback, the sense signal DOUT may be enabled. After the time for performing the preselection operation has passed, the write pulse generator 210 may enable the reset pulse signal RSTP and the set pulse signal SETP. When the set pulse signal SETP is enabled, the preselection signal generator 240 may disable the preselection signal PRESEL. When the write data WDT is reset data, the reset write signal generator 220 may output the reset pulse signal RSTP as the reset write signal RSTWT. When the write data WDT is set data, the set write signal generator 230 may output the set pulse signal SETP as the set write signal SETWT.

[0037] Figure 4 It's a picture. Figure 1 FIG. 1 is a diagram showing a configuration of the first global control circuit 151 shown in FIG. Figure 4, the first global control circuit 151 may include: a first high voltage generator 410, a second high voltage generator 420, and a third high voltage generator 430. The first high voltage generator 410 may receive a first high power supply voltage VH1 and a preselection signal PRESEL. The first high voltage generator 410 may generate a first high voltage based on the preselection signal PRESEL, and provide the first high voltage to the first global electrode GBL. The first high voltage generator 410 may also receive a clamping signal VCLP. The clamping signal VCLP may be a bias voltage having a constant voltage level. The first high voltage generator 410 may reduce the voltage level of the first high power supply voltage VH1 based on the clamping signal VCLP, and provide the reduced voltage as the first high voltage. The first high voltage generator 410 may include a first transistor 411 and a second transistor 412. The first transistor 411 may be a P-channel MOS transistor, and the second transistor 412 may be an N-channel MOS transistor. The first transistor 411 may have a gate configured to receive a complementary signal PRESELB of a preselection signal and a source configured to receive a first high power supply voltage VH1. The second transistor 412 may have a gate configured to receive a clamping signal VCLP, a drain coupled to the drain of the first transistor 411, and a source coupled to the first global electrode GBL. When the preselection signal PRESEL is enabled, the first transistor 411 may provide the first high power supply voltage VH1 to the second transistor 412, and the second transistor 412 may generate a first high voltage by lowering the voltage provided from the first transistor 411 by a threshold voltage of the second transistor 412, and provide the first high voltage to the first global electrode GBL.

[0038] The second high voltage generator 420 may receive the first high power supply voltage VH1 and the reset write signal RSTWT. The second high voltage generator 420 may generate a second high voltage from the first high power supply voltage VH1 based on the reset write signal RSTWT, and provide the second high voltage to the first global electrode GBL. The second high voltage generator 420 may include a third transistor 421. The third transistor 421 may be a P-channel MOS transistor. The third transistor 421 may have a gate configured to receive a complementary signal RSTWTB of the reset write signal, a source configured to receive the first high power supply voltage VH1, and a drain coupled to the first global electrode GBL. When the reset write signal RSTWT is enabled, the third transistor 421 may provide the first high power supply voltage VH1 as the second high voltage to the first global electrode GBL.

[0039] The third high voltage generator 430 may receive the second high power supply voltage VH2 and the set write signal SETWT. The third high voltage generator 430 may generate a third high voltage from the second high power supply voltage VH2 based on the set write signal SETWT, and provide the third high voltage to the first global electrode GBL. The third high voltage generator 430 may include a fourth transistor 431. The fourth transistor 431 may be a P-channel MOS transistor. The fourth transistor 431 may have a gate configured to receive a complementary signal SETWTB of the set write signal, a source configured to receive the second high power supply voltage VH2, and a drain coupled to the first global electrode GBL. When the set write signal SETWT is enabled, the fourth transistor 431 may provide the second high power supply voltage VH2 as the third high voltage to the first global electrode GBL.

[0040] Figure 5 It's a picture. Figure 1 FIG. 1 is a diagram of the configuration of the second global control circuit 152 shown in FIG. Figure 5 , the second global control circuit 152 may include: a first low voltage generator 510, a second low voltage generator 520, and a third low voltage generator 530. The first low voltage generator 510 may receive a preselection signal PRESEL and a first low power supply voltage VL1. The first low voltage generator 510 may provide the first low power supply voltage VL1 to the second global electrode GWL based on the preselection signal PRESEL, and control the first current to flow through the second global electrode GWL. The first low voltage generator 510 may include a fifth transistor 511 and a first current source 512. The fifth transistor 511 may be an N-channel MOS transistor. The fifth transistor 511 may have a gate configured to receive the preselection signal PRESEL and a drain coupled to the second global electrode GWL. The first current source 512 may be a constant current source configured to supply a first current. One terminal of the first current source 512 may be coupled to the source of the fifth transistor 511, and the other terminal of the first current source 512 may be configured to receive the first low power supply voltage VL1. When the preselect signal PRESEL is enabled, the fifth transistor 511 may couple the first current source 512 to the second global electrode GWL, provide the first low power voltage VL1 as the first low voltage to the second global electrode GWL, and control the first current to flow through the second global electrode GWL.

[0041] The second low voltage generator 520 may provide a second low voltage to the second global electrode GWL based on the reset write signal RSTWT, and control the second current to flow through the second global electrode GWL. The second low voltage generator 520 may include a sixth transistor 521 and a second current source 522. The sixth transistor 521 may be an N-channel MOS transistor. The sixth transistor 521 may have a gate configured to receive the reset write signal RSTWT and a drain coupled to the second global electrode GWL. The second current source 522 may be a constant current source configured to supply a second current. One terminal of the second current source 522 may be coupled to the source of the sixth transistor 521, and the other terminal of the second current source 522 may be configured to receive the second low supply voltage VL2. When the reset write signal RSTWT is enabled, the sixth transistor 521 may couple the second current source 522 to the second global electrode GWL, provide the second low supply voltage VL2 as the second low voltage to the second global electrode GWL, and control the second current to flow through the second global electrode GWL.

[0042] The third low voltage generator 530 may provide a third low voltage to the second global electrode GWL based on the set write signal SETWT, and control the third current to flow through the second global electrode GWL. The third low voltage generator 530 may include a seventh transistor 531 and a third current source 532. The seventh transistor 531 may be an N-channel MOS transistor. The seventh transistor 531 may have a gate configured to receive the set write signal SETWT and a drain coupled to the second global electrode GWL. The third current source 532 may be a constant current source configured to supply a third current. One terminal of the third current source 532 may be coupled to the source of the seventh transistor 531, and the other terminal of the third current source 532 may be configured to receive the second low supply voltage VL2. When the set write signal SETWT is enabled, the seventh transistor 531 may couple the third current source 532 to the second global electrode GWL, provide the second low supply voltage VL2 as the third low voltage to the second global electrode GWL, and control the third current to flow through the second global electrode GWL.

[0043] Figure 6 is a graph illustrating the threshold voltage distribution of a memory cell. Figure 6, the horizontal axis may indicate a voltage level. A memory cell programmed in a low resistance state may be a set cell SET and have a relatively low threshold voltage. A memory cell programmed in a high resistance state may be a reset cell RESET and have a relatively high threshold voltage. The set cell SET may have a threshold voltage between a set distribution minimum voltage VSETmin and a set distribution maximum voltage VSETmax. The reset cell RESET may have a threshold voltage between a reset distribution minimum voltage VRSTmin and a reset distribution maximum voltage VRSTmax. The threshold voltage VOP of an over-reset and / or open cell may have a voltage level higher than the reset distribution maximum voltage VRSTmax. The read voltage VRD may have a voltage level between a set distribution maximum voltage VSETmax and a reset distribution minimum voltage VRSTmin. The read voltage VRD may correspond to a demarcation voltage capable of distinguishing between a set cell SET and a reset cell RESET. The read voltage VRD may be used for a read operation of a non-volatile memory device, and may be used for a write operation of a non-volatile memory device that performs a pre-read operation. The pre-read operation may indicate an operation of determining the resistance state of a memory cell before writing one of the set data and the reset data to the memory cell. The pre-select voltage VPRE may have a voltage level equal to or higher than the reset distribution maximum voltage VRSTmax so as to cause snapback of both the memory cell in the low resistance state and the memory cell in the high resistance state.

[0044] Figure 7 is a flowchart illustrating an operating method of a nonvolatile memory device according to the present embodiment, and Fig. 8A , Figure 8B and Figure 8C is a timing diagram illustrating the operation of a nonvolatile memory device according to an embodiment. Figures 1 to 8C, the operation of the nonvolatile memory device 100 according to the present embodiment is described as follows. When performing a write operation of the nonvolatile memory device 100, the nonvolatile memory device 100 may select a specific memory cell based on a column address signal and a row address signal. When the write operation is started, the write signal WT may be enabled, and the write control circuit 140 may enable the preselection signal PRESEL. At S71, the nonvolatile memory device 100 may perform a preselection operation on the selected memory cell. The write circuit 140 may perform a preselection operation on the selected memory cell based on the preselection signal PRESEL. At S72, the nonvolatile memory device 100 may determine whether a snapback occurs in the selected memory cell. When a snapback occurs in the selected memory cell via the preselection operation, the SA 160 may enable the sensing signal DOUT, and the processing steps may proceed from S72 to S73. When a snapback does not occur in the selected memory cell, the SA 160 may maintain the sensing signal DOUT in a disabled state, and the processing steps may proceed from S72 to S76. The write circuits 140 and 150 can selectively perform a reset write operation and a set write operation on the selected storage cell based on the write data WDT and whether the selected storage cell snaps back. When the selected storage cell snaps back, one of the reset write operation and the set write operation can be performed on the selected storage cell. At S73, the non-volatile storage device 100 can determine whether the write data WDT is reset data or set data. When the write data WDT is reset data, the processing steps can be performed from S73 to S74. When the write data WDT is set data, the processing steps can be performed from S73 to S75. At S74, the write driver 150 can apply a reset write current to the selected storage cell to write the reset data to the selected storage cell. The write control circuit 140 can output a reset write pulse RSTP as a reset write signal RSTWT based on the sense signal DOUT and the write data WDT, and the write driver 150 can apply a reset write voltage to the selected storage cell based on the reset write signal RSTWT, and control the second current to flow through the selected storage cell. The selected memory cell may be programmed to a high resistance state to store reset data, and the write operation may end. At S75, the write driver 150 may apply a set write current to the selected memory cell to write the set data to the selected memory cell. The write control circuit 140 may output a set write pulse SETP as a set write signal SETWT based on the sense signal DOUT and the write data WDT, and the write driver 150 may apply a set write voltage to the selected memory cell based on the set write signal SETWT, and control a third current to flow through the selected memory cell. The selected memory cell may be programmed to a low resistance state to store the set data, and the write operation may end.

[0045] When snapback does not occur in the selected storage cell in step S72, in step S76, voltage and current may not be applied to the selected storage cell. When snapback does not occur in the selected storage cell, SA 160 may keep the sensing signal DOUT in a disabled state. When snapback does not occur in the selected storage cell, the write circuits 140 and 150 may not perform a reset write operation and a set write operation on the selected storage cell regardless of the write data WDT, and interrupt the preselected voltage applied to the selected storage cell. The write control circuit 140 may not enable both the reset write signal RSTWT and the set write signal SETWT based on the sensing signal DOUT. Therefore, the write driver 150 may not apply voltage and current to the selected storage cell, and the write operation may end.

[0046] exist Fig. 8A , Figure 8B and Figure 8C In FIG. 1 , “VGBL” represents the voltage level of the first global electrode GBL, “VGWL” represents the voltage level of the second global electrode GWL, and “Icell” represents the current flowing through the selected memory cell. Fig. 8A , Figure 8B and Figure 8C As shown, when a write operation of the nonvolatile memory device is performed, the second global control circuit 152 can apply a first low voltage to the second global electrode GWL based on the preselection signal PRESEL, and the voltage level VGWL of the second global electrode GWL can drop to the voltage level of the first low voltage. In addition, the second global control circuit 152 can control the first current ISN to flow through the second global electrode GWL. The first global control circuit 151 can apply a first high voltage based on the preselection signal PRESEL, and the voltage level VGBL of the first global electrode GBL can rise to the voltage level of the first high voltage. When the voltage level at both ends of the selected memory cell reaches a voltage level corresponding to the preselection voltage VPRE, the selected memory cell can undergo a snapback. As shown in FIG. Fig. 8A and Figure 8B As shown, when the selected memory cell is not an over-reset and / or open cell, the selected memory cell may snap back and the spike current Ispike may flow through the memory cell. When the spike current Ispike flows, the voltage level VGBL of the first global electrode GBL may drop, and the voltage level VGWL of the second global electrode GWL may rise. SA 160 may sense the change of the voltage level VGWL of the second global electrode GWL and enable the sensing signal DOUT.

[0047] refer to Fig. 8A, when the write data WDT is reset data, the write control circuit 140 may enable the reset write signal RSTWT. The first global control circuit 151 may apply a second high voltage to the first global electrode GBL, and the voltage level VGBL of the first global electrode GBL may rise to a second high voltage. The second global control circuit 152 may apply a second low voltage to the second global electrode GWL, and control the second current IRST to flow through the second global electrode GWL. When the voltage level VGWL of the second global electrode GWL drops to the second low voltage, the voltage level across the selected memory cell may reach the reset write voltage VRST, and when the second current IRST flows through the selected memory cell, the selected memory cell may be programmed to a high resistance state. When the reset write signal RSTWT is disabled, the voltage level VGBL of the first global electrode GBL may drop, and the voltage level VGWL of the second global electrode GWL may rise. When the write signal WT is disabled, the write operation may end.

[0048] refer to Figure 8B , when the write data WDT is set data, the write control circuit 140 may enable the set write signal SETWT. The first global control circuit 151 may apply a third high voltage to the first global electrode GBL, and the voltage level VGBL of the first global electrode GBL may drop to the third high voltage. The second global control circuit 152 may apply a third low voltage to the second global electrode GWL, and control the third current ISET to flow through the second global electrode GWL. When the voltage level VGWL of the second global electrode GWL drops to the third low voltage, the voltage level across the selected memory cell may reach the set write voltage VSET, and when the third current ISET flows through the selected memory cell, the selected memory cell may be programmed to a low resistance state. When the set write signal SETWT is disabled, the voltage level VGBL of the first global electrode GBL may drop, and the voltage level VGWL of the second global electrode GWL may rise. When the write signal WT is disabled, the write operation may end.

[0049] refer to Figure 8C, when the selected memory cell is an over-reset and / or open cell, the selected memory cell may not snap back. Therefore, the spike current Ispike may not flow through the selected memory cell, and the voltage levels of the first global electrode GBL and the second global electrode GWL may not change. SA 160 may keep the sense signal DOUT in a disabled state, and the write control circuit 140 may not enable both the reset write signal RSTWT and the set write signal SETWT regardless of the write data WDT. When the preselection signal PRESEL is disabled, the voltage level VGBL of the first global electrode GBL may drop, and the voltage level VGWL of the second global electrode GWL may rise. Because the write driver 150 does not apply voltage and current to the first global electrode GBL and the second global electrode GWL, the write operation may end when the write signal WT is disabled.

[0050] Fig. 9 is a block diagram illustrating an electronic device including a semiconductor memory device according to an embodiment. Fig. 9 , the electronic device 4200 may include: a processor 4210, a memory 4220, and an input / output (I / O) device 4230. The processor 4210, the memory 4220, and the I / O device 4230 may be coupled via a bus 4246.

[0051] The memory 4220 may receive control signals from the processor 4210. The memory 4220 may store codes and data for the operation of the processor 4210. The memory 4220 may be used to store data accessed via the bus 4246. The memory 4220 may include the above-described nonvolatile memory device 100 according to the present embodiment. For specific implementations and modifications of the present embodiment, additional circuits and control signals may be provided.

[0052] The electronic device 4200 may constitute various electronic control devices that require the memory 4220. For example, the electronic device 4200 may be applied to a computer system, a wireless communication device, or any device that can send / receive information in a wireless environment. Examples of wireless communication devices may include: PDAs, laptop computers, portable computers, network tablets, wireless phones, mobile phones, digital music players, MP3 players, navigation systems, SSDs (solid state drives), and home appliances.

[0053] Fig.10 is a block diagram illustrating a data storage device including a semiconductor memory device according to an embodiment. Fig.10 , a data storage device such as SSD 4311 may be provided. SSD 4311 may include: an interface 4313 , a controller 4315 , a non-volatile memory 4318 , and a buffer memory 4319 .

[0054] SSD 4311 is used to store information using semiconductor devices. Compared with a hard disk drive (HDD), SSD 4311 has higher speed, less mechanical delay or lower failure rate, and less heat or noise. In addition, compared with HDD, SSD 4311 can also have reduced size and weight. SSD 4311 can be widely used in notebook PCs, netbooks, desktop PCs, MP3 players, or portable storage devices.

[0055] The controller 4315 may be formed adjacent to the interface 4313 and electrically coupled to the interface 4313. The controller 4315 may be a microprocessor including a memory controller and a buffer controller. The nonvolatile memory 4318 may be formed adjacent to the controller 4315 and electrically coupled to the controller 4315 via the connection terminal TRM. The SSD 4311 may have a data storage capacity corresponding to the nonvolatile memory 4318. The buffer memory 4319 may be formed adjacent to the controller 4315 and electrically coupled to the controller 4315.

[0056] The interface 4313 may be coupled to the host 4302 and used to send and receive electrical signals such as data. For example, the interface 4313 may use standards such as SATA, IDE, SCSI, and / or combinations thereof. The non-volatile memory 4318 may be coupled to the interface 4313 via the controller 4315.

[0057] The nonvolatile memory 4318 may be used to store data received via the interface 4313. The nonvolatile memory 4318 may include the above-described nonvolatile memory device 100 according to the present embodiment. Although power supplied to the SSD 4311 is removed, data stored in the nonvolatile memory 4318 may be retained.

[0058] The buffer memory 4319 may include a volatile memory or a nonvolatile memory. The volatile memory may be a DRAM and / or an SRAM. The nonvolatile memory may include the above-mentioned nonvolatile memory device 100 according to this embodiment.

[0059] The interface 4313 may have a data processing speed higher than the operating speed of the non-volatile memory 4318. The buffer memory 4319 may be used to temporarily store data. Data received via the interface 4313 may be temporarily stored in the buffer memory 4319 by the controller 4315, and then permanently stored in the non-volatile memory 4318 according to the data recording speed of the non-volatile memory 4318.

[0060] In addition, frequently used data among the data stored in the nonvolatile memory 4318 may be pre-read and temporarily stored in the buffer memory 4319. That is, the buffer memory 4319 may be used to increase the efficient operation speed of the SSD 4311 and reduce the error occurrence rate.

[0061] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Therefore, the nonvolatile memory device and the operating method thereof described herein should not be limited based on the described embodiments.

Claims

1. A non-volatile storage device, comprising: a sense amplifier configured to sense whether snapback occurs in a selected memory cell; as well as Write a circuit that is configured as: applying a preselected voltage to the selected memory cell based on a write signal, the preselected voltage corresponding to a reset distribution maximum voltage; When snapback occurs in the selected memory cell, applying one of a reset write voltage and a set write voltage to the selected memory cell based on write data, wherein the preselected voltage is lower than the reset write voltage and higher than the set write voltage; and When snapback does not occur in the selected memory cell, no current and no voltage are applied to the selected memory cell.

2. The nonvolatile storage device according to claim 1, wherein: The writing circuit comprises: Write control circuit, which is configured as: generating a preselect signal based on the write signal; When snapback occurs in the selected memory cell, generating one of a reset write signal and a set write signal based on the write data; and When snapback does not occur in the selected memory cell, disabling the preselect signal and preventing the reset write signal and the set write signal from being generated; and Write to the drive, which is configured as: applying the preselect voltage to the selected memory cell based on the preselect signal; applying the reset write voltage to the selected memory cell based on the reset write signal; and The set write voltage is applied to the selected memory cell based on the set write signal.

3. The nonvolatile storage device according to claim 2, wherein: The write control circuit is configured as follows: generating the preselect signal based on the write signal, generating the reset write signal and the set write signal based on the write data and a sense signal output from the sense amplifier, and When the sense signal is disabled, the reset write signal is not generated and the set write signal is not generated.

4. The nonvolatile storage device according to claim 2, wherein: The write control circuit comprises: a write pulse generator configured to generate a reset pulse signal and a set pulse signal based on the write signal; a reset write signal generator configured to generate the reset write signal based on the write data, the reset pulse signal, and a sense signal output from the sense amplifier; a set write signal generator configured to generate the set write signal based on the write data, the set pulse signal and the sense signal; and A preselect signal generator is configured to generate the preselect signal based on at least one of the write signal, the reset pulse signal, and the set pulse signal.

5. The nonvolatile memory device according to claim 2, wherein: The write driver comprises: a first global control circuit configured to apply one of a first high voltage, a second high voltage, and a third high voltage to a first global electrode coupled to the selected memory cell based on the preselect signal, the reset write signal, and the set write signal; and a second global control circuit configured to apply one of a first low voltage, a second low voltage, and a third low voltage to a second global electrode coupled to the selected memory cell based on the preselection signal, the reset write signal, and the set write signal, and configured to control one of a first current, a second current, and a third current to flow through the second global electrode.

6. The nonvolatile memory device according to claim 5, wherein: The first high voltage is lower than the second high voltage and higher than the third high voltage.

7. The nonvolatile memory device according to claim 5, wherein: the first low voltage is higher than the second low voltage and the third low voltage, and the second low voltage is equal to or lower than the third low voltage, The third current is smaller than the second current and larger than the first current.

8. The nonvolatile memory device according to claim 5, wherein: A difference between the first high voltage and the first low voltage corresponds to the preselected voltage; A difference between the second high voltage and the second low voltage corresponds to the reset write voltage; as well as A difference between the third high voltage and the third low voltage corresponds to the set write voltage.

9. An operating method of a non-volatile storage device, the operating method comprising: applying a preselected voltage to the selected memory cell, the preselected voltage corresponding to a reset distribution maximum voltage; sensing whether snapback occurs in the selected storage unit; as well as When snapback occurs in the selected memory cell, one of a reset write operation and a set write operation is performed on the selected memory cell based on write data, and when snapback does not occur in the selected memory cell, no voltage and current are applied to the selected memory cell.

10. A non-volatile storage device, comprising: Write control circuit, which is configured as: generating a preselect signal based on the write signal; When the sense signal is enabled, generating one of a reset write signal and a set write signal; as well as When the sense signal is disabled, the preselect signal is disabled and the reset write signal and the set write signal are not generated; a sense amplifier configured to sense whether snapback occurs in the memory cell and generate the sense signal; as well as Write to the drive, which is configured as: performing a preselect operation on a selected memory cell based on the preselect signal; performing a reset write operation on the selected memory cell based on the reset write signal; as well as A set write operation is performed on the selected memory cell based on the set write signal.

11. The nonvolatile memory device according to claim 10, wherein: The write control circuit comprises: a write pulse generator configured to generate a reset pulse signal and a set pulse signal based on the write signal; a reset write signal generator configured to generate the reset write signal based on the reset pulse signal, write data and the sensing signal; a set write signal generator configured to generate the set write signal based on the set pulse signal, the write data and the sense signal; and A preselect signal generator is configured to generate the preselect signal based on at least one of the write signal, the reset pulse signal, and the set pulse signal.

12. The nonvolatile memory device according to claim 10, wherein: The write driver is configured as: providing a preselected voltage and a first current to the selected memory cell based on the preselected signal; providing a reset write voltage and a second current to the selected memory cell based on the reset write signal; as well as A set write voltage and a third current are provided to the selected memory cell based on the set write signal.

13. The nonvolatile memory device according to claim 12, wherein: The preselected voltage is lower than the reset write voltage and higher than the set write voltage, The third current is greater than the first current but less than the second current.

14. The nonvolatile memory device according to claim 12, wherein: The preselected voltage corresponds to a reset distribution maximum voltage.

15. The nonvolatile memory device according to claim 10, wherein: The write driver comprises: a first global control circuit configured to apply one of a first high voltage, a second high voltage, and a third high voltage to a first global electrode coupled to the selected memory cell based on the preselect signal, the reset write signal, and the set write signal; and a second global control circuit configured to apply one of a first low voltage, a second low voltage, and a third low voltage to a second global electrode coupled to the selected memory cell based on the preselection signal, the reset write signal, and the set write signal, and configured to control one of a first current, a second current, and a third current to flow through the second global electrode.

16. The nonvolatile memory device according to claim 15, wherein: The first high voltage is lower than the second high voltage and higher than the third high voltage, wherein the first low voltage is higher than the second low voltage and the third low voltage, and the second low voltage is equal to or lower than the third low voltage, The third current is smaller than the second current and larger than the first current.

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