Methods for Creating Air Gap

Abstract

The present invention relates to a method for creating an air gap. A tin oxide film is used to create an air gap during semiconductor substrate processing. A plasma formed in a process gas containing H2 can be used to selectively etch the tin oxide film disposed between exposed other material layers such as SiO2 and SiN. The etching creates a recessed feature between the surrounding material to replace the tin oxide. A third material such as SiO2 is deposited on the resulting recessed feature without completely filling the recessed feature, thereby forming an air gap. In some embodiments, a method for selectively etching tin oxide in the presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO or SiCN includes contacting a substrate with a plasma formed in a process gas containing at least about 50% H2. The etching of tin oxide can be performed without using an external bias on the substrate, and is preferably performed at a temperature below about 100°C.

Description

[0001] This application is a divisional application of the application with application number 201810148464.5, application date February 13, 2018, and invention name “Method for Creating an Air Gap”. Technical Field

[0002] The present invention relates to methods of semiconductor device fabrication. In particular, embodiments of the present invention relate to methods of creating air gaps during semiconductor substrate processing. Background Art

[0003] In semiconductor device manufacturing, deposition and etching techniques are used to pattern materials on substrates. Patterning generally requires etching one material in the presence of another material with high etch selectivity. As the size of patterned features on substrates decreases, etch selectivity requirements become more stringent. In addition, wet etching methods such as etching SiO2 with HF become less ideal on substrates with high aspect ratio recessed features due to problems with etchant penetration into recessed features.

[0004] Highly selective etching methods are required for patterning in a variety of applications, including the formation of dynamic random access memory (DRAM), patterning in the manufacture of fin field effect transistors (FinFETs), and patterning in back-end-of-line (BEOL) processing. Summary of the invention

[0005] Materials that can be selectively etched with high etch selectivity in the presence of commonly used dielectrics such as SiO2 and SiN and related etching methods are particularly desirable. SnO2 is provided herein as a material that can be selectively etched relative to SiO2, SiN, and a variety of other materials using highly selective dry etching chemistries. Methods for forming air gaps in semiconductor device fabrication using SnO2 as a sacrificial spacer material (e.g., during FinFET fabrication) are also provided.

[0006] According to one aspect, a method for processing a semiconductor substrate is provided. The method includes: providing a semiconductor substrate having an exposed SnO2 layer (e.g., a SnO2 layer deposited by atomic layer deposition); and etching the SnO2 layer at a temperature below about 100°C, wherein the etching includes exposing the semiconductor substrate to a plasma formed in a process gas containing at least about 50% by volume H2. In some embodiments, the provided semiconductor substrate also includes an exposed second material selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN, and hydrogen plasma etching of SnO2 is performed with an etching selectivity of at least about 10 (e.g., at least about 80) relative to the second material. The second material can be exposed on the substrate before the SnO2 etching begins, or in some embodiments, the second material can be exposed during the SnO2 etching process. In some embodiments, the second material is SiO2, and the etching removes SnO2 with an etching selectivity of at least about 10 relative to SiO2.

[0007] The composition of the process gas in SnO2 etching can vary and may include other gases in addition to H2. However, in some embodiments, the process gas is primarily composed of H2 (e.g., 100% H2). In some embodiments, the process gas includes at least about 50% H2 and also includes an inert gas, such as helium. In some embodiments, the process gas may consist essentially of H2 and an inert gas. In some embodiments, the concentration of H2 in the process gas is at least about 80%. Optionally, the process gas may further include hydrocarbons and / or Cl2. In one example, the process gas includes H2 (50% or more), helium, and a hydrocarbon. The plasma in the process gas may be formed using high frequency and / or low frequency plasma generation. It is noteworthy that the use of an external bias on the substrate is optional. In some embodiments, etching is performed without providing an external bias to the substrate. In some embodiments, a voltage between about 0.0018 W / cm 2 and 0.36W / cm 2 In some embodiments, the pressure in the processing chamber during etching is between about 1 mTorr and 175 mTorr.

[0008] In another aspect, an apparatus for etching a SnO2 layer is provided. The apparatus comprises: a processing chamber having a substrate holder configured to hold the semiconductor substrate during etching; a plasma generator configured to generate plasma in a process gas; and a controller. The controller comprises program instructions for implementing any of the methods described herein. In one embodiment, the controller comprises program instructions for causing the etching of the SnO2 layer on the semiconductor substrate at a temperature below about 100°C, wherein causing the etching comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least about 50% H2.

[0009] In another aspect, a non-transitory computer machine readable medium is provided, wherein the medium includes program instructions for controlling an etching device. The program instructions include code for causing the etching of the SnO2 layer on the semiconductor substrate at a temperature below about 100°C, wherein causing the etching includes exposing the semiconductor substrate to a plasma formed in a process gas containing at least about 50% H2.

[0010] On the other hand, a method for generating an air gap on a semiconductor substrate is provided. The method includes: (a) providing a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer located between the first material layer and the second material layer; (b) using a hydrogen plasma etching chemistry to selectively etch the exposed SnO2 relative to the first material and the second material, thereby forming a recessed feature between the first material and the second material; and (c) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer. In some implementations, the first material is selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN, and the second material is selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN. In some embodiments, the first material and the second material are the same material. In some embodiments, the first material and the second material are different materials. In some embodiments, the third material is SiO2.

[0011] In some implementations, hydrogen plasma etching of the SnO2 layer includes exposing the semiconductor substrate to a plasma formed in a process gas comprising at least about 50% H2. In some embodiments, the etching includes etching at a temperature below about 100°C. The described method is particularly useful for forming air gaps in narrow recessed features. In one implementation, the width of the SnO2 layer is between about (Angstroms) and between.

[0012] In one embodiment, a substrate having a SnO2 layer between a first material layer and a second material layer is formed using the following sequence of steps. The process begins by forming a gate (e.g., a protruding feature made of a high-k oxide such as hafnium oxide) on the semiconductor substrate; conformally forming a layer of the first material (e.g., SiN) over the semiconductor substrate so that the first material covers both the sidewalls and the top surface of the gate; conformally forming a SnO2 layer (to between about 100 and 150 nm) on the first material layer; and conformally forming a SnO2 layer (to between about 100 and 150 nm) on the first material layer. and The process further comprises forming a layer of a second material (e.g., SiO2) on the SnO2 layer so that the second material covers the SnO2 on both the sidewalls and the top surface of the gate. The process then removes the second material from the horizontal surface of the substrate, thereby forming a structure with an exposed SnO2 layer between the exposed first material layer and the second material layer.

[0013] In another aspect, a system for forming an air gap on a semiconductor substrate is provided. The system includes: one or more deposition chambers; one or more etching chambers; and a controller. The controller includes program instructions for implementing any of the air gap forming methods described herein. For example, the controller may include instructions for causing the following steps: (i) selectively etching the exposed SnO2 relative to both the first material and the second material using a hydrogen plasma etching chemistry on a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer between the first material layer and the second material layer, thereby forming a recessed feature between the first material and the second material; and (ii) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer.

[0014] In another aspect, the system includes any one of the apparatus and systems described herein and a stepper.

[0015] In another aspect, a non-transitory computer machine-readable medium is provided, comprising program instructions for controlling a system, wherein the program instructions comprise code for: (i) selectively etching the exposed SnO2 relative to both the first material and the second material using a hydrogen plasma etching chemistry on a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer between the first material layer and the second material layer, thereby forming a recessed feature between the first material and the second material; and (ii) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer.

[0016] In another aspect, a method for processing a semiconductor substrate is provided, wherein the method involves depositing a SnO2 dummy gate. The method comprises: (a) forming a SnO2 dummy gate on the semiconductor substrate; (b) processing the semiconductor substrate in the presence of the SnO2 dummy gate; (c) etching the SnO2 dummy gate with a plasma formed in a process gas including H2 to form a recessed feature to replace the dummy gate; and (d) depositing a high-k dielectric material into the recessed feature formed to form a gate to replace the dummy gate. In another aspect, a system for processing a semiconductor substrate is provided, wherein the system includes: one or more deposition processing chambers; one or more etching processing chambers; and a controller comprising program instructions, wherein the program instructions are used to cause the following steps: (i) forming a SnO2 dummy gate on the semiconductor substrate; (ii) processing the semiconductor substrate in the presence of the SnO2 dummy gate; (iii) etching the SnO2 dummy gate with a plasma formed in a process gas including H2 to form a recessed feature to replace the dummy gate; and (iv) depositing a high-k dielectric material into the formed recessed feature to form a gate to replace the dummy gate. On the other hand, a non-temporary computer machine readable medium is provided, which includes program instructions for controlling a system, wherein the program instructions include code for causing the following steps: (i) forming a SnO2 dummy gate on the semiconductor substrate; (ii) processing the semiconductor substrate in the presence of the SnO2 dummy gate; (iii) etching the SnO2 dummy gate with a plasma formed in a process gas including H2 to form a recessed feature to replace the dummy gate; and (iv) depositing a high-k dielectric material into the recessed feature formed to form a gate to replace the dummy gate.

[0017] In some embodiments, the provided method is integrated with a photolithography patterning sequence and also includes: applying a photoresist to the semiconductor substrate; exposing the photoresist to light; patterning the photoresist and transferring the pattern to the substrate; and selectively removing the photoresist from the substrate.

[0018] These and other aspects of implementations of the subject matter described in this specification are set forth in the drawings and the description that follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a process flow diagram of a treatment method according to an embodiment provided herein.

[0020] Figure 2 is a process flow diagram of a treatment method according to an embodiment provided herein.

[0021] Figures 3A-3G A schematic cross-sectional view of a semiconductor substrate undergoing processing with air gap formation according to embodiments described herein is shown.

[0022] FIG. 4A to FIG. 4T Schematic diagram showing a semiconductor substrate undergoing processing during FinFET device fabrication according to embodiments described herein.

[0023] Figure 5 is a schematic diagram of an apparatus suitable for etching SnO2 using a hydrogen plasma etch chemistry according to embodiments provided herein.

[0024] Figure 6 A schematic diagram of a multi-station processing system according to embodiments provided herein is shown. DETAILED DESCRIPTION

[0025] Methods for etching tin (IV) oxide (SnO2) in semiconductor device manufacturing are provided. In some embodiments, the provided methods are used to etch tin oxide with high selectivity relative to one or more of SiO2, SiC, SiN, SiOC, SiNO, SiCNO and SiCN. In some embodiments, the etching selectivity is greater than 10, such as greater than 30, such as greater than 50, or greater than 80. Etching selectivity refers to the ratio of the etching rate of SnO2 to the etching rate of other materials for selected process conditions. In some examples, an etching selectivity of 100 is achieved for etching SnO2 relative to SiO2. These etching selectivities are achieved for etching methods that include contacting a semiconductor substrate with a plasma formed in a process gas containing H2. The provided methods involve converting solid SnO2 into gaseous SnH4 by exposing SnO2 to a hydrogen plasma. The gaseous SnH4 product can then be easily removed from the processing chamber by purging and / or exhausting. In some embodiments, another material (e.g., SiO2, SiC, SiN, SiOC, SiNO, SiCNO or SiCN) is exposed on the semiconductor substrate at the beginning of SnO2 etching. In other embodiments, another material is not exposed at the beginning of SnO2 etching, but is exposed during the etching process.

[0026] SnO2 can be deposited, for example, by ALD or PECVD, and can contain small amounts of other materials, such as carbon and hydrogen (typically less than 10 atomic %). It should also be understood that in tin oxides, small deviations from the stoichiometric ratio of tin to oxygen of 1:2 are possible and within the range of SnO2 structures. For example, in some examples of SnO2, the atomic ratio of O to Sn is between about 2.0-2.3. Tin oxides having an O to Sn ratio between about 1.5 and 2.5 are within the range of SnO2 materials used herein.

[0027] SiO2, SiC, SiN, SiOC, SiNO, SiCNO and SiCN materials may be doped or undoped and may optionally include hydrogen. Dopants, when present, generally do not exceed an atomic concentration of 10% (excluding hydrogen). These materials may be deposited using various methods, such as CVD, PECVD and ALD. Various silicon-containing precursors may be used to deposit these materials, including silane, tetraalkylsilane, trialkylsilane, TEOS, etc. For example, SiO2 may be deposited using TEOS or silane as a silicon-containing precursor.

[0028] The term "semiconductor substrate" as used herein refers to a substrate at any stage of semiconductor device fabrication that contains semiconductor material anywhere in its structure. It should be understood that the semiconductor material in the semiconductor substrate need not be exposed. A semiconductor wafer having multiple layers of other materials (e.g., dielectrics) covering the semiconductor material is an example of a semiconductor substrate.

[0029] The methods provided can be used to etch SnO2 layers of various widths and aspect ratios. These methods are useful for etching narrow layers (e.g., For example The invention is particularly advantageous for etching SnO2 layers with relatively high aspect ratios, and for producing recessed features with relatively high aspect ratios, such as for etching SnO2 to create recessed features with aspect ratios of at least about 5:1 (e.g., aspect ratios between about 10:1 and 100:1). Although the provided methods are not limited to these applications, the use of the hydrogen plasma etching methods provided herein to etch narrow layers and / or form high aspect ratio recessed features is particularly useful because conventional methods and materials (e.g., wet HF etching of SiN spacers) are not suitable for these applications.

[0030] exist Figure 1 The process flow chart shown in the figure illustrates an etching method according to an embodiment provided herein. In operation 1101, a semiconductor substrate having an exposed SnO2 layer is provided. The substrate is placed in a processing chamber of an etching device, wherein the device is configured to generate a plasma in a process gas. Next, in operation 1103, a plasma is generated in a process gas containing H2. In operation 1105, the substrate is contacted with the formed hydrogen plasma, and the SnO2 layer is selectively etched relative to any of the SiO2, SiC, SiN, SiOC, SiNO, SiCNO and SiCN materials on the substrate. Selective etching involves etching SnO2 with an etching selectivity greater than 1, more preferably greater than 10, for example greater than 50 relative to any of the listed materials.

[0031] In some embodiments, the semiconductor substrate provided in operation 1101 includes an exposed second material layer in addition to the exposed SnO2 layer, wherein the second material includes one or more of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN. In other embodiments, the second material is not exposed when the SnO2 etching begins, but becomes exposed after the SnO2 has been etched for a period of time.

[0032] The substrate provided in 1101 is obtained after depositing and optionally patterning a SnO2 layer and a second material (e.g., any combination of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN). The SnO2 layer is deposited by any suitable method (such as by CVD (including PECVD), ALD (including PEALD), sputtering, etc.). In some embodiments, the SnO2 film is preferably deposited conformally so that it follows the surface of the substrate, including the surface of any protruding and recessed features on the substrate. In some embodiments, the SnO2 layer is conformally deposited to between about Thickness between. One of the suitable deposition methods for conformal SnO2 film is ALD. Thermal or plasma enhanced ALD can be used. In a typical thermal ALD method, a substrate is provided to an ALD processing chamber and sequentially exposed to a tin-containing precursor and an oxygen-containing reactant, wherein the tin-containing precursor and the oxygen-containing reactant are allowed to react on the surface of the substrate to form SnO2. After the substrate is exposed to the tin-containing precursor and before the oxygen-containing reactant enters the processing chamber, the ALD processing chamber is usually purged with an inert gas to prevent reactions from occurring in the main part of the processing chamber. In addition, the ALD processing chamber is usually purged with an inert gas after treating the substrate with the oxygen-containing reactant. Repeat several cycles of continuous exposure, for example, about 10-100 cycles can be performed until a SnO layer with the desired thickness is deposited. Examples of suitable tin-containing precursors include halogenated tin-containing precursors (e.g., SnCl4 and SnBr4) and non-halogenated tin-containing precursors, such as organic tin compounds, which include alkyl-substituted tin amides and the like. Specific examples of alkyl-substituted tin amides suitable for ALD are tetrakis(dimethylamino)tin, tetrakis(ethylmethylamino)tin, N 2 ,N 3-di-tert-butyl-butane-2,3-diaminotin(II) and (1,3-bis(1,1-dimethylethyl)-4,5-dimethyl-(4R,5R)-1,3,2-diazastannolidin-2-ylidene). Oxygen-containing reactants include, but are not limited to, oxygen, ozone, water, hydrogen peroxide, and NO. Mixtures of oxygen-containing reactants may also be used. Deposition conditions will vary according to A The process is typically carried out at a temperature between about 20°C and 500°C and a pressure below atmospheric pressure. The temperature and pressure are selected to keep the reactants in a gaseous form in the processing chamber to avoid condensation. Each reactant is provided to the processing chamber in a separate gaseous form or in a gaseous form mixed with a carrier gas such as argon, helium or nitrogen. The flow rate of these mixtures will depend on the size of the processing chamber, and in some embodiments is between about 10 sccm and 10,000 sccm.

[0033] A specific example of thermal ALD process conditions suitable for depositing the conformal SnO2 layer provided herein is described in an article by Li et al. entitled "Tin Oxide with Controlled Morphology and Crystallinity by Atomic Layer Deposition onto Graphene Nanosheets for Enhanced Lithium Storage" (Advanced Functional Materials, 2012, 22, 8, 1647-1654), the entire contents of which are incorporated herein by reference. The process includes sequentially and alternately exposing a substrate in an ALD vacuum chamber to SnCl4 (a tin-containing precursor) and deionized water (an oxygen-containing reactant) at a temperature of 200-400°C. In a specific example of an ALD cycle, a mixture of SnCl4 vapor and a N2 carrier gas is introduced into the ALD processing chamber for 0.5 seconds and then exposed to the substrate for 3 seconds. Next, the ALD chamber is purged with N2 for 10 seconds to remove SnCl4 from the main body of the chamber, and a mixture of H2O vapor and N2 carrier gas is flowed into the chamber for 1 second and exposed to the substrate for 3 seconds. Next, the ALD chamber is purged with N2 and the cycle is repeated. The ALD process is performed at a pressure below atmospheric pressure (e.g., 0.4 Torr) and a temperature of 200-400°C.

[0034] Another example of thermal ALD process conditions suitable for depositing SnO films in the method provided herein is given in Du et al., entitled "In situ Examination of Tin Oxide Atomic Layer Deposition using Quartz Crystal Microbalance and Fourier Transform Infrared Techniques" (J. Vac. Sci. Technol. A 23, 581 (2005)), the entire contents of which are incorporated herein by reference. In this process, the substrate is sequentially exposed to SnCl4 and H2O2 in an ALD processing chamber at a temperature between about 150°C and 430°C.

[0035] Although it is suitable to use a halogenated tin precursor in ALD in many embodiments, in some embodiments, it is more preferred to use a non-halogenated organotin precursor to avoid corrosion problems that may occur when using a halogenated precursor such as SnCl4. Examples of suitable non-halogenated organotin precursors include alkylaminotin (alkylated tin amide) precursors, such as tetrakis (dimethylamino) tin. An example of a suitable thermal ALD deposition method using this precursor is provided in an article by Elam et al., entitled "Atomic Layer Deposition of Tin Oxide Films using Tetrakis (dimethylamino) tin" (J. Vac. Sci. Technol. A 26, 244 (2008)), the entire contents of which are incorporated herein by reference. In this method, a substrate is sequentially exposed to tetrakis (dimethylamino) tin and H2O2 in an ALD chamber at a temperature between about 50°C and 300°C. Advantageously, the use of such a precursor allows SnO2 films to be deposited at low temperatures of 100°C or less. For example, SnO2 films can be deposited at 50°C without using plasma to increase the reaction rate. Another example of thermal ALD of SnO using tetrakis(dimethylamino)tin and H2O2 is provided in an article by Elam et al., entitled "Atomic Layer Deposition of Indium Tin Oxide Thin Films Using Nonhalogenated Precursors" (J. Phys. Chem. C 2008, 112, 1938-1945), the entire contents of which are incorporated herein by reference.

[0036] Another example of a low temperature thermal ALD process using a reactive organotin precursor is provided in an article by Heo et al., entitled "Low temperature Atomic Layer Deposition of Tin Oxide" (Chem. Mater., 2010, 22 (7) 4964-4973), the entire contents of which are incorporated herein by reference. In this deposition process (which is suitable for depositing SnO2 films provided herein), a substrate is sequentially exposed to N 2 ,N 3 -di-tert-butyl-butane-2,3-diamino-tin(II) and 50% H2O2. These reactants are vaporized and each reactant is mixed with N2 carrier gas and provided to the processing chamber. After each exposure of the substrate to the reactants, the chamber is purged with N2. Deposition can be performed at a temperature between about 50°C-150°C.

[0037] Although hydrogen peroxide is commonly used as an oxygen-containing reactant for forming SnO2 in the ALD process, it may sometimes be insufficient to control the growth of SnO2 films due to the decomposition of H2O2. In some embodiments, a more stable oxygen-containing precursor, such as NO, is used. An example of suitable process conditions using NO as an oxygen-containing reactant is provided in an article entitled "Atomic Layer Deposition of Tin Oxide with Nitric Oxide as an Oxidant Gas" (J. Mater. Chem., 2012, 22, 4599) by Heo et al., the entire contents of which are incorporated herein by reference. Deposition involves sequentially exposing the substrate to cyclic Sn(II)amide (1,3-bis(1,1-dimethylethyl)-4,5-dimethyl-(4R,5R)-1,3,2-diazatinane-2-subunit and NO at a temperature between about 130-250°C.

[0038] In some embodiments, SnO2 film is deposited by PEALD. The same type of tin-containing precursor and oxygen-containing reactant as described above for thermal ALD can be used. In PEALD, the ALD device is equipped with a system for generating plasma in a processing chamber and treating the substrate with plasma. In a typical PEALD processing sequence, the substrate is provided to the PEALD processing chamber and exposed to the tin-containing precursor adsorbed on the substrate surface. The processing chamber is purged with an inert gas (such as argon or helium) to remove the precursor from the processing chamber, and the substrate is exposed to the oxygen-containing reactant introduced into the processing chamber. While the oxygen-containing reactant is introduced or after a period of time, plasma is formed in the processing chamber. Plasma promotes the reaction between the tin-containing precursor and the oxygen-containing reactant on the substrate surface, resulting in the formation of SnO2. Next, the processing chamber is purged with an inert gas, and the cycle of dosing the tin precursor, purging, dosing the oxygen-containing reactant, plasma treatment and the second purge is repeated as needed for many times to form a SnO2 film of desired thickness.

[0039] An example of process conditions suitable for PEALD formation of SnO2 films is provided in an article by Seop et al., entitled "The Fabrication of Tin Oxide Films by Atomic Layer Deposition using Tetrakis(ethylmethylamino)tin Precursor" (Transactions on Electrical and Electronic Materials, 2009, 10, 5, 173-176), the entire contents of which are incorporated herein by reference. A substrate is provided to a PEALD processing chamber and exposed to tetrakis(ethylmethylamino)tin for 4 seconds without plasma. Next, the tin-containing precursor is removed from the processing chamber by flowing argon gas through the processing chamber for 20 seconds. O2 is then injected for 2 seconds, at a radio frequency (RF) power of 100 W, for an additional 2 seconds. This is followed by an argon purge, completing a PEALD cycle. In this example, the process is carried out at a temperature range between 50-200°C and a pressure of 0.8 Torr.

[0040] Although ALD (both thermal and plasma enhanced) is one of the preferred methods for depositing SnO 2 films, it should be understood that other SnO 2 deposition methods such as CVD, PECVD, and sputtering may also be used.

[0041] The second material (any of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN) can be deposited by a variety of methods, including PECVD, CVD, ALD, and PEALD. In some embodiments, the second material is deposited by PECVD. In this method, a plasma is formed in a process gas containing a silicon-containing precursor and a reactant containing one or more elements of the second material under conditions controlled for depositing the second material on a substrate. For example, SiO2 can be deposited by forming a plasma in a process gas containing a silicon-containing precursor and an oxygen-containing reactant; SiC can be deposited by forming a plasma in a process gas containing a silicon-containing precursor and a carbon-containing reactant; SiN can be deposited by forming a plasma in a process gas containing a silicon-containing precursor and a nitrogen-containing reactant; SiOC can be deposited by forming a plasma in a process gas containing a silicon-containing precursor, an oxygen-containing reactant, and a carbon-containing reactant; SiNO can be deposited by forming a plasma in a process gas containing a silicon-containing precursor, an oxygen-containing reactant, and a nitrogen-containing reactant; SiCNO can be deposited by forming a plasma in a process gas containing a silicon-containing precursor, an oxygen-containing reactant, a carbon-containing reactant, and a nitrogen-containing reactant; and SiCN can be deposited by forming a plasma in a process gas containing a silicon-containing precursor, a carbon-containing reactant, and a nitrogen-containing reactant. In those cases where the silicon-containing precursor further includes any necessary elements of the second material, the silicon-containing precursor and the reactant can be the same. For example, during the deposition of SiO2, TEOS can be used as a silicon-containing precursor and an oxygen-containing reactant. Examples of silicon-containing precursors include silane, disilane, tetraalkylsilane, trialkylsilane, siloxane, TEOS, etc. Examples of oxygen-containing reactants include CO2, N2O, O2, O3, H2O. Examples of nitrogen-containing reactants include N2 and NH3. Examples of carbon-containing reactants include hydrocarbons, such as methane, ethane, propane, etc. The process gases used to deposit these materials may also include carrier gases, such as He, Ar, Ne, etc.

[0042] SnO2 etching methods utilizing hydrogen plasma can be implemented in various devices under various process conditions. In some embodiments, the method involves providing a semiconductor substrate having an exposed tin oxide layer to an etching chamber, and contacting the substrate with a plasma formed in a process gas comprising H2 and an optional carrier gas (such as helium or another inert gas). The term "etching chamber" or "etching apparatus" refers to a chamber and apparatus configured for etching. In some embodiments, an "etching chamber" or "etching apparatus" is specifically configured for etching operations. In other embodiments, an "etching chamber" or "etching apparatus" can be configured to perform other operations in addition to etching, such as deposition. For example, in some embodiments, an etching chamber can also be used for ALD deposition.

[0043] In some embodiments, the plasma used for hydrogen plasma etching is generated in the same processing chamber that houses the semiconductor substrate. In other embodiments, the plasma is remotely generated and introduced into the processing chamber that houses the substrate through one or more inlets in the processing chamber.

[0044] The etching is controlled to convert SnO2 into volatile SnH4. Preferably, the H2 content in the process gas is at least about 50% by volume, such as at least about 80% by volume (can be up to and including 100%). In some embodiments, the process gas may further include a hydrocarbon, such as CH4. In some embodiments, the process gas also includes Cl2. For example, the process gas may be essentially composed of H2 and an inert gas (such as He), or the process gas may be essentially composed of H2, an inert gas and a hydrocarbon (CH4). Etching is performed at a temperature of less than about 100° C. measured near the substrate. The etching reaction advantageously produces only volatile materials, such as SnH4, which can be easily removed from the etching process chamber by exhaust and / or purging. The etching process temperature is preferably selected to be less than about 100° C., because higher temperatures may cause the formed SnH4 to decompose and form particles that may contaminate the process chamber and the substrate. The composition of the process gas and the processing conditions are selected to reduce or eliminate the formation of particles during etching. Importantly, the etching reaction does not require any significant sputtering component and can be performed without an external bias on the substrate and in the absence of heavy ions (e.g., argon ions). Reducing the sputtering component may be beneficial for improving the etch selectivity relative to the second material on the substrate. Therefore, in some embodiments, etching is performed without providing an external bias to the substrate and / or involves the use of helium (a light gas) as a carrier gas to reduce sputtering.

[0045] The plasma used for hydrogen plasma etching can be generated using various frequencies (low and high). Examples of suitable frequencies include 400 KHz, 2 MHz, 13.56 MHz, 27 MHz, or 2.45 GHz. In some embodiments, the power used to generate the plasma can range from about 50 W to 1,000 W, corresponding to between about 0.0018 W / cm 2 and 0.36W / cm 2 The bias on the substrate is optional and the bias power can be in the range of about 0 W to 500 W. The suitable gas flow rate for each showerhead (for processing a 300 mm wafer) is:

[0046] i.H2: 25 to 750 sccm;

[0047] ii. Cl2: 0 to 500 sccm (e.g., 5–200 sccm);

[0048] iii. He: 0 to 500 sccm (e.g., 5–100 sccm); and

[0049] iv. CH4: 0 to 500 sccm (e.g., 5–100 sccm).

[0050] In some embodiments, the etching process can be performed at a pressure between about 1 and 175 mTorr.

[0051] In some embodiments, the plasma is generated using high frequency generation (e.g., 13.56 MHz or 27 MHz) and the power corresponding to between 0.07 W / cm 2 and 0.18W / cm 2 The plasma is provided at a plasma power between about 200 W and 500 W with a power density between 0 and 200 W. The power of the substrate bias is between about 0 W and 200 W. The gas flow rate suitable for each showerhead (for processing a 300 mm wafer) is:

[0052] i. H2: 100 to 300 sccm;

[0053] ii. Cl2: 0 to 200 sccm (e.g., 5–100 sccm);

[0054] iii. He: 0 to 100 sccm (e.g., 5–50 sccm);

[0055] iv. CH4: 0 to 100 sccm (e.g., 5–50 sccm).

[0056] In these embodiments, the etching process is performed at a pressure between approximately 1 and 30 mTorr.

[0057] In some embodiments, before etching, the substrate including the exposed SnO2 layer further includes an exposed material layer selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO and SiCN, and the provided etching method etches SnO2 with high selectivity relative to these materials. In some embodiments, etching completely removes the exposed SnO2 from the substrate surface without completely removing the material selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO and SiCN.

[0058] In another aspect, a method for forming an air gap on a substrate is provided, wherein SnO2 is used as a removable spacer material in forming the air gap. For example, the air gap spacer made of SnO2 can be used in a FinFET device.

[0059] Conventional techniques use one or more of the following. SiO2 is used in DRAM manufacturing and is removed using HF. The use of this chemistry is therefore limited due to HF's chemical attack on other films and problems with penetrating very high aspect ratio structures (>15:1). In logic manufacturing, the use of traditional FinFET air gap spacers may be too complex due to too many steps. In addition, there is no perfect combination of materials to choose from. The use of wet etching processes makes small features and / or high aspect ratio feature processing problematic. These shortcomings are addressed here by introducing SnO2 air gap spacers and processing methods.

[0060] Figure 2 2 is a process flow chart showing an embodiment of a method for creating an air gap on a semiconductor substrate using a removable SnO2 spacer. The method begins at operation 2201, in which a semiconductor substrate having an exposed first material layer and an exposed second material layer and an exposed SnO2 layer located between the first material layer and the second material layer is provided. The first material and the second material can be the same material or different materials. For example, the first material and the second material can be independently selected from SiO2, SiC, SiN, SiOC, SiNO, SiCNO and SiCN. In some embodiments, the first material and the second material are both SiO2. In other embodiments, the first material is SiO2 and the second material is SiN. In general, any combination of materials can be selected. Then, in operation 2203, the exposed SnO2 is selectively etched relative to both the first material and the second material using the hydrogen plasma etching chemistry described herein. The etching removes SnO2 in the presence of the exposed first material and the second material and forms a recessed feature to replace the removed SnO2. The etch selectivity for removing SnO2 relative to the first and second materials is preferably at least about 5, such as at least about 10, or at least about 50. An etch selectivity greater than 80, such as an etch selectivity of 100, can also be achieved using the described method. Next, in operation 2205, a third material is deposited on the recessed feature without completely filling the recessed feature, thereby forming an air gap between the first material layer and the second material layer. The third material is any suitable material and can be the same or different from each of the first material and the second material. In some embodiments, the third material is a dielectric. In some embodiments, the third material is SiO2, which is deposited, for example, by PECVD or HDP (high density plasma) CVD.

[0061] Advantageously, the etching process for SnO2 provided herein does not require wet etching and does not require exposure to fluorine-containing chemicals. Advantageously, the etching process can be performed on a substrate having a very narrow width (e.g., ) SnO2 layer without causing structural collapse of the device. Structural collapse is a problem encountered during wet etching of spacers with very small dimensions. In general, the width of the SnO2 layer in the air gap formation sequence can vary over a wide range (e.g., ), but the provided method is suitable for processing Substrates with narrow SnO2 spacers are particularly advantageous.

[0062] According to one of the embodiments, Figures 3A-3G An example of a processing sequence for forming an air gap is provided in , which shows a schematic cross-sectional view of a semiconductor substrate during air gap formation. Figures 3A-3E 1 shows processing steps that can be used to obtain a substrate including an exposed SnO2 layer between an exposed first material layer and an exposed second material layer. It should be understood that various other methods can be used to obtain such a substrate. The method shown includes forming a gate 301 on a substrate 303, producing a gate 301 as shown in FIG. Figure 3A The gate is a protruding feature on the substrate. In some embodiments, the gate 301 is a high-k oxide, such as, for example, hafnium oxide. Next, as Figure 3B As shown, a first material layer 305 is conformally formed on the substrate such that it covers the substrate 303 and the gate 301. Importantly, the layer 305 covers the gate 301 both on the sidewalls of the gate 301 and on the top surface of the gate 301. In one illustrative example, the layer 305 is a SiN layer. For example, conformal deposition can be achieved by ALD. Next, as shown in FIG. Figure 3C As shown, a SnO2 layer 307 is conformally formed on layer 305. The SnO2 layer 307 is in contact with the underlying layer 305 and is located above the substrate 303 and above the gate 301. The SnO2 layer covers the gate at both the sidewalls of the gate and the top surface of the gate. The SnO2 layer can be deposited by ALD or PECVD. Next, a second material layer 309 is conformally deposited on the SnO2 layer 307 above the substrate, producing a Figure 3D The structure shown. In some embodiments, the second material is SiO2. The second material contacts the SnO2 layer and is located above the substrate 303 and the gate 301, covering the gate at both the sidewalls of the gate and the top surface of the gate. In the next step, the structure is planarized (e.g., using chemical mechanical polishing). This step removes the second material (e.g., SiO2) layer from the top surface of the gate and exposes the SnO2 layer at the sidewalls of the gate. Figure 3E The structure shown shows the substrate after planarization. It shows that the exposed SnO2 layer 307 is located between the exposed first material layer 305 and the exposed second material layer 309 at the sidewall of the gate. This structure can be Figure 22201 of the process flow diagram shown in FIG. 2202. If the SnO2 layer is deposited substantially conformally, the thickness of the SnO2 layer deposited on the horizontal surface will be similar to the width of the SnO2 layer exposed on the gate sidewalls. For example, if the SnO2 layer is deposited to a thickness between about The exposed SnO2 layer at the sidewall of the gate will have a thickness between about The width between.

[0063] Next, a hydrogen plasma etch was performed as described herein. Figure 3E The substrate shown in FIG. 1 is contacted with a plasma formed in a process gas containing H2 in an etching chamber, and the exposed SnO2 layer 307 (relative to other exposed materials) is selectively etched to form a recessed feature between the second material layer 309 and the first material layer 305. The resulting structure is Figure 3F , which shows a recessed feature 311 between layer 309 and layer 305. Finally, in a subsequent step, a layer 313 of a third material (e.g., SiO2) is deposited, for example by HDP CVD, such that it covers the recessed feature 311 without completely filling the recessed feature, thereby creating an air gap.

[0064] A more specific example of a method for forming an air gap includes: (a) forming a gate on a substrate, wherein the gate includes a high-k oxide; (b) conformally depositing a SiN layer in contact with the gate (both on the sidewalls of the gate and on the top surface of the gate) by ALD; (c) conformally forming a SnO2 layer on the SiN layer, for example by ALD or PECVD; (d) conformally forming a SiO2 layer on the SnO2 layer; (e) planarizing the structure (e.g., by chemical mechanical polishing), wherein the planarization removes SiO2 from horizontal surfaces and exposes the SnO2 and the first material at the sidewalls of the gate, thereby providing an exposed SiN layer, exposed SiO2, and an exposed SnO2 layer located between these layers; (f) etching the exposed SnO2 with a high etch selectivity relative to SiN and SiO2 using a hydrogen plasma as described herein, thereby forming a recessed feature between the SiN and SiO2 layers; and (g) depositing SiO2 on the recessed feature without completely filling the recessed feature, thereby forming an air gap between the first material layer and the second material layer. In some embodiments, the width of the SnO2 layer deposited and removed by hydrogen plasma etching is about between.

[0065] A detailed process scheme for forming air gaps in FinFET device fabrication is described in U.S. Patent No. 9,515,156, co-owned by Besser et al., entitled “Air Gap Spacer Integration For Improved Fin Device Performance,” published on December 6, 2016, which is incorporated herein by reference in its entirety for purposes of describing air gap formation methods that may be used in conjunction with the SnO2 spacers provided herein. Figures 4A-4T Methods of forming air gaps in the context of FinFET device fabrication according to some embodiments are described, Figures 4A-4T A perspective view of a semiconductor substrate during various stages of FinFET device fabrication is shown.

[0066] In some embodiments, a FinFET device with an air gap spacer and a method of integrating an air gap into a FinFET device using a sacrificial SnO2 spacer are provided. The air gap spacer is formed using a sacrificial SnO2 spacer during the integration process. The sacrificial spacer is then removed after the self-aligned source / drain contacts are formed. The air gap spacer reduces the FinFET parasitic capacitance. Low parasitic capacitance can be achieved without sacrificing process window or relaxing lithography overlay requirements.

[0067] Reference now Figure 4A-4B , respectively, show the substrate after shallow trench spacing (STI) recess etching and formation of a dummy gate. Figure 4A In the embodiment of the present invention, the substrate 100 includes an interlayer dielectric (ILD) layer 110 and a plurality of fins 114. The ILD layer 110 may be made of a low-k dielectric, a doped oxide, a flowable oxide, silicon dioxide (SiO2), or other suitable materials. In some embodiments, the plurality of fins 114 may be made of silicon (Si) with STI oxide inserted therein. The STI oxide may also be located on the top surface of the plurality of fins 114.

[0068] exist Figure 4B In the embodiment of the present invention, a dummy gate 118 is deposited on the plurality of fins 114 and etched. In some embodiments, the dummy gate 118 is arranged on the ILD layer 110 and extends laterally to the plurality of fins 114. In some embodiments, the dummy gate 118 is made of polysilicon. A hard mask layer 122 may be used to mask the dummy gate 118 during etching.

[0069] Reference now Figure 4C-4D , respectively, the sacrificial SnO2 spacer is deposited and etched and the dummy gate is removed. Figure 4C In the embodiment, a sacrificial SnO2 spacer 128 is deposited around the outer surface of the dummy gate 118 and etched, for example, using a hydrogen plasma etch as described herein. Figure 4D In the embodiment, the ILD layer 132 is deposited around the sacrificial SnO2 spacer 128. In addition, the dummy gate 118 and the hard mask layer 122 are removed by etching or ashing. In some embodiments, the silicon forming the dummy gate 118 is selectively etched relative to the SnO2 and the silicon dioxide (SiO2) material of the substrate 100.

[0070] exist Figure 4E , the formation of a replacement metal gate (RMG) is shown. The replacement metal gate (RMG) 138 is deposited at the previous location of the dummy gate 118. In some embodiments, the RMG 138 has a high dielectric (HK) constant and a predetermined thickness between 1 and 10 nm. In some embodiments, the RMG 138 is made of the following materials: a high dielectric constant material, such as hafnium oxide (HfO2), HfSiO2, aluminum oxide (Al2O3), zirconium oxide (ZrO2), or titanium oxide (TiO2); a metal work function setting material, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN x )(where x is an integer), tungsten carbon nitride (WCN x ), cobalt (Co), or other metals; and bulk conductive metals, such as tungsten (W), cobalt (Co), or aluminum (Al) and their alloys. In some embodiments, chemical mechanical polishing (CMP) can be performed after the deposition of RMG 138. In some embodiments, the top surface of RMG 138 after CMP is coplanar with the top surface of the sacrificial SnO2 spacer 128 and the ILD layer 132.

[0071] Reference now Figure 4F , RMG 138 is selectively and partially etched relative to SnO2 and silicon dioxide (SiO2). More specifically, RMG 138 is partially and selectively etched in a downward direction relative to the top surfaces of sacrificial SnO2 spacers 128 and ILD layer 132 to create recesses 139 in RMG 138. A top surface 141 of RMG 138 is located below a plane including the top surfaces of sacrificial SnO2 spacers 128 and ILD layer 132.

[0072] Reference now Figure 4G-4H , respectively showing the gate cap layer deposition and the chemical mechanical polishing (CMP) of the gate cap layer. Figure 4GIn the present invention, the gate cap layer 144 is deposited within the recess in the RMG 138 and on the top surface of the substrate 100. In some embodiments, the gate cap layer 144 can be made of silicon oxycarbide (SiOC) or other suitable materials. In some embodiments, the gate cap layer 144 is deposited using a process as described in commonly assigned U.S. Patent Application Publication No. 2013 / 0330935, entitled "Remote Plasma Based Deposition of SiOC Class Films," filed on December 12, 2013, the entire contents of which are incorporated herein by reference. In some embodiments, the gate cap layer 144 is deposited using the remote plasma process described therein. Figure 4H In the embodiment, CMP of gate cap layer 144 is performed to create gate cap layer 145 onto RMG 138. In some embodiments, a top surface of gate cap layer 145 is coplanar with top surfaces of sacrificial SnO2 spacer 128 and ILD layer 132 after CMP.

[0073] Reference now Figures 4I-4J , respectively showing the self-aligned contact (SAC) region etching, removal of the SAC fill and sacrificial spacers. Fig. 4I In the embodiment, regions of the ILD layer 132 surrounding opposite sides of the plurality of fins 114 are masked and etched using an etch that selectively etches the ILD relative to the gate cap layer and sacrificial SnO 2 spacers to expose the plurality of fins 114 and create self-aligned contact regions.

[0074] exist Figure 4J In the embodiment, the self-aligned contact region is filled with a SAC material 152. In some embodiments, the SAC material 152 includes a metal layer 155 or a barrier layer 153 and a metal layer 155 deposited on the barrier layer 153. In some embodiments, the barrier layer 153 includes a double layer of titanium (Ti) and titanium nitride (TiN), and the metal layer 155 includes tungsten (W), but other materials may also be used, such as WCNx for barrier and Co for metal layer. Figure 4K In the embodiment of the present invention, the sacrificial SnO2 spacer 128 is removed. For example, the sacrificial SnO2 spacer 128 can be selectively etched relative to the exposed material using the hydrogen plasma etching method described herein. For example, the SnO2 material can be present between the SiOC layer 145 and the ILD layer (e.g., doped or undoped SiO2) 132, and can be selectively etched relative to these materials using hydrogen plasma.

[0075] Reference now Figure 4L-4N , a sealing layer is deposited on the substrate and CMP is performed to create air gap spacers. Figure 4LIn the embodiment of the present invention, a sealing layer 156 is deposited on the top surface of the substrate 100. During the deposition process, the upper portion of the air gap 159 created after removing the sacrificial SnO2 spacer 128 is at least partially filled by the sealing layer 156. In some embodiments, the sealing layer 156 is made of ILD, silicon dioxide (SiO2), carbon-doped silicon dioxide, or silicon oxycarbide (SiOC). In some embodiments, the sealing layer 156 is deposited using plasma enhanced chemical vapor deposition (PECVD), but other deposition processes may also be used.

[0076] In some embodiments, sealing layer 156 comprises SiCO deposited using plasma enhanced chemical vapor deposition such as described in commonly assigned U.S. Patent Application Publication No. 2013 / 0330935, entitled “Remote Plasma Based Deposition of SiOC Class Films,” previously incorporated by reference.

[0077] exist Figure 4M In the embodiment, CMP is used to remove a portion of the sealing layer 156 located on the top surface of the substrate 100 to create an air gap seal 157. In some embodiments, the top surface of the air gap seal 157 is coplanar with the top surfaces of the gate cap layer 145 and the ILD layer 132 after CMP. Figure 4N , a cross section of the substrate is shown along a plane parallel to and spaced apart from the plurality of fins 114. An air gap 159 is located below the air gap seal 157.

[0078] Reference now Fig.4O , an etch stop layer 164 is deposited on the top surface of the substrate 100. In some embodiments, the etch stop layer 164 comprises SiOC, but other materials may also be used. In some embodiments, the SiOC is deposited as described in the commonly assigned U.S. Patent Application Publication No. 2013 / 0330935 entitled "Remote Plasma Based Deposition of SiOC Class Films", the entire contents of which are incorporated herein by reference. An ILD layer 166 is deposited on the etch stop layer 164.

[0079] Reference now Figure 4P-4T , various etching steps are performed to open different parts of the substrate. Figure 4P-4Q In FIG. 1 , various embodiments of etching steps are shown. Figure 4P In the embodiment of the present invention, the ILD layer 166 is etched to selectively expose the underlying layers in the portion 190 of the etch stop layer 164. Figure 4QIn the process, the etch stop layer 164 is etched to open portions of the gate cap layer 145, the air gap seal 157, the metal layer 155, and the ILD layer 132 for further processing.

[0080] exist Figure 4R and 4S In the embodiment of the present invention, the ILD layer 166 and the etch stop layer 164 are etched to selectively expose the underlying layers in the portion 192 of the substrate 100. Figure 4S In FIG. 1 , various portions of the air gap seal 157 , the metal layer 155 , and the ILD layer 132 are opened for further processing.

[0081] exist Figure 4T , the ILD layer 166 is patterned and etched to expose the underlying layers in the portions 198 and 200 of the substrate 100. The air gap seal 157, the metal layer 155, the RMG 138, and a portion of the ILD layer 132 are opened for further processing. It is understood that various other sub-layers may be opened for further processing.

[0082] Other Implementations

[0083] In various other embodiments, the SnO2 layer and hydrogen plasma etching may be used in the following applications.

[0084] In some embodiments, the SnO2 layer is used as a dummy gate instead of the conventional polysilicon dummy gate. For example, in this embodiment, the above reference is modified Figures 4A-4TThe process flow described is such that the dummy gate 118 is made of SnO2 and the spacer 128 is made of a material that does not contain SnO2. For example, in this embodiment, the spacer 128 can be a SiN spacer. The modified method includes etching the dummy gate 118 using an H2 plasma chemistry to remove the dummy gate. In one embodiment, the method includes forming a SnO2 dummy gate on a semiconductor substrate; processing the semiconductor substrate in the presence of the SnO2 dummy gate, wherein the processing may involve deposition and / or etching of materials on the semiconductor substrate; etching the SnO2 dummy gate using a plasma formed in a process gas including H2 to form a recessed feature to replace the dummy gate, and depositing a high-k dielectric material into the formed recessed feature to form a gate to replace the dummy gate. In some embodiments, hydrogen plasma etching during dummy gate removal involves etching using a plasma formed in a process gas including at least about 50% H2 and at a temperature below about 100°C. In some embodiments, the etching is performed selectively with respect to one or more materials selected from the group consisting of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, and SiCN materials, which may be exposed on the substrate prior to etching or become exposed during etching. Advantages of using SnO2 for the dummy gate and using H2 plasma for the dummy gate etching include ease of selective removal of SnO2 with respect to SiO2 and low-k spacers and high temperature resistance.

[0085] In other embodiments, the SnO2 layer is used as a high resistance resistor in BEOL applications. This is a useful application because polysilicon is not available in BEOL.

[0086] In other embodiments, a SnO2 layer is used as an implant barrier. This application requires low deposition temperatures for SnO2 deposition, and highly selective removal that can be achieved by hydrogen plasma etching. Advantageously, no HF immersion is required when hydrogen plasma removal is used.

[0087] Device

[0088] The hydrogen plasma etching method described herein can be performed in a variety of apparatuses. Suitable apparatuses include an etching process chamber, a substrate holder in the etching process chamber configured to hold the substrate in position during etching, and a plasma generating mechanism configured to generate plasma in a process gas.

[0089] Examples of suitable apparatus include inductively coupled plasma (ICP) reactors, which in certain embodiments may also be suitable for cyclic deposition and activation processes including atomic layer etching (ALE) operations and atomic layer deposition (ALD) operations. Such ICP reactors are also described in U.S. Patent No. 9,362,133, entitled “Method for Forming a Mask by Etching Conformal Film on Patterned Ashable Hardmask,” published on June 7, 2016, which is incorporated herein by reference in its entirety and for all purposes. Although an ICP reactor is described in detail herein, it should be understood that a capacitively coupled plasma reactor may also be used.

[0090] Figure 5 A cross-sectional view of an inductively coupled plasma integrated etch and deposition apparatus 400 suitable for performing the hydrogen plasma etch described herein is schematically shown, an example of which is manufactured by Lam Research Corp. located in Fremont, California. Reactor. The inductively coupled plasma device 400 includes an entire processing chamber 424 that is structurally defined by a chamber wall 401 and a window 411. The chamber wall 401 can be made of stainless steel or aluminum. The window 411 can be made of quartz or other dielectric materials. An optional internal plasma grid 450 divides the entire processing chamber into an upper sub-chamber 402 and a lower sub-chamber 403. In most embodiments, the plasma grid 450 can be removed, thereby utilizing the chamber space formed by the sub-chambers 402 and 403. The chuck 417 is located in the lower sub-chamber 403, near the bottom inner surface. The chuck 417 is configured to receive and hold a semiconductor wafer 419, and etching and deposition processes are performed on the semiconductor wafer 419. The chuck 417 can be an electrostatic chuck for supporting the wafer 419 when the wafer 419 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 417 and has an upper surface that is approximately flat with the top surface of the wafer 419 when the wafer 419 is present above the chuck 417. The chuck 417 also includes electrostatic electrodes for clamping and releasing the wafer 419. A filter and a DC clamping power supply (not shown) may be provided for this purpose. Other control systems for lifting the wafer 419 off the chuck 417 may also be provided. The chuck 417 may be charged using an RF power supply 423. The RF power supply 423 is connected to a matching circuit 421 via a connection 427. The matching circuit 421 is connected to the chuck 417 via a connection 425. In this manner, the RF power supply 423 is connected to the chuck 417. In various embodiments, the bias power of the electrostatic chuck may be set to approximately 50 Vb or may be set to a different bias power, depending on the process performed according to the disclosed embodiments. For example, the bias power may be between about 20 Vb and about 100 Vb, or between about 30 Vb and about 150 Vb.

[0091] Elements for plasma generation include a coil 433 located above the window 411. In some embodiments, no coil is used in the disclosed embodiments. The coil 433 is made of a conductive material and includes at least one complete turn. Figure 5The example of the coil 433 shown in includes three turns. The cross-section of the coil 433 is shown with symbols, and the coil with an "X" extends rotationally into the page, while the coil with a "●" extends rotationally out of the page. The element for plasma generation also includes an RF power supply 441 configured to provide RF power to the coil 433. Typically, the RF power supply 441 is connected to the matching circuit 439 via connection 445. The matching circuit 439 is connected to the coil 433 via connection 443. In this way, the RF power supply 441 is connected to the coil 433. An optional Faraday shield 449a is positioned between the coil 433 and the window 411. The Faraday shield 449a can maintain a spaced relationship relative to the coil 433. In some embodiments, the Faraday shield 449a is disposed directly above the window 411. In some embodiments, the Faraday shield 449b is located between the window 411 and the chuck 417. In some embodiments, the Faraday shield 449b does not maintain a spaced relationship relative to the coil 433. For example, the Faraday shield 449b may have no gap directly below the window 411. The coil 433, the Faraday shield 449a, and the window 411 are each configured to be substantially parallel to each other. The Faraday shield 449a may prevent metal or other substances from being deposited on the window 411 of the process chamber 424.

[0092] Process gases (e.g., H2 and He, etc.) can flow into the processing chamber through one or more main gas flow inlets 460 located in the upper sub-chamber 402 and / or through one or more side gas flow inlets 470. Similarly, although not explicitly shown, similar gas flow inlets can be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump (e.g., a one-stage or two-stage mechanical dry pump and / or a turbomolecular pump 440) can be used to extract process gases from the processing chamber 424 and maintain the pressure in the processing chamber 424. For example, a vacuum pump can be used to evacuate the lower sub-chamber 403 during a purge operation. A valve-controlled conduit can be used to connect the vacuum pump fluid to the processing chamber 424 so as to selectively control the application of the vacuum environment provided by the vacuum pump. This can be accomplished using a closed-loop controlled flow restriction device (e.g., a throttle valve (not shown) or a swing valve (not shown)) during the operation of the plasma process. Similarly, a vacuum pump and a valve-controlled fluid connection to the capacitively coupled plasma processing chamber can also be used.

[0093] During operation of the device 400, one or more process gases, such as H2-containing gases, can be supplied through gas flow inlets 460 and / or 470. In some embodiments, the process gas can be supplied only through the main gas flow inlet 460, or only through the side gas flow inlet 470. In some cases, the gas flow inlet shown in the figure can be replaced by a more complex gas flow inlet (e.g., one or more nozzles). Faraday shield 449a and / or optional grid 450 may include internal channels and holes that allow process gases to be delivered to the processing chamber 424. Any one or both of the Faraday shield 449a and the optional grid 450 can be used as a nozzle for delivering process gases. In some embodiments, the liquid vaporization and delivery system can be located upstream of the processing chamber 424, so that once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the processing chamber 424 via gas flow inlet 460 and / or 470.

[0094] RF power is provided to the coil 433 from the RF power supply 441 to cause an RF current to flow through the coil 433. The RF current flowing through the coil 433 generates an electromagnetic field around the coil 433. The electromagnetic field generates an induced current in the upper sub-chamber 402. The physical and chemical interactions of the various generated ions and radicals with the wafer 419 selectively etch features of the wafer and selectively deposit layers on the wafer 419.

[0095] If a plasma grid 450 is used so that both an upper sub-chamber 402 and a lower sub-chamber 403 are present, an induced current acts on the gas present in the upper sub-chamber 402 to produce an electron-ion plasma in the upper sub-chamber 402. The optional internal plasma grid 450 limits the amount of hot electrons in the lower sub-chamber 403. In some embodiments, the apparatus 400 is designed and operated so that the plasma present in the lower sub-chamber 403 is an ion-ion plasma.

[0096] Both the upper electron-ion plasma and the lower ion-ion plasma can contain positive and negative ions, although the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etching and / or deposition byproducts can be removed from the lower sub-chamber 403 through port 422. For example, SnH4 produced during etching of SnO2 using H2 plasma can be removed through port 422 during purging and / or extraction. The chuck 417 disclosed herein can operate at an elevated temperature between about 10°C and about 250°C. The temperature will depend on the process operation and the specific recipe. In some embodiments, the control device etches at a temperature below about 100°C.

[0097] The apparatus 400 can be coupled to a facility (not shown) when installed in a clean room or manufacturing facility. The facility includes plumbing that provides process gases, vacuum, temperature control, and environmental particle control. When installed in the target manufacturing facility, these facilities are coupled to the apparatus 400. In addition, the apparatus 400 can be coupled to a transfer chamber that allows a robot to transfer semiconductor wafers into and out of the apparatus 400 using typical automation techniques.

[0098] In some embodiments, a system controller 430 (which may include one or more physical or logical controllers) controls some or all of the operations of the process chamber 424. The system controller 430 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 400 includes a switching system for controlling the flow rate of process gases. In some embodiments, the controller includes program instructions for causing the steps of any of the methods provided herein.

[0099] In some implementations, the controller 430 is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronic devices can be integrated into the system controller 430, which can control various components or subcomponents of one or more systems. Depending on the processing parameters and / or system type, the system controller can be programmed to control any process disclosed herein, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer delivery in and out of tools and other delivery tools and / or load locks connected to or interfaced with a specific system.

[0100] In a broad sense, the system controller 430 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the controller in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0101] In some implementations, the system controller 430 may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or in all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, study trends or performance criteria from multiple manufacturing operations, change the parameters of the current process, set the processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then delivered from the remote computer to the system. In some examples, the system controller 430 receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the system controller 430 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0102] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0103] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0104] Figure 6 A semiconductor processing cluster architecture with various modules that interface with a vacuum transfer module 538 (VTM) is depicted. The arrangement of various modules that "transfer" wafers between multiple storage facilities and processing modules can be referred to as a "cluster tool architecture" system. The airlock 530 (also referred to as a load lock or transfer module) interfaces with the VTM 538, which in turn interfaces with four processing modules 520a-520d that can be individually optimized to perform various manufacturing processes. For example, the processing modules 520a-520d can be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. In some embodiments, SnO2 deposition and SnO2 etching are performed in the same module. In some embodiments, SnO2 deposition and SnO2 etching are performed in different modules of the same tool. One or more substrate etching processing modules (any one of 520a-520d) can be implemented as disclosed herein, for example, for depositing conformal films, selectively etching SnO2, forming air gaps, and other suitable functions according to the disclosed embodiments. The airlocks 530 and processing modules 520a-520d may be referred to as “stations.” Each station has a facet 536 that interfaces the station with a VTM 538. Within each facet, sensors 1-18 are used to detect the passage of wafers 526 as they move between stations.

[0105] The robot 522 transfers wafers 526 between stations. In one embodiment, the robot 522 has one arm, and in another embodiment, the robot 522 has two arms, where each arm has an end effector 524 to pick up a wafer (e.g., wafer 526) for transport. In the atmospheric transport module (ATM) 540, the front end robot 532 is used to transfer the wafer 526 from the box or front opening unpacking box (FOUP) 534 in the load port module (LPM) 542 to the airlock 530. The module center 528 within the processing module 520a-520d is a location for placing the wafer 526. The aligner 544 in the ATM 540 is used to align the wafer.

[0106] In an exemplary processing method, a wafer is placed in one of the FOUPs 534 in the LPM 542. The front-end robot 532 transfers the wafer from the FOUP 534 to the aligner 544, which enables the wafer 526 to be properly centered before being etched or processed. After alignment, the wafer 526 is moved into the airlock 530 by the front-end robot 532. Since the airlock 530 has the ability to match the environment between the ATM 540 and the VTM 538, the wafer 526 can move between the two pressure environments without being damaged. From the airlock 530, the wafer 526 is moved by the robot 522 via the VTM 538 to one of the processing modules 520a-520d. To achieve this wafer movement, the robot 522 uses an end effector 524 on each of its arms. Once the wafer 526 has been processed, it is moved from the processing module 520a-520d to the airlock 530 by the robot 522. From here, the wafer 526 can be moved by the front end robot 532 to one of the FOUPs 534 or to the aligner 544.

[0107] It should be noted that the computer controlling the wafer movement may be local to the cluster architecture, or may be located outside the cluster architecture in the manufacturing shop or at a remote location and connected to the cluster architecture via a network. Figure 5 The controller described can utilize Figure 6 A machine-readable medium containing instructions for controlling process operations according to the present invention may be coupled to a system controller.

[0108] In some embodiments, an apparatus is provided, wherein the apparatus comprises: a processing chamber having a substrate holder configured to hold the semiconductor substrate during etching; a plasma generator configured to generate plasma in a process gas; and a controller. The controller comprises program instructions for implementing any of the methods described herein. In one embodiment, the controller comprises program instructions for causing the etching of the SnO2 layer on the semiconductor substrate at a temperature below about 100°C, wherein causing the etching comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least about 50% H2.

[0109] In another aspect, a non-transitory computer machine readable medium is provided, comprising code for causing the etching of the SnO2 layer on the semiconductor substrate at a temperature below about 100°C, wherein causing the etching comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least about 50% H2.

[0110] In another aspect, a system for forming an air gap on a semiconductor substrate is provided. The system includes: one or more deposition processing chambers; one or more etching chambers; and a controller. The controller includes program instructions for implementing any of the air gap forming methods described herein. For example, the controller may include instructions for causing the following steps: (i) selectively etching the exposed SnO2 relative to both the first material and the second material on a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer between the first material layer and the second material layer using a hydrogen plasma etching chemistry, thereby forming a recessed feature between the first material and the second material; and (ii) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer.

[0111] In another aspect, the system includes any one of the apparatus and systems described herein and a stepper.

[0112] In another aspect, a non-transitory computer machine-readable medium is provided, comprising code for: (i) selectively etching the exposed SnO2 relative to both the first material and the second material using a hydrogen plasma etching chemistry on a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer located between the first material layer and the second material layer, thereby forming a recessed feature between the first material and the second material; and (ii) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer.

[0113] Further implementation plans

[0114] The apparatus and processes described herein can be used in conjunction with photolithographic patterning tools or processes, for example, for preparing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, these apparatus and processes will be used or operated together in a common manufacturing facility. The photolithographic patterning of a film typically includes some or all of the following steps, each of which enables multiple feasible tools: (1) applying a photoresist to a workpiece, i.e., a substrate, using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or heating furnace or UV curing tool; (3) exposing the photoresist to visible light or ultraviolet light or X-rays using a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern to an underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

Claims

1. A method for processing a semiconductor substrate, the method comprising: (a) sequentially exposing the semiconductor substrate to a tin-containing precursor and an oxygen-containing precursor to deposit SnO2 and form a semiconductor substrate having an exposed SnO2 layer; (b) etching the SnO2 layer at a temperature below 100°C, wherein the etching comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least 50% H2 to form volatile tin hydride.

2. The method according to claim 1, wherein the tin-containing precursor has the general formula R x -Sn-A 4-x , wherein R is selected from the group consisting of hydrogen, alkyl, alkenyl and alkynyl, and A=YR' z , wherein Y is N, R′ is selected from the group consisting of alkyl, alkenyl, and alkynyl, x is 0, 1, 2, or 3, and z is 2.

3. The method according to claim 2, wherein A = YR' z Each R' in is the same.

4. The method of claim 3, wherein the tin-containing precursor is tetrakis(dimethylamino)tin.

5. The method according to claim 2, wherein A = YR' z Each R' in is different.

6. The method of claim 5, wherein the tin-containing precursor is tetrakis(ethylmethylamino)tin.

7. The method according to claim 2, wherein the tin-containing precursor is selected from N 2 ,N 3 -di-tert-butyl-butane-2,3-diaminotin(II) and 1,3-bis(1,2-methylethyl)-4,5-dimethyl-(4R,5R)-1,3,2-diazastannane-2-ylidene.

8. The method of claim 1, wherein the tin-containing precursor is an alkyl-substituted tin amide.

9. The method of claim 1, wherein the oxygen-containing precursor is selected from the group consisting of oxygen, ozone, water, hydrogen peroxide, and NO.

10. The method of claim 1, wherein depositing the SnO2 layer comprises purging a process chamber with an inert gas between exposing the semiconductor substrate to the tin-containing precursor and exposing the substrate to the oxygen-containing precursor.

11. The method of claim 1, wherein depositing the SnO2 layer is performed under processing parameters that maintain the tin-containing precursor and the oxygen-containing precursor separate from the gas phase.

12. The method of claim 11, wherein the process parameter is a temperature of the process chamber between 20°C and 500°C.

13. The method of claim 11, wherein the process parameter is a flow rate at which the tin-containing precursor and the oxygen-containing precursor each independently flow between 10 sccm and 10,000 sccm.

14. The method according to claim 1, wherein: The tin-containing precursor and the oxygen-containing precursor are each independently combined with a carrier gas selected from the group consisting of helium, argon, and nitrogen.

15. The method according to claim 1, wherein: The deposition of the SnO2 layer was performed using atomic layer deposition.

16. The method according to claim 15, wherein: The deposition of the SnO2 layer was performed using plasma enhanced atomic layer deposition.

17. An apparatus for semiconductor processing, the apparatus comprising at least one processing chamber and a controller containing program instructions, the program instructions being configured to cause the following steps: (i) sequentially exposing a semiconductor substrate to a tin-containing precursor and an oxygen-containing precursor to deposit SnO2 and form a semiconductor substrate having an exposed SnO2 layer; (ii) etching the SnO2 layer at a temperature below 100°C, wherein the etching comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least 50% H2 to form volatile tin hydride.

18. The apparatus of claim 17, wherein the tin-containing precursor has the general formula R x -Sn-A 4-x , wherein R is selected from the group consisting of hydrogen, alkyl, alkenyl and alkynyl, and A=YR'z, wherein Y=N, R'=alkyl, alkenyl, alkynyl, x is 0, 1, 2 or 3, and z is 2.

19. A method for creating an air gap on a semiconductor substrate, the method comprising: (a) providing a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer located between the first material layer and the second material layer, wherein the exposed SnO2 layer is formed by sequentially exposing the semiconductor substrate to a tin-containing precursor and an oxygen-containing precursor; (b) etching the exposed SnO2 selectively relative to the first material and the second material using a hydrogen plasma etch chemistry to form a recessed feature between the first material and the second material, wherein the etching includes forming volatile tin hydride; as well as (c) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer.

20. A system for forming an air gap on a semiconductor substrate, the system comprising: (a) one or more deposition processing chambers; (b) one or more etching process chambers; and (c) a controller comprising program instructions for causing the following steps: (i) forming an exposed SnO2 layer by sequentially exposing a semiconductor substrate to a tin-containing precursor and an oxygen-containing precursor; (ii) using a hydrogen plasma etching chemistry on a semiconductor substrate having an exposed first material layer, an exposed second material layer, and an exposed SnO2 layer between the first material layer and the second material layer to selectively etch the exposed SnO2 relative to both the first material and the second material to form a recessed feature between the first material and the second material, wherein the etching includes forming volatile tin hydride; as well as (iii) depositing a third material on the recessed feature without completely filling the recessed feature, thereby forming the air gap between the first material layer and the second material layer.

21. A method for processing a semiconductor substrate, the method comprising: (a) forming a SnO2 dummy gate on the semiconductor substrate by sequentially exposing the semiconductor substrate to a tin-containing precursor and an oxygen-containing precursor; (b) processing the semiconductor substrate in the presence of the SnO2 dummy gate; (c) etching the SnO 2 dummy gate using a plasma formed in a process gas including H 2 to form a recessed feature to replace the dummy gate, wherein the etching includes forming volatile tin hydride; (d) depositing a high-k dielectric material into the formed recessed features to form a gate in place of the dummy gate.

22. A system for processing a semiconductor substrate, the system comprising: (a) one or more deposition processing chambers; (b) one or more etching process chambers; and (c) a controller comprising program instructions for causing the following steps: (i) forming a SnO2 dummy gate on the semiconductor substrate by sequentially exposing the semiconductor substrate to a tin-containing precursor and an oxygen-containing precursor; (ii) processing the semiconductor substrate in the presence of the SnO2 dummy gate; (iii) etching the SnO 2 dummy gate using a plasma formed in a process gas including H 2 to form a recessed feature to replace the dummy gate, wherein the etching includes forming volatile tin hydride; (iv) depositing a high-k dielectric material into the formed recessed features to form a gate in place of the dummy gate.

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