Display device, device for manufacturing the same, and method for manufacturing the same

Abstract

A display device, a device for manufacturing the same, and a method for manufacturing the same are provided. The display device comprises: a substrate, comprising a first display area, a second display area, and a third display area, the first display area comprises a first pixel area, a second pixel area, and a first transmission area, the second display area is adjacent to the first display area, the second display area comprises a third pixel area, a fourth pixel area, a second transmission area, and a third transmission area, and the third display area is adjacent to the second display area.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0085820 filed on July 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Aspects of some example embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0003] The display device can be used for various purposes. In addition, as the thickness and weight of the display device have been reduced as technology has advanced, the use range of the display device has increased.

[0004] Depending on the purpose of the display device, different methods may be used to design the shape of the display device, and different functions may be embedded in or linked to the display device.

[0005] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0006] One or more example embodiments include a display device including a sensor area in which a sensor or other suitable component can be arranged in the display area. Some example embodiments may also include an apparatus for manufacturing a display device and a method for manufacturing a display device. However, the above technical features are only examples, and the scope of the disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the disclosed presented example embodiments.

[0008] According to some example embodiments, a display device includes: a substrate including a first display area, a second display area, and a third display area, the first display area including a first pixel area, a second pixel area, and a first transmission area, the second display area is arranged adjacent to the first display area, the second display area includes a third pixel area, a fourth pixel area, a second transmission area, and a third transmission area, the third display area is arranged adjacent to the second display area; first pixels arranged in the first pixel area, each of the first pixels including a first pixel electrode, a first pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes; second pixels arranged in the second pixel area, each of the first pixels including a first pixel electrode, a first pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes; each comprising a second pixel electrode, a second pair of electrodes, and a second intermediate layer between the second pixel electrode and the second pair of electrodes; third pixels arranged in a third pixel area, each of the third pixels comprising a third pixel electrode, a third pair of electrodes, and a third intermediate layer between the third pixel electrode and the third pair of electrodes; and fourth pixels arranged in a fourth pixel area, each of the fourth pixels comprising a fourth pixel electrode, a fourth pair of electrodes, and a fourth intermediate layer between the fourth pixel electrode and the fourth pair of electrodes, wherein the third pair of electrodes is connected to the first pair of electrodes or the second pair of electrodes, the third pair of electrodes and the fourth pair of electrodes are connected to each other, and the third pair of electrodes and the fourth pair of electrodes have different planar areas from each other.

[0009] According to some example embodiments, the first pixel region, the second pixel region, and the first transmission region may be alternately arranged as a grid.

[0010] According to some example embodiments, the first transmission region may be defined as a region defined by the first pixel region and the second pixel region connected to each other.

[0011] According to some example embodiments, the first pair of electrodes and the second pair of electrodes may partially surface-contact each other.

[0012] According to some example embodiments, the second pair of electrodes may be arranged on the first pair of electrodes in the surface contact region.

[0013] According to some example embodiments, the first transmission region and the third transmission region may have different shapes from each other.

[0014] According to some example embodiments, the light transmittance of the first display area may be different from the light transmittance of at least one of the second display area and the third display area.

[0015] According to some example embodiments, the first display area may provide an image having a resolution lower than a resolution of an image provided by at least one of the second display area and the third display area.

[0016] According to some example embodiments, the main pixels may be arranged in the third display area, each of the main pixels may include a main pixel electrode, a main counter electrode, and a main intermediate layer between the main pixel electrode and the main counter electrode, and the main counter electrode may be arranged on the entire surface of the third display area.

[0017] According to some example embodiments, the main counter electrode may be connected to a fourth counter electrode in the second display area.

[0018] According to some example embodiments, a plurality of main counter electrodes having a stripe (also referred to as a bar) shape may be provided, and the plurality of main counter electrodes may be spaced apart from each other.

[0019] According to some example embodiments, a display device includes: a substrate including a first display area, a second display area, and a third display area, the first display area including a first pixel area, a second pixel area, and a first transmission area, the second display area is arranged adjacent to the first display area, the second display area includes a third pixel area, a fourth pixel area, a second transmission area, and a third transmission area, and the third display area is arranged adjacent to the second display area; first pixels arranged in the first pixel area, each of the first pixels including a first pixel electrode, a first pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes; second pixels arranged in the second pixel area, each of the second pixels including a second pixel electrode, a second pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes a second intermediate layer between the second pixel electrode and the second pair of electrodes; third pixels arranged in the third pixel area, each of the third pixels comprising a third pixel electrode, a third pair of electrodes and a third intermediate layer between the third pixel electrode and the third pair of electrodes; fourth pixels arranged in the fourth pixel area, each of the fourth pixels comprising a fourth pixel electrode, a fourth pair of electrodes and a fourth intermediate layer between the fourth pixel electrode and the fourth pair of electrodes; and a component arranged on the surface of the substrate so as to correspond to the first display area, the component comprising an electronic element that emits or receives light, wherein the third pair of electrodes is connected to the first pair of electrodes or the second pair of electrodes, the third pair of electrodes and the fourth pair of electrodes are connected to each other, and the third pair of electrodes and the fourth pair of electrodes have different planar areas from each other.

[0020] According to some example embodiments, the component may emit or receive light passing through the first transmission area, and light transmittance of the second display area and light transmittance of the third display area may be smaller than light transmittance of the first display area.

[0021] According to some example embodiments, an apparatus for manufacturing a display device includes: a chamber, a portion of which is selectively opened / closed; a first support member arranged in the chamber, the first support member supporting a substrate; a mask assembly arranged in the chamber, the mask assembly facing the substrate; a second support member arranged in the chamber, the second support member supporting the mask assembly; and a deposition source arranged in the chamber, the deposition source supplying a deposition material onto the substrate, wherein the mask assembly includes a first mask assembly and a second mask assembly that are replaceable with each other, the second mask assembly including: a mask frame; and a mask sheet mounted on the mask frame, and the mask sheet includes a first opening, a second opening arranged in a portion different from the first opening in the mask sheet, and a third opening arranged in a portion different from the first opening and the second opening in the mask sheet, wherein the second opening is connected to the third opening, the first opening is separated from the second opening and the third opening, the first opening and the second opening have shapes different from each other, and an area of ​​the first opening is smaller than an area of ​​the second opening.

[0022] According to some example embodiments, the deposition source may be in a corner of the chamber.

[0023] According to some example embodiments, the first opening may have a square shape, and the second opening may have a rectangular shape.

[0024] According to some example embodiments, at least one of the first support and the second support may adjust a position of the substrate relative to the first mask assembly.

[0025] According to some example embodiments, the plurality of third openings may be provided to be spaced apart from each other, and each of the plurality of third openings may be provided in a line shape.

[0026] According to some example embodiments, a method for manufacturing a display device includes: arranging a substrate and a first mask assembly in a chamber; forming a first pair of electrodes in a first display region of the substrate by using a deposition material that has been supplied from a deposition source and has passed through the first mask assembly; changing a position of at least one of the substrate and the first mask assembly; forming a second pair of electrodes in the first display region by using a deposition material that has been supplied from a deposition source and has passed through the first mask assembly, the first pair of electrodes and the second pair of electrodes at least partially overlapping each other, and after replacing the first mask assembly with the second mask assembly and supplying the deposition material from the deposition source onto the substrate, forming a third pair of electrodes and a fourth pair of electrodes in the second display region, forming a main pair of electrodes in a third display region of the substrate, wherein the third pair of electrodes connects one of the first pair of electrodes and the second pair of electrodes to the fourth pair of electrodes, and the third pair of electrodes and the fourth pair of electrodes have different planar areas from each other.

[0027] According to some example embodiments, a first transmission region may be disposed between the first pair of electrodes and the second pair of electrodes.

[0028] According to some example embodiments, the first pair of electrodes and the second pair of electrodes may partially surface-contact each other.

[0029] According to some example embodiments, a second transmission region may be provided between one of the first and second pairs of electrodes, the third pair of electrodes, and the fourth pair of electrodes, and a third transmission region may be provided between one of the first and second pairs of electrodes, the third pair of electrodes, the fourth pair of electrodes, and the main pair of electrodes.

[0030] According to some example embodiments, the second transmission region and the third transmission region may have shapes different from each other.

[0031] According to some example embodiments, the first display area may provide an image having a resolution lower than a resolution of an image provided by at least one of the second display area and the third display area.

[0032] According to some example embodiments, the light transmittance of the first display area may be different from the light transmittance of at least one of the second display area and the third display area.

[0033] According to some example embodiments, a light transmittance of the second display region may be smaller than a light transmittance of the first display region and greater than a light transmittance of the third display region.

[0034] Other aspects, features, and characteristics of the disclosure will become better understood with regard to the accompanying drawings, claims, and detailed description.

[0035] Such general and specific aspects of some example embodiments of the present disclosure may be performed using systems, methods, computer-readable storage media, and / or a combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects, features and characteristics of certain example embodiments disclosed will become more apparent through the following description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 is a perspective view of a display device according to some example embodiments;

[0038] Figure 2 is a cross-sectional view of a display device according to some example embodiments;

[0039] Figure 3 is a plan view of a display panel according to some example embodiments;

[0040] Figure 4 It is shown Figure 3 a plan view of an enlarged view of a first display area;

[0041] Figure 5 and Figure 6 is an equivalent circuit diagram of a pixel in a display panel according to some example embodiments;

[0042] Figure 7 is a diagram of a pixel circuit in a pixel according to some example embodiments;

[0043] Figure 8 It is along Figure 7 A cross-sectional view taken along line II-I' and line II-II';

[0044] Fig. 9 and Fig.10 is a plan view showing a portion of a first display area according to some example embodiments;

[0045] Fig.11 and Fig.12 It is along Fig. 9 A cross-sectional view taken along line BB' for illustrating some manufacturing processes of a display panel according to some example embodiments;

[0046] Fig.13 It is along Fig. 9 A cross-sectional view taken along line BB';

[0047] Fig.14 is a plan view of an arrangement of counter electrodes in a display panel according to some example embodiments;

[0048] Fig.15 It is along Fig.14 A cross-sectional view taken along line CC';

[0049] Fig.16 It is along Fig.14 A cross-sectional view taken along line D-D';

[0050] Fig.17 is a cross-sectional view of an apparatus for manufacturing a display device according to some example embodiments;

[0051] Fig.18 According to some example embodiments Fig.17 a perspective view of a first mask assembly;

[0052] Fig.19 is a diagram showing some example embodiments Fig.17 a plan view of a portion of a first mask sheet;

[0053] Fig. 20 is a diagram showing some example embodiments Fig.17 a plan view of a portion of a second mask sheet;

[0054] Fig.21 is a plan view of an arrangement of counter electrodes in a display panel according to some example embodiments;

[0055] Fig. 22 is a diagram showing some example embodiments Fig.17 a plan view of a portion of a second mask sheet;

[0056] Fig.23 is a plan view of an arrangement of counter electrodes in a display panel according to some example embodiments; and

[0057] Fig.24 is a diagram showing some example embodiments Fig.17 A plan view of a portion of a second mask sheet. DETAILED DESCRIPTION

[0058] Because the present disclosure allows for various changes and many embodiments, aspects of some example embodiments will be shown in the drawings and described in more detail in the written description. Reference is made to the drawings for illustrating one or more example embodiments in order to obtain a sufficient understanding, advantages thereof, and some characteristics of some example embodiments. However, the example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein.

[0059] The exemplary embodiments will be described in more detail below with reference to the accompanying drawings. Regardless of the figure number, those components that are the same or corresponding are given the same reference numerals, and redundant descriptions are omitted.

[0060] Although terms such as "first", "second", etc. may be used to describe various components, such components are not limited to the above terms. The above terms are only used to distinguish one component from another.

[0061] An expression used in the singular includes the expression in the plural unless it has an obviously different meaning in the context.

[0062] In this specification, it will be understood that the terms "comprises", "having" and "including" are intended to indicate the presence of the features, quantities, steps, actions, components, parts or combinations thereof disclosed in the specification, and are not intended to exclude the possibility that one or more other features, quantities, steps, actions, components, parts or combinations thereof may exist or may be added.

[0063] It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. That is, for example, there may be intermediate layers, intermediate regions or intermediate components.

[0064] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0065] The X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0066] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially simultaneously or in the reverse order of the described order.

[0067] Figure 1 is a perspective view of a display apparatus 1 according to some example embodiments.

[0068] Reference Figure 1 , the display device 1 includes a display area DA that implements (or displays) an image and a non-display area NDA that does not implement (or display) an image. The display area DA includes a first display area DA1, a second display area DA2, and a third display area DA3. The display device 1 can provide a main image based on light emitted from a plurality of main pixels PXm arranged in the third display area DA3.

[0069] As will be referred to below Figure 2 Described in more detail, at least one of the first display area DA1 and the second display area DA2 may be an area in which a component such as a sensor using infrared rays, visible rays, or sound is arranged. Hereinafter, for ease of description, a case in which a component is arranged in the first display area DA1 will be described, but the embodiment is not limited thereto.

[0070] Therefore, according to some example embodiments, the display device 1 may include a display area DA having a plurality of sub-display areas (e.g., DA1, DA2, and DA3, although the embodiments are not limited to three sub-display areas, and various embodiments may include any suitable number of sub-display areas according to the design of the display device 1). One or more of the sub-display areas may be an area at which a plurality of main pixels PXm for displaying an image are arranged. In addition, one or more of the sub-display areas may be an area at which an image may be displayed by a pixel, but may also be an area at which one or more components (such as a sensor or a transmitter) may be located in order to receive or sense an input signal (e.g., light, sound, etc.) and / or to emit or transmit an output signal (e.g., light, sound, etc.).

[0071] The first display area DA1 may include a first transmission area TA1 through which light and / or sound may be output or emitted from the component to the outside, or through which light and / or sound traveling from an external source may be transmitted to the component. According to some example embodiments, when light is transmitted through the first display area DA1, a light transmittance may be approximately 10% or more, for example, 20% or more, 25% or more, 50% or more, 85% or more, or 90% or more.

[0072] The transmittance of the first display area DA1 may be different from at least one of the transmittance of the second display area DA2 and the transmittance of the third display area DA3. For example, the transmittance of the first display area DA1 may be greater than the transmittance of the second display area DA2 or the transmittance of the third display area DA3. According to some example embodiments, the transmittance of the first display area DA1 may be greater than the transmittance of the second display area DA2 and the transmittance of the third display area DA3. In this case, the transmittance of the second display area DA2 may be greater than the transmittance of the third display area DA3. For example, the transmittance of the second display area DA2 may be equal to the arithmetic mean of the sum of the transmittance of the first display area DA1 and the transmittance of the third display area DA3.

[0073] According to some example embodiments, a plurality of auxiliary pixels PXa may be arranged in the first display area DA1, and an image (e.g., a set or predetermined image) may be provided by using light emitted from the plurality of auxiliary pixels PXa. The image provided from the first display area DA1 is an auxiliary image having a resolution lower than that of an image provided from at least one of the second display area DA2 and the third display area DA3. That is, since the first display area DA1 includes a first transmission area TA1 through which light and / or sound may be transmitted, the number of auxiliary pixels PXa arranged per unit area may be less than the number of connection pixels PXc arranged per unit area in the second display area DA2 or the number of main pixels PXm arranged per unit area in the third display area DA3. According to some example embodiments, the number of auxiliary pixels PXa arranged per unit area in the first display area DA1 may be less than the number of connection pixels PXc arranged per unit area in the second display area DA2 and the number of main pixels PXm arranged per unit area in the third display area DA3. In this case, the number of connection pixels PXc arranged per unit area in the second display area DA2 may be smaller than the number of main pixels PXm arranged per unit area in the third display area DA3.

[0074] Hereinafter, according to some example embodiments, although the display device 1 is described as an organic light emitting display device, the disclosure is not limited thereto. According to some example embodiments, the display device 1 may be an inorganic light emitting display, a quantum dot light emitting display, or the like.

[0075] Reference Figure 1 The first display area DA1 is at one side of the second display area DA2 in a rectangular shape, but is not limited thereto. The first display area DA1 may have a circular shape, an elliptical shape, or a polygonal shape such as a triangle, a pentagon, etc., and the position and number of the first display area DA1 may be variously modified.

[0076] Figure 2 is a cross-sectional view of a display apparatus 1 according to some example embodiments. Figure 2 can correspond to along Figure 1 A cross section taken along line AA'.

[0077] Reference Figure 2 , the display device 1 may include a display panel 10 and an assembly 20 , wherein the display panel 10 includes a display element, and the assembly 20 is under the display panel 10 to correspond to the first display area DA1 .

[0078] The display panel 10 may include a substrate 100, a display element layer 200 on the substrate 100, and a thin film encapsulation layer 300 as an encapsulation member for sealing the display element layer 200. In addition, the display panel 10 may further include a lower protective film 175 disposed under the substrate 100.

[0079] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer.

[0080] The display element layer 200 may include a circuit layer including a thin film transistor TFT, an organic light emitting diode OLED as a display element, and an insulating layer IL between the thin film transistor TFT and the organic light emitting diode OLED.

[0081] In the third display area DA3, main pixels PXm each including a thin film transistor TFT and an organic light emitting diode OLED connected to the thin film transistor TFT are arranged. In the second display area DA2, connection pixels PXc each including a thin film transistor TFT and an organic light emitting diode OLED connected to the thin film transistor TFT are arranged. In the first display area DA1, auxiliary pixels PXa each including a thin film transistor TFT and an organic light emitting diode OLED connected to the thin film transistor TFT are arranged, and lines electrically connected to the main pixels PXm, the connection pixels PXc, and the auxiliary pixels PXa may be arranged.

[0082] In addition, a first transmission area TA1 in which pixels are not arranged may be in the first display area DA1. The first transmission area TA1 may be understood as an area through which light / signals emitted from or incident to the component 20 are transmitted. Similar to the first display area DA1, second and third transmission areas TA2 and TA3 may be in the second display area DA2.

[0083] The component 20 may be in the first display area DA1 and the second display area DA2. For example, the component 20 may be in the first display area DA1. The component 20 may be an electronic component using light or sound. For example, the component 20 may include a sensor that receives light (e.g., an infrared sensor), a sensor that outputs and senses light or sound to measure distance or to sense fingerprints, etc., a small-sized lamp that emits light, or a speaker that outputs sound. Electronic components using light may use light of various bands such as visible light, IR, ultraviolet (UV) rays, etc. A plurality of components 20 may be in the first display area DA1. For example, a light-emitting device and a light-receiving device may be provided as the component 20 in one first display area DA1. Alternatively, one component 20 may include a light-emitting portion and a light-receiving portion.

[0084] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 2 The thin film encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 .

[0085] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. The polymer material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or a combination thereof.

[0086] The lower protective film 175 is attached to the lower portion of the substrate 100 to protect and support the substrate 100. The lower protective film 175 may include an opening 175OP corresponding to the first display area DA1. Since the lower protective film 175 includes the opening 175OP, the light transmittance of the first display area DA1 may be improved. The lower protective film 175 may include polyethylene terephthalate (PET) or polyimide (PI).

[0087] The area of ​​the first display area DA1 may be larger than the area of ​​the region where the components 20 are arranged. Figure 2 , the first display area DA1 is shown to have an area equal to that of the opening 175OP, but the area of ​​the opening 175OP in the lower protective film 175 may not be equal to that of the first display area DA1. For example, the area of ​​the opening 175OP may be smaller than that of the first display area DA1.

[0088] According to some example embodiments, components such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, a transparent window, etc. may be further disposed on the display panel 10 .

[0089] In addition, according to some example embodiments, the thin film encapsulation layer 300 is used as an encapsulation member for encapsulating the display element layer 200, but one or more embodiments are not limited thereto. For example, an encapsulation substrate bonded to the substrate 100 via a sealant or glass frit may be used as a member for encapsulating the display element layer 200.

[0090] Figure 3 is a plan view of a display panel 10 according to some example embodiments. Figure 4 It is shown Figure 3 FIG. 1 is a plan view of an enlarged view of the first display area DA1.

[0091] Reference Figure 3 and Figure 4, various elements of the display panel 10 are on a substrate 100. The substrate 100 includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA includes a second display area DA2, a third display area DA3 in which a main image is displayed, and a first display area DA1 including a first transmission area TA1 and displaying an auxiliary image.

[0092] A plurality of main pixels PXm are in the third display area DA3. A plurality of connection pixels PXc are in the second display area DA2. Each of the main pixels PXm and each of the connection pixels PXc may include a display element such as an organic light emitting diode OLED. Each of the main pixels PXm and each of the connection pixels PXc may emit light (e.g., red light, green light, blue light, or white light) via the organic light emitting diode OLED. In the specification, as described above, each of the main pixels PXm and each of the connection pixels PXc may be understood as a pixel that emits red light, green light, blue light, or white light. The second display area DA2 and the third display area DA3 are referred to above. Figure 2 The described packaging member is covered so as to be protected from external air or moisture.

[0093] The first display area DA1 may be at one side of the second display area DA2, and a plurality of auxiliary pixels PXa may be in the first display area DA1. Each of the auxiliary pixels PXa may include a display element such as an organic light emitting diode OLED. Each of the auxiliary pixels PXa may emit light (e.g., red light, green light, blue light, or white light) via the organic light emitting diode OLED. In the specification, as described above, the auxiliary pixel PXa may be understood as a pixel that emits red light, green light, blue light, or white light. In addition, the first display area DA1 may include a first transmission area TA1.

[0094] Because the first display area DA1 includes the first transmission area TA1, the resolution of the first display area DA1 may be smaller than the resolution of at least one of the second display area DA2 and the third display area DA3. For example, the resolution of the first display area DA1 may be half of the resolution of at least one of the second display area DA2 and the third display area DA3. In some embodiments, the resolution of at least one of the second display area DA2 and the third display area DA3 may be 400 ppi or greater, and the resolution of the first display area DA1 may be approximately 200 ppi or greater.

[0095] The following will refer to Figure 4 The first display area DA1 is described in more detail.

[0096] The first display area DA1 may include an auxiliary pixel area PA1 and a first transmission area TA1, and the auxiliary pixel area PA1 includes at least one auxiliary pixel PXa. The auxiliary pixel area PA1 and the first transmission area TA1 are alternately arranged in the first direction DR1 and the second direction DR2, for example, arranged as a grid. In an exemplary embodiment, when it is described that a region includes an element / component, it means that the element / component is located in the region. Similarly, when it is described that a region does not include an element / component, it means that the element / component is not arranged in the region.

[0097] The auxiliary pixel area PA1 may include an auxiliary pixel Pr emitting red light, an auxiliary pixel Pg emitting green light, and an auxiliary pixel Pb emitting blue light. Figure 4 The pentile type auxiliary pixel PXa is shown, but the auxiliary pixel PXa may have various shapes (eg, a stripe shape, etc.). Figure 4 In FIG. 1 , eight auxiliary pixels PXa are in the auxiliary pixel area PA1 , but the number of the auxiliary pixels PXa may be changed according to the resolution of the first display area DA1 .

[0098] According to some example embodiments, one main pixel PXm, one connection pixel PXc, and one auxiliary pixel PXa may include the same pixel circuits as each other. However, one or more embodiments are not limited thereto. The pixel circuits in the main pixel PXm, the pixel circuits in the connection pixel PXc, and the pixel circuits in the auxiliary pixel PXa may be different from each other.

[0099] The first transmission area TA1 may not include the auxiliary pixel PXa. Not including the auxiliary pixel PXa may mean that the auxiliary pixel PXa does not include a display element such as an organic light emitting diode OLED. That is, it is understood that the first transmission area TA1 does not include a pixel electrode, an intermediate layer and a counter electrode of the organic light emitting diode OLED and a pixel circuit electrically connected to the organic light emitting diode OLED. Some of the signal lines PL, DL, SL and EL connected to supply signals to the auxiliary pixels PXa in the auxiliary pixel area PA1 may pass through the first transmission area TA1. However, even in this case, in order to improve the transmittance of the first transmission area TA1, the signal lines PL, DL, SL and EL may be arched around the center of the first transmission area TA1.

[0100] According to some example embodiments, a conductive layer may be on the substrate 100 corresponding to the auxiliary pixel area PA1 of the first display area DA1. The conductive layer may be below the auxiliary pixel PXa, for example, may be between the thin film transistor of the auxiliary pixel PXa and the substrate 100. The conductive layer may prevent or reduce external light emitted from the component 20 from being incident on the pixel circuit (PC, see for example) of the auxiliary pixel PXa. Figure 5) and the situation affecting the auxiliary pixel PXa. A constant voltage or signal is applied to the conductive layer to prevent damage to the pixel circuit PC due to electrostatic discharge. There may be multiple conductive layers in the first display area DA1, and if necessary, the conductive layers may receive different voltages from each other.

[0101] The second transmission area TA2 and the third transmission area TA3 may be similar to the first transmission area TA1. That is, the second transmission area TA2 and the third transmission area TA3 may not include the connection pixel PXc. Here, the description of not including the connection pixel PXc is similar to the above description of not including the auxiliary pixel PXa, and therefore, its detailed description is omitted here.

[0102] Return to reference Figure 3 Each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa may be electrically connected to a peripheral circuit in the non-display area NDA. In the non-display area NDA, a first scan driving circuit 110, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power line 160, and a second power line 170 may be arranged.

[0103] The first scan driving circuit 110 may provide a scan signal to each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa via a scan line SL. The first scan driving circuit 110 may provide an emission control signal to each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa via an emission control line EL. The second scan driving circuit 120 may be arranged in parallel with the first scan driving circuit 110 and a display area DA may be arranged between the second scan driving circuit 120 and the first scan driving circuit 110. Some of the main pixels PXm, the connection pixels PXc, and the auxiliary pixels PXa arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and the other pixels may be connected to the second scan driving circuit 120. According to some example embodiments, the second scan driving circuit 120 may be omitted.

[0104] The terminal 140 may be arranged at one side of the substrate 100. The terminal 140 may be exposed without being covered by the insulating layer and may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB may transmit a signal or power from the controller to the display panel 10. The control signal generated by the controller may be transmitted to the first scan driving circuit 110 and the second scan driving circuit 120, respectively, via the printed circuit board PCB. The controller may provide a first power voltage ELVDD and a second power voltage (or common voltage) ELVSS (see FIG. 1 ) to the first power line 160 and the second power line 170, respectively, via the first connection line 161 and the second connection line 171. Figure 5 and Figure 6 ). The first power voltage ELVDD is supplied to each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa via the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be provided to the counter electrode of each pixel PXm or PXa connected to the second power line 170.

[0105] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa via the connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Figure 3 It is shown that the data driving circuit 150 is disposed on the printed circuit board PCB, but according to some example embodiments, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be between the terminal 140 and the first power line 160.

[0106] The first power line 160 may include a first sub-line 162 and a second sub-line 163 extending parallel to each other in the X direction with the display area DA interposed therebetween. The second power line 170 has a ring shape having an open side to partially surround the display area DA.

[0107] Figure 5 and Figure 6 is an equivalent circuit diagram of a pixel in the display panel 10 according to some example embodiments.

[0108] Reference Figure 5 and Figure 6 , each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa includes a pixel circuit PC connected to the scan line SL and the data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0109] The pixel circuit PC includes a driving thin film transistor (TFT) T1, a switching TFT T2 and a storage capacitor Cst. The switching TFT T2 is connected to the scan line SL and the data line DL and transmits a data signal Dm input through the data line DL to the driving TFT T1 according to a scan signal Sn input through the scan line SL.

[0110] The storage capacitor Cst is connected to the switching TFT T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage transferred from the switching TFT T2 and a first power voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0111] The driving TFT T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with brightness (e.g., set or predetermined brightness) according to the driving current.

[0112] Figure 5 An example is shown in which the pixel circuit PC includes two TFTs and one storage capacitor, but one or more embodiments are not limited thereto. Figure 6 As shown in , the pixel circuit PC may include seven TFTs and one storage capacitor. Figure 6 In FIG. 1 , the pixel circuit PC includes one storage capacitor Cst, but the pixel circuit PC may include two or more storage capacitors.

[0113] Reference Figure 6 , each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor Cst and a plurality of TFTs. The TFTs and the storage capacitor Cst may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0114] exist Figure 6 In the embodiment, each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa is connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, but one or more embodiments are not limited thereto. According to some example embodiments, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent pixels.

[0115] The signal lines include a scan line SL transmitting a scan signal Sn, a previous scan line SL-1 transmitting a previous scan signal Sn-1 to the first initialization TFT T4 and the second initialization TFT T7, an emission control line EL transmitting an emission control signal En to the operation control TFT T5 and the emission control TFT T6, and a data line DL intersecting the scan line SL and transmitting a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving TFT T1 and the pixel electrode.

[0116] The driving gate electrode G1 of the driving TFT T1 is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line PL via the operation control TFT T5, and the driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 to supply the driving current I to the organic light emitting diode OLED. OLED .

[0117] A switching gate electrode G2 of the switching TFT T2 is connected to the scan line SL, a switching source electrode S2 of the switching TFT T2 is connected to the data line DL, and a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1 and is simultaneously connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 is turned on according to the scan signal Sn received through the scan line SL and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving TFT T1.

[0118] The compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1 and is simultaneously connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6, and the compensation drain electrode D3 of the compensation TFT T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1 to each other and to diode-connect the driving TFT T1.

[0119] A first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line SL-1, a first initialization source electrode S4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL, and a first initialization drain electrode D4 of the first initialization TFT T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1, and performs an initialization operation for initializing the voltage at the driving gate electrode G1 of the driving TFT T1.

[0120] An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL, an operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line PL, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0121] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and the emission control drain electrode D6 of the emission control TFT T6 is electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0122] The operation control TFT T5 and the emission control TFT T6 are simultaneously turned on according to the emission control signal En transmitted through the emission control line EL to transmit the driving voltage ELVDD to the organic light emitting diode OLED and allow the driving current I OLED Flow in organic light-emitting diodes OLED.

[0123] The second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SL-1, the second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0124] Figure 6 A case is shown in which the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1, but one or more embodiments are not limited thereto. According to some example embodiments, the first initialization TFT T4 may be connected to the previous scan line SL-1 to operate according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., a subsequent scan line) to operate according to a signal transmitted to the signal line.

[0125] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED receives the driving current I from the driving TFT T1. OLED And emit light to display images.

[0126] exist Figure 6 In the embodiment, the compensation TFT T3 and the first initialization TFT T4 have double gate electrodes, but the compensation TFT T3 and the first initialization TFT T4 may each have one gate electrode.

[0127] Figure 7 is a diagram of a pixel circuit in a pixel according to some example embodiments. Figure 8 It is along Figure 7 Cross-sectional views taken along line II' and line II-II'.

[0128] Reference Figure 7 and Figure 8 , the driving TFT T1 , the switching TFT T2 , the compensation TFT T3 , the first initialization TFT T4 , the operation control TFT T5 , the emission control TFT T6 , and the second initialization TFT T7 are arranged along the semiconductor layer 1130 .

[0129] The semiconductor layer 1130 is disposed on the substrate 100 on which a buffer layer including an inorganic insulating material is disposed. According to some example embodiments, the semiconductor layer 1130 may include low temperature polysilicon (LTPS). Since polysilicon material has high electron mobility (100 cm 2 / Vs or greater), so polycrystalline silicon material can be used as a semiconductor layer of a TFT in the display device 1 due to its low energy consumption and excellent reliability. However, one or more embodiments are not limited thereto, that is, according to some example embodiments, the semiconductor layer 1130 may include amorphous silicon (a-Si) and / or an oxide semiconductor. Alternatively, the semiconductor layer in some of the plurality of TFTs may include LTPS, and the semiconductor layer in some other TFTs may include a-Si and / or an oxide semiconductor.

[0130] Some areas in the semiconductor layer 1130 correspond to the semiconductor layer of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7. In other words, the semiconductor layer 1130 of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are connected to each other and bent in various shapes.

[0131] The semiconductor layer 1130 includes a channel region and a source region and a drain region at opposite sides of the channel region, which can be respectively understood as a source electrode and a drain electrode of a corresponding TFT. Hereinafter, for ease of description, the source region and the drain region will be referred to as a source electrode and a drain electrode.

[0132] The driving TFT T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 at opposite sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 has a curved shape (e.g., an Ω shape) to establish a long channel length in a narrow space. When the driving channel region has a long length, the driving range of the gate voltage increases, and therefore, the gray level of light emitted from the organic light emitting diode OLED can be finely controlled, and the quality of the displayed image can be improved.

[0133] The switching TFT T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 at opposite sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0134] The compensation TFT T3 is a dual TFT including a compensation gate electrode G3 respectively overlapping two compensation channel regions and a compensation source electrode S3 and a compensation drain electrode D3 at opposite sides of the two compensation channel regions. The compensation TFT T3 may be connected to the driving gate electrode G1 of the driving TFT T1 via a node connection line 1174 to be described later.

[0135] The first initialization TFT T4 is a double TFT including a first initialization gate electrode G4 overlapping two first initialization channel regions, respectively, and a first initialization source electrode S4 and a first initialization drain electrode D4 at opposite sides of the two first initialization channel regions.

[0136] The operation control TFT T5 may include an operation control gate electrode G5 overlapping an operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 at opposite sides of the operation control gate electrode G5. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0137] The emission control TFT T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and an emission control source electrode S6 and an emission control drain electrode D6 at opposite sides of the emission control gate electrode G6. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0138] The second initialization TFT T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 at opposite sides of the second initialization gate electrode G7.

[0139] The above TFTs may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0140] The scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1 can be arranged on the semiconductor layer 1130, and (some) insulating layers are provided between the semiconductor layer 1130 and the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1.

[0141] The scan line SL may extend in the first direction DR1. Some regions of the scan line SL may correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, regions of the scan line SL overlapping the channel regions of the switching TFT T2 and the compensation TFT T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0142] The previous scan line SL-1 extends along the first direction DR1, and some regions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, regions of the previous scan line SL-1 overlapping the channel regions of the first initialization TFT T4 and the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0143] The emission control line EL extends along the first direction DR1. Some regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, regions of the emission control line EL overlapping the channel regions of the operation control TFT T5 and the emission control TFT T6 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0144] The driving gate electrode G1 is a floating electrode that may be connected to the compensation TFT T3 via a node connection line 1174 .

[0145] The electrode voltage line HL can be arranged on the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1, and (some) insulating layers are provided between the electrode voltage line HL and the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1.

[0146] The electrode voltage line HL may extend in the first direction DR1 to intersect the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL covers at least a portion of the driving gate electrode G1 and may construct a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may become a lower electrode CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may become an upper electrode CE2 of the storage capacitor Cst.

[0147] The upper electrode CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL can be connected to the driving voltage line PL on the electrode voltage line HL via the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be understood as a driving voltage line in the lateral direction.

[0148] The driving voltage line PL extends in the second direction DR2, and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the first direction DR1 intersecting the second direction DR2. Therefore, the plurality of driving voltage lines PL and electrode voltage lines HL in the display area DA may generate a mesh structure.

[0149] The data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may be arranged on the electrode voltage line HL with (some) insulating layers provided between the electrode voltage line HL and the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 .

[0150] The data line DL extends in the second direction DR2 and may be connected to the switching source electrode S2 of the switching TFT T2 via the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0151] The driving voltage line PL extends in the second direction DR2 and is connected to the electrode voltage line HL via the contact hole CNT as described above. In addition, the driving voltage line PL may be connected to the operation control TFT T5 via the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 via the contact hole 1155.

[0152] One end of the initialization connection line 1173 is connected to the first and second initialization TFTs T4 and T7 via the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to an initialization voltage line VL to be described later via the contact hole 1151 .

[0153] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 via the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 via the contact hole 1157 .

[0154] The initialization voltage line VL may be disposed on the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 with (some) insulating layers provided therebetween.

[0155] The initialization voltage line VL extends in the first direction DR1. The initialization voltage line VL may be connected to the first initialization TFT T4 and the second initialization TFT T7 via the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, -2V, etc.).

[0156] The initialization voltage line VL is arranged at the pixel electrode 210 (see Figure 8 ) and may include the same material as that of the pixel electrode 210. The pixel electrode 210 may be connected to the emission control TFT T6. The pixel electrode 210 is connected to the connection metal 1175 via the contact hole 1163, and the connection metal 1175 may be connected to the emission control drain electrode D6 via the contact hole 1153.

[0157] exist Figure 7 In the embodiment, the initialization voltage line VL is arranged at the same layer as that of the pixel electrode 210 , but according to some example embodiments, the initialization voltage line VL may be arranged at the same layer as the electrode voltage line HL.

[0158] In the following, reference will be made to Figure 8 A stack structure of components included in the display panel 10 according to some example embodiments is described.

[0159] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer.

[0160] The buffer layer 111 is positioned on the substrate 100 to reduce or block the infiltration of impurities, moisture or external air from the lower portion of the substrate 100 and to provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material, an organic material, or an inorganic-organic composite material such as an oxide material or a nitride material, and may have a single-layer structure or a multi-layer structure including an inorganic material and an organic material. A barrier layer for preventing or reducing the infiltration of external air may be further provided between the substrate 100 and the buffer layer 111.

[0161] The gate electrodes G1 and G6 are disposed on the semiconductor layers A1 and A6, respectively, and the first gate insulating layer 112 is disposed between the gate electrodes G1 and G6 and the semiconductor layers A1 and A6. The gate electrodes G1 and G6 may each include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer structure or a multi-layer structure. As an example, the gate electrodes G1 and G6 may each have a single layer including Mo. The scan line SL (see Figure 7 ), the previous scan line SL-1, and the emission control line EL may be disposed at the same layer as the gate electrodes G1 and G6. That is, the gate electrodes G1 and G6, the scan line SL (see Figure 7 ), the previous scan line SL-1 and the emission control line EL may be disposed on the first gate insulating layer 112.

[0162] The first gate insulating layer 112 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc peroxide (ZnO 2 ) of insulating material.

[0163] The second gate insulating layer 113 may be provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc peroxide (ZnO 2 ) of insulating material.

[0164] The lower electrode CE1 of the storage capacitor Cst may be integrally provided with the driving gate electrode G1 of the driving TFT T1. For example, the driving gate electrode G1 of the driving TFT T1 may serve as the lower electrode CE1 of the storage capacitor Cst.

[0165] The upper electrode CE2 of the storage capacitor Cst overlaps the lower electrode CE1, and the second gate insulating layer 113 is between the upper electrode CE2 and the lower electrode CE1 of the storage capacitor Cst. In this case, the second gate insulating layer 113 can be used as a dielectric layer of the storage capacitor Cst. The upper electrode CE2 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a single-layer structure or a multi-layer structure. As an example, the upper electrode CE2 may have a single layer including Mo or a multi-layer structure including Mo / Al / Mo.

[0166] In the drawings, the storage capacitor Cst is shown to overlap the driving TFT T1, but one or more disclosed embodiments are not limited thereto. Various modifications may be made to the storage capacitor Cst, for example, the storage capacitor Cst may be arranged not to overlap the driving TFT T1.

[0167] The upper electrode CE2 may serve as the electrode voltage line HL. For example, a portion of the electrode voltage line HL may serve as the upper electrode CE2 of the storage capacitor Cst.

[0168] The interlayer insulating layer 115 may be provided to cover the upper electrode CE2. The interlayer insulating layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc peroxide (ZnO 2 ) of insulating material. Figure 8 In the embodiment, the interlayer insulating layer 115 has a single-layer structure, but according to some example embodiments, the interlayer insulating layer 115 may have a multi-layer structure.

[0169] The data line DL, the driving voltage line PL, and the connection metal 1175 may be disposed on the interlayer insulating layer 115. The data line DL, the driving voltage line PL, and the connection metal 1175 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a single-layer structure or a multi-layer structure including the above materials. For example, each of the data line DL, the driving voltage line PL, and the connection metal 1175 may have a multi-layer structure including Ti / Al / Ti.

[0170] The upper electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL via a contact hole CNT defined in the interlayer insulating layer 115. This means that the electrode voltage line HL is connected to the driving voltage line PL via the contact hole CNT. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL.

[0171] The connection metal 1175 is connected to the semiconductor layer A6 of the emission control TFT T6 via the contact hole 1153 penetrating the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control TFT T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED via the connection metal 1175.

[0172] The planarization layer 117 is positioned on the data line DL, the driving voltage line PL, and the connection metal 1175 , and the organic light emitting diode OLED may be positioned on the planarization layer 117 .

[0173] The planarization layer 117 may have a flat upper surface to make the pixel electrode 210 flat. The planarization layer 117 may include a single-layer structure or a multi-layer structure including an organic material. The planarization layer 117 may include a general-purpose polymer (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative with a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer and a blend thereof. The planarization layer 117 may include an inorganic material. The planarization layer 117 may include a silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc peroxide (ZnO 2 ). When the planarization layer 117 includes an inorganic material, chemical planarization polishing may be performed if necessary. Alternatively, the planarization layer 117 may include both an organic material and an inorganic material.

[0174] The pixel electrode 210 may be a (semi) transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer, wherein the reflective layer includes silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and mixtures thereof. The transparent or semi-transparent electrode layer may include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one electrode material selected from the group consisting of indium gallium oxide (ITO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may include a stack structure including ITO / Ag / ITO.

[0175] The pixel defining layer 119 may be positioned on the planarization layer 117, and the pixel defining layer 119 includes an opening 119OP exposing a central portion of the pixel electrode 210 to define a light emitting region of the pixel. In addition, the pixel defining layer 119 increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 to prevent arcing at the edge of the pixel electrode 210. The pixel defining layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be obtained by spin coating or the like.

[0176] The intermediate layer 220 of the organic light emitting diode OLED may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent material or a phosphorescent material that emits red, green, blue or white light. The organic light emitting layer may include a low molecular organic material or a polymer organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL) may be selectively arranged below the organic light emitting layer and on the organic light emitting layer. The intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210, respectively. However, one or more embodiments are not limited thereto. The intermediate layer 220 may be variously modified, that is, the intermediate layer 220 may be arranged to extend over a plurality of pixel electrodes 210, that is, the intermediate layer 220 may be shared over a plurality of pixel electrodes 210.

[0177] The counter electrode 230 may be a transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode and may be configured to include a metal thin film including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and a mixture thereof having a small work function. In addition, a metal such as ITO, IZO, ZnO, or In 2 O 3A transparent conductive oxide (TCO) may be further disposed on the metal film.

[0178] When the pixel electrode 210 is a reflective electrode and the counter electrode 230 is a transmissive electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and the display device 1 is a top emission type. When the pixel electrode 210 is a transparent or semi-transparent electrode and the counter electrode 230 is a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and the display device 1 may be a bottom emission type. However, one or more embodiments are not limited thereto. The display device 1 according to some example embodiments may be a dual emission type in which light is emitted to the top surface and the bottom surface.

[0179] According to some example embodiments, the counter electrode 230 is included in the auxiliary pixel PXa positioned in the first display area DA1. However, since the first display area DA1 includes the auxiliary pixel area PA1 in which the auxiliary pixel PXa is positioned and the first transmission area TA1, the counter electrode 230 may not be partially included in some areas corresponding to the first transmission area TA1. In a top emission type display device, light may be emitted toward the counter electrode 230, but transmittance may be reduced to some extent due to the counter electrode 230. Therefore, since the area corresponding to the first transmission area TA1 does not include the counter electrode 230, the transmittance of the first transmission area TA1 may be improved.

[0180] To this end, the counter electrode 230 in the first display area DA1 may be patterned to correspond to each auxiliary pixel area PA1. The counter electrode 230 in the first display area DA1 may be formed by partially removing an area corresponding to the first transmission area TA1 through a laser lift-off process or through a fine metal mask (FMM) patterning process. Hereinafter, it will be assumed that the counter electrode 230 is formed in the first display area DA1 through an FMM patterning process.

[0181] The counter electrode 230 may also be included in the connection pixel PXc in the second display area DA2. However, since the second display area DA2 includes the connection pixel area, the second transmission area TA2, and the third transmission area TA3 in which the connection pixel PXc is located, the counter electrode 230 may not be included in some areas corresponding to the second transmission area TA2 and the third transmission area TA3. In a top emission type display device, light may be emitted toward the counter electrode 230, but the transmittance may be reduced to a certain extent due to the counter electrode 230. Therefore, the counter electrode 230 is not provided in the area corresponding to the second transmission area TA2 and the third transmission area TA3, and thus the transmittance of the second transmission area TA2 and the third transmission area TA3 may be improved.

[0182] To this end, the counter electrode 230 in the second display area DA2 may be patterned to correspond to each connection pixel area. The counter electrode 230 in the second display area DA2 may be formed by a laser lift-off process or by a FMM patterning process by partially removing some areas corresponding to the second transmission area TA2 and the third transmission area TA3. Hereinafter, it will be assumed that the counter electrode 230 is formed in the second display area DA2 by the FMM patterning process.

[0183] The counter electrode 230 is disposed over the entire surface of the third display area DA3, and some edges may be positioned in the non-display area NDA. The counter electrode 230 may be integrally disposed with respect to the main pixels PXm (i.e., a plurality of organic light emitting diodes OLED) in the third display area DA3 to correspond to the plurality of pixel electrodes 210.

[0184] Fig. 9 and Fig.10 is a plan view illustrating a portion of the first display area DA1 according to some example embodiments.

[0185] Reference Fig. 9 and Fig.10 As described above, the first display area DA1 includes the auxiliary pixel area PA1 and the first transmission area TA1, and the auxiliary pixel PXa is arranged in the auxiliary pixel area PA1. The auxiliary pixel area PA1 includes Fig. 9 As shown in FIG. 1 and FIG. 2 , the auxiliary pixel PXa includes the first pixel region PA1-1 and the second pixel region PA1-2. Fig. 9 The first pixels PXa1 and the second pixels PXa2 are shown in FIG. The plurality of first pixels PXa1 are in the first pixel area PA1-1, and the plurality of second pixels PXa2 are in the second pixel area PA1-2.

[0186] According to some example embodiments, the first pair of electrodes 230a is in the first pixel area PA1-1, and the second pair of electrodes 230b is in the second pixel area PA1-2. The first pair of electrodes 230a may correspond to the first pixel area PA1-1, and the second pair of electrodes 230b may correspond to the second pixel area PA1-2. In addition, the first pair of electrodes 230a and the second pair of electrodes 230b may partially contact each other. Here, the first pair of electrodes 230a and the second pair of electrodes 230b may have the same shape as each other.

[0187] Reference Fig.10, a plurality of first pixels PXa1 are arranged in the first pixel area PA1-1. Each of the plurality of first pixels PXa1 includes a scan line SL for receiving a scan signal and a data line DL for receiving a data signal. The scan line SL extends in a first direction DR1, and the data line DL may extend in a second direction DR2 that crosses the first direction DR1 (e.g., intersects the first direction DR1). Here, other signal lines PL, EL, SL-1, VL (see Figure 7 ) may also be disposed in the first pixel area PA1-1.

[0188] The data line DL and the scan line SL may be partially positioned in the first transmission area TA1. In this case, the scan line SL may have, for example, an arched portion that is arched around the edge of the first transmission area TA1 so as to improve the transmittance of the first transmission area TA1. The arched portion may also be applied to the other signal lines PL, EL, SL-1, and VL (see FIG. 1 ) other than the scan line SL. Figure 7 ).

[0189] The plurality of first pixels PXa1 in the first pixel region PA1 - 1 may include a first pair of electrodes 230 a integrally disposed with respect to one first pixel region PA1 - 1 .

[0190] The plurality of second pixels PXa2 in the second pixel region PA1 - 2 may include a second counter electrode 230 b integrally disposed with respect to one second pixel region PA1 - 2 .

[0191] The first pixel area PA1-1 and the second pixel area PA1-2 may be arranged on different rows from each other. In this case, the first pixel area PA1-1 and the second pixel area PA1-2 may surround the first transmission area TA1. That is, the first pixel area PA1-1 and the second pixel area PA1-2 may be arranged in a zigzag shape. For example, Fig. 9 and Fig.10 As shown in FIG. 1 , the first pixel regions PA1 - 1 and the second pixel regions PA1 - 2 may be alternately arranged in a third direction DR3 and / or a fourth direction DR4 crossing the first direction DR1 and the second direction DR2 .

[0192] The first pair of electrodes 230a and the second pair of electrodes 230b may correspond to the first pixel area PA1-1 and the second pixel area PA1-2, respectively, and may partially contact each other. A first contact area CTA1 where the first pair of electrodes 230a and the second pair of electrodes 230b contact each other exists between the first pixel area PA1-1 and the second pixel area PA1-2 adjacent to the first pixel area PA1-1, and the first pair of electrodes 230a and the second pair of electrodes 230b may be electrically connected to each other via the first contact area CTA1.

[0193] In this case, since the first and second counter electrodes 230a and 230b are connected to each other via the first contact area CTA1, the resistance of the first and second counter electrodes 230a and 230b in the first display area DA1 may be prevented from increasing.

[0194] Fig.11 and Fig.12 It is along Fig. 9 A cross-sectional view taken along line BB′ for illustrating some manufacturing processes of the display panel 10 according to some example embodiments. Fig.13 It is along Fig. 9 A cross-sectional view taken along line BB'.

[0195] Reference Figures 11 to 13 An insulating layer IL in which the pixel circuit PC is positioned is formed on the substrate 100, and a first pixel electrode 210a and a second pixel electrode 210b electrically connected to the pixel circuit PC are formed. The first pixel electrode 210a is in the first pixel area PA1-1, and the second pixel electrode 210b is in the second pixel area PA1-2.

[0196] A pixel defining layer 119 having an opening exposing a central portion of the first pixel electrode 210a and a central portion of the second pixel electrode 210b is disposed on the first pixel electrode 210a and the second pixel electrode 210b. A first intermediate layer 220a is disposed on the exposed portion of the first pixel electrode 210a, and a second intermediate layer 220b is disposed on the exposed portion of the second pixel electrode 210b, wherein the exposed portion is exposed through the opening of the pixel defining layer 119. It is understood that the first intermediate layer 220a and the second intermediate layer 220b include the same as those described above with reference to Figure 8 The material of the intermediate layer 220 is the same material as described.

[0197] Afterwards, the first pair of electrodes 230a and the second pair of electrodes 230b may be disposed on the first intermediate layer 220a and the second intermediate layer 220b. According to some example embodiments, the first pair of electrodes 230a and the second pair of electrodes 230b may be obtained by different processes. Here, the first pair of electrodes 230a and the second pair of electrodes 230b may be formed using the first mask sheet 422A of the first mask assembly to be described later. That is, after forming the first pair of electrodes 230a, at least one of the first mask assembly and the substrate 100 is moved to a position different from the initial position, and then the second pair of electrodes 230b may be formed on the substrate 100. According to some example embodiments, after forming the second pair of electrodes 230b, at least one of the first mask assembly and the substrate 100 is moved to a position different from the initial position, and then the first pair of electrodes 230a may be formed on the substrate 100. Hereinafter, for ease of description, the case where the second pair of electrodes 230b is formed by moving the position of the substrate 100 after forming the first pair of electrodes 230a will be described in detail below.

[0198] In detail, Fig.11 As shown in FIG. 1 , a first pair of electrodes 230 a are formed on the first intermediate layer 220 a. When the deposition material having passed through the first opening 422A-1 of the first mask sheet 422A is deposited on the substrate 100, the first pair of electrodes 230 a may be formed. Fig.12 As shown in FIG. 1 , the substrate 100 is moved to Fig.11 The left side of the second middle layer 220b is formed to form a second pair of electrodes 230b on the second intermediate layer 220b. The second pair of electrodes 230b can be manufactured through the first opening 422A-1 of the first mask sheet 422A.

[0199] Reference Fig.13 , the first pair of electrodes 230a and the second pair of electrodes 230b obtained as above may be in surface contact with each other in the first contact area CTA1. The surface contact between the first pair of electrodes 230a and the second pair of electrodes 230b may be understood as the second pair of electrodes 230b being stacked on the first pair of electrodes 230a to contact each other, and there is no intermediate layer between the second pair of electrodes 230b and the first pair of electrodes 230a.

[0200] In the first contact area CTA1, the second pair of electrodes 230b is arranged on the first pair of electrodes 230a. This means that the second pair of electrodes 230b is obtained in a post-process of forming the first pair of electrodes 230a. According to some example embodiments, when the first pair of electrodes 230a is formed after the second pair of electrodes 230b is formed, the first pair of electrodes 230a may be arranged on the second pair of electrodes 230b in the first contact area CTA1. Because the first pair of electrodes 230a and the second pair of electrodes 230b are in surface contact with each other in the first contact area CTA1, the first contact area CTA1 may have a thickness less than twice the thickness of the area in which only the first pair of electrodes 230a or the second pair of electrodes 230b are arranged. In addition, the first contact area CTA1 may not be arranged in the light emitting area of ​​the first pixel PXa1 and the second pixel PXa2. Here, the light emitting area is formed in the first opening OP1 and the second opening OP2 of the pixel defining layer 119, and the first opening OP1 and the second opening OP2 expose the central portion of the first pixel electrode 210a and the central portion of the second pixel electrode 210b, respectively. That is, the first contact area CTA1 may be disposed not to overlap the first opening OP1 and the second opening OP2 formed in the pixel defining layer 119 .

[0201] As the area of ​​the first contact area CTA1 increases, the resistance of the first pair of electrodes 230a and the second pair of electrodes 230b can be further reduced. However, as described above, when the area of ​​the first contact area CTA1 increases to be greater than a certain degree, the first contact area CTA1 overlaps with the light-emitting areas of the first pixel PXa1 and the second pixel PXa2, which reduces the light-emitting performance of the first pixel PXa1 and the second pixel PXa2.

[0202] Therefore, the area of ​​the first contact area CTA1 may be set so as not to block the first opening OP1 and the second opening OP2 .

[0203] Reference Figure 2 , Fig.11 and Fig.13 , compared with the first pixel area PA1-1, the first transmission area TA1 may not include a display element such as an organic light emitting diode OLED and a pixel circuit PC electrically connected to the display element. In addition, the first transmission area TA1 may be defined as an area where some layers on the substrate 100 are removed.

[0204] Fig.14 is a plan view of an arrangement of counter electrodes in the display panel 10 according to some example embodiments. Fig.15 It is along Fig.14 A cross-sectional view taken along line CC'. Fig.16 It is along Fig.14 A cross-sectional view taken along line D-D'.

[0205] Reference Figures 14 to 16 The first display area DA1 may include the first pixel area PA1-1, the second pixel area PA1-2, and the first transmission area TA1 as described above. Here, the first pair of electrodes 230a may be in the first pixel area PA1-1, and the second pair of electrodes 230b may be in the second pixel area PA1-2.

[0206] The second display area DA2 may include a third pixel area PA2-1, a fourth pixel area PA2-2, a second transmission area TA2, and a third transmission area TA3. The connection pixel area PA2 may include a third pixel area PA2-1 and a fourth pixel area PA2-2. Here, the third pair of electrodes 230c may be in the third pixel area PA2-1, and the fourth pair of electrodes 230d may be in the fourth pixel area PA2-2.

[0207] In the above case, the third pair of electrodes 230c and the fourth pair of electrodes 230d may have shapes different from each other. For example, the third pair of electrodes 230c may have the same shape as the first pair of electrodes 230a or the second pair of electrodes 230b, and the fourth pair of electrodes 230d may have a shape different from the shape of the third pair of electrodes 230c. Specifically, the third pair of electrodes 230c may have a square shape, and the fourth pair of electrodes 230d may have a rectangular shape. In addition, the fourth pair of electrodes 230d may be equal to or greater than at least two third pairs of electrodes 230c connected to each other.

[0208] The third display area DA3 may include a main pixel area PA3 and the main counter electrode 230 e may be in the main pixel area PA3 .

[0209] In the above case, the third counter electrode 230 c and the fourth counter electrode 230 d may be formed simultaneously with the formation of the main counter electrode 230 e .

[0210] A plurality of third pairs of electrodes 230c and a plurality of fourth pairs of electrodes 230d may be provided. The plurality of third pairs of electrodes 230c may be spaced apart from each other. In addition, the plurality of fourth pairs of electrodes 230d may be spaced apart from each other. In this case, the plurality of third pairs of electrodes 230c and the plurality of fourth pairs of electrodes 230d may be spaced apart from each other. Fig.14 In addition, each of the third pair of electrodes 230c and each of the fourth pair of electrodes 230d may be arranged in a row in the X direction. Fig.14 are arranged in the Y direction to be connected to each other.

[0211] The third pair of electrodes 230c may be connected to the first pair of electrodes 230a or the second pair of electrodes 230b. Here, the third pair of electrodes 230c may include a second contact area CTA2 overlapping the first pair of electrodes 230a or the second pair of electrodes 230b. In this case, in the second contact area CTA2, the third pair of electrodes 230c may be in surface contact with the first pair of electrodes 230a or the second pair of electrodes 230b. In addition, in the second contact area CTA2, the third pair of electrodes 230c may be arranged on the first pair of electrodes 230a or the second pair of electrodes 230b, or may be arranged below the first pair of electrodes 230a or the second pair of electrodes 230b. Hereinafter, for ease of description, a case in which the third pair of electrodes 230c is arranged on the second pair of electrodes 230b in the second contact area CTA2 will be described in detail below.

[0212] In the above case, the thickness of the second contact area CTA2 may be greater than the thickness of the second counter electrode 230b or the thickness of the third counter electrode 230c. For example, the thickness of the second contact area CTA2 may be about twice the thickness of the second counter electrode 230b or about twice the thickness of the third counter electrode 230c.

[0213] In the above case, the third pair of electrodes 230c and the fourth pair of electrodes 230d connected to each other may have a third contact area CTA3, and the third pair of electrodes 230c and the fourth pair of electrodes 230d overlap each other in the third contact area CTA3. In this case, the thickness of the third contact area CTA3 may be the same as or similar to the thickness of the third pair of electrodes 230c or the thickness of the fourth pair of electrodes 230d. That is, because the third pair of electrodes 230c and the fourth pair of electrodes 230d are simultaneously formed in the third contact area CTA3, one of the third pair of electrodes 230c and the fourth pair of electrodes 230d may directly contact the upper surface of the other of the third pair of electrodes 230c and the fourth pair of electrodes 230d. In this case, the third pair of electrodes 230c and the fourth pair of electrodes 230d may be in surface contact with each other. Hereinafter, for the convenience of description, the following will be described in detail. Fig.16 The fourth pair of electrodes 230d is shown on the third pair of electrodes 230c.

[0214] The fourth counter electrode 230d may be connected to the main counter electrode 230e. Here, the fourth counter electrode 230d may be partially spaced apart from the main counter electrode 230e, and may be partially in direct contact with the main counter electrode 230e. Here, the fourth counter electrode 230d has a T shape to be connected to the main counter electrode 230e. That is, a portion of the fourth counter electrode 230d may protrude toward the main counter electrode 230e, and another portion of the fourth counter electrode 230d may protrude in a direction perpendicular to the portion of the fourth counter electrode 230d.

[0215] The second transmission area TA2 may be positioned between one of the first and second counter electrodes 230a and 230b, the third counter electrode 230c, and the fourth counter electrode 230d. The second transmission area TA2 may have the same shape and size as those of the first transmission area TA1.

[0216] The third transmission area TA3 may be disposed between one of the first and second counter electrodes 230a and 230b, the third counter electrode 230c, the fourth counter electrode 230d, and the main counter electrode 230e. Here, the third transmission area TA3 may have a shape different from that of the second transmission area TA2.

[0217] In each of the first pixel area PA1-1, the second pixel area PA1-2, the third pixel area PA2-1, and the fourth pixel area PA2-2, one or more pixels may be arranged. For example, the first pixel PXa1 may be arranged in the first pixel area PA1-1, and the second pixel PXa2 may be arranged in the second pixel area PA1-2. In addition, one or more third pixels PXc1 may be arranged in the third pixel area PA2-1, and one or more fourth pixels PXc2 may be arranged in the fourth pixel area PA2-2. In addition, the main pixel PXm may be arranged in the main pixel area PA3. The above pixels are the same or similar to the pixels in the above description.

[0218] Fig.17 is a cross-sectional view of an apparatus 400 for manufacturing the display apparatus 1 according to some example embodiments. Fig.18 yes Fig.17 4. A perspective view of a first mask assembly 420A. Fig.19 It is shown Fig.17 FIG. 4 is a plan view of a portion of a first mask sheet 422A. Fig. 20 It is shown Fig.17 FIG. 4 is a plan view of a portion of a second mask sheet 422B.

[0219] Reference Figures 17 to 20 , the display panel 10 of the display device 1 may be manufactured by using the apparatus 400 for manufacturing a display device.

[0220] The apparatus 400 for manufacturing the display apparatus 1 may include a chamber 410 , a first mask assembly 420A, a second mask assembly 420B, a first support 430 , a second support 440 , a deposition source 450 , a magnetic force generator 460 , a visual portion 470 , and a pressure regulator 480 .

[0221] The chamber 410 may include a space therein and may have an opening portion. Here, a gate valve 411 may be provided at the opening portion of the chamber 410 to open / close the opening portion.

[0222] The first mask assembly 420A may be optionally in the chamber 410. Here, the first mask assembly 420A may include a first mask frame 421A and a first mask sheet 422A. The first mask frame 421A includes a plurality of frames connected to each other and may have an opening therein. Here, the first mask frame 421A may include one opening or a plurality of openings distinguished from each other. In this case, the first mask frame 421A may be formed as a grille such as a window frame. The first mask sheet 422A may be fixed at the first mask frame 421A and be in a tensioned state. Here, the first mask sheet 422A may have a first opening 422A-1 through which a deposition material may pass.

[0223] The first mask sheet 422A may include a first opening 422A-1 through which a material is deposited to form the first pair of electrodes 230a or the second pair of electrodes 230b described above.

[0224] The first opening 422A-1 may have a shape corresponding to the shape of the first pixel area PA1-1 or the second pixel area PA1-2. For example, the first opening 422A-1 may have a rectangular shape, a square shape, or a rhombus shape. In the above case, the deposition material that has passed through the first opening 422A-1 is deposited on the substrate 100 to form the first pair of electrodes 230a or the second pair of electrodes 230b. When there are multiple first openings 422A-1, the multiple first openings 422A-1 may be sufficiently spaced apart from each other, so that the deposition material that has passed through each of the first openings 422A-1 may not be connected to other deposition materials after being deposited on the substrate 100.

[0225] The first opening 422A-1 may be arranged to form a counter electrode in an area corresponding to the first display area DA1 of the substrate 100. Specifically, the first opening 422A-1 may be arranged only in the first area AR1-1 of the first mask sheet 422A. In this case, the second area AR1-2 of the first mask sheet 422A may not include an additional opening. The first area AR1-1 may correspond to the first display area DA1 of the substrate 100, and the second area AR1-2 may correspond to the second display area DA2 and the third display area DA3 of the substrate 100.

[0226] The second mask assembly 420B may replace the first mask assembly 420A. That is, after forming the first and second pairs of electrodes 230a and 230b in the first display area DA1 by using the first mask assembly 420A, the third pair of electrodes 230c, the fourth pair of electrodes 230d, and the main pair of electrodes 230e may be formed in the second and third display areas DA2 and DA3 using the second mask assembly 420B.

[0227] The second mask assembly 420B may include a second mask frame 421B and a second mask sheet 422B. The second mask frame 421B is similar or identical to the first mask frame 421A, and a detailed description thereof is omitted herein.

[0228] The second mask sheet 422B may include a second opening 422B-1, a third opening 422B-2, and a fourth opening 422B-3 for forming the third counter electrode 230c, the fourth counter electrode 230d, and the main counter electrode 230e.

[0229] The second opening 422B-1 may have the same shape as the first opening 422A-1. The third opening 422B-2 may have a shape different from the shape of the second opening 422B-1. For example, the third opening 422B-2 may be larger than the second opening 422B-1. In this case, the third opening 422B-2 may have a size corresponding to at least two second openings 422B-1. The second opening 422B-1 may be separated from the third opening 422B-2. Here, the first width W1 of the second mask sheet 422B between the second opening 422B-1 and the third opening 422B-2 is small enough so that the deposition materials that have respectively passed through the second opening 422B-1 and the third opening 422B-2 and deposited on the substrate 100 can be connected to each other.

[0230] The fourth opening 422B-3 may be connected to the third opening 422B-2. The second width W2 of the second mask sheet 422B between the fourth opening 422B-3 and the third opening 422B-2 is greater than the first width W1, so only a portion of the fourth pair of electrodes 230d may be connected to the main pair of electrodes 230e. In this case, due to the portion of the second mask sheet 422B between the second opening 422B-1 and the third opening 422B-2 and the portion between the third opening 422B-2 and the fourth opening 422B-3, when the second mask sheet 422B is tightened, the strength of the second mask sheet 422B may be ensured to a certain extent.

[0231] The second opening 422B-1 to the fourth opening 422B-3 may be in the fourth area AR2-2 of the second mask sheet 422B, and the fourth area AR2-2 corresponds to the second area AR1-2 of the first mask sheet 422A. However, the additional opening may not be provided in the third area AR2-1 of the second mask sheet 422B, and the third area AR2-1 corresponds to the first area AR1-1 of the first mask sheet 422A.

[0232] The substrate 100 may be mounted on the first support 430. Here, the first support 430 may adjust the position of the substrate 100. For example, the first support 430 may include a UVW stage.

[0233] The first mask assembly 420A or the second mask assembly 420B may be mounted on the second support 440. Here, similar to the first support 430, the second support 440 may adjust the position of the first mask assembly 420A or the second mask assembly 420B.

[0234] The deposition source 450 may evaporate or sublimate the deposition material after accommodating the deposition material to supply the deposition material to the chamber 410. Here, the deposition source 450 may include a heater therein, and heat the deposition material in the deposition source 450 by using the heater to melt or sublime the deposition material. In the above case, the deposition source 450 may be arranged at the center or corner of the chamber 410. Hereinafter, for ease of description, a case where the deposition source 450 is at the corner of the chamber 410 will be described in detail below.

[0235] The magnetic force generator 460 is in the chamber 410 to allow the substrate 100 and the first mask assembly 420A or the substrate 100 and the second mask assembly 420B to be in close contact with each other. Here, the magnetic force generator 460 may include an electromagnet or a permanent magnet that generates a magnetic force.

[0236] The vision part 470 is in the chamber 410 to photograph the position of the first mask assembly 420A and the substrate 100 or the position of the second mask assembly 420B and the substrate 100. Here, the vision part 470 may photograph an alignment mark of at least one of the first mask assembly 420A, the second mask assembly 420B and the substrate 100, etc.

[0237] The pressure regulator 480 may be connected to the chamber 410 to adjust the pressure in the chamber 410. The pressure regulator 480 may include a connection pipe 481 connected to the chamber 410 and a pump 482 provided on the connection pipe 481.

[0238] The display device 1 may be manufactured by the apparatus 400 for manufacturing a display device. Here, the apparatus 400 for manufacturing a display device may manufacture the display device 1 according to one or more embodiments to be described below as well as the embodiments described above. Hereinafter, for the convenience of description, the apparatus 400 for manufacturing the display device 1 will be described in detail. Fig.14 . Fig.14 The same reference numerals throughout the drawings represent the same elements.

[0239] In detail, the substrate 100 on which the insulating layer is formed and the first mask assembly 420A may be disposed in the chamber 410. Here, the pixel electrode and the organic light emitting layer of the thin film transistor and the organic light emitting diode may have been formed.

[0240] After the substrate 100 and the first mask assembly 420A are mounted on the first support 430 and the second support 440, respectively, the substrate 100 and the first mask assembly 420A may be photographed through the vision part 470. Thereafter, the substrate 100 and the first mask assembly 420A may be aligned.

[0241] When the deposition source 450 operates and supplies the deposition material, the deposition material may pass through the first opening 422A-1 of the first mask sheet 422A and may be deposited on the organic light emitting layer and the pixel defining layer of the substrate 100. Here, the deposition material having passed through the first opening 422A-1 may form the first pair of electrodes 230a or the second pair of electrodes 230b as described above. Hereinafter, for ease of description, a case in which the deposition material forms the first pair of electrodes 230a will be described in detail.

[0242] When the deposition material is deposited as described above, the first pair of electrodes 230a may be arranged in one column. There may be a plurality of columns spaced apart from each other.

[0243] When the above process is completed, the position of at least one of the substrate 100 and the first mask assembly 420A may be changed. For example, after the position of the first mask assembly 420A is fixed, the position of the substrate 100 may be changed. According to some example embodiments, after the position of the substrate 100 is fixed, the position of the first mask assembly 420A may be changed. According to some example embodiments, the positions of both the substrate 100 and the first mask assembly 420A may be changed. Hereinafter, for ease of description, a case in which the position of the substrate 100 is changed while the position of the first mask assembly 420A is fixed will be described in detail.

[0244] When the position of the substrate 100 is changed, the first opening 422A-1 may be arranged to correspond to a portion of the substrate 100 in which the first counter electrode 230a is not formed. That is, the first opening 422A-1 may be arranged between two adjacent first counter electrodes 230a.

[0245] After changing the position of the substrate 100, when the deposition source 450 supplies the deposition material, the deposition material may pass through the first opening 422A-1 and may be deposited on the substrate 100. The deposition material having passed through the first opening 422A-1 may be deposited on the substrate 100 to form a second pair of electrodes 230b. The second pair of electrodes 230b is disposed between the first pair of electrodes 230a and may be connected to the first pair of electrodes 230a via the first contact area CTA1.

[0246] When the above process is completed, the operation of the deposition source 450 is stopped or the deposition source 450 is blocked from supplying the deposition material, and then the internal pressure of the chamber 410 may be maintained at an atmospheric pressure level via the pressure regulator 480 .

[0247] After the gate valve 411 is opened, the first mask assembly 420A is withdrawn from the inside of the chamber 410 to the outside, and the second mask assembly 420B can be loaded into the chamber 410 from the outside of the chamber 410. When the second mask assembly 420B is mounted on the second support 440, the second mask assembly 420B and the substrate 100 can be aligned. In addition, the pressure regulator 480 can maintain the internal pressure of the chamber 410 at a level similar to a vacuum state. The deposition source 450 supplies the deposition material onto the substrate 100 to form the third counter electrode 230c, the fourth counter electrode 230d, and the main counter electrode 230e on the substrate 100.

[0248] In detail, when the third pair of electrodes 230c is formed on the substrate 100, the third pair of electrodes 230c may be connected to one of the first pair of electrodes 230a and the second pair of electrodes 230b. When the third pair of electrodes 230c is formed, the second contact area CTA2 may be provided between the third pair of electrodes 230c and one of the first pair of electrodes 230a and the second pair of electrodes 230b. In the second contact area CTA2, the third pair of electrodes 230c may be arranged on an upper surface of one of the first pair of electrodes 230a and the second pair of electrodes 230b. According to some example embodiments, the third pair of electrodes 230c, the fourth pair of electrodes 230d, and the main pair of electrodes 230e are formed on the substrate 100, and then the first pair of electrodes 230a and the second pair of electrodes 230b are sequentially formed. In this case, one of the first pair of electrodes 230a and the second pair of electrodes 230b may be arranged on the upper surface of the third pair of electrodes 230c.

[0249] When the third and fourth counter electrodes 230c and 230d are formed as described above, the first width W1 of the second mask sheet 422B between the second opening 422B-1 and the third opening 422B-2 is small enough so that the third and fourth counter electrodes 230c and 230d on the substrate 100 can overlap each other to be connected to each other.

[0250] Therefore, the counter electrodes arranged on the substrate 100 may be connected to each other via the contact regions.

[0251] In addition, the apparatus 400 for manufacturing the display apparatus 1 may prevent pixels in each display area from not emitting light by connecting the counter electrodes in the display area DA to each other.

[0252] Fig.21 is a plan view of an arrangement of counter electrodes in the display panel 10 according to some example embodiments. Fig. 22 is a diagram showing some example embodiments Fig.17 FIG. 4 is a plan view of a portion of a second mask sheet 422B.

[0253] Reference Fig.21 and Fig. 22 , the display device 1 can be similar to the above reference Figures 1 to 14 The display device 1 described herein. In the following, for the convenience of description, the following will be described in detail. Fig.14 The difference in the arrangement of the electrodes is shown in .

[0254] The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d may be connected to Fig.14 The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c and the fourth pair of electrodes 230d are the same. The plurality of main pairs of electrodes 230e may be spaced apart from each other and have a strip shape. Here, the plurality of main pairs of electrodes 230e may be spaced apart from each other and have a strip shape. Fig.21 In this case, each of the main counter electrodes 230e may not be connected to another, and one of the plurality of main counter electrodes 230e may be connected to the plurality of fourth counter electrodes 230d. Here, each of the main counter electrodes 230e may be connected to each of the wirings arranged on the side surface of the substrate 100.

[0255] In order to form the main counter electrode 230e, the second mask sheet 422B may include fourth openings 422B-3 spaced apart from each other. Here, a plurality of fourth openings 422B-3 may be arranged in one direction to be spaced apart from each other. A portion of the second mask sheet 422B is arranged between adjacent fourth openings 422B-3 to distinguish adjacent fourth openings 422B-3 from each other.

[0256] In the above case, the deposition material having passed through the fourth opening 422B-3 can form a main counter electrode 230e in the third display area DA3, and as described above, the deposition material having passed through different fourth openings 422B-3 can be deposited in different areas of the substrate 100 to form main counter electrodes 230e different from each other.

[0257] Fig.23 is a plan view of an arrangement of counter electrodes in the display panel 10 according to some example embodiments. Fig.24 is a diagram showing some example embodiments Fig.17 FIG. 4 is a plan view of a portion of a second mask sheet 422B.

[0258] Reference Fig.23 and Fig.24 , the display device 1 can be similar to the above reference Figures 1 to 14 The display device 1 described herein. In the following, for the convenience of description, the following will be described in detail. Fig.14 The difference in the arrangement of the electrodes is shown in .

[0259] The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d may be connected to Fig.14 The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c and the fourth pair of electrodes 230d are the same. The plurality of main pairs of electrodes 230e may be spaced apart from each other. Here, the plurality of main pairs of electrodes 230e may be spaced apart from each other. Fig.23 Specifically, the two main counter electrodes 230e can be arranged in the Y-axis direction. Fig.23 In this case, the two main counter electrodes 230e may not be connected to each other, but may be separated from each other. The main counter electrodes 230e may not be connected to each other, and some of the plurality of main counter electrodes 230e may be connected to the fourth counter electrode 230d, respectively. Here, each of the main counter electrodes 230e may be connected to each of the wirings arranged on the side surface of the substrate 100.

[0260] In order to form the main counter electrode 230e, the second mask sheet 422B may include fourth openings 422B-3 spaced apart from each other. Here, a plurality of fourth openings 422B-3 may be arranged in one direction and in another direction to be spaced apart from each other, and each of the plurality of fourth openings 422B-3 has a line shape. A portion of the second mask sheet 422B is arranged between adjacent fourth openings 422B-3 to distinguish adjacent fourth openings 422B-3 from each other. That is, among the plurality of fourth openings 422B-3, two fourth openings 422B-3 are arranged in a column and a plurality of columns each having two fourth openings 422B-3 are arranged in a plurality of rows.

[0261] In the above case, the deposition material having passed through the fourth opening 422B-3 can form a main counter electrode 230e in the third display area DA3, and as described above, the deposition material having passed through different fourth openings 422B-3 can be deposited in different areas of the substrate 100 to form main counter electrodes 230e different from each other.

[0262] According to one or more embodiments, a display panel having an expanded display area to display an image even in an area where components are arranged and a display device including the display panel may be implemented. However, the scope of the disclosure is not limited to the above effects.

[0263] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made herein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display device, comprising: A substrate, comprising a first display area, a second display area and a third display area, wherein the first display area comprises a first pixel area, a second pixel area and a first transmission area, the second display area is adjacent to the first display area, the second display area comprises a plurality of third pixel areas arranged along a horizontal direction, a plurality of fourth pixel areas arranged along the horizontal direction, a second transmission area and a third transmission area, and the third display area is adjacent to the second display area; a plurality of first pixels, each of the plurality of first pixels comprising a first pixel electrode, a first pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes in the first pixel region; a plurality of second pixels, each of the plurality of second pixels comprising a second pixel electrode, a second pair of electrodes, and a second intermediate layer between the second pixel electrode and the second pair of electrodes in the second pixel region; a plurality of third pixels, wherein each of the plurality of third pixels comprises a third pixel electrode, a third counter electrode, and a third intermediate layer between the third pixel electrode and the third counter electrode in the plurality of third pixel regions; as well as a plurality of fourth pixels, wherein each of the plurality of fourth pixels includes a fourth pixel electrode, a fourth pair of electrodes, and a fourth intermediate layer between the fourth pixel electrode and the fourth pair of electrodes; wherein the third pair of electrodes is connected to the first pair of electrodes or the second pair of electrodes, the third pair of electrodes and the fourth pair of electrodes are connected to each other, and the third pair of electrodes and the fourth pair of electrodes have different plane areas from each other, and The fourth pair of electrodes in each fourth pixel region overlaps with at least two adjacent third pairs of electrodes in each third pixel region in a vertical direction intersecting the horizontal direction.

2. The display device according to claim 1, wherein: The first pixel regions, the second pixel regions, and the first transmission regions are alternately arranged to form a grid.

3. The display device according to claim 1, wherein: The first transmission region is defined as a region defined by the first pixel region and the second pixel region connected to each other.

4. The display device according to claim 1, wherein: The first pair of electrodes and the second pair of electrodes are partially in surface contact with each other.

5. The display device according to claim 4, wherein: The second pair of electrodes is arranged on the first pair of electrodes in a surface contact region.

6. The display device according to claim 1, wherein: The first transmission area and the third transmission area have different shapes from each other.

7. The display device according to claim 1, wherein: The light transmittance of the first display area is different from the light transmittance of at least one of the second display area and the third display area.

8. The display device according to claim 1, wherein: The first display area provides an image having a resolution less than a resolution of an image provided by at least one of the second display area and the third display area.

9. The display device according to claim 1, wherein: The main pixels are arranged in the third display area, each of the main pixels includes a main pixel electrode, a main counter electrode and a main intermediate layer between the main pixel electrode and the main counter electrode, and The main counter electrode is arranged on the entire surface of the third display area.

10. The display device according to claim 9, wherein: The main pair of electrodes is connected to the fourth pair of electrodes in the second display area.

11. The display device according to claim 1, further comprising: A plurality of main counter electrodes having a strip shape, wherein The plurality of main counter electrodes are spaced apart from each other.

12. A display device, comprising: A substrate, comprising a first display area, a second display area and a third display area, wherein the first display area comprises a first pixel area, a second pixel area and a first transmission area, the second display area is adjacent to the first display area, the second display area comprises a plurality of third pixel areas arranged along a horizontal direction, a plurality of fourth pixel areas arranged along the horizontal direction, a second transmission area and a third transmission area, and the third display area is adjacent to the second display area; a plurality of first pixels, each of the plurality of first pixels comprising a first pixel electrode, a first pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes in the first pixel region; a plurality of second pixels, each of the plurality of second pixels comprising a second pixel electrode, a second pair of electrodes, and a second intermediate layer between the second pixel electrode and the second pair of electrodes in the second pixel region; a plurality of third pixels, wherein each of the plurality of third pixels comprises a third pixel electrode, a third counter electrode, and a third intermediate layer between the third pixel electrode and the third counter electrode in the plurality of third pixel regions; a plurality of fourth pixels, wherein each of the plurality of fourth pixels comprises a fourth pixel electrode, a fourth pair of electrodes, and a fourth intermediate layer between the fourth pixel electrode and the fourth pair of electrodes; as well as a component on a surface of the substrate so as to correspond to the first display area, the component including an electronic element configured to emit or receive light, wherein the third pair of electrodes is connected to the first pair of electrodes or the second pair of electrodes, the third pair of electrodes and the fourth pair of electrodes are connected to each other, and the third pair of electrodes and the fourth pair of electrodes have different plane areas from each other, and The fourth pair of electrodes in each fourth pixel region overlaps with at least two adjacent third pairs of electrodes in each third pixel region in a vertical direction intersecting the horizontal direction.

13. The display device according to claim 12, wherein: The component is configured to emit or receive light passing through the first transmission area, and The light transmittance of the second display area and the light transmittance of the third display area are smaller than the light transmittance of the first display area.

14. A method for manufacturing a display device, the method comprising: disposing a substrate and a first mask assembly in a chamber; forming a plurality of first pairs of electrodes in a first display region of the substrate by using a deposition material from a deposition source through the first mask assembly; changing a position of at least one of the substrate and the first mask assembly; forming a plurality of second pairs of electrodes in the first display area by using the deposition material from the deposition source through the first mask assembly, the first pairs of electrodes and the second pairs of electrodes at least partially overlapping each other; as well as After replacing the first mask assembly with a second mask assembly and supplying the deposition material from the deposition source onto the substrate, a plurality of third pairs of electrodes arranged along a horizontal direction and a plurality of fourth pairs of electrodes arranged along the horizontal direction are formed in a second display region, and a main pair of electrodes is formed in a third display region of the substrate, wherein each of the plurality of third pairs of electrodes connects one of the first pair of electrodes and the second pair of electrodes to a corresponding fourth pair of electrodes in the plurality of fourth pairs of electrodes, and each of the plurality of third pairs of electrodes and each of the plurality of fourth pairs of electrodes have different planar areas from each other, and Each of the plurality of fourth pairs of electrodes overlaps with at least two adjacent third pairs of electrodes of the plurality of third pairs of electrodes in a vertical direction intersecting the horizontal direction.

15. The method according to claim 14, wherein: A first transmission region is disposed between the first pair of electrodes and the second pair of electrodes.

16. The method according to claim 14, wherein: The first pair of electrodes and the second pair of electrodes are partially in surface contact with each other.

17. The method according to claim 14, wherein: A second transmission region is provided between one of the first pair of electrodes and the second pair of electrodes, the third pair of electrodes and the fourth pair of electrodes, and a third transmission region is provided between one of the first pair of electrodes and the second pair of electrodes, the third pair of electrodes, the fourth pair of electrodes and the main pair of electrodes.

18. The method according to claim 17, wherein: The second transmission area and the third transmission area have shapes different from each other.

19. The method according to claim 14, wherein: The first display area is configured to display an image having a resolution smaller than a resolution of an image displayed by at least one of the second display area and the third display area.

20. The method according to claim 14, wherein: The light transmittance of the first display area is different from the light transmittance of at least one of the second display area and the third display area.

21. The method according to claim 20, wherein: The light transmittance of the second display area is smaller than the light transmittance of the first display area and larger than the light transmittance of the third display area.

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