Display device

Abstract

A display device includes: a base layer; a display element disposed on the base layer; and a signal line disposed on the base layer and electrically connected to the display element. The signal line includes a conductive layer and a capping layer. The capping layer is disposed on the conductive layer and includes vanadium nitride (VN) and zinc oxide (ZnO). The display device can reduce reflection of external light sources, thereby providing improved visibility.

Description

[0001] Cross-reference to related application(s)

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0086560 filed in the Korean Intellectual Property Office on July 17, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device having low optical reflectance to external light. Background Art

[0004] A display device includes signal lines for displaying images or sensing external signals, and an electronic device connected to the signal lines. The signal lines and the electronic device include conductive patterns. Because the conductive patterns are made of highly reflective metal, they reflect external light, allowing the user to identify the conductive patterns. If external light is reflected and the signal lines or electronic devices are visible to the user, the visibility of the image displayed on the display device may be degraded. Summary of the Invention

[0005] Embodiments provide a display device having improved visibility. The display device includes signal lines having low reflectance to external light, and this allows the display device to have improved visibility characteristics.

[0006] According to an embodiment, a display device may include a base layer, a display element, and a signal line. The display element may be disposed on the base layer. The signal line may be disposed on the base layer and may be electrically connected to the display element. The signal line may include a conductive layer and a capping layer. The capping layer may be disposed on the conductive layer and may include vanadium nitride (VN) and zinc oxide (ZnO).

[0007] In an embodiment, the capping layer may further include aluminum oxide (Al 2 O 3 ).

[0008] In an embodiment, in the capping layer, the content of vanadium nitride may be in the range of about 25 at % to about 80 at %, the content of zinc oxide may be in the range of about 20 at % to about 70 at %, and the content of aluminum oxide may be in the range of about 3 at % to about 10 at %, and the sum of the content of vanadium nitride, the content of zinc oxide, and the content of aluminum oxide is 100 at %.

[0009] In an embodiment, the reflectance of the capping layer may be lower than the reflectance of the conductive layer.

[0010] In an embodiment, the capping layer may be disposed directly on the conductive layer.

[0011] In an embodiment, an average reflectance of the signal line to visible light may be equal to or less than about 20%.

[0012] In an embodiment, the signal line may further include an intermediate layer, which may be disposed between the conductive layer and the capping layer. The intermediate layer may have a refractive index between the refractive index of the conductive layer and the refractive index of the capping layer.

[0013] In an embodiment, the intermediate layer may include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, and aluminum oxide.

[0014] In an embodiment, the thickness of the capping layer may be about to about within the range.

[0015] In an embodiment, the display device may further include a thin film transistor, which may be disposed on the substrate layer. The display element may be electrically connected to the thin film transistor. The signal line may include a first signal line and a second signal line. The first signal line may be disposed on the substrate layer. The second signal line may intersect with the first signal line and may be electrically separated from the first signal line.

[0016] In an embodiment, a thin film transistor may include a semiconductor pattern disposed on a substrate layer; a control electrode; an input electrode; and an output electrode. When viewed in plan view, the control electrode may overlap with the semiconductor pattern. The control electrode and the first signal line may be disposed on the same layer. The input electrode and the output electrode may be electrically connected to the semiconductor pattern. The input electrode, the output electrode, and the second signal line may be disposed on the same layer. Each of the control electrode, the input electrode, and the output electrode may include a conductive layer and a capping layer, and the capping layer may be disposed on the conductive layer.

[0017] In an embodiment, the display element may be a liquid crystal display element.

[0018] In an embodiment, the display device may further include an input sensing unit, which may be provided on the display element. The input sensing unit may include an input sensing electrode and an input sensing line. Each of the input sensing electrode and the input sensing line may include a conductive layer and a capping layer, which may be provided on the conductive layer and may include vanadium nitride (VN) and zinc oxide (ZnO).

[0019] In an embodiment, the display element may include an organic light emitting display element including an organic light emitting material or a quantum dot light emitting material.

[0020] In an embodiment, the conductive layer may include copper.

[0021] According to an embodiment, a display device may include a first signal line and a second signal line. The first signal line and the second signal line may be spaced apart from each other. At least one of the first signal line and the second signal line may include a conductive layer and a capping layer. The capping layer may be provided on the conductive layer and may include vanadium nitride (VN) and zinc oxide (ZnO).

[0022] In an embodiment, the capping layer may further include aluminum oxide (Al 2 O 3 ).

[0023] In an embodiment, in the capping layer, the content of vanadium nitride may be in the range of about 25 at % to about 80 at %, the content of zinc oxide may be in the range of about 20 at % to about 70 at %, and the content of aluminum oxide may be in the range of about 3 at % to about 10 at %.

[0024] In an embodiment, the thickness of the capping layer may be about to about within the range.

[0025] In an embodiment, the average reflectance of the capping layer to visible light may be equal to or less than about 25%. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The embodiments will be more clearly understood from the following description of the accompanying drawings.The accompanying drawings illustrate non-limiting embodiments as described herein.

[0027] Figure 1 A perspective view illustrating a display device according to an embodiment.

[0028] Figure 2A and Figure 2B Schematic cross-sectional views illustrating signal lines according to an embodiment.

[0029] Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B Graphs illustrating optical reflectivity characteristics according to some embodiments.

[0030] Figure 5 FIG. 1 is a schematic block diagram illustrating a display device according to an embodiment.

[0031] Figure 6 A plan view illustrating a portion of a display panel according to an embodiment.

[0032] Figure 7A A plan view illustrating a portion of a display panel according to an embodiment.

[0033] Figure 7B To follow Figure 7A Schematic cross-sectional view taken along line II'.

[0034] Figure 8A A plan view illustrating a display panel according to an embodiment.

[0035] Figure 8B Schematic cross-sectional views illustrating a display module according to an embodiment.

[0036] Figure 9A To explain Figure 8B An enlarged schematic cross-sectional view of portion “AA” of FIG.

[0037] Figures 9B to 9E A plan view illustrating an input sensing unit according to an embodiment.

[0038] Figure 9F To explain Figure 9B Magnified view of the components shown in .

[0039] Figure 10 To explain Figure 9B Magnified view of area A2.

[0040] Figure 11 To explain the Figure 10 Schematic cross-sectional view of a vertical section taken along line II-II'.

[0041] 12A to 12C Schematic cross-sectional views illustrating a method of forming a signal line according to an embodiment.

[0042] It should be noted that these figures are intended to illustrate the general characteristics of methods, structures, and / or materials used in certain example embodiments and are intended to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values or properties encompassed by the embodiments. For example, the relative thicknesses and positions of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0043] Embodiments will now be described more fully with reference to the accompanying drawings in which embodiments are shown. However, embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts to those skilled in the art. In the accompanying drawings, the thicknesses of layers and regions are exaggerated for clarity. Identical reference numerals in the accompanying drawings represent identical elements, and their descriptions will therefore be omitted.

[0044] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element. The same numbers indicate the same elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the related enumerated items. Other words used to describe the relationship between elements or layers should be interpreted in the same way (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on").

[0045] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers, and / or cross-sections, these elements, components, regions, layers, and / or cross-sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or cross-section from another element, component, region, layer, or cross-section. Thus, a first element, component, region, layer, or cross-section discussed below may be referred to as a second element, component, region, layer, or cross-section without departing from the teachings of the example embodiments.

[0046] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," "on," etc. may be used herein to describe the relationship of an element or feature to another element (or elements) or another feature (or features) as illustrated in the figures. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, the elements described as being "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that if used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] The phrase "at least one of," for purposes of its meaning and interpretation, is intended to include the meaning of "at least one selected from the group consisting of." For example, "at least one of A and B" is understood to mean "A, B, or A and B." When following a list of elements, the term "at least one of" modifies the entire list of elements and does not modify the individual elements of the list.

[0049] The term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "and" and "or" may be used in conjunction or antonym conjunction sense and may be understood to be equivalent to "and / or".

[0050] As used herein, "about" is inclusive of the recited value and means within an acceptable range of deviation as determined by one of ordinary skill in the art for the particular value, taking into account the measurement in question and the errors associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of the recited value.

[0051] Embodiments are described herein with reference to schematic cross-sectional illustrations showing the embodiments and intermediate structures thereof. Variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments should not be construed as limited to the specific shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0053] Figure 1 2 is a perspective view illustrating a display device DD according to an embodiment.

[0054] Figure 1The example in which a portable terminal having four curved edges is provided as a display device DD is explained. However, the present invention is not limited to this example, and in an embodiment, one of a flat, curved, bendable, rollable, foldable, and retractable display device may be provided as the display device DD. Although not shown, the display device DD may be used for large electronic devices (e.g., televisions and outdoor billboards) or small or medium-sized electronic devices (e.g., personal computers, notebook computers, personal digital assistants, car navigation systems, game consoles, portable electronic devices, watch-type electronic devices, and cameras). However, it should be understood that these are merely embodiments of the present invention, and other electronic devices may be used unless they depart from the spirit of the present invention.

[0055] The display device DD may include a display surface divided into different areas. The display device DD may include a display area DD-DA on which an image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. Figure 1 , a clock widget is illustrated as an example of the image IM. The non-display area DD-NDA may surround the display area DD-DA.

[0056] In an embodiment, based on the display direction of the image IM, the front surface or top surface and the rear surface or bottom surface of each element or component may be defined. The front surface and the rear surface may be two opposite surfaces facing each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. The directions indicated by the first to third directions DR1, DR2 and DR3 may be relative concepts, and in some embodiments, they may be used to indicate other directions. Hereinafter, the first to third directions may be the directions indicated by the first to third directions DR1, DR2 and DR3, respectively, and will be referenced with the same reference numerals. In the specification, the expression "when viewed in a plan view" means observing the structure under consideration in the third direction DR3 (i.e., the normal direction).

[0057] In an embodiment, the display device DD may include a signal line SL (eg, see Figure 2A ), which is used to transmit signals for various purposes (such as display of an image or sensing of an external signal). Hereinafter, the signal line SL according to the embodiment (for example, see Figure 2A ).

[0058] Figure 2A and Figure 2B Schematic cross-sectional view illustrating the signal line SL or the signal line SL-1 according to the embodiment. Figure 2A , the signal line SL can be provided on the support member BS. The support member BS can be, for example, a reference Figure 7B or Figure 9AThe first base layer BS1, the thin encapsulation layer TFE, or the first touch insulating layer TS-IL1 are described in more detail. However, the present invention is not limited to this example, and in an embodiment, as long as the signal line SL can be supported by the support BS, there is no limitation on the support BS.

[0059] refer to Figure 2A , the signal line SL may include a conductive layer CL and a capping layer CAP. The conductive layer CL may be formed of or include a conductive material. For example, the conductive layer CL may be formed of or include at least one of metal materials. In detail, the conductive layer CL may be formed of or include at least one of the following: copper, aluminum, molybdenum, titanium, silver, and zinc. In an embodiment, the conductive layer CL may be formed of or include copper, which has low resistance and may potentially achieve a fast signal transmission speed. However, the present invention is not limited to this example, and in an embodiment, the conductive layer CL may be formed of or include at least one of other conductive materials: for example, indium tin oxide (ITO), indium zinc oxide (IZO), and graphene.

[0060] The conductive layer CL may have a thickness of about to When the thickness of the conductive layer CL is less than about When the thickness of the conductive layer CL is greater than about When the support member BS supporting the signal line SL (eg, Figure 7B The first base layer BS1) may be easily damaged by tensile stress.

[0061] Figure 2A and Figure 2B Although the example in which the conductive layer CL has a single-layer structure is described, in embodiments, the conductive layer CL may have a multi-layer structure. In the multi-layer structure, the conductive layer CL may include layers containing different metal atoms or layers containing the same metal atoms but different from each other in terms of the content ratio of the metal atoms.

[0062] The capping layer CAP may be disposed (or directly disposed) on the conductive layer CL. The capping layer CAP may include vanadium nitride (VN) and zinc oxide (ZnO). Since vanadium nitride has a low reflectance, the capping layer CAP may have a reflectance lower than that of the conductive layer CL. Accordingly, the signal line SL including the capping layer CAP may have a low reflectance to incident external light and may not be recognized by the user. Since the capping layer CAP includes zinc oxide, the signal line SL may be formed by a wet process. For example, in the case where the capping layer includes only vanadium nitride, a patterning process using an etching solution may be difficult, but due to the zinc oxide included in the capping layer CAP according to the embodiment, the capping layer CAP can be patterned by an etching process.

[0063] The capping layer CAP may further include aluminum oxide (Al2O3). When the capping layer CAP further includes aluminum oxide, the capping layer CAP may be deposited by a direct current (DC) sputtering process. This may make it possible to deposit a capping layer having a uniform film thickness over a large area.

[0064] The content of vanadium nitride in the capping layer CAP may be in the range of about 25 at % to about 80 at %. For example, the content of vanadium nitride in the capping layer CAP may be in the range of about 30 at % to about 70 at %. When the content of vanadium nitride in the capping layer CAP is less than 25 at %, the reflectivity of the capping layer CAP may increase. This may result in an increase in the reflectivity of the signal line SL to external light and a decrease in the visibility of the display device DD. When the content of vanadium nitride in the capping layer CAP is greater than 80 at %, the content of zinc oxide (ZnO) or aluminum oxide (Al2O3) in the capping layer CAP may decrease, and this may cause various technical problems in the etching or sputtering process. In this specification, the unit "at %" means atomic percentage.

[0065] The content of zinc oxide in the capping layer CAP may be in the range of about 20 at % to about 70 at %. For example, the content of zinc oxide in the capping layer CAP may be in the range of about 30 at % to about 60 at %. When the content of zinc oxide in the capping layer CAP is less than about 20 at %, the etching rate of the capping layer CAP may be reduced, and this may cause difficulty in patterning the capping layer CAP through an etching process. When the content of zinc oxide in the capping layer CAP is greater than about 70 at %, the etching rate of the capping layer CAP may be too high, and this may cause difficulty in controlling the etching process.

[0066] The content of aluminum oxide in the capping layer CAP may be in a range of about 3 at % to about 10 at %. When the content of aluminum oxide in the capping layer CAP is less than 3 at %, it may be difficult to deposit the capping layer CAP by a DC sputtering process. When the content of aluminum oxide in the capping layer CAP is greater than 10 at %, the optical characteristics of the capping layer CAP may be degraded.

[0067] The capping layer CAP may have a thickness of about to about When the thickness of the capping layer CAP is within this range, it is possible to increase the destructive interference of visible light incident from the outside and thereby increase the amount of the extinction rate of visible light. For example, when the thickness of the capping layer CAP is about to about When the reflectance of the green light is within the range of , the destructive interference amount of the green light having the central wavelength of about 550 nm may be increased. Therefore, the display device DD may have satisfactory reflectance characteristics with respect to external light and may have improved visibility characteristics.

[0068] The thickness of the capping layer CAP may be equal to or less than about When the thickness of the capping layer CAP is greater than When etching the capping layer CAP, it may take a long time, and therefore, in the process of etching the capping layer CAP and the conductive layer CL, the capping layer CAP may be formed to have a width W2 greater than the width W1 of the conductive layer CL. For example, a sharp tip may be formed, which may lead to degradation in the reliability of the display device DD.

[0069] The average reflectance of the capping layer CAP to visible light may be equal to or less than about 25%, and more particularly, equal to or less than about 20%.

[0070] The average reflectance of the signal line SL to visible light may be equal to or less than about 20%, and more particularly, equal to or less than about 10%. Figure 2B , the signal line SL-1 may further include an intermediate layer ML disposed between the conductive layer CL and the capping layer CAP. The intermediate layer ML may be disposed (or directly disposed) between the conductive layer CL and the capping layer CAP. The intermediate layer ML may have a refractive index between the refractive index of the conductive layer CL and the refractive index of the capping layer CAP. For example, the refractive index n of the intermediate layer ML is ml It can be given by the following equation 1.

[0071] [Equation 1]

[0072]

[0073] In Equation 1, n ml is the refractive index of the middle layer ML, n cl is the refractive index of the conductive layer CL, and n cap is the refractive index of the capping layer CAP.

[0074] Because the signal line SL-1 further includes an intermediate layer ML having a refractive index between that of the conductive layer CL and the capping layer CAP, it is possible to reduce the amount of light incident from the outside and reflected outward from the interface between the capping layer CAP and the conductive layer CL. Accordingly, it is possible to more effectively reduce the optical reflectance of the signal line SL-1.

[0075] The middle layer ML may be formed of or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, and aluminum oxide.

[0076] Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B Graphs illustrating optical reflectivity characteristics according to some embodiments. Figure 3A and Figure 3BThe average reflectance values of the capping layers CAP of the signal lines SL according to Embodiments 1 to 5 are shown.

[0077] In Embodiments 1 to 5, the capping layer CAP is formed to have A spectrometer is used to measure the reflectance of the capping layer CAP to visible light with a wavelength of about 380nm-780nm.

[0078] Each of the capping layers CAP according to Embodiments 1 to 5 is formed of vanadium nitride, zinc oxide, and aluminum oxide, and the contents of vanadium nitride, zinc oxide, and aluminum oxide are summarized in Table 1 below.

[0079] [Table 1]

[0080] Vanadium nitride (at%) Zinc oxide (at%) Alumina (at%) Implementation Method 1 40 55 5 Implementation Method 2 45 50 5 Implementation 3 50 45 5 Implementation 4 55 40 5 Implementation 5 60 35 5

[0081] refer to Figure 3A and Figure 3B When the contents of vanadium nitride, zinc oxide, and aluminum oxide in the capping layer CAP are 25 at % to 80 at %, 20 at % to 70 at %, and 3 at % to 10 at %, respectively, the capping layer CAP exhibits an excellent reflectance equal to or less than about 25%. When the contents of vanadium nitride, zinc oxide, and aluminum oxide in the capping layer CAP are 40 at % to 60 at %, 35 at % to 55 at %, and 5 at %, respectively, the capping layer CAP exhibits an excellent reflectance equal to or less than about 25%. Figure 3A The capping layers CAP according to Embodiments 1 to 5 exhibit uniformly low reflectance characteristics across the entire visible wavelength range. An excellent average reflectance of approximately 16.8% was obtained in Embodiment 3, where the vanadium nitride content was approximately 50 at %.

[0082] Figure 4A and Figure 4B The average reflectance values of the signal lines SL according to Embodiment 1-1 to Embodiment 1-5 are shown.

[0083] In Embodiment 1-1 to Embodiment 1-5, the conductive layer CL is formed to have The capping layer CAP is formed to have the same thickness as in Embodiments 1 to 5. The reflectance of the signal line SL to visible light having a wavelength of approximately 380 nm to 780 nm is measured using a spectrometer.

[0084] In the signal line SL according to Embodiment 1-1 to Embodiment 1-5, the conductive layer CL is formed of copper. Each of the capping layers CAP according to Embodiment 1-1 to Embodiment 1-5 is formed of vanadium nitride, zinc oxide, and aluminum oxide, and the contents of vanadium nitride, zinc oxide, and aluminum oxide are the same as those in the capping layers CAP according to Embodiment 1 to Embodiment 5.

[0085] refer to Figure 4A and Figure 4B , the signal lines SL according to Embodiments 1-1 to 1-5 exhibit an excellent reflectance of approximately 20% or less. In particular, the measured reflectance is lower than the reflectance measured from the capping layer CAP alone, and the reflectance for visible light with a wavelength in the range of approximately 550nm to 650nm is significantly reduced. This is because the conductive layer CL adds an additional destructive interference effect within a specific wavelength range. In Embodiments 1-2, 1-3, and 1-5, the signal lines SL exhibit an excellent average reflectance of approximately 10%.

[0086] As will be described below, reference Figures 2A to 4B The described signal lines SL may function as gate lines, data lines, input electrodes, output electrodes, control electrodes, input sensing lines, and input sensing electrodes of the display device DD, and this may make it possible to improve visibility of the display device DD. However, embodiments are not limited to these examples of the signal lines SL.

[0087] Figure 5 2 is a schematic block diagram illustrating a display device DD according to an embodiment. Figure 6 A plan view illustrating a portion of a display panel according to an embodiment. Figure 7A A plan view illustrating a portion of a display panel according to an embodiment. Figure 7B To follow Figure 7A Schematic cross-sectional view taken along line II'.

[0088] like Figure 5 As shown in FIG. 1 , the display device DD may include a signal control unit TC, a gate driving part GTD, a data driving part DTD, and a display panel DP.

[0089] In an embodiment, the display panel DP may be electrically connected to the gate driving part GTD and the data driving part DTD, and may be operated by electrical signals provided from the gate driving part GTD and the data driving part DTD. The display panel DP may be, for example, one of an organic light emitting display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, and an electrowetting display panel, but the embodiment is not limited to a specific type of display panel. Figure 5 、 Figure 6 、 Figure 7A and Figure 7B , a liquid crystal display device including a liquid crystal display element is described as an example of the display device DD.

[0090] The display device DD may further include a backlight unit (not shown) for providing light to the display panel DP and an optical member including a polarizer. The display panel DP may control the transmittance of light emitted from the backlight unit to display an image. However, the embodiment is not limited to this example, and in the case where the display panel DP is provided as an organic light-emitting display panel, the backlight unit may be omitted.

[0091] The display panel DP may include signal lines G1-Gm and signal lines D1-Dn and pixels PX electrically connected to the signal lines G1-Gm and signal lines D1-Dn. The signal lines G1-Gm and signal lines D1-Dn may include gate lines G1-Gm and data lines D1-Dn. In the specification, the gate lines G1-Gm may be referred to as first signal lines, and the data lines D1-Dn may be referred to as second signal lines.

[0092] The gate lines G1-Gm may extend in the first direction DR1, may be arranged in the second direction DR2, and may electrically connect the gate driving part GTD to the pixels PX. The gate lines G1-Gm may provide gate signals provided from the gate driving part GTD to the pixels PX.

[0093] The data lines D1-Dn may extend in the second direction DR2 and may be arranged in the first direction DR1. The data lines D1-Dn may electrically connect the data driving component DTD to the pixels PX. The data lines D1-Dn may provide data signals provided from the data driving component DTD to the pixels PX. The data lines D1-Dn may be provided to intersect with the gate lines G1-Gm and may be electrically separated from the gate lines G1-Gm.

[0094] Each pixel PX can be electrically connected to a corresponding one of gate lines G1-Gm and a corresponding one of data lines D1-Dn. Each pixel PX can include a thin film transistor and a liquid crystal capacitor electrically connected to the thin film transistor. The amount of charge in the liquid crystal capacitor of each pixel PX can be controlled to display an image.

[0095] The signal control unit TC can provide electrical signals for controlling the operation of the gate driving unit GTD and the data driving unit DTD to the gate driving unit GTD and the data driving unit DTD. The signal control unit TC can receive an input image signal RGB, convert the input image signal RGB into image data R'G'B' suitable for the operation of the display panel DP, and output the image data R'G'B'. The signal control unit TC can receive various control signals CS (e.g., a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, and a data enable signal) and output a first control signal CONT1 and a second control signal CONT2.

[0096] The data driving component DTD may receive a first control signal CONT1 and image data R'G'B'. The data driving component DTD may convert the image data R'G'B' into data voltages and provide the converted data voltages to the data lines D1-Dn. The first control signal CONT1 may include a horizontal start signal for starting the operation of the data driving component DTD, an inversion signal for inverting the polarity of the data voltage, an output instruction signal for determining when to output the data voltage from the data driving component DTD, and the like.

[0097] The gate drive unit GTD may output a gate signal to the gate lines G1-Gm in response to the second control signal CONT2. The second control signal CONT2 may include a vertical start signal for starting the operation of the gate drive unit GTD, a gate clock signal for determining when to output a gate voltage, an output enable signal for determining the on-pulse width of the gate voltage, and the like.

[0098] refer to Figure 6 The display panel DP may include a first substrate 100, a second substrate 200, and a liquid crystal layer 300. The first substrate 100 may include a pixel area PA. Pixels PX may be respectively arranged in the pixel area PA. In an embodiment, the pixel area PA may be used to display light generated by each pixel PX.

[0099] The liquid crystal layer 300 may be disposed between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 may include liquid crystal molecules (not shown). The liquid crystal molecules may include a material whose alignment can be controlled by an electric field generated in the pixel area PA.

[0100] Figure 7A 1 illustrates a plan view of the first substrate 100. For ease of explanation, Figure 7A The first substrate 100 is explained Figure 6 The pixel area PA of FIG. 1 is a portion corresponding to the four adjacent pixel areas PA1, PA2, PA3 and PA4. Figure 7A and Figure 7B An embodiment is described.

[0101] Four pixels PX1, PX2, PX3, and PX4 may be respectively arranged in four pixel areas PA1, PA2, PA3, and PA4. Each of the four pixels PX1, PX2, PX3, and PX4 may be electrically connected to a corresponding one of the gate lines and a corresponding one of the data lines. For example, the four pixels PX1, PX2, PX3, and PX4 may include a first pixel PX1 electrically connected to a first gate line G1 and a first data line D1, a second pixel PX2 electrically connected to the first gate line G1 and a second data line D2, a third pixel PX3 electrically connected to the second gate line G2 and the first data line D1, and a fourth pixel PX4 electrically connected to the second gate line G2 and the second data line D2. For ease of explanation, in an embodiment, one of the four pixel areas PA1, PA2, PA3, and PA4 (hereinafter, the first pixel area PA1) will be described as an example of a pixel area.

[0102] The first pixel region PA1 may be used to display light generated by the first pixel PX1. Pixels in other pixel regions may be provided to have a structure corresponding to the first pixel PX1. However, embodiments are not limited to this example or specific embodiment, and in embodiments, pixels in other pixel regions may have a structure different from that in the first pixel region PA1.

[0103] The first pixel PX1 may include a first thin film transistor TR1 and a liquid crystal display element LDD. The liquid crystal display element LDD may include a first pixel electrode PE1, a common electrode CE, and a liquid crystal layer 300.

[0104] The first substrate 100 may include a first base layer BS1, a first gate line G1, a second gate line G2, a first data line D1, a second data line D2, a first thin film transistor TR1, a second thin film transistor TR2, and insulating layers 10 and 20. The insulating layers 10 and 20 may include a first insulating layer 10 and a second insulating layer 20, as shown in FIG. Figure 7B In explanation.

[0105] The first base layer BS1 may be formed of or include an insulating material. The first base layer BS1 may be optically transparent. Accordingly, light generated by a backlight unit (not shown) disposed below the first base layer BS1 may be easily provided to the liquid crystal layer 300 through the first base layer BS1. The first base layer BS1 may include, for example, a glass substrate or a plastic substrate. Specifically, the first base layer BS1 may be a flexible substrate and may include at least one of a plastic substrate, a glass substrate, a metal substrate, and a substrate made of an organic composite material / inorganic composite material. The plastic substrate may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0106] The first gate line G1 and the second gate line G2 may be disposed between the first base layer BS1 and the first insulating layer 10. The first gate line G1 may include a portion (hereinafter, a first control electrode CE1) protruding parallel to the first direction DR1. The first thin film transistor TR1 may be electrically connected to the first gate line G1 to receive a gate signal provided from the first gate line G1.

[0107] The first insulating layer 10 may cover the first gate line G1 and the first control electrode CE1. The first insulating layer 10 may be formed of or include at least one of an organic material and an inorganic material.

[0108] The first semiconductor pattern SCP1 may be disposed on the first insulating layer 10. When viewed in a schematic cross-sectional view, the first semiconductor pattern SCP1 may be spaced apart from the first control electrode CE1 with the first insulating layer 10 interposed therebetween.

[0109] The first semiconductor pattern SCP1 may be formed of or include at least one of semiconductor materials. For example, the semiconductor material may include at least one of amorphous silicon, polycrystalline silicon, single crystal silicon, oxide semiconductor, and compound semiconductor.

[0110] The second insulating layer 20 may cover the first input electrode IE1 and the first output electrode OE1. The second insulating layer 20 may be formed of or include at least one of an organic material and an inorganic material. The first input electrode IE1 and the first output electrode OE1 may be disposed between the first insulating layer 10 and the second insulating layer 20.

[0111] The first input electrode IE1 may be a portion of the first data line D1 protruding in the second direction DR2. The first input electrode IE1, the first output electrode OE1, and the first data line D1 may be disposed on the same layer. For example, the first input electrode IE1, the first output electrode OE1, and the first data line D1 may be disposed on the first insulating layer 10.

[0112] When viewed in plan, the first input electrode IE1 may have a shape surrounding an end of the first output electrode OE1. An opposite end of the first output electrode OE1 may extend from the end and may overlap with the contact hole for electrical connection with the first pixel electrode PE1. Each of the first input electrode IE1 and the first output electrode OE1 may be disposed on the first semiconductor pattern SCP1 to directly contact the first semiconductor pattern SCP1.

[0113] However, the present invention is not limited to this example, and in an embodiment, the first input electrode IE1 and the first output electrode OE1 may be disposed on a layer different from that of the first semiconductor pattern SCP1 and may be coupled to the first semiconductor pattern SCP1 through an additional contact hole, etc. The structure of the first thin film transistor TR1 may vary variously, but the embodiment is not limited to a specific structure of the first thin film transistor TR1.

[0114] In an embodiment, at least one of the gate lines G1 and G2 and the data lines D1 and D2 may have a Figure 2A or Figure 2B The structure of the signal line SL or the signal line SL-1 described above is the same as that of the signal line SL. Figure 7B As shown in FIG, all gate lines G1 and gate lines G2 and data lines D1 and data lines D2 may have the same Figure 2A and Figure 2B The structure of the signal line SL or the signal line SL-1 described above is the same as that of the signal line SL or the signal line SL-1 described above. Therefore, the gate lines G1 and G2 and the data lines D1 and D2 of the display device DD may have a low reflectance to external light and may not be recognized by the user. Accordingly, the visibility of the display device DD may be improved. However, the present invention is not limited to this example, and in an embodiment, at least one of the data lines D1 and D2 and the gate lines G1 and G2 may have a reflectance similar to that of the reference line. Figure 2A and Figure 2B The structure of the signal line SL or the signal line SL- 1 described above is different from the structure.

[0115] In an embodiment, the first control electrode CE1 may be offset from the first gate line G1 and may have the same layer structure as the first gate line G1. The first input electrode IE1 may be offset from the first data line D1 and may have the same layer structure as the first data line D1. The first output electrode OE1 and the first data line D1 may be disposed on the same layer. The first control electrode CE1, the first input electrode IE1, and the first output electrode OE1 may have the same layer structure as the reference electrode. Figure 2A or Figure 2B The structure of the signal line SL or the signal line SL-1 described above is the same as that of the signal line SL. Therefore, the visibility of the display device DD can be improved.

[0116] The first pixel electrode PE1 may be disposed on the second insulating layer 20. The first pixel electrode PE1 and the second pixel electrode PE2 may be spaced apart from each other in the second direction DR2, with the second data line D2 interposed between the first pixel electrode PE1 and the second pixel electrode PE2. The third pixel electrode PE3 and the fourth pixel electrode PE4 may be spaced apart from the first pixel electrode PE1 and the second pixel electrode PE2, respectively, with the first gate line G1 interposed between the third pixel electrode PE3 and the first pixel electrode PE1, and between the fourth pixel electrode PE4 and the second pixel electrode PE2.

[0117] The first pixel electrode PE1 may penetrate the second insulating layer 20 and may be coupled to the first thin film transistor TR1. The first pixel electrode PE1 may receive a voltage output from the first thin film transistor TR1.

[0118] The first pixel electrode PE1 may include a first vertical portion VP1, a first horizontal portion HP1, and branch portions B1-B4. The first vertical portion VP1, the first horizontal portion HP1, and the branch portions B1-B4 may be electrically connected to each other to form a single object serving as the first pixel electrode PE1.

[0119] The first vertical portion VP1 may extend in the first direction DR1. The first vertical portion VP1 may extend parallel to the first and second data lines D1 and D2.

[0120] The first horizontal portion HP1 may be electrically connected to the first vertical portion VP1. The first horizontal portion HP1 may extend in the second direction DR2. The first horizontal portion HP1 may intersect with the first vertical portion VP1 and may be electrically connected to the first vertical portion VP1. In an embodiment, the first vertical portion VP1 and the first horizontal portion HP1 are illustrated as intersecting at their respective center portions. However, the present invention is not limited to this example, and in an embodiment, the first horizontal portion HP1 may be disposed at a position offset from the center portion of the first vertical portion VP1 toward the end. In some embodiments, the first vertical portion VP1 may be disposed at a position offset from the center portion of the first horizontal portion HP1 toward the end, but the present invention is not limited to a specific embodiment.

[0121] The branch portions B1-B4 may be electrically connected to the first horizontal portion HP1 or the first vertical portion VP1. Each of the branch portions B1-B4 may extend in a direction crossing the first direction DR1 and the second direction DR2.

[0122] The branch portions B1-B4 may radially extend from the first horizontal portion HP1 and the first vertical portion VP1. The branch portions B1-B4 may be classified into a plurality of branch portions depending on the extending directions of the branch portions B1-B4.

[0123] For example, the branch portions B1-B4 may include first to fourth branch portions B1-B4. Slits may be formed between the first branch portions B1, the second branch portions B2, the third branch portions B3, and the fourth branch portions B4. The slits may correspond to empty spaces between the first branch portions B1, the second branch portions B2, the third branch portions B3, and the fourth branch portions B4.

[0124] The first branch portions B1 may extend from the first horizontal portion HP1 or the first vertical portion VP1 in the third direction DR3 . The first branch portions B1 may be a pattern arranged to be spaced apart from each other in the fourth direction DR4 .

[0125] The second branch portions B2 may extend from the first horizontal portion HP1 or the first vertical portion VP1 in the fourth direction DR4. The second branch portions B2 may be a pattern arranged to be spaced apart from each other in the third direction DR3.

[0126] The third branch portions B3 may extend from the first horizontal portion HP1 or the first vertical portion VP1 in the fifth direction DR5. The third branch portions B3 may be a pattern arranged to be spaced apart from each other in the third direction DR3.

[0127] The fifth direction DR5 may be an opposite direction of the fourth direction DR4. Therefore, the third branch portions B3 may extend parallel to the second branch portions B2.

[0128] The fourth branch portions B4 may extend from the first horizontal portion HP1 or the first vertical portion VP1 in the sixth direction DR6. The fourth branch portions B4 may be patterns arranged to be spaced apart from each other in the fourth direction DR4.

[0129] The sixth direction DR6 may be an opposite direction to the third direction DR3 .The fourth branch portion B4 may extend parallel to the first branch portion B1 .

[0130] Because the first pixel electrode PE1 includes the branch portions B1-B4, various gradients can be achieved in a single pixel region. For example, regions where the first branch portion B1, the second branch portion B2, the third branch portion B3, and the fourth branch portion B4 are respectively disposed can be defined as separate domains.

[0131] The liquid crystal molecules in the liquid crystal layer 300 may have alignment characteristics depending on the extending directions of the first to fourth branch portions B1-B4. Therefore, it is possible to realize various gradients in respective domains of a single pixel region, and thus, the display panel DP can be used to display images with improved color reproducibility characteristics and to realize a high-resolution display device.

[0132] refer to Figure 7BThe second substrate 200 may include a second base layer BS2, a polarizing layer POL, a color filter CF, and a light blocking layer BM. The second base layer BS2 may be an optically transparent insulating substrate.

[0133] A polarizing layer POL may be disposed on the second substrate layer BS2. The polarizing layer POL may block a portion of external light. The polarizing layer POL may function as an anti-reflection layer to minimize reflection of external light. Thus, the visibility of the display device DD may be improved. The polarizing layer POL may include a circular or linear polarizer or a λ / 4 phase retarder.

[0134] The light blocking layer BM and the color filter CF may be disposed on the polarizing layer POL.

[0135] A light-blocking layer BM may be provided between pixels PX. The light-blocking layer BM may include carbon black particles. The provision of the light-blocking layer BM may prevent light mixing problems between adjacent pixel regions. In an embodiment, the light-blocking layer BM may be omitted.

[0136] The color filter CF may be disposed adjacent to a portion of the light-blocking layer BM. In an embodiment, the color filter CF may be disposed between portions of the light-blocking layer BM. The color filter CF may transmit light within a desired wavelength range and absorb light within other wavelength ranges. For example, the color filter CF may be a blue filter that transmits blue light, a green filter that transmits green light, or a red filter that transmits red light.

[0137] The liquid crystal display element LDD may be disposed between the first substrate 100 and the second substrate 200. The liquid crystal display element LDD may include a first pixel electrode PE1, a liquid crystal layer 300, and a common electrode CE. The liquid crystal layer 300 may include liquid crystal molecules LC. Figure 7B The first pixel area PA1 is explained, so in Figure 7B The first pixel electrode PE1 is explained in FIG.

[0138] The common electrode CE may generate an electric field together with the first pixel electrode PE1 . The common electrode CE may overlap each of the pixel electrode PE1 , the pixel electrode PE2 , the pixel electrode PE3 , and the pixel electrode PE4 .

[0139] The display panel DP may further include alignment layers. The alignment layers may be disposed between the liquid crystal layer 300 and the second insulating layer 20 and between the liquid crystal layer 300 and the common electrode CE, respectively. Each of the alignment layers may be used to control the initial alignment of the liquid crystal molecules LC.

[0140] Figure 8A A plan view illustrating a display panel DPa according to an embodiment. Figure 8B 2 is a schematic cross-sectional view illustrating a display module DM according to an embodiment. Figure 8AAn example is explained in which the display panel DPa is an organic light emitting display panel.

[0141] like Figure 8A As shown in FIG, when viewed in a plan view, the organic light emitting display panel DPa may include a display area DA and a non-display area NDA. The display area DA and the non-display area NDA of the organic light emitting display panel DPa may correspond to Figure 1 In an embodiment, the display area DD-DA and the non-display area DD-NDA of the display device DD may be different depending on the structure and / or design of the organic light emitting display panel DPa. Figure 1 The display area DD-DA and the non-display area DD-NDA of the display device DD are different in terms of at least one of their positions, shapes and areas.

[0142] The organic light emitting display panel DPa may include pixels PXa. The area where the pixels PXa are provided may be defined as a display area DA. In an embodiment, a non-display area NDA may be defined along an edge of the display area DA.

[0143] The organic light emitting display panel DPa may include a gate line GLa, a data line DLa, a light emitting line EL, a control signal line SL-D, an initialization voltage line SL-Vint, a voltage line SL-VDD, and a pad portion PD.

[0144] Each of the gate lines GLa can be electrically connected to a corresponding pixel in the pixels PXa, and each of the data lines DLa can be electrically connected to a corresponding pixel in the pixels PXa. The light emitting line EL can be arranged parallel to a corresponding one of the gate lines GLa. The control signal line SL-D can provide a control signal to the gate drive circuit GDC. The initialization voltage line SL-Vint can provide an initialization voltage to the pixel PXa. The voltage line SL-VDD can be electrically connected to the pixel PXa to provide a first voltage to the pixel PXa. The voltage line SL-VDD may include a line extending in a first direction DR1 and a line extending in a second direction DR2.

[0145] A gate driving circuit GDC electrically connected to the gate line GLa and the light emitting line EL may be provided in one of the side areas of the non-display area NDA. Some of the gate line GLa, the data line DLa, the light emitting line EL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD may be provided on the same layer, and the others may be provided on another layer.

[0146] The pad portion PD may be electrically connected to an end of each of the data line DLa, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD.

[0147] At least one of the gate line GLa, the data line DLa, the light emitting line EL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD may have a voltage that is equal to the reference voltage. Figure 2A or Figure 2B The structure of the signal line SL or the signal line SL-1 described above is the same as that of the signal line SL. This can reduce the reflectance of the display device DD to external light and improve the visibility of the display device DD. This will be described in more detail below.

[0148] like Figure 8B As shown in FIG, the organic light-emitting display panel DPa may include a base layer SUB, a circuit layer DP-CL disposed on the base layer SUB, an organic light-emitting display element DP-OLED disposed on the circuit layer DP-CL, and a thin encapsulation layer TFE provided on the organic light-emitting display element DP-OLED.

[0149] The substrate layer SUB may include at least one plastic film. The substrate layer SUB may be a flexible substrate and may include at least one of a plastic substrate, a glass substrate, a metal substrate, and a substrate made of an organic composite material / inorganic composite material. The plastic substrate may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0150] The circuit layer DP-CL may include an insulating layer, a conductive layer, and a semiconductor layer. The conductive layer of the circuit layer DP-CL may constitute a signal line or a pixel control circuit.

[0151] In the present disclosure, an organic light-emitting display element DP-OLED may include an anode, a cathode, and a functional layer and a light-emitting layer disposed between the anode and the cathode. The functional layer may include an electron transport layer or a hole transport layer for efficiently transporting electrons or holes. The functional layer may be formed of or include an organic compound. The light-emitting layer may be formed of or include an organic light-emitting material, but the embodiment is not limited to this example. For example, the light-emitting layer may be formed of or include a quantum dot light-emitting material.

[0152] The thin encapsulation layer TFE may seal the organic light-emitting display element DP-OLED. The thin encapsulation layer TFE may include at least one inorganic thin film and at least one organic thin film. For example, the thin encapsulation layer TFE may include at least two inorganic layers and an organic layer inserted between the at least two inorganic layers. The inorganic layer may protect the organic light-emitting display element DP-OLED from moisture or oxygen, and the organic layer may protect the organic light-emitting display element DP-OLED from contaminating materials such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer may include an acrylic organic layer, but the embodiment is not limited thereto. According to the embodiment, by adjusting the thickness of the organic layer, the uniformity of the sensitivity of the input sensing unit TS may be improved. This will be described in more detail below.

[0153] The input sensing unit TS may be disposed (or directly disposed) on the thin encapsulation layer TFE. However, embodiments are not limited to this example, and in embodiments, the inorganic layer and the input sensing unit TS may be sequentially stacked on the thin encapsulation layer TFE. The inorganic layer may be a buffer layer. The inorganic layer may be at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. However, embodiments are not limited to this example. Although the inorganic layer is described as a separate element, the inorganic layer may be part of the thin encapsulation layer TFE.

[0154] The input sensing unit TS may include an input sensor and an input signal line. The input sensor and the input signal line may have a single-layer structure or a multi-layer structure.

[0155] The input sensor and the input signal line may be formed of or include at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. In an embodiment, the input sensor and the input signal line may include a metal layer (e.g., made of molybdenum, silver, titanium, copper, aluminum, or an alloy thereof). The topmost layer of the input sensor and the input signal line may include a capping layer CAP according to an embodiment (e.g., Figure 2A The input sensor and the input signal line may have the same layer structure as each other or may have different layer structures from each other. The input sensing unit TS will be described in more detail below.

[0156] Figure 9A To explain Figure 8B In detail, Figure 9A Explained Figure 8B Amplifying structure of the input sensing unit TS. Figures 9B to 9E is a plan view illustrating an input sensing unit TS according to an embodiment.

[0157] like Figure 9A , the input sensing unit TS may include a first conductive pattern TS-CP1, a first insulating layer TS-IL1 (hereinafter, a first touch insulating layer), a second conductive pattern TS-CP2, and a second touch insulating layer TS-IL2 (hereinafter, a second touch insulating layer). The first conductive pattern TS-CP1 may be disposed (or directly disposed) on the thin encapsulation layer TFE. However, the present invention is not limited to this example, and in embodiments, an additional inorganic layer (e.g., a buffer layer) may be further disposed between the first conductive pattern TS-CP1 and the thin encapsulation layer TFE.

[0158] In some embodiments, the second touch insulating layer TS-IL2 may be omitted. A portion of the second conductive pattern TS-CP2 may intersect with the first conductive pattern TS-CP1. The second conductive pattern TS-CP2 may be electrically separated from the first conductive pattern TS-CP1, with the first touch insulating layer TS-IL1 interposed between the second conductive pattern TS-CP2 and the first conductive pattern TS-CP1; and the second conductive pattern TS-CP2 may be provided to intersect with the first conductive pattern TS-CP1.

[0159] Each of the first conductive pattern TS-CP1 and the second conductive pattern TS-CP2 may have a double-layer structure as shown. However, the embodiment is not limited to this example, and at least one of the first conductive pattern TS-CP1 and the second conductive pattern TS-CP2 may have a single-layer structure or a multi-layer structure including three or more layers stacked in the third direction DR3.

[0160] Each of the first touch insulation layer TS-IL1 and the second touch insulation layer TS-IL2 may have a Figure 2A or Figure 2B The structure of the signal line SL or the signal line SL-1 described above is the same as that of the signal line SL. This will be described in more detail below.

[0161] The shape of the first touch insulating layer TS-IL1 may vary as long as the first touch insulating layer TS-IL1 can be used to electrically separate the first conductive pattern TS-CP1 from the second conductive pattern TS-CP2. The first touch insulating layer TS-IL1 may completely cover the thin encapsulation layer TFE or may include an insulating pattern. In an embodiment, the insulating pattern may be provided to overlap with the first connection portion BR1 or the second connection portion BR2, which will be described below.

[0162] In the embodiments, a double-layer input sensing unit is described as an example of an input sensing unit TS, but the present invention is not limited to this example. A single-layer input sensing unit may include a conductive layer and an insulating layer covering the conductive layer. The conductive layer may include an input sensor and an input signal line electrically connected to the input sensor. The single-layer input sensing unit may obtain coordinate information using self-capacitance.

[0163] like Figure 9B As shown in FIG, the input sensing unit TS may include a first input sensing electrode TE1 and a second input sensing electrode TE2. The first input sensing electrode TE1 may include a first connection portion BR1, a first input sensor unit SP1 electrically connected to each other via the first connection portion BR1, and a first input signal line ISL1 electrically connected to the first input sensor unit SP1. The second input sensing electrode TE2 may include a second connection portion BR2, a second input sensor unit SP2 electrically connected to each other via the second connection portion BR2, and a second input signal line ISL2 electrically connected to the second input sensor unit SP2. A connection electrode TSD may be provided between the first input sensing electrode TE1 and the first input signal line ISL1, and between the second input sensing electrode TE2 and the second input signal line ISL2. The connection electrode TSD may be electrically connected to the ends of the first input sensing electrode TE1 and the second input sensing electrode TE2 and may be used to transmit signals. In some embodiments, the connection electrode TSD may be omitted.

[0164] In the specification, the first input signal line ISL1 may be referred to as a first signal line, and the second input signal line ISL2 may be referred to as a second signal line.

[0165] The first input sensor unit SP1 may be arranged in the first direction DR1, and the second input sensor unit SP2 may be arranged in the second direction DR2. The first input sensor unit SP1 and the second input sensor unit SP2 may be spaced apart from each other.

[0166] The first input sensing electrodes TE1 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The second input sensing electrodes TE2 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0167] Each of the first connection portions BR1 may electrically connect two adjacent first input sensor units SP1 to each other. Each of the second connection portions BR2 may electrically connect two adjacent second input sensor units SP2 to each other. In order to provide a better understanding of the embodiment, some of the first connection portions BR1 and the second connection portions BR2 may be illustrated with an exaggerated thickness. Figure 9B middle.

[0168] The input sensing unit TS may further include an input pad portion TS-PD. Each of the first and second input signal lines ISL1 and ISL2 may be electrically connected to a corresponding one of the input pad portions TS-PD.

[0169] The first input sensor unit SP1 may be capacitively coupled to the second input sensor unit SP2. When an input sensing signal is applied to the first input sensor unit SP1, a capacitor may be formed between the first input sensor unit SP1 and the second input sensor unit SP2.

[0170] Below, we will refer to Figure 9C 、 Figure 9D and Figure 9E The input sensing unit TS is described in more detail.

[0171] like Figure 9C As shown in FIG, the first conductive pattern TS-CP1 may include a second connection portion BR2. The second connection portion BR2 may be formed by patterning a conductive layer formed (or directly formed) on the thin encapsulation layer TFE of the organic light-emitting display panel DPa. In other words, the first conductive pattern TS-CP1 may be disposed (or directly disposed) on the thin encapsulation layer TFE of the organic light-emitting display panel DPa.

[0172] The first touch insulating layer TS-IL1 may be disposed on the first conductive pattern TS-CP1. The first touch insulating layer TS-IL1 may be disposed (or directly disposed) on the thin encapsulation layer TFE of the organic light emitting display panel DPa to cover each of the second connection portions BR2. Figure 9D As shown in FIG, a contact hole CH may be defined in the first touch insulating layer TS-IL1 to partially expose the second connection portion BR2. The contact hole CH may be formed by a photolithography process. The second connection portion BR2 of the first conductive pattern TS-CP1 may be electrically connected to the second input sensor unit SP2 through the contact hole CH.

[0173] refer to Figure 9E The second conductive pattern TS-CP2 may be disposed on the first touch insulating layer TS-IL1 and may include a first connection portion BR1, first input sensor units SP1 electrically connected to each other via the first connection portion BR1, and second input sensor units SP2 spaced apart from the first input sensor units SP1. As described above, the second input sensor units SP2 may be electrically connected to the first connection portion BR1 of the second conductive pattern TS-CP2 via the contact holes CH defined in the first touch insulating layer TS-IL1.

[0174] Figure 9F To explain Figure 9B An enlarged view of area A1 showing some components. Figure 10 To explain Figure 9B Magnified view of area A2.

[0175] refer to Figure 9F and Figure 10Each of the first and second input sensor cells SP1 and SP2 may include mesh lines MSL defining mesh holes MH. The line width of each of the mesh lines MSL may be several micrometers. Each of the first and second input sensor cells SP1 and SP2 may have a mesh shape. Although not shown, the first and second input signal lines ISL1 and ISL2 may also have a mesh shape. Each of the first and second input sensor cells SP1 and SP2 may overlap the non-luminescent area NPXA.

[0176] When viewed in a plan view, the mesh holes MH may have at least two different areas. Although the mesh holes MH are explained as corresponding to the light-emitting areas PXA in a one-to-one manner, the embodiment is not limited to this example. For example, each mesh hole MH may correspond to two or more light-emitting areas PXA. If necessary, the areas of the light-emitting areas PXA may vary differently. In this regard, when viewed in a plan view, the mesh holes MH may have at least two different areas. For example, the light-emitting areas PXA may include a red light-emitting area, a green light-emitting area, and a blue light-emitting area, and the area of the light-emitting area PXA may be determined depending on its color. However, the embodiment is not limited to this example. For example, the light-emitting areas PXA may have the same area, and the mesh holes MH may also have the same area.

[0177] like Figure 10 , the first connection portion BR1 and the second connection portion BR2 may be arranged to intersect each other. The first connection portion BR1 and the second connection portion BR2 may be electrically separated from each other, with the first touch insulation layer TS-IL1 interposed therebetween, and the first connection portion BR1 and the second connection portion BR2 may intersect each other. However, the embodiment is not limited to this example.

[0178] like Figure 10 , each of the first connection portion BR1 and the second connection portion BR2 may have a mesh shape. However, the present invention is not limited to this example, and in an embodiment, the second connection portion BR2 may not have a mesh shape.

[0179] exist Figure 10 , adjacent first input sensor units SP1 are illustrated as being electrically connected to each other through two first connection portions BR1, but the embodiment is not limited to this example. For example, adjacent first input sensor units SP1 may be electrically connected to each other through one second connection portion BR2.

[0180] Figure 11 To explain the Figure 10 A schematic cross-sectional view of a vertical section taken along line II-II'. Figure 11In the embodiment, the second connecting portion BR2 may correspond to Figure 9A The first conductive pattern TS-CP1 shown in FIG, and the first input sensor unit SP1, the first connection portion BR1, and the second input sensor unit SP2 may correspond to the second conductive pattern TS-CP2.

[0181] refer to Figure 9A and Figure 11 , the first conductive pattern TS-CP1 and the second conductive pattern TS-CP2 may have the same Figure 2A or Figure 2B In other words, the first input signal line ISL1, the second input signal line ISL2, the first input sensing electrode TE1, the second input sensing electrode TE2, the first connection portion BR1 and the second connection portion BR2 may have the same structure as that of the reference signal line SL or the signal line SL-1. Figure 2A or Figure 2B The first input signal line ISL1, the second input signal line ISL2, the first input sensing electrode TE1, the second input sensing electrode TE2, the first connection portion BR1 and the second connection portion BR2 may each independently include a conductive layer CL (e.g., Figure 2A and a capping layer CAP (eg, a conductive layer CL) provided on the conductive layer CL. Figure 2A The capping layer CAP can reduce the reflectance of the input sensing unit TS, and the input sensing unit TS may not be recognized by the user. Accordingly, the visibility of the display device DD can be improved.

[0182] Figure 9A and Figure 11 It is explained that all the first conductive patterns TS-CP1 and the second conductive patterns TS-CP2 have the same Figure 2A or Figure 2B The example of the structure of the signal line SL or the signal line SL-1 described above is the same, but in an embodiment, only one of the first conductive pattern TS-CP1 and the second conductive pattern TS-CP2 may have the same structure as Figure 2A or Figure 2B The structure of the signal line SL or the signal line SL-1 is the same as that of the signal line SL.

[0183] Figures 9A to 11 The example in which the input sensing unit TS has a double-layer structure is explained. However, in the case where the input sensing unit TS has a single-layer structure (which has one conductive layer), such a conductive layer may have the same Figure 2A or Figure 2B The structure of the signal line SL or the signal line SL-1 is the same as that of the signal line SL.

[0184] 12A to 12CA schematic cross-sectional view illustrating a method for forming a signal line according to an embodiment. Figure 2A and Figure 2B Described elements may be identified by the same reference numerals.

[0185] refer to Figure 12A , the initial conductive layer CL-S and the initial capping layer CAP-S may be stacked (or sequentially stacked) on the support member BS. The initial conductive layer CL-S may include the same material as that of the conductive layer CL, and the initial capping layer CAP-S may include the same material as that of the capping layer CAP. The initial conductive layer CL-S and the initial capping layer CAP-S may be formed by a deposition or coating process. In an embodiment, each of the initial conductive layer CL-S and the initial capping layer CAP-S may be formed by a sputtering process (e.g., a DC sputtering process). In an embodiment, the initial conductive layer CL-S and the initial capping layer CAP-S may be formed by a process that can be performed sequentially and continuously.

[0186] refer to Figure 12B and Figure 12C The initial conductive layer CL-S and the initial capping layer CAP-S may be patterned to form some patterns. The patterns may correspond to the first gate line G1 (eg, Figure 7A For example, the pattern may correspond to the second conductive pattern TS-CP2 (eg, Figure 9A second conductive pattern TS-CP2).

[0187] The initial conductive layer CL-S and the initial capping layer CAP-S may be patterned through an etching process. A photoresist pattern PR may be formed on the initial conductive layer CL-S and the initial capping layer CAP-S through a photolithography process, and an etching solution ET may be provided onto the structure having the photoresist pattern PR. Portions of the initial conductive layer CL-S and the initial capping layer CAP-S exposed by the photoresist pattern PR may be etched and removed by the etching solution ET.

[0188] The etching solution ET may be a non-hydrogen peroxide solution. For example, the etching solution ET may be a non-hydrogen peroxide solution containing phosphoric acid, nitric acid, and acetic acid. The initial conductive layer CL-S and the initial capping layer CAP-S may be formed from materials reactive with the aforementioned etching solution ET. However, the present invention is not limited to this example, and in an embodiment, if an etching solution containing hydrogen peroxide can be used to effectively etch the initial conductive layer CL-S and the initial capping layer CAP-S, it may be selected as the etching solution ET.

[0189] The initial conductive layer CL-S and the initial capping layer CAP-S may be etched in the order in which they are exposed to the etching solution ET. Therefore, the initial capping layer CAP-S and the initial conductive layer CL-S may be etched in the listed order.

[0190] When the content of zinc oxide in the initial capping layer CAP-S is less than about 70 at % and the initial conductive layer CL-S is formed of copper, the signal line SL can be etched at an appropriately adjusted etching rate and no tip portion may be formed. When the thickness is , the signal line SL may be formed without forming the tip portion. The tip portion may be formed on a layer (eg, Figure 7B Therefore, in the case of forming the tip portion, the layer formed in the subsequent process may be easily damaged by external impact, and this may cause the manufacturing process to be locally damaged. Figure 1 The reliability of the process of the display device DD is deteriorated.

[0191] In contrast, in the method of forming a signal line according to an embodiment, it is possible to form the signal line without forming a tip portion, and thus, a display device DD (eg, a display device DD) having low reflectivity and high process reliability can be manufactured. Figure 1 display device DD).

[0192] In an embodiment, the signal line may include a conductive layer and a capping layer, wherein the capping layer is provided (or directly provided) on the conductive layer and contains vanadium nitride and zinc oxide. The signal line may have a low reflectance to external light, and therefore, the signal line may make it possible to realize a display device with improved visibility.

[0193] According to an embodiment, a display device may include a signal line having a low reflectance to external light, and thus, visibility of the display device may be improved.

[0194] While embodiments have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A display device, comprising: basal layer; a display element, the display element being disposed on the base layer; and a signal line provided on the base layer and electrically connected to the display element, The signal lines include: conductive layer; and A capping layer is provided on the conductive layer and includes aluminum oxide, vanadium nitride, and zinc oxide.

2. The display device according to claim 1, wherein in the capping layer: The content of vanadium nitride is in the range of 25 at % to 80 at %, The content of zinc oxide is in the range of 20 at % to 70 at %, and The content of aluminum oxide is in the range of 3 at % to 10 at %, The sum of the content of the vanadium nitride, the content of the zinc oxide, and the content of the aluminum oxide is 100 at %. The display device according to claim 1 , wherein a reflectance of the capping layer is lower than a reflectance of the conductive layer. 4 . The display device according to claim 1 , wherein an average reflectance of the signal line to visible light is equal to or less than 20%.

5. The display device according to claim 1 , wherein the signal line further comprises an intermediate layer provided between the conductive layer and the capping layer, and The intermediate layer has a refractive index between the refractive index of the conductive layer and the refractive index of the capping layer. 6 . The display device according to claim 5 , wherein the intermediate layer includes at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, and aluminum oxide.

7. The display device according to claim 1, wherein the thickness of the capping layer is to within the range.

8. A display device, comprising: First signal line; and a second signal line, the second signal line being spaced apart from the first signal line, At least one of the first signal line and the second signal line comprises: conductive layer; and A capping layer is provided on the conductive layer and includes aluminum oxide, vanadium nitride, and zinc oxide. 9 . The display device according to claim 8 , wherein an average reflectance of the capping layer to visible light is equal to or less than 25%.

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