Power semiconductor devices and methods

Abstract

Power semiconductor devices and methods are disclosed. The power semiconductor device (1) includes: a semiconductor body (10) having a front surface (10-1) and including a drift region (100) with dopants of a first conductivity type; and an edge-terminating region (105) included in the semiconductor body (10). The edge-terminating region (105) includes: a portion of the drift region (100); and a first semiconductor region (103) extending along the front surface (10-1). The first semiconductor region (103) includes dopants of first and second conductivity types, wherein the integrated vertical dopant concentration of the second conductivity type dopant within the first semiconductor region (103) is higher than the integrated vertical dopant concentration of the first conductivity type dopant. The first dose profile (D_1), representing the vertical integral net dopant concentration of the first and second conductivity types of dopants in the first doped semiconductor region (103), exhibits a smaller degree of fluctuation along the horizontal direction (X, Y) compared to the second dose profile (D_2), representing the vertical integral dopant concentration of the second conductivity type of dopants in the first doped semiconductor region (103).

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor devices and embodiments of methods for manufacturing power semiconductor devices. In particular, this specification relates to aspects of power semiconductor devices including doped semiconductor regions within edge termination regions. Background Technology

[0002] Many functions of modern devices in automotive, consumer, and industrial applications—such as converting electrical energy and driving electric motors or generators—rely on power semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a variety of applications, including, but not limited to, switching in power supplies and power converters.

[0003] Power semiconductor devices typically include a semiconductor body configured to conduct load current along a load current path between two load terminals of the device.

[0004] Furthermore, to conduct load current, the power semiconductor device may include one or more power cells, which may be arranged in the so-called active region (or active area) of the power semiconductor device. For example, in the case of a controllable power semiconductor device (e.g., a transistor), the load current path may be controlled by means of an insulated electrode, often also referred to as the gate electrode. For example, when a corresponding control signal is received from, for example, a driver unit, the control electrode may set the power semiconductor device to one of an on state and an off state. In some cases, the gate electrode may be included within a trench of the power semiconductor switch, wherein the trench may be arranged, for example, in a strip-like or needle-like configuration.

[0005] Power semiconductor devices may be laterally defined by edges such as lateral chip edges. Between the edge and the active region comprising one or more power cells, an edge-terminating region may be arranged, which may include an edge-terminating structure. Such an edge-terminating structure can be used for the purpose of influencing the path of the electric field within the semiconductor body, in order to, for example, ensure reliable blocking capability of the power semiconductor device. The edge-terminating structure may include one or more components disposed within the semiconductor body and one or more components disposed above the surface of the semiconductor body.

[0006] Some common edge-termination structures, such as lateral doping variation (VLD) edge-termination structures, comprise one or more doped semiconductor regions with defined shapes. It is generally desirable to create such doped semiconductor regions at relatively low cost, for example, in a manner that allows for relatively fine definition of their shapes but does not require specialized lithography techniques with very fine resolution. Summary of the Invention

[0007] The aspects described herein relate to a specific design of a doped semiconductor region within the edge-termination region of a power semiconductor device, wherein a portion of a first implanted dopant dose of one conductivity type (e.g., p-type) is compensated by a second implanted dopant dose of a complementary conductivity type (e.g., n-type). For example, the second implanted dopant can diffuse to a smaller lateral extent compared to the first implanted dopant. As a result, fluctuations in the vertically integrated net dopant concentration of the doped semiconductor region can be reduced.

[0008] According to an embodiment, a power semiconductor device includes: a semiconductor body having a front surface and including a drift region with dopants of a first conductivity type; and an edge-terminating region included in the semiconductor body and including: a portion of the drift region; a first semiconductor region extending along the front surface, the first semiconductor region including dopants of the first conductivity type and dopants of a second conductivity type complementary to the first conductivity type, wherein the integrated vertical dopant concentration of the second conductivity type dopants in the first semiconductor region is higher than the integrated vertical dopant concentration of the first conductivity type dopants. The first semiconductor region and the drift region form a continuous pn junction. A first dose profile representing the vertical integrated net dopant concentration of the first conductivity type dopants and the second conductivity type dopants in the first doped semiconductor region exhibits a smaller degree of undulation in the horizontal direction compared to a second dose profile representing the vertical integrated dopant concentration of the second conductivity type dopants in the first doped semiconductor region.

[0009] According to another embodiment, a method for manufacturing a power semiconductor device is provided. The method includes: providing a semiconductor body having a front surface and including a drift region with a dopant of a first conductivity type; and forming an edge-terminating region within the semiconductor body. Forming the edge-terminating region includes forming a first doped semiconductor region extending along the front surface and forming a continuous pn junction with the drift region, wherein forming the first doped semiconductor region includes the steps of: implanting a dopant of a second conductivity type through the front surface by means of a first mask implantation, wherein the first mask is used for the first mask implantation, the first mask defining a first opening region and a first masking region; and implanting a dopant of the first conductivity type through the front surface by means of a second mask implantation, wherein the second mask is used for the second mask implantation, the second mask defining a second opening region and a second masking region. The first mask and the second mask are arranged on the semiconductor body in such a way that the opening region of the second mask placed on the first doped semiconductor region during the second implantation step horizontally overlaps with the opening region of the first mask placed on the first doped semiconductor region during the first mask implantation. Furthermore, the first mask and the second mask are arranged on the semiconductor body in such a way that the closed region of the second mask placed on the first doped semiconductor region during the second implantation step horizontally overlaps with the closed region of the first mask placed on the first doped semiconductor region during the first mask implantation.

[0010] According to a further embodiment, a method of manufacturing a power semiconductor device includes: providing a semiconductor body having a front surface and including a drift region of a dopant having a first conductivity type; and forming an edge termination region within the semiconductor body, wherein forming the edge termination region includes: forming a first doped semiconductor region extending along the front surface and forming a continuous pn junction with the drift region; and forming a further doped semiconductor region in the semiconductor body. Forming a first doped semiconductor region and a further doped semiconductor region includes the following steps: forming a structured shielding layer on the front side, the structured shielding layer covering the first doped semiconductor region to be formed, wherein the structured shielding layer is not present on the further doped semiconductor region to be formed; in a first implantation step, using a first mask, implanting a dopant through the structured shielding layer and into the semiconductor body at a first implantation energy; in a further implantation step, using a first mask, implanting a dopant into the structured shielding layer and into the semiconductor body at a second implantation energy lower than the first implantation energy; wherein the first mask is open above the further doped semiconductor region to be formed, and wherein the first mask defines a first opening region and a first masking region, wherein, in a cross-section along the horizontal direction, the area ratio of the opening region above the first semiconductor region to the masking region decreases in the direction from the active region of the power semiconductor device to the lateral edge of the semiconductor body.

[0011] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0012] The components in the figures are not necessarily to scale. Instead, the focus is on illustrating the principles of the invention. Furthermore, in each figure, the same reference numerals indicate corresponding components. In the figures:

[0013] Figures 1A to 1G Each of the above schematically and exemplary illustrations depicts a process step of a method for producing a power semiconductor device according to one or more embodiments;

[0014] Figures 2A to 2G Each of the above schematically and exemplary illustrations depicts a process step of a method for producing a power semiconductor device according to one or more embodiments;

[0015] Figures 3A to 3F Each of the above schematically and exemplary illustrations depicts a process step of a method for producing a power semiconductor device according to one or more embodiments;

[0016] Figures 4A to 4E Each of the above schematically and exemplary illustrations depicts a process step of a method for producing a power semiconductor device according to one or more embodiments;

[0017] Figures 5A to 5D Each of the above schematically and exemplary illustrations depicts a process step of a method for producing a power semiconductor device according to one or more embodiments;

[0018] Figure 6 A segment of a vertical cross-section of a power semiconductor device according to one or more embodiments is illustrated schematically and exemplary.

[0019] Figure 7 A segment of a vertical cross-section of a power semiconductor device according to one or more embodiments is illustrated schematically and exemplary.

[0020] Figure 8 A segment of a vertical cross-section of a power semiconductor device according to one or more embodiments is illustrated schematically and exemplary.

[0021] Figure 9 A segment of a vertical cross-section of a power semiconductor device according to one or more embodiments is illustrated schematically and exemplary.

[0022] Figure 10 A segment of a vertical cross-section of a power semiconductor device according to one or more embodiments is illustrated schematically and exemplary.

[0023] Figures 11A to 11E Each of the schematic and exemplary illustrations depicts a segment of the injection mask used in a method according to one or more embodiments;

[0024] Figures 12A to 12E Each schematically and exemplary illustration depicts a segment of two different injection masks used in a method according to one or more embodiments;

[0025] Figure 13 The diagram schematically and exemplary illustrates the lateral profile of the doping dose (after diffusion) according to one or more embodiments;

[0026] Figure 14 The diagram schematically and exemplary illustrates the lateral profile of the net doping dose (after diffusion) according to one or more embodiments;

[0027] Figure 15 The diagram schematically and exemplary illustrates the lateral profile of the net doping dose (after diffusion) according to one or more embodiments;

[0028] Figure 16 The diagram schematically and exemplary illustrates the lateral profile of the net doping dose (after diffusion) according to one or more embodiments;

[0029] Figures 17A to 17C Each schematically and exemplary illustration depicts a lateral profile of the doping dose (after diffusion) according to one or more embodiments; and

[0030] Figures 18A to 18C Each of the schematic and exemplary illustrations depicts a segment of the injection mask used in a method according to one or more embodiments. Detailed Implementation

[0031] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and specific embodiments in which the invention may be practiced are illustrated by way of example.

[0032] In this regard, directional terms such as "top," "bottom," "below," "front," "back," "rear," "lead," "end," and "above" may be used with reference to the orientation of the figures described. Because the components of the embodiments can be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description is not intended to be limiting, and the scope of the invention is defined by the appended claims.

[0033] Reference will now be made in detail to various embodiments, with one or more examples of each embodiment illustrated in the figures. Each example is provided by way of explanation and is not intended to limit the invention. For example, a feature illustrated or described as one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another further embodiment. It is intended that the invention include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same reference numerals designate the same elements or manufacturing steps in different drawings.

[0034] As used in this specification, the term "horizontal" is intended to describe an orientation of a horizontal surface that is substantially parallel to a semiconductor substrate or semiconductor structure. This can be, for example, the surface of a semiconductor wafer, die, or chip. For example, both the first lateral (or horizontal) direction X and the second lateral (or horizontal) direction Y mentioned below and / or shown in the figures can be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0035] As used in this specification, the term "vertical" is intended to describe an orientation that is substantially arranged perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the vertical direction Z mentioned below and / or shown in the figures may be a direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0036] In this specification, n-doping generally refers to "first conductivity type" and p-doping refers to "second conductivity type". Alternatively, the opposite doping relationship can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0037] In the context of this specification, the terms "using ohmic contact," "using electrical contact," "using ohmic connection," and "electrical connection" are intended to describe a low-ohmic electrical connection or low-ohmic current path between two regions, segments, zones, portions, or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a portion or component of a semiconductor device. Further, in the context of this specification, the term "contact" is intended to describe a direct physical connection between two elements of a respective semiconductor device; for example, a transition between two elements in contact with each other may not include further intermediate elements, etc.

[0038] Furthermore, in the context of this specification, unless otherwise stated, the term "electrically insulated" is used in the context of its generally valid understanding and is therefore intended to describe two or more components positioned separately from each other and without any ohmic connection connecting those components. However, components electrically insulated from each other can still be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. For example, the two electrodes of a capacitor can be electrically insulated from each other and simultaneously coupled to each other mechanically and capacitively, for example, by means of an insulation (e.g., a dielectric).

[0039] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices presenting a single cell, strip cell, or honeycomb (also referred to as "needle" or "pillar") cell configuration, such as power semiconductor devices that can be used within a power converter or power supply. Therefore, in embodiments, such devices can be configured to carry load current to be fed to a load and / or corresponding load current provided by a power source. For example, a power semiconductor device may include one or more active power semiconductor cells, such as monolithically integrated diode cells, derivatives of monolithically integrated diode cells (e.g., a monolithically integrated cell of two diodes connected in reverse series), monolithically integrated transistor cells (e.g., a monolithically integrated IGBT or MOSFET cell), and / or derivatives thereof. Such diode cells / transistor cells can be integrated in a power semiconductor module. Multiple such power cells can constitute a cell field region of an active region where a power semiconductor device is arranged.

[0040] As used in this specification, the term "power semiconductor device" is intended to describe a semiconductor device having high voltage blocking capability and / or high current carrying capability on a single chip. In other words, such a power semiconductor device is intended for use with high currents typically in the ampere range, such as tens or hundreds of amperes, and / or such a power semiconductor device is intended for use with high voltages typically above 15V, more typically 100V and above (e.g., at least 400V or even higher, such as at least 3 kV, or even 6 kV or higher).

[0041] For example, the power semiconductor devices described below can be single semiconductor chips presenting a single cell configuration, a strip cell configuration, or a cellular cell configuration, and can be configured to be used as power components in low, medium, and / or high voltage applications.

[0042] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices, such as those used for storing data, computing data, and / or other types of semiconductor-based data processing.

[0043] Figures 1A to 1G Each of the above schematically and exemplary illustrations depicts a processing step of a method for producing a power semiconductor device 1 according to one or more embodiments.

[0044] At the beginning, a semiconductor body 10 having a front surface 10-1 is provided (see...). Figure 1A For example, the semiconductor body 10 may be provided in the form of a wafer having wafer surfaces 10-1 extending in each of a first horizontal direction X and a second horizontal direction Y (i.e., in the horizontal plane XY).

[0045] The semiconductor body 10 includes a drift region 100 of a first conductivity type (e.g., n-type). For example, the drift region may be an intrinsically doped region of the semiconductor body 10. Alternatively, the drift region may have been formed by implantation of a dopant of the first conductivity type. The drift region may be, for example, n-type. - The doped region can be configured to conduct load current through the (processed) power semiconductor device 1.

[0046] As a further step, the method may include forming an edge termination region 105 within the semiconductor body 10. For example, according to... Figures 1A to 1G In some embodiments, the edge termination region 105 may form at least a portion of a lateral doping variation (VLD) edge termination region. That is, the edge termination region 105 to be formed may exhibit a lateral variation in the average net dopant concentration in the direction from the active region toward the lateral edge of the semiconductor body 10, such that a higher average dose exists closer to the active region compared to a location near the lateral edge. Therefore, in embodiments, the method may include producing such a VLD region or at least a portion thereof.

[0047] Forming the edge termination region 105 may include forming a first doped semiconductor region 103 in the semiconductor body 10 by means of a dopant of a second conductivity type (e.g., p-type) through a first mask implantation on the front surface 10-1. For example, as a result of the first mask implantation, a first implantation surface region 1031 may be formed below the first opening region (see...). Figure 1B For example, a first mask 21 (such as a resist mask or a hard mask) can be used for first mask injection, the first mask defining a first opening region and a first masking region (see...). Figure 1A ).

[0048] Regarding the layout of the first mask 21, for example, in cross-sections along the horizontal directions X and Y (e.g., in cross-sections along each of the first horizontal direction X and the second horizontal direction Y), the area ratio of the first opening region to the first masking region above the first semiconductor region 103 may be in the direction from the active region of the power semiconductor device 1 to the lateral edge of the semiconductor body 10 ( Figures 1A to 1G (Not illustrated) decreases (e.g., decreases on average, i.e., not necessarily monotonically). Therefore, as intended for the VLD edge termination region 105, lateral variations in dopant concentration can be achieved. This will be further explained below. Figures 18A to 18C This can be more easily understood at that time.

[0049] Forming the first doped semiconductor region 103 may further include at least one diffusion step to diffuse a dopant of a second conductivity type. In this diffusion step, the first implanted surface region 1031 may be widened and deepened to form as schematically and exemplary illustrated. Figures 1C to 1D Such a first doped semiconductor region 103. For example, as a result of at least one diffusion step, the first doped semiconductor region 103 can extend seamlessly along the front surface 10-1 inside the semiconductor body 10 and form a continuous pn junction J with the drift region 100.

[0050] The pn junction J can limit the path of fluctuations or undulations, such as in Figure 1D As illustrated schematically and exemplary. For example, in an embodiment, the vertically extending wave profile C of the dopant describing the second conductivity type from the front side 10-1 to the semiconductor body 10 may exhibit multiple local maxima, wherein adjacent local maxima of the wave profile C may be spaced apart from each other by at least a third horizontal h3 distance, the third horizontal h3 distance totaling at least 2 μm (see [link to documentation]). Figure 1D ).

[0051] Forming the first doped semiconductor region 103 may further include implanting a dopant of a first conductivity type (e.g., n-type) through the front surface 10-1 (see [link to documentation]) by means of a second mask implantation step. Figure 1E As a result of the second mask injection, the second injection surface region 1041 can be formed below the second opening region (see...). Figure 1F ).

[0052] For example, a second mask 22 is used for a second mask injection, defining a second opening region and a second masking region. It should be noted that the second mask 22 can be the same as the first mask 21. In other words, the same masks 21 and 22 can be used for both the first and second mask injections.

[0053] More generally, the second implantation can be performed using a structuring associated with one of the first implantations. In an embodiment, the first mask 21 and the second mask 22 can be arranged on the semiconductor body 10 such that the opening region of the second mask 22, placed on the first doped semiconductor region 103 during the second implantation step, horizontally overlaps with the opening region of the first mask 21, placed on the first doped semiconductor region 103 during the first mask implantation. Further, the first mask 21 and the second mask 22 can be arranged on the semiconductor body 10 such that the closed region of the second mask 22, placed on the first doped semiconductor region 103 during the second implantation step, horizontally overlaps with the closed region of the first mask 21, placed on the first doped semiconductor region 103 during the first mask implantation.

[0054] For example, the opening region of the second mask 22 may be entirely located within the region where the opening region of the first mask 21 already exists. Therefore, the opening region of the second mask 22 may be smaller than the opening region of the first mask 21.

[0055] According to Figures 1B to 1F In some embodiments, at least one of the diffusion steps mentioned above may be performed before injecting a dopant of the first conductivity type.

[0056] The dopant of the first conductivity type, already implanted in the second implantation step, can also diffuse to widen and deepen the second implantation surface region 1041 into the second doped semiconductor region 104 (see [link]). Figure 1G For example, a dopant of the first conductivity type can diffuse to a smaller lateral extent than a dopant of the second conductivity type, such that the second doped semiconductor region 104 remains arranged (e.g., separated from each other) within the first implantation region 103, as in Figure 1G As shown in the diagram.

[0057] The result could be a first doped semiconductor region 103 (including a second doped semiconductor region 104) exhibiting a more uniform net dose distribution compared to a VLD structure created using conventional methods with the same structure size (i.e., the same size first mask opening). This will be referred to below. Figures 13 to 17C To explain in further detail, Figures 13 to 17C The illustration shows an exemplary lateral dose profile of the first doped semiconductor region 103.

[0058] For example, in one embodiment, implanted dopants of a first conductivity type can be formed in regions where they have a higher concentration compared to dopants of a second conductivity type (within the second doped semiconductor region 104). This can be referred to as local overcompensation. Alternatively, implanted dopants of the first conductivity type can have a lower concentration compared to dopants of the second conductivity type anywhere, which can be referred to as partial compensation.

[0059] Figures 2A to 2G The above reference is illustrated schematically and exemplary. Figures 1A to 1G The described method includes a variant of the processing steps. In this variant, dopants of a first conductivity type and a second conductivity type are implanted through a shielding layer 3 (such as an oxide layer), which is disposed above the front surface 10-1 (e.g., directly on the front surface 10-1). Thus, for example, Figures 2A to 2G A method for generating VLD region 103 when thick oxide 3 is arranged over edge termination region 105 can be shown.

[0060] For example, when the first mask 21 and / or the second mask 22 are resist masks, the thickness of the resist used for masks 21, 22 can be at least twice the thickness of the thick oxide 3 beneath the resist.

[0061] Furthermore, such as in Figures 3A to 3F As schematically and exemplaryly illustrated, the proposed method can also be integrated into more comprehensive processes that may require additional lithographic layers. This is particularly relevant when a relatively thick oxide 3 (e.g., an oxide thicker than other oxides in other portions of the gate oxide and / or semiconductor body 10) is present above the edge termination region 105 to be formed (see [reference]). Figures 2A to 2G The masks 21 and 22 used to form the edge termination region 105 (e.g., VLD region 103) can also be used for additional implantation with lower energy, which is masked by the thick oxide 3 but not masked in other portions of the semiconductor body 10 that are neither covered by the thick oxide 3 nor by the masks 21 and 22. See [link to documentation]. Figures 3A to 3F This can be referenced to the masks 21, 22(s) used for the first implantation and / or for the second implantation. However, it should be noted that, for example, the thin oxide 4 (thinner than the thick oxide 3) may be present in other portions of the semiconductor body, as in... Figures 3A to 3F As shown in the diagram. For example, the thickness of such a thin oxide 4 can be at most one-third the thickness of the oxide layer 3. For example, the thickness of the thin oxide 4 can be in the range of 20 nm to 200 nm.

[0062] Therefore, in embodiments of the proposed method, a dopant of a first conductivity type and / or a dopant of a second conductivity type is implanted through a shielding layer 3, such as an oxide layer, disposed above the front surface 10-1. The method may further include forming a third doped semiconductor region 106 extending along the front surface 10-1 in a region where the front surface 10-1 is not covered by an oxide layer (such as oxide layer 3), or where the front surface 10-1 is at most covered by a thin oxide layer 4, as in… Figures 3A to 3F As illustrated in the example diagram. Therefore, according to... Figures 3A to 3F In the embodiment illustrated in the figure, a further (third) doped semiconductor region 106, for example in the form of a deep p-well, can be created next to the VLD region 10.

[0063] For example, the shielding layer 3 may include or be composed of an oxide layer having a thickness of at least 400 nm. Further, in an embodiment, a third mask implantation may be performed at a lower energy than the first mask implantation, such that the second type of dopant does not penetrate the oxide layer 3 during the third mask implantation. This is in Figure 3C The illustration is exemplarily shown in the figure. Figure 3C In addition to the implantation surface region 1061 within the semiconductor body 10 where the shielding layer 3 is absent, an implantation region 1062 within the shielding layer 3 is also shown. Further, Figures 3B to 3C The diagram shows a first implantation surface region 1031 and a (deeper) implantation region 1032 in the semiconductor body 10, which are generated from the first mask implantation. After diffusion, the implantation surface region 1061 and the (deeper) implantation region 1031 together can form a third doped semiconductor region 106, such as in, for example, in Figure 3D As shown in the diagram.

[0064] In an embodiment, the same mask 21 can be used for both the first and third mask injections. Alternatively, the same mask 22 can be used for both the first and third mask injections. For example, in this case, the same (second) mask 22 can be used to perform a further (fourth) injection, wherein the fourth injection can create an n-well that functions, for example, as a channel stop region (not shown).

[0065] For example, in one embodiment, a method for processing a power semiconductor device according to one or more embodiments may include:

[0066] - Provide a semiconductor body 10 having a front surface 10-1 and including a drift region 100 with a dopant having a first conductivity type;

[0067] - An edge termination region 105 is formed inside the semiconductor body 10, wherein forming the edge termination region 105 includes:

[0068] - A first doped semiconductor region 103 is formed, extending along the front surface 10-1 and forming a continuous pn junction J with the drift region 100.

[0069] - Forming a further doped semiconductor region 106 in the semiconductor body 10, wherein the formation of the first doped semiconductor region 103 and the further doped semiconductor region 106 includes the following steps:

[0070] - A structured shielding layer 3 is formed on the front side 10-1, the structured shielding layer 3 covering the first doped semiconductor region 103 to be formed, wherein the structured shielding layer 3 is not present on the further doped semiconductor region 106 to be formed (however, it should be noted that a thin oxide 4 may be present on the further doped semiconductor region 106 to be formed).

[0071] - In the first implantation step, the dopant is implanted through the structured shielding layer 3 and into the semiconductor body 10 by means of the first mask 21 under the first implantation energy;

[0072] - In a further implantation step, the dopant is implanted into the structured shielding layer 3 and into the semiconductor body 10 at a second implantation energy lower than the first implantation energy by means of the first mask 21.

[0073] The first mask 21 is open over the further doped semiconductor region 106 to be formed, and the first mask 21 defines a first opening region and a first masking region, wherein in a cross section along the horizontal X, Y directions, the area ratio of the opening region over the first semiconductor region 103 to the masking region decreases in the direction from the active region of the power semiconductor device 1 to the lateral edge of the semiconductor body 10 (e.g., decreases on average, i.e., not necessarily monotonically).

[0074] In one embodiment, the dopant implanted through the first mask 21 in the first step may have an implantation maximum value located in the shielding layer 3 above the first doped semiconductor region 103 to be formed. Further, in another embodiment, the dopant implanted through the first mask 21 in the second implantation step may have an implantation maximum value located in the first semiconductor region 103.

[0075] For example, the formation of the first doped semiconductor region 103 and the further doped semiconductor region 106 may further include performing at least one diffusion step to diffuse the dopant.

[0076] Figures 4A to 4EAn embodiment is illustrated schematically and exemplary, in which the same mask 21 is used for both the first implantation (of the dopant of the second conductivity type) and the second implantation (of the dopant of the first conductivity type). Mask 21 can be, for example, a resist mask or a hard mask. In the case of a resist mask, no diffusion treatment may be applied between the first and second implantations. In this case, two elements with different diffusion constants should be used as dopants (e.g., boron for p-type and arsenic for n-type), see [reference needed]. Figures 4A to 4D .

[0077] For example, in an embodiment, a dopant of a first conductivity type may have a first diffusion constant in the semiconductor body 10, and a dopant of a second conductivity type may have a second diffusion constant in the semiconductor body 10, the second diffusion constant being at least 3 times greater than the first diffusion constant.

[0078] In an embodiment, the diffusion length of the dopant of the first conductivity type is within 30% to 70% of the diffusion length of the dopant of the second conductivity type. The diffusion length can be defined using a vertical doping profile. Thus, the diffusion length can be defined as the difference in depth between the location of the maximum value of the doping profile and the location where the profile has reached a concentration with the maximum value divided by e (Euler number e = 2.718…).

[0079] For example, in an embodiment, the maximum structural size of the masks 21, 22 used to form the first doped semiconductor region 103 is no greater than twice the diffusion length of the p-type dopant, such as no greater than 1.5 times the diffusion length of the p-type dopant.

[0080] Furthermore, in an exemplary embodiment, the amount of n-type dopant implanted into the semiconductor body 10 is in the range of 10% to 60% of the amount of p-type dopant implanted into the semiconductor body 10 in the first doped semiconductor region 103.

[0081] Figures 5A to 5D Different embodiments are illustrated schematically and exemplary, in which two masks 21, 22 with different openings are used for the first implantation and the second implantation, respectively. Therefore, the second mask 22 used for the second implantation can differ from the first mask 21 used for the first implantation. For example, as illustrated, the second mask 22 can have a smaller opening compared to the first mask 21. The second opening region of the second mask 22 can therefore be entirely located within the first opening region of the first mask 21. In these cases, two elements (such as boron and phosphorus) with similar diffusion constants can be used as dopants implanted in the first implantation step and the second implantation step, respectively, and they can diffuse through the same annealing(s) treatment(s). See also Figures 5A to 5D .

[0082] Therefore, in the embodiments, the dopant of the first conductivity type may have a first diffusion constant in the semiconductor body 10, and the dopant of the second conductivity type may have a second diffusion constant in the semiconductor body 10, the second diffusion constant differing from the first diffusion constant by a factor in the range of at most 0.5 to 2. In other words, the corresponding diffusion constants of the first conductivity type dopant and the second conductivity type dopant may be similar, as in the case of boron and phosphorus, for example.

[0083] In an embodiment, as mentioned above, the shielding layer 3 may be present at the location of the mask opening during at least one of the two implantations. For example, the shielding layer 3 may comprise or be composed of a thick oxide 3, wherein the thick oxide may have a thickness of, for example, at least 400 nm and / or at the location may be at least twice the thickness at different locations. Implantation through the thick oxide 3 can be performed using energy high enough to penetrate the oxide layer 3. Other portions of the semiconductor body not covered by the thick oxide 3 may be covered by a thin oxide 4 or may be completely uncovered by oxide.

[0084] Figures 6 to 10 Each schematically and exemplary illustration depicts a segment of a vertical cross-section of a power semiconductor device 1 (such as, for example, a diode, IGBT, or MOSFET) according to one or more embodiments. In each case, the illustrated segment includes an edge-terminating region 105 (including a first doped semiconductor region 103 in the form of a VLD structure), which may have been constructed using the methods described above for one or more embodiments. Therefore, the content already stated above with reference to variations of the method for producing the power semiconductor device 1 can be similarly applied. Figures 6 to 10 The embodiment of power semiconductor device 1, and vice versa.

[0085] For example, according to Figure 6 The power semiconductor device 1 may include the first doped semiconductor region 103 in the form of a VLD edge-termination region 103, as described above. It should be noted that the second doped semiconductor region 104 described above is not in… Figure 6 The VLD edge termination region 103 extends along the front surface 10-1 of the semiconductor body 10, which is covered by one or more insulating layers 13, 19.

[0086] exist Figure 6 On the upper left side, the illustrated cross-section of the power semiconductor device 1 shows the portion of the deep p-well 106 electrically connected to the front metallization 11. The front metallization 11 may form part of the first load terminal structure of the power semiconductor device 1.

[0087] As in Figure 6As shown on the right side, the channel stop region 107 can be additionally included in the semiconductor body 10. The channel stop region 107 may have a dopant of a second conductivity type and may be in contact with the channel stop electrode 121, as illustrated. Alternatively, as in... Figure 9 As shown in the diagram, the channel stop region 107 may have a dopant of the first conductivity type.

[0088] Regarding the wave profile C of VLD region 103, attention should be paid to Figure 6 The illustrations are not to scale. For example, in actual embodiments, the wave structure is compared to... Figure 6 The wave structure can be much more detailed than the one depicted only schematically in the text.

[0089] For example, compared to further away to the edge of the chip (i.e., further away) Figure 6 The location (to the right of the image) is near the active region of the power semiconductor device 1, compared to VLD region 103. Figure 6 The left side (in the middle) can have a higher average dopant dose.

[0090] Figure 7 A further variation of the VLD region 103, which can be produced using the method described above, is schematically and exemplaryly illustrated. In this case, a second doped semiconductor region 104 (which may be predominantly n-doped) is explicitly shown within the first doped semiconductor region 103. It should be noted that compensation implantation may be used only in a portion of the VLD region 103. For example, during the second implantation, the front surface 10-1 may be used, for example, in the inner portion of the VLD region 103, i.e., near the active region of the power semiconductor device 1 (…). Figure 7 The left side of the middle section was completely obscured.

[0091] Figure 8 Another cross-section of the power semiconductor device 1, including a VLD region 103, is schematically and exemplaryly illustrated. This VLD region 103 may have been generated using the methods described above (including a second doped semiconductor region 104, not shown). For example, a mask 22 for a (n-type) second implantation (e.g., phosphorus or arsenic) may also be used for an n-implantation 108 at the outer edge of the edge termination, which can be used to prevent excessively wide extension of the space charge region during the blocking state of the power semiconductor device 1.

[0092] Figure 9A further cross-section of a power semiconductor device 1 including a VLD region 103 is schematically and exemplaryly illustrated. The VLD region 103 may have been generated using the method described above. In this case, the segment depicted in the vertical cross-section also includes the back side of the power semiconductor device 1. For example, a back-side metallization 12 is disposed on the back-side surface 10-2 of the semiconductor body 10. The back-side metallization 12 may form at least a portion of the second load terminal structure of the power semiconductor device 1. Further, a back-side emitter region 100-1 may be disposed on the back side in contact with the back-side metallization 12. The back-side emitter region 100-1 may include a dopant at a higher concentration than the drift region 100. For example, the power semiconductor device 1 may be or may include a power diode, in which case the back-side emitter region 100-1 may be of a first conductivity type (e.g., n-type).

[0093] Figure 10 A further cross-section of the power semiconductor device 1, including the VLD region 103, is schematically and exemplaryly illustrated. The VLD region 103 may have been formed using the method described above. In this case, in addition to the edge region 15, the illustrated segment also includes the outer periphery of the active region 14 of the power semiconductor device 1 (towards...). Figure 10 (Left side in the diagram). The active region 14 may include an active cell field region, which includes a plurality of transistor cells 140. For example, as illustrated, the transistor cells 140 may have a trench gate configuration. Furthermore, an insulating structure 190 may be provided. The design of such transistor cells 140 is well known to those skilled in the art and therefore will not be described in further detail here.

[0094] For example, the power semiconductor device may have an IGBT configuration. In this case, the back-side emitter region 100-1 may be of a second conductivity type. Alternatively, for example, the power semiconductor device 1 may have a MOSFET configuration, in which case the back-side emitter region 100-1 may be of a first conductivity type.

[0095] about Figure 9 and Figure 10 In summary, it should be noted that the edge termination region 103 (e.g., in the form of a VLD region) can belong to a diode (see example...). Figure 9 ) or IGBT (see example) Figure 10 (or edge termination structure of other high-voltage devices.)

[0096] Figures 11A to 11EEach schematic and exemplary illustration depicts a segment of the implantation mask 21, 22 that may be used in the method described above according to one or more embodiments. The shaded areas represent portions of the front surface 10-1 covered by the mask 21, 22. Conversely, the white areas between the shaded areas remain empty to allow dopant to be implanted in the white areas.

[0097] As illustrated, a variety of shapes can be used for the structured mask 21, such as, for example, squares, boxes, or hexagons. These shapes can correspond to the areas being covered (see Figure 21). Figure 11A , Figure 11B , Figure 11D ) or corresponding to areas reserved for injection (see Figure 11C , Figure 11E ).

[0098] exist Figures 11A to 11C In the example, the open areas are 50% / 75% / 25% of the total area. Of course, these amounts can be changed by selecting different sized structures and / or different spacing.

[0099] exist Figures 11A to 11C In the middle, arrows L1 to L7 indicate the positions on it. Figures 13 to 16 The path of the corresponding dopant dose (i.e., the dopant concentration vertically integrated with respect to the depth 10-1 below the front surface) is shown in the figure, as will be explained further below.

[0100] It should be noted that, although Figures 11A to 11E The mask layout depicted is exemplarily labeled with reference numerals for the first mask 21, but the second mask 22 may also be presented in such a form.

[0101] Figures 12A to 12E Each schematically and exemplary illustration depicts a segment of two distinct implantation masks 21, 22 used in a method according to one or more embodiments. For example, the shaded region corresponds to the opening region of the second mask 22, i.e., the region in which a dopant of a first conductivity type (e.g., n-type) is implanted in the second implantation step. The unshaded region marks the outer contour of the opening region of the first mask 21, i.e., the unshaded region is the region in which a dopant of a second conductivity type (e.g., p-type) is implanted in the first mask implantation.

[0102] It should be noted that Figures 12A to 12E The non-shaded areas can also extend below the shaded areas. In other words, the opening area of ​​the first mask 21 can be larger than the opening area of ​​the second mask 22, where the latter can be completely disposed inside the former. In other words, in the embodiment, the first mask 21 can be open anywhere where the second mask 22 is open.

[0103] For example, if the second mask 22 used for the second injection is different from the first mask 21 used for the first injection, the second mask 22 may be related to the first mask 21 in a certain way, for example by presenting a shape that is similar in principle, but in which the opening is a certain amount smaller than the opening of the first mask 21.

[0104] Figures 13 to 16 Each schematically and exemplary illustration depicts several lateral contours of the injection dose according to one or more embodiments. In each case, along the... Figures 11A to 11C The different paths (arrows) L1 to L7 indicated in the text show the vertically integrated dopant dose in the first doped semiconductor region 103.

[0105] exist Figures 13 to 16 In each of them, curves C1, C2, and C3 belong to the category based on... Figure 11B The mask pattern (masked square; 75% opening area). Curve C1 corresponds to... Figure 11B The horizontal path L1 (completely inside the opening area of ​​the mask). Curve C2 corresponds to... Figure 11B The diagonal path L2 (partially inside the opening region and partially inside the shielding region). Curve C3 corresponds to... Figure 11B The horizontal path L3 is partially inside the opening area and partially inside the cover area.

[0106] Furthermore, in Figures 13 to 16 In each of these, curve C4 belongs to the category based on... Figure 11A The mask pattern (an injected elongated frame with 50% of the opening area) is such that curve C4 corresponds to the horizontal path L4 (partially inside the opening area and partially inside the masking area).

[0107] Curves C5, C6, and C7 belong to the category of curves in each case according to... Figure 11C The mask pattern (opening / injected square; 25% opening area). Curve C7 corresponds to... Figure 11C The horizontal path L7 (completely inside the cover area) corresponds to curve C6. Figure 11C The diagonal path L6 (partially inside the opening region and partially inside the shielding region). Curve C5 corresponds to... Figure 11C The horizontal path L5 is partially inside the opening area and partially inside the cover area.

[0108] Figure 13 This illustrates the situation without compensation injection n, i.e., without the second injection described above, for the case according to Figures 11A to 11CThe dose profiles C1 to C7 are shown for three different mask patterns. The dose is presented for a mask pattern with a structure size of 4 μm and an assumed diffusion length of 2.55 μm. The doses are normalized to values ​​corresponding to 100% of the opening area. It can be seen that the doses deviate very strongly from the intended average values ​​for their respective openings (corresponding to the 75%, 50%, and 25% opening mask areas mentioned above).

[0109] For comparison, Figure 14 Dosage profiles C1 to C7 are shown from corresponding mask patterns of the same structure size in which compensated n-implantation according to the invention has been performed, wherein the same diffusion length as above is assumed for p-dopers and a smaller diffusion length is assumed for n-dopers. As a result of compensated n-implantation, the deviation is significantly smaller. For these cases, the difference between the p-dosage and the n-dosage (i.e., the net dose obtained) is shown.

[0110] Figure 15 This is shown again in the case of no compensated n-injection (as in...) Figure 13 (As before) — but this time with a smaller structure size of 3 μm and assuming the same diffusion length as above — dose profiles C1 to C7 for three different mask patterns. It can be seen that the lateral profiles are much more uniform for the smaller structure size.

[0111] For comparison, Figure 16 This shows the case where n-injection compensation was performed (assuming the same as...). Figure 15 The same structural size and with Figure 14 (The same diffusion length in the middle). Since the profile is already more uniform without compensation (see...). Figure 15 Therefore, a lower dose is required for further homogenization. Furthermore, a strong improvement can be seen here after compensation.

[0112] Figures 17A to 17C Each schematic and exemplary illustration depicts the lateral profile of the vertical implantation dose in the first doped semiconductor region 103 according to one or more embodiments. In each case, the dotted curve D_2 is the acceptor dose profile, which may have already been implanted in the first mask implantation. The dashed curve D_3 is the donor dose profile, which may have already been implanted in the (compensated) second implantation step. The solid curve D_1 is the resulting net dose profile, i.e., the difference between dose profiles D_2 and D_3. The dashed curve D_4 is the reference dose profile (derived from conventional processing without compensation n-implantation). The dose profiles D1 to D4 exhibit certain fluctuations (or undulations) in each case and are depicted over several periods.

[0113] exist Figure 17AThe example shown in the diagram illustrates a reduction in very strong fluctuations. As can be clearly seen, the first dose profile D_1, representing the vertical integral net dopant concentration (i.e., net dose) of the dopant of the first conductivity type and the dopant of the second conductivity type in the first doped semiconductor region 103, exhibits a smaller degree of fluctuation along the horizontal directions X, Y (e.g., the horizontal direction of the vertical cross-section mentioned above) compared to the second dose profile D_2, representing the vertical integral dopant concentration of the (only) dopant of the second conductivity type in the first doped semiconductor region 103.

[0114] For example, in an embodiment, the relative fluctuation amplitude Ar_1 of the first dose profile D_1 is at most 80% (such as at most 70%) of the relative fluctuation amplitude Ar_2 of the second dose profile D_2, and the relative fluctuation amplitude Ar_i (i=1,2) is defined as:

[0115] Ar_i=(dmax_i-dmin_i) / (dmax_i+dmin_i)

[0116] Where i = 1, 2, dmax_i is the dose value at the local maximum of dose profile D_i, and dmin_i is the dose value at the nearest local minimum of dose profile D_i. For example, by means of the compensating injection according to the invention, the relative fluctuation amplitude can thus be reduced from a value of Ar_2 = 50% to a value of at most Ar_1 = 35%, such as to a value of Ar_1 = 30% or even to a value of Ar_1 = 10%.

[0117] Furthermore, in the embodiment, the average relative fluctuation amplitude of the first dose profile D_1<Ar_1> The total is the average relative fluctuation of the second dose profile D_2.<Ar_2> At most 80%, wherein the average is obtained on a segment of the first dose profile D_1 and a corresponding segment of the second dose profile D_2, respectively, the segment comprising at least two local maxima and a local minimum disposed therebetween in each case.

[0118] Furthermore, in the embodiment, the average relative fluctuation amplitude of the first dose profile D_1<Ar_1> The total is the average relative fluctuation of the second dose profile D_2.<Ar_2> At most 80%, wherein the average is obtained on a segment of the first dose profile D_1 and a corresponding segment of the second dose profile D_2, respectively, the segments comprising at least five local maxima and adjacent local minima in each case.

[0119] Further, in the embodiment, the total relative fluctuation amplitude Ar_2 of the second dose profile D_2 is at least 0.5, and the relative fluctuation amplitude is defined as the relative fluctuation amplitude Ar_2 of the second dose profile D_2, which is defined as:

[0120] Ar_2=(dmax_2-dmin_2) / (dmax_2+dmin_2),

[0121] Where dmax_2 is the dose value at the local maximum value of the second dose profile D_2, and dmin_2 is the dose value at the local minimum value adjacent to the second dose profile D_2.

[0122] Furthermore, in the embodiment, the average relative fluctuation amplitude of the second dose profile D_2<Ar_2> The total is at least 0.5, where the average is obtained on a segment of the second dose profile D_2, which includes at least five local maxima and adjacent local minima.

[0123] exist Figure 17A In the example, each of the reference dose profile D_4 and the second dose profile D_2 has a relative fluctuation of 50% (Ar_2=0.5), while the dose profile (curve D_1) according to the invention has a relative fluctuation of only 10% (Ar_1=0.1).

[0124] Figure 17B An example is shown where the volatility is reduced only moderately: here, the relative volatility of the resulting curve D_1 is A_1 = 0.3 or 30%.

[0125] Figures 17A to 17B Examples involve situations where the fluctuation occurs along a direction Y in which the average dose remains constant, for example parallel to the chip edge in a linear portion of the edge-terminating structure (e.g., perpendicular to). Figures 6 to 10 (Two-dimensional cut). In corresponding to, for example Figures 6 to 10 In the lateral direction X, the profile will decrease towards the chip edge, as in... Figure 17C That is illustrated schematically.

[0126] According to Figures 17A to 17C In each of the examples, the neighboring local maxima of the first dose profile D_1 may be spaced apart from each other by at least a first horizontal distance h1, the first horizontal distance h1 totaling at least 2 μm. Additionally or alternatively, in the embodiments, the neighboring local maxima of the second dose profile D_2 may be spaced apart from each other by at least a second horizontal distance h2, the second horizontal distance h2 totaling at least 2 μm.

[0127] Figures 18A to 18C Each schematic and exemplary illustration depicts a segment of a VLD-type implantation pattern that can be used in a method according to one or more embodiments. The illustrated closed regions are areas in which doped elements are implanted (i.e., for example, openings in the first mask 21 and / or the second mask 22). For example, in Figures 18A to 18CIn the middle, the chip edge is to the right (i.e., it is positioned further away in the x direction), and the active region of the power semiconductor device 1 is to the left. Figures 17A to 17B The doping dose can correspond to a path along the second horizontal direction Y, where the dopant profile can be determined according to, for example... Figure 18A The pattern shown in the image is generated.

[0128] exist Figure 18B and Figure 18C The figures illustrate two further examples, showing a combination of longitudinal strip patterns for medium effective dose ranges and patterns of rectangular openings and mask structures for low and high doses.

[0129] For example, according to Figures 18A to 18C The area ratio of the opening region of the first mask 21 above the first semiconductor region 103 to the masked region of the first mask 21 in a cross-section along the second horizontal direction Y can decrease in the direction from the active region of the power semiconductor device 1 to the lateral edge of the semiconductor body 10 (e.g., decreasing on average, i.e., not necessarily monotonically decreasing). For example, in some embodiments, such a decrease can occur along both the first horizontal direction X and the second horizontal direction Y.

[0130] The embodiments relating to power semiconductor devices and corresponding processing methods have been explained above.

[0131] For example, these semiconductor devices are based on silicon (Si). Therefore, the single-crystal semiconductor regions or layers—such as the semiconductor body 10 and its regions / bands (e.g., regions, etc.)—can be single-crystal Si regions or Si layers. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0132] However, it should be understood that the semiconductor body 10 and its various regions / bands can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, basic semiconductor materials (such as silicon (Si) or germanium (Ge)), group IV compound semiconductor materials (such as silicon carbide (SiC) or silicon germanium (SiGe)), binary, ternary, or quaternary III-V semiconductor materials (such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP)), and binary or ternary II-VI semiconductor materials (such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe)). The aforementioned semiconductor materials are also referred to as "homogeneous junction semiconductor materials." Heterojunction semiconductor materials are formed when two different semiconductor materials are combined. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), and silicon-silicon carbide (Si). x C 1-x Silicon-SiGe heterojunction semiconductor materials are used. For power semiconductor switching applications, Si, SiC, GaAs, and GaN materials are currently the main materials used.

[0133] For ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to cover not only the different orientations depicted in the figures but also the different orientations of the corresponding devices. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., and are not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0134] As used herein, the terms “having,” “containing,” “including,” “comprising,” “including,” and “present,” etc., are open-ended terms that indicate the presence of the declared element or feature but do not exclude additional elements or features.

[0135] While taking into account the above variations and scope of application, it should be understood that the invention is not limited to the foregoing description or the accompanying drawings. Rather, the invention is limited only by the following claims and their legal equivalents.

Claims

1. A power semiconductor device (1), comprising: - Semiconductor body (10) having a front surface (10-1) and including a drift region (100) of a dopant having a first conductivity type; - An edge termination region (105), which is included in the semiconductor body (10) and includes: ○ Part of the drift zone (100); ○ A first semiconductor region (103) extends along the front surface (10-1). The first semiconductor region (103) includes a dopant of a first conductivity type and a dopant of a second conductivity type that is complementary to the first conductivity type. The integrated vertical dopant concentration of the second conductivity type dopant in the first semiconductor region (103) is higher than the integrated vertical dopant concentration of the first conductivity type dopant. The first semiconductor region (103) and the drift region (100) form a continuous pn junction (J). The first dose profile (D_1), representing the vertical integral net dopant concentration of the first conductivity type dopant and the second conductivity type dopant in the first semiconductor region (103), exhibits a smaller degree of fluctuation along the horizontal direction (X, Y) compared to the second dose profile (D_2), representing the vertical integral dopant concentration of the second conductivity type dopant in the first semiconductor region (103).

2. The power semiconductor device (1) according to claim 1, wherein, The relative fluctuation amplitudes Ar_1 of the first dose profile D_1 total at most 80% of the relative fluctuation amplitudes Ar_2 of the second dose profile D_2, and the relative fluctuation amplitudes Ar_i (i = 1, 2) are limited as follows: Ar_i=(dmax_i-dmin_i) / (dmax_i+dmin_i), Where i = 1, 2, dmax_i is the dose value at the local maximum of dose profile D_i, and dmin_i is the dose value at the nearest local minimum of dose profile D_i.

3. The power semiconductor device (1) according to claim 2, wherein the average relative fluctuation of the first dose profile D_1<Ar_1> The total is the average relative fluctuation of the second dose profile D_2.<Ar_2> At most 80%, wherein the average is obtained on a segment of the first dose profile D_1 and a corresponding segment of the second dose profile D_2, respectively, the segment comprising at least two local maxima and a local minimum disposed between the at least two local maxima.

4. The power semiconductor device (1) according to claim 2 or 3, wherein the average relative fluctuation of the first dose profile D_1<Ar_1> The total is the average relative fluctuation of the second dose profile D_2.<Ar_2> At most 80%, wherein the average is obtained on a segment of the first dose profile D_1 and a corresponding segment of the second dose profile D_2, respectively, the segments comprising at least five local maxima and adjacent local minima in each case.

5. The power semiconductor device (1) according to any one of claims 1-3, wherein the total relative fluctuation amplitude Ar_2 of the second dose profile D_2 is at least 0.5, and the relative fluctuation amplitude is defined as the relative fluctuation amplitude Ar_2 of the second dose profile D_2, which is defined as: Ar_2=(dmax_2-dmin_2) / (dmax_2+dmin_2), Where dmax_2 is the dose value at the local maximum value of the second dose profile D_2, and dmin_2 is the dose value at the local minimum value adjacent to the second dose profile D_2.

6. The power semiconductor device (1) according to claim 5, wherein the average relative fluctuation of the second dose profile D_2<Ar_2> The total is at least 0.5, where the average is obtained on a segment of the second dose profile D_2, which includes at least five local maxima and adjacent local minima.

7. The power semiconductor device (1) according to any one of claims 1-3, wherein the edge termination region (105) forms at least a portion of the lateral doping variation edge termination region.

8. The power semiconductor device (1) according to any one of claims 1-3, wherein, - The neighboring local maxima of the first dose profile (D_1) are spaced apart from each other by at least a first horizontal distance (h1), the first horizontal distances (h1) totaling at least 2 μm; and / or - The adjacent local maxima of the second dose profile (D_2) are spaced apart from each other by at least a second horizontal distance (h2), the total second horizontal distance (h2) being at least 2 μm.

9. A method for processing a power semiconductor device (1), comprising: - Provide a semiconductor body (10) having a front surface (10-1) and including a drift region (100) of a dopant having a first conductivity type; - An edge termination region (105) is formed within the semiconductor body (10), wherein forming the edge termination region (105) includes: ○ Forming a first doped semiconductor region (103) extending along the front surface (10-1) and forming a continuous pn junction (J) with the drift region (100), wherein forming the first doped semiconductor region (103) includes the following steps: • A dopant of the second conductivity type is implanted through the front surface (10-1) by means of a first mask implantation, wherein the first mask (21) is used for the first mask implantation, and the first mask defines a first opening region and a first masking region. • A dopant of the first conductivity type is implanted through the front surface (10-1) by means of a second mask implantation, wherein the second mask (21, 22) is used for the second mask implantation, and the second mask defines a second opening region and a second masking region. The first mask (21) and the second mask (22) are arranged on the semiconductor body (10) in such a way that the opening region of the second mask (22) placed on the first doped semiconductor region (103) during the second implantation step horizontally overlaps with the opening region of the first mask (21) placed on the first doped semiconductor region (103) during the first mask implantation step. The first mask (21) and the second mask (22) are arranged on the semiconductor body (10) in such a way that the closed region of the second mask (22) placed on the first doped semiconductor region (103) during the second implantation step horizontally overlaps with the closed region of the first mask (21) placed on the first doped semiconductor region (103) during the first mask implantation step, wherein the first doped semiconductor region (103) is formed such that the first dose profile (D_1) representing the vertical integral net dopant concentration of the first conductivity type dopant and the second conductivity type dopant in the first doped semiconductor region (103) exhibits a smaller degree of undulation along the horizontal direction (X, Y) compared with the second dose profile (D_2) representing the vertical integral dopant concentration of the second conductivity type dopant in the first doped semiconductor region (103).

10. The method according to claim 9, wherein, In a cross section along the horizontal direction (X, Y), the area ratio of the opening region of the first mask (21) above the first doped semiconductor region (103) to the area of ​​the masked region of the first mask (21) decreases in the direction from the active region of the power semiconductor device (1) to the lateral edge of the semiconductor body (10).

11. The method according to claim 10, wherein, Forming the first doped semiconductor region (103) includes performing at least one diffusion step to diffuse a dopant of a second conductivity type.

12. The method according to claim 11, wherein, The at least one diffusion step is performed before injecting a dopant of the first conductivity type.

13. The method according to any one of claims 9 to 11, wherein, Forming the first doped semiconductor region (103) and the second doped semiconductor region (104) includes diffusing the implanted dopant of the first conductivity type and the implanted dopant of the second conductivity type in the same diffusion step.

14. The method according to any one of claims 9 to 12, wherein, The same mask (21) was used for the first mask injection and the second mask injection.

15. The method according to any one of claims 9 to 12, wherein a dopant of a first conductivity type has a first diffusion constant in the semiconductor body (10), and wherein a dopant of a second conductivity type has a second diffusion constant in the semiconductor body (10), the second diffusion constant differing from the first diffusion constant by a factor in the range of 0.5 to 2.

16. The method according to any one of claims 9 to 12, wherein a dopant of a first conductivity type has a first diffusion constant in the semiconductor body (10), and wherein a dopant of a second conductivity type has a second diffusion constant in the semiconductor body (10), the second diffusion constant being at least 3 times greater than the first diffusion constant.

17. The method according to any one of claims 9 to 12, wherein, Implanting a dopant of a first conductivity type and / or a dopant of a second conductivity type through a shielding layer (3) disposed above the front surface (10-1), wherein the method comprises: - By means of a third implantation through the front surface (10-1) of a dopant of the first conductivity type or a dopant of the second conductivity type, a third doped semiconductor region (106) extending along the front surface (10-1) is formed in the region where the front surface (10-1) is not covered by the shielding layer (3).

18. The method according to claim 17, wherein, The same mask (21) was used for the first mask injection and the third mask injection.

19. The method according to claim 18, wherein, The third mask injection is performed at a lower energy than the first mask injection, so that the second type of dopant does not penetrate the shielding layer during the third mask injection (3).

20. A method for processing a power semiconductor device (1), comprising: - Provide a semiconductor body (10) having a front surface (10-1) and including a drift region (100) of a dopant having a first conductivity type; - An edge termination region (105) is formed within the semiconductor body (10), wherein forming the edge termination region (105) includes: - A first doped semiconductor region (103) is formed, extending along the front surface (10-1) and forming a continuous pn junction (J) with the drift region (100). - Further doped semiconductor regions (106) are formed in the semiconductor body (10). The formation of the first doped semiconductor region (103) and the further doped semiconductor region (106) includes the following steps: - A structured shielding layer (3) is formed on the front side (10-1), the structured shielding layer (3) covering the first doped semiconductor region (103) to be formed, wherein the structured shielding layer (3) is not present on the further doped semiconductor region (106) to be formed. - In the first injection step, the dopant is injected through the structured shielding layer (3) and into the semiconductor body (10) by means of the first mask (21) under the first injection energy; - In a further implantation step, the dopant is implanted into the structured shielding layer (3) and into the semiconductor body (10) at a second implantation energy lower than the first implantation energy by means of a first mask (21); The first mask (21) is open over the further doped semiconductor region (106) to be formed, and the first mask (21) defines a first opening region and a first masking region, wherein, in a cross-section along the horizontal direction (X, Y), the area ratio of the first opening region over the first doped semiconductor region (103) to the first masking region decreases in the direction from the active region of the power semiconductor device (1) to the lateral edge of the semiconductor body (10), wherein the first doped semiconductor region (103) is formed such that a first dose profile (D_1) representing the vertical integral net dopant concentration of a first conductivity type dopant and a second conductivity type dopant in the first doped semiconductor region (103) exhibits a smaller degree of undulation along the horizontal direction (X, Y) compared to a second dose profile (D_2) representing the vertical integral dopant concentration of a second conductivity type dopant in the first doped semiconductor region (103).

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