IGBT drive protection circuit, drive circuit, driver and test device

Abstract

The present application discloses an IGBT driving protection circuit, a driving circuit, a driver and a testing device. A differential circuit outputs a first pulse signal when an input control signal jumps from a high level to a low level. An integrating circuit integrates the first pulse signal and outputs a first integrated signal of a first preset duration. A first control circuit generates a first control signal of a second preset duration according to the first integrated signal of the first preset duration and outputs the signal to a gate of the IGBT circuit, so that the gate of the IGBT circuit is reversely biased for the second preset duration, so that the IGBT circuit is in a cut-off state. The gate of the IGBT circuit stops being reversely biased after the second preset duration, thereby avoiding that the emitter of the IGBT circuit forms a current path with the gate of the IGBT circuit through the power supply ground when the IGBT circuit breaks down, and eliminating the loop current formed between the IGBT circuit and the internal power supply when the IGBT circuit is short-circuited.

Description

Technical Field

[0001] The present application belongs to the field of IGBT drive technology, and in particular, relates to an IGBT drive protection circuit, a drive circuit, a driver, and a test device. Background Art

[0002] Traditional IGBT (Insulated Gate Bipolar Transistor) drivers have the following defects: when the IGBT module is broken down, the gate and emitter of the IGBT module are short-circuited, and a closed-loop static current is formed between the IGBT module and the IGBT driver when the IGBT module should be in the off state: power ground → IGBT module → driver tube of the driver → power ground. This closed-loop static current will cause the devices in the current loop and the internal power supply to heat up, thereby causing damage to the devices in the current loop and the internal power supply. Summary of the invention

[0003] The purpose of the present application is to provide an IGBT drive protection circuit, aiming to solve the problem that when a traditional IGBT module is broken down, a closed-loop static circulating current is formed between the IGBT driver, the IGBT module and the internal power supply.

[0004] A first aspect of an embodiment of the present application provides an IGBT drive protection circuit, comprising:

[0005] A differential circuit is configured to receive an input control signal and generate a first pulse signal when the input control signal changes from a high level to a low level;

[0006] an integration circuit connected to the differentiation circuit and configured to integrate the first pulse signal to output a first integration signal of a first preset duration; and

[0007] The first control circuit is connected to the integration circuit and is configured to generate a first control signal of a second preset duration according to the first integration signal of the first preset duration to reversely bias the gate of the IGBT circuit for a second preset duration.

[0008] In one embodiment, the differential circuit includes a first resistor, a second resistor and a first capacitor;

[0009] The first end of the first resistor is the input control signal input end of the differential circuit, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor and the first end of the second resistor are connected together to form the first pulse signal output end of the differential circuit, and the second end of the second resistor is connected to the power ground.

[0010] In one embodiment, the integration circuit includes a first diode, a second capacitor and a third resistor;

[0011] The anode of the first diode is the first pulse signal input terminal of the integration circuit, the cathode of the first diode, the first end of the second capacitor and the first end of the third resistor are connected together to form the first integration signal output terminal of the first preset time length of the integration circuit, and the second end of the second capacitor and the second end of the third resistor are both connected to the power ground.

[0012] In one embodiment, the first control circuit includes a first NAND gate, a first input terminal of the first NAND gate constitutes a first integral signal input terminal of a first preset time length of the first control circuit, and an output terminal of the first NAND gate constitutes a first control signal output terminal of a second preset time length of the first control circuit.

[0013] A second aspect of the embodiments of the present application provides an IGBT driving circuit, comprising a driving circuit and an IGBT driving protection circuit as described in any one of the first aspects;

[0014] The differential circuit is further configured to generate a second pulse signal when the input control signal changes from a low level to a high level;

[0015] The integration circuit is further configured to integrate the second pulse signal to output a second integration signal of a third preset time length;

[0016] The driving circuit includes a first inverting circuit and a second control circuit;

[0017] a first inverting circuit, configured to generate a high-level inverting signal when the input control signal jumps from a high level to a low level, and to generate a low-level inverting signal when the input control signal jumps from a low level to a high level;

[0018] The first control circuit is connected to the first inverting circuit, and is specifically configured to generate a first control signal of a second preset duration according to the high-level inverting signal and the first integrated signal of the first preset duration, and to generate a second control signal of a fourth preset duration according to the input control signal and the second integrated signal of the third preset duration;

[0019] The second control circuit is connected to the first control circuit and is configured to output a reverse bias voltage of the second preset time length according to the first control signal of the second preset time length to reversely bias the gate of the IGBT circuit for the second preset time length, and to output a positive bias voltage of the fourth preset time length according to the second control signal of the fourth preset time length to forward bias the gate of the IGBT circuit for the fourth preset time length.

[0020] In one embodiment, the second control circuit includes:

[0021] The isolation component is connected to the first control circuit and is configured to isolate the first control signal of the second preset duration to output a third control signal of the second preset duration, and to isolate the second control signal of the fourth preset duration to output a fourth control signal of the fourth preset duration; and

[0022] The driving power component is connected to the isolation component and is configured to output a reverse bias voltage of the second preset time length according to a second control signal of the second preset time length to reversely bias the gate of the IGBT circuit for the second preset time length, and to output a positive bias voltage of the fourth preset time length according to a fourth control signal of the fourth preset time length to forward bias the gate of the IGBT circuit for the fourth preset time length.

[0023] In one embodiment, the isolation component includes a first optical coupler, a second optical coupler, a fourth resistor and a fifth resistor;

[0024] The first end of the fourth resistor and the first end of the fifth resistor constitute the first control signal input end of the second preset time length of the isolation component and the second control signal of the fourth preset time length of the isolation component, the second end of the fourth resistor is connected to the positive electrode of the first optocoupler, the negative electrode of the first optocoupler is connected to the power ground, the second end of the fifth resistor is connected to the negative electrode of the second optocoupler, the positive electrode of the second optocoupler is connected to the positive electrode of the internal power supply, the output end of the first optocoupler and the output end of the second optocoupler constitute the third control signal output end of the second preset time length of the isolation component and the fourth control signal output end of the fourth preset time length of the isolation component.

[0025] In one embodiment, the driving power component includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first field effect transistor and a second field effect transistor;

[0026] The first end of the sixth resistor and the first end of the seventh resistor constitute the third control signal input end of the second preset time length of the driving power component and the fourth control signal input end of the fourth preset time length of the driving power component. The second end of the sixth resistor is connected to the gate of the first field effect transistor, and the source of the first field effect transistor is connected to the positive electrode of the internal power supply. The second end of the seventh resistor is connected to the gate of the second field effect transistor, and the source of the second field effect transistor and the first end of the eighth resistor are both connected to the power ground. The drain of the first field effect transistor, the drain of the second field effect transistor, the second end of the eighth resistor and the first end of the ninth resistor are connected in common. The second end of the ninth resistor is the inverting bias voltage output end of the second preset time length of the driving power component and the positive bias voltage output end of the fourth preset time length of the driving power component.

[0027] A third aspect of the embodiments of the present application provides a driver, comprising the IGBT driving circuit as described in any one of the second aspects.

[0028] A fourth aspect of the embodiments of the present application provides a testing device, including an optical fiber receiving circuit, a second inverter circuit, and an IGBT driving circuit as described in any one of the second aspects;

[0029] The optical fiber receiving circuit is configured to receive an optical signal and output an electrical signal according to the optical signal;

[0030] The second inverter circuit is connected to the optical fiber receiving circuit and the IGBT driving circuit respectively, and is configured to output the input control signal according to the electrical signal.

[0031] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: a first pulse signal is outputted through a differential circuit when an input control signal jumps from a high level to a low level; an integration circuit integrates the first pulse signal and outputs a first integration signal of a first preset duration; a first control circuit generates a first control signal of a second preset duration according to the first integration signal of the first preset duration and outputs it to the gate of the IGBT circuit, so that the gate of the IGBT circuit is reversely biased for the second preset duration, so that the IGBT circuit is in a cut-off state; the gate of the IGBT circuit stops being reversely biased after the second preset duration, thereby avoiding the emitter of the IGBT circuit from forming a current path with the gate of the IGBT circuit through the power supply ground when the IGBT circuit breaks down, and eliminating the loop current formed between the IGBT circuit and the internal power supply when the IGBT circuit is short-circuited. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 An example principle block diagram of an IGBT drive protection circuit provided in an embodiment of the present application;

[0033] Figure 2 An exemplary circuit schematic diagram of an IGBT drive protection circuit provided in an embodiment of the present application;

[0034] Figure 3 A first exemplary principle block diagram of a driving circuit provided in an embodiment of the present application;

[0035] Figure 4 A second exemplary principle block diagram of a driving circuit provided in an embodiment of the present application;

[0036] Figure 5 An exemplary circuit schematic diagram of a driving circuit provided in an embodiment of the present application;

[0037] Figure 6 An example principle block diagram of a test device provided in an embodiment of the present application;

[0038] Figure 7 An example circuit schematic diagram of a test device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] Figure 1 The first principle block diagram of the IGBT driving protection circuit provided by the embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0041] A driving protection circuit for an IGBT includes a differential circuit 100 , an integral circuit 200 and a first control circuit 300 .

[0042] The differentiating circuit 100 is configured to receive an input control signal and generate a first pulse signal when the input control signal changes from a high level to a low level.

[0043] The integration circuit 200 is connected to the differentiation circuit 100 and is configured to integrate the first pulse signal to output a first integrated signal of a first preset duration.

[0044] The first control circuit 300 is connected to the integration circuit 200 and is configured to generate a first control signal of a second preset duration according to a first integration signal of a first preset duration to reversely bias the gate of the IGBT circuit 500 for a second preset duration.

[0045] In this embodiment, the differential circuit 100 outputs a first pulse signal when receiving an input control signal and when the input control signal jumps from a high level to a low level, the integration circuit 200 integrates the first pulse signal and outputs a first integration signal of a first preset time length, the first control circuit 300 generates a first control signal of a second preset time length according to the first integration signal of the first preset time length, and the gate of the IGBT circuit 500 is reversely biased at the second preset time length (such as the gate of the IGBT circuit 500 is turned on to the power ground at the second preset time length), so that the IGBT circuit 500 is in a cut-off state. state, the gate of the IGBT circuit 500 stops being reverse biased after the second preset time period. When the IGBT circuit 500 breaks down, the gate and emitter of the IGBT circuit 500 are short-circuited. Because the first control circuit 300 controls the IGBT circuit 500 to stop being reverse biased (disconnecting from the power ground) after the second preset time period, the emitter of the IGBT circuit 500 will not form a path with the gate of the IGBT circuit 500 through the power ground. Therefore, the loop current formed between the IGBT circuit 500 and the internal power supply when the IGBT circuit 500 is short-circuited is eliminated.

[0046] The power ground in the whole text refers to the negative pole of the internal power supply, and the input control signal carries information for controlling the on or off of the IGBT.

[0047] See also Figure 2 In one embodiment, the differential circuit 100 includes a first resistor R1, a second resistor R2 and a first capacitor C1.

[0048] The first end of the first resistor R1 is the input control signal input end of the differential circuit 100, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 and the first end of the second resistor R2 are connected together to form the first pulse signal output end of the differential circuit 100, and the second end of the second resistor R2 is connected to the power ground.

[0049] See also Figure 2 In one embodiment, the integration circuit 200 includes a first diode D1, a second capacitor C2 and a third resistor R3.

[0050] The anode of the first diode D1 is the first pulse signal input terminal of the integration circuit 200, the cathode of the first diode D1, the first end of the second capacitor C2 and the first end of the third resistor R3 are connected together to form the first integration signal output terminal of the first preset time length of the integration circuit 200, and the second end of the second capacitor C2 and the second end of the third resistor R3 are both connected to the power ground.

[0051] See also Figure 2In one embodiment, the first control circuit 300 includes a first NAND gate U4, a first input end of the first NAND gate U4 constitutes a first integral signal input end of a first preset time length of the first control circuit 300, and an output end of the first NAND gate U4 constitutes a first control signal output end of a second preset time length of the first control circuit 300.

[0052] The following is combined with the working principle Figure 2 The driving protection circuit of the IGBT shown in the figure is illustrated. When the input control signal received by the first end of the first resistor R1 changes from a high level to a low level, the electric energy stored in the first capacitor C1 is quickly released through the second resistor R2 to form a first pulse signal. The first pulse signal is output to the second capacitor C2 through the first diode D1. In the rising edge stage of the first pulse signal, the first pulse signal charges the second capacitor C2. In the falling edge stage of the first pulse signal, the second capacitor C2 is discharged for a first preset time (equivalent to outputting a first integral signal of a first preset time, and the voltage analog value of the first integral signal decreases with time). The first input end of the first NAND gate U4 inputs the first integral signal of a first preset time, and the voltage analog value of the first integral signal decreases with time within the second preset time. The amount will be greater than the low level threshold of the first NAND gate U4, so the first NAND gate U4 outputs a low level within the second preset time to control the gate of the IGBT circuit 500 to be connected to the power ground. After the second preset time, the voltage analog value of the first integrated signal is less than the low level threshold of the first NAND gate U4, so the first NAND gate U4 outputs a high level to control the gate of the IGBT circuit 500 to stop being connected to the power ground. Therefore, the damage to the internal power supply and the IGBT circuit 500 caused by the breakdown short circuit and the formation of a loop current with the internal power supply can be reduced. In addition, because the differential circuit 100 is at the nanosecond level and the integration circuit 200 is at the microsecond level, the second preset time can be shortened, thereby quickly stopping the reverse bias of the gate of the IGBT circuit 500.

[0053] See also Figure 3 An embodiment of the present application also provides an IGBT driving circuit, comprising a driving circuit and an IGBT driving protection circuit of any of the above embodiments.

[0054] The differential circuit 100 is further configured to generate a second pulse signal when the input control signal changes from a low level to a high level.

[0055] The integration circuit 200 is further configured to integrate the second pulse signal to output a second integrated signal of a third preset duration.

[0056] The driving circuit includes a first inverter circuit 420 and a second control circuit 410 .

[0057] The first inverting circuit 420 is configured to generate a high-level inverting signal when the input control signal changes from a high level to a low level, and to generate a low-level inverting signal when the input control signal changes from a low level to a high level.

[0058] The first control circuit 300 is connected to the first inverting circuit 420, and is specifically configured to generate a first control signal of a second preset time length based on a high-level inverting signal and a first integrated signal of a first preset time length, and to generate a second control signal of a fourth preset time length based on an input control signal and a second integrated signal of a third preset time length.

[0059] The second control circuit 410 is connected to the first control circuit 300, and is configured to output a reverse bias voltage of a second preset time length according to a first control signal of a second preset time length to reversely bias the gate of the IGBT circuit 500 for the second preset time length, and to output a positive bias voltage of a fourth preset time length according to a second control signal of a fourth preset time length to forward bias the gate of the IGBT circuit 500 for the fourth preset time length.

[0060] In this embodiment, the differential circuit 100 generates a first pulse signal when the input control signal jumps from a high level to a low level so that the integration circuit 200 generates and outputs a first integration signal of a first preset time length. At this time, the input control signal is a low level, and the input control signal is generated by the first inverting circuit 420 to generate a high level and output to the first control circuit 300. The first control circuit 300 outputs the first control signal within the second preset time length according to the high level generated by the first inverting circuit 420 and the first integration signal of the first preset time length. The second control circuit 410 outputs an inverted bias voltage to the IGBT when the first control signal is input. The gate of the circuit 500 is used to turn off the IGBT circuit 500; the differential circuit 100 generates a second pulse signal when the input control signal jumps from a low level to a high level to enable the integration circuit 200 to generate and output a second integration signal of a third preset time length. At this time, the input control signal is at a high level, and the first control circuit 300 outputs a second control signal to the second control circuit 410 within a fourth preset time length according to the input control signal and the second integration signal of the third preset time length. The second control circuit 410 outputs a positive phase bias voltage to the gate of the IGBT circuit 500 at the second control signal to turn on the IGBT circuit 500.

[0061] See also Figure 4 In one embodiment, the second control circuit 410 includes an isolation component 411 and a driving power component 412 .

[0062] The isolation component 411 is connected to the first control circuit 300 and is configured to isolate the first control signal of the second preset duration to output a third control signal of the second preset duration, and to isolate the second control signal of the fourth preset duration to output a fourth control signal of the fourth preset duration.

[0063] The driving power component 412 is connected to the isolation component 411, and is configured to output a reverse bias voltage of a second preset time length according to a second control signal of a second preset time length to reversely bias the gate of the IGBT circuit 500 for the second preset time length, and to output a positive bias voltage of a fourth preset time length according to a fourth control signal of a fourth preset time length to forward bias the gate of the IGBT circuit 500 for the fourth preset time length.

[0064] In this embodiment, the control signal is isolated by the isolation component 411, thereby improving the safety and reliability of the circuit.

[0065] See also Figure 5 In one embodiment, the isolation component 411 includes a first optical coupler U5, a second optical coupler U6, a fourth resistor R4 and a fifth resistor R5;

[0066] The first end of the fourth resistor R4 and the first end of the fifth resistor R5 constitute the first control signal input end of the second preset time length of the isolation component 411 and the second control signal input end of the fourth preset time length of the isolation component 411, the second end of the fourth resistor R4 is connected to the positive electrode of the first optocoupler U5, the negative electrode of the first optocoupler U5 is connected to the power ground, the second end of the fifth resistor R5 is connected to the negative electrode of the second optocoupler U6, the positive electrode of the second optocoupler U6 is connected to the positive electrode of the internal power supply, the output end of the first optocoupler U5 and the output end of the second optocoupler U6 constitute the third control signal output end of the second preset time length of the isolation component 411 and the fourth control signal output end of the fourth preset time length of the isolation component 411.

[0067] Among them, the high level output from the output end of the first optocoupler U5 and the high level output from the output end of the second optocoupler U6 constitute the third control signal, and the low level output from the output end of the first optocoupler U5 and the low level output from the output end of the second optocoupler U6 constitute the fourth control signal.

[0068] See also Figure 5 In one embodiment, the driving power component 412 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first field effect transistor Q1, and a second field effect transistor Q2;

[0069] The first end of the sixth resistor R6 and the first end of the seventh resistor R7 constitute the third control signal input end of the second preset time length of the driving power component 412 and the fourth control signal input end of the fourth preset time length of the driving power component 412, the second end of the sixth resistor R6 is connected to the gate of the first field effect transistor Q1, the source of the first field effect transistor Q1 is connected to the positive electrode of the internal power supply, the second end of the seventh resistor R7 is connected to the gate of the second field effect transistor Q2, the source of the second field effect transistor Q2 and the first end of the eighth resistor R8 are both connected to the power ground, the drain of the first field effect transistor Q1, the drain of the second field effect transistor Q2, the second end of the eighth resistor R8 and the first end of the ninth resistor R9 are connected in common, and the second end of the ninth resistor R9 is the inverting bias voltage output end of the second preset time length of the driving power component 412 and the positive bias voltage output end of the fourth preset time length of the driving power component 412.

[0070] See also Figure 5 The first inverting circuit 420 includes a first inverter U2, and the first inverter U2 is configured to generate a high-level inverted signal when the input control signal jumps from a high level to a low level.

[0071] The following is combined with the working principle Figure 5The IGBT driving circuit shown in the figure is illustrated. When the input control signal received by the first end of the first resistor R1 changes from a high level to a low level, the first capacitor C1 outputs a first pulse signal (negative pulse) to the second capacitor C2. The first pulse signal charges the second capacitor C2 at its rising edge stage. The second capacitor C2 discharges at the falling edge stage of the first pulse signal and outputs a first integrated signal (high level) of a first preset time length. Within the second preset time length, the first integrated signal is greater than the high level threshold of the first NAND gate U4 and the high level threshold of the second NAND gate U3. At the same time, the low level of the input control signal is converted into a high level through the first inverter U2 and input into the first NAND gate U4. The first NAND gate U3 The two input terminals of the gate U4 are both input with a high level within the second preset time length, so the first NAND gate U4 outputs a low level to the cathode of the second optocoupler U6, and the output terminal of the second optocoupler U6 outputs a high level to the gate of the second field effect tube Q2 to turn on the second field effect tube Q2, and the gate of the IGBT circuit 500 is turned on to the power ground through the second field effect tube Q2. In addition, because the input control signal connected to one of the input terminals of the second NAND gate U3 is at a low level, the second NAND gate U3 outputs a high level to the anode of the first optocoupler U5, and the output terminal of the first optocoupler U5 outputs a high level to the gate of the first field effect tube Q1 to turn off the first field effect tube Q1, and the gate of the IGBT circuit 500 stops passing through the first field effect tube Q2. A field effect tube Q1 is connected to the positive pole of the internal power supply, so the IGBT circuit 500 is in the cut-off state; when the input control signal received by the first end of the first resistor R1 jumps from a low level to a high level, the first capacitor C1 outputs a second pulse signal (positive pulse) to the second capacitor C2, and the second capacitor C2 discharges and outputs a second integral signal (low level) of a third preset time length, wherein within the fourth preset time length, the second integral signal is less than the low level threshold of the first NAND gate U4 and the low level threshold of the second NAND gate U3, and at the same time, the high level of the input control signal is converted into a low level through the first inverter U2 and input to the first NAND gate U4, and at least one of the two input terminals of the first NAND gate U4 inputs a low level, so This first NAND gate U4 outputs a high level to the negative electrode of the second optocoupler U6, and the output end of the second optocoupler U6 outputs a low level to the gate of the second field effect tube Q2 to cut off the second field effect tube Q2, and the gate of the IGBT circuit 500 stops being connected to the power ground through the second field effect tube Q2. Both input ends of the second NAND gate U3 input a high level, so the second NAND gate U3 outputs a low level to the positive electrode of the first optocoupler U5, and the output end of the first optocoupler U5 outputs a low level to the gate of the first field effect tube Q1 to turn on the first field effect tube Q1. The gate of the IGBT circuit 500 is connected to the positive electrode of the internal power supply through the first field effect tube Q1, so the IGBT circuit 500 is in the on state.

[0072] The embodiment of the present application also provides a driver, the driver is used to drive the IGBT circuit 500, and the driver includes an IGBT driving circuit as in any of the above embodiments. Because the driver of the present application includes the IGBT driving circuit of any of the above embodiments, it at least has the beneficial effects corresponding to the IGBT driving circuit of any of the above embodiments.

[0073] The embodiment of the present application further provides a testing device, including an optical fiber receiving circuit 600, a second inverter circuit 700, and an IGBT driving circuit as described in any of the above embodiments.

[0074] The optical fiber receiving circuit 600 is configured to receive an optical signal and output an electrical signal according to the optical signal.

[0075] The second inverter circuit 700 is connected to the optical fiber receiving circuit 600 and the IGBT driving circuit respectively, and is configured to output an input control signal according to the electrical signal.

[0076] Among them, the testing device is IGBT dynamic testing equipment.

[0077] Because the testing device of the present application includes the IGBT driving circuit of any one of the above embodiments, it at least has the beneficial effects corresponding to the IGBT driving circuit of any one of the above embodiments.

[0078] In one embodiment, the second inverter circuit 700 includes a second inverter U1 , and the second inverter U1 is configured to invert the electrical signal and output the input control signal.

[0079] In one embodiment, the optical fiber receiving circuit 600 includes an optical fiber receiving head UBF1 and a third capacitor C3, the voltage terminal VCC of the optical fiber receiving head UBF1 and the first end of the third capacitor C3 are connected in common and connected to the positive electrode of the internal power supply, the ground terminal GND of the optical fiber receiving head UBF1 and the second end of the third capacitor C3 are both connected to the power ground, and the first output terminal RL of the optical fiber receiving head UBF1 and the second output terminal VO of the optical fiber receiving head UBF1 are connected in common to form the input control signal output terminal of the optical fiber receiving circuit 600.

[0080] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A driving protection circuit for an IGBT, characterized in that: include: A differential circuit is configured to receive an input control signal and generate a first pulse signal when the input control signal changes from a high level to a low level; an integration circuit, connected to the differentiation circuit, and configured to integrate the first pulse signal to output a first integration signal of a first preset duration; and a first control circuit connected to the integration circuit and configured to generate a first control signal of a second preset duration according to the first integration signal of the first preset duration to reversely bias the gate of the IGBT circuit for a second preset duration; The first control circuit includes a first NAND gate, a first input end of the first NAND gate constitutes a first integral signal input end of a first preset time length of the first control circuit, and an output end of the first NAND gate constitutes a first control signal output end of a second preset time length of the first control circuit.

2. The IGBT driving protection circuit according to claim 1, characterized in that: The differential circuit includes a first resistor, a second resistor and a first capacitor; The first end of the first resistor is the input control signal input end of the differential circuit, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor and the first end of the second resistor are connected together to form the first pulse signal output end of the differential circuit, and the second end of the second resistor is connected to the power ground.

3. The IGBT driving protection circuit according to claim 1, characterized in that: The integration circuit includes a first diode, a second capacitor and a third resistor; The anode of the first diode is the first pulse signal input terminal of the integration circuit, the cathode of the first diode, the first end of the second capacitor and the first end of the third resistor are connected together to form the first integration signal output terminal of the first preset time length of the integration circuit, and the second end of the second capacitor and the second end of the third resistor are both connected to the power ground.

4. An IGBT driving circuit, characterized in that: A drive protection circuit comprising a drive circuit and an IGBT according to any one of claims 1 to 3; The differential circuit is further configured to generate a second pulse signal when the input control signal changes from a low level to a high level; The integration circuit is further configured to integrate the second pulse signal to output a second integration signal of a third preset time length; The driving circuit includes a first inverting circuit and a second control circuit; a first inverting circuit, configured to generate a high-level inverting signal when the input control signal jumps from a high level to a low level, and to generate a low-level inverting signal when the input control signal jumps from a low level to a high level; The first control circuit is connected to the first inverting circuit, and is specifically configured to generate a first control signal of a second preset duration according to the high-level inverting signal and the first integrated signal of the first preset duration, and to generate a second control signal of a fourth preset duration according to the input control signal and the second integrated signal of the third preset duration; The second control circuit is connected to the first control circuit and is configured to output a reverse bias voltage of the second preset time length according to the first control signal of the second preset time length to reversely bias the gate of the IGBT circuit for the second preset time length, and to output a positive bias voltage of the fourth preset time length according to the second control signal of the fourth preset time length to forward bias the gate of the IGBT circuit for the fourth preset time length.

5. The IGBT driving circuit according to claim 4, characterized in that: The second control circuit comprises: an isolation component connected to the first control circuit, configured to isolate the first control signal of the second preset duration to output a third control signal of the second preset duration, and to isolate the second control signal of the fourth preset duration to output a fourth control signal of the fourth preset duration; and A driving power component is connected to the isolation component and is configured to output a reverse bias voltage of the second preset time length according to a second control signal of the second preset time length to reversely bias the gate of the IGBT circuit for the second preset time length, and to output a positive bias voltage of the fourth preset time length according to a fourth control signal of the fourth preset time length to forward bias the gate of the IGBT circuit for the fourth preset time length.

6. The IGBT driving circuit according to claim 5, characterized in that: The isolation component includes a first optical coupler, a second optical coupler, a fourth resistor and a fifth resistor; The first end of the fourth resistor and the first end of the fifth resistor constitute the first control signal input end of the second preset time length of the isolation component and the second control signal of the fourth preset time length of the isolation component, the second end of the fourth resistor is connected to the positive electrode of the first optocoupler, and the negative electrode of the first optocoupler is connected to the power ground, the second end of the fifth resistor is connected to the negative electrode of the second optocoupler, and the positive electrode of the second optocoupler is connected to the positive electrode of the internal power supply, the output end of the first optocoupler and the output end of the second optocoupler constitute the third control signal output end of the second preset time length of the isolation component and the fourth control signal output end of the fourth preset time length of the isolation component.

7. The IGBT driving circuit according to claim 5, characterized in that: The driving power component includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first field effect transistor and a second field effect transistor; The first end of the sixth resistor and the first end of the seventh resistor constitute the third control signal input end of the second preset time length of the driving power component and the fourth control signal input end of the fourth preset time length of the driving power component. The second end of the sixth resistor is connected to the gate of the first field effect transistor, and the source of the first field effect transistor is connected to the positive electrode of the internal power supply. The second end of the seventh resistor is connected to the gate of the second field effect transistor, and the source of the second field effect transistor and the first end of the eighth resistor are both connected to the power ground. The drain of the first field effect transistor, the drain of the second field effect transistor, the second end of the eighth resistor and the first end of the ninth resistor are connected in common. The second end of the ninth resistor is the inverting bias voltage output end of the second preset time length of the driving power component and the positive bias voltage output end of the fourth preset time length of the driving power component.

8. A driver, characterized in that: The invention comprises the IGBT driving circuit as claimed in any one of claims 4 to 7.

9. A testing device, characterized in that: It comprises an optical fiber receiving circuit, a second inverter circuit and an IGBT driving circuit as claimed in any one of claims 4 to 7; The optical fiber receiving circuit is configured to receive an optical signal and output an electrical signal according to the optical signal; The second inverter circuit is connected to the optical fiber receiving circuit and the IGBT driving circuit respectively, and is configured to output the input control signal according to the electrical signal.

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