A memory management method, device and system

Abstract

A memory management method, device and system. The memory management method is executed by a memory management hardware accelerator, and the memory management hardware accelerator is coupled to an application subsystem (501) and a communication subsystem (503) respectively. The application subsystem (501) is used to run a main operating system, and the communication subsystem (503) is used to run a communication operating system. The method comprises: obtaining a memory address set (S001) corresponding to a dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set comprises one or more memory addresses; and sending a part of the memory addresses in the memory address set to a component of the communication subsystem (S002).

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a memory management method, device and system. Background Art

[0002] In modern society, computing devices are everywhere, from small computing devices such as mobile phones, personal computers, and smart watches to large computing devices such as servers, switches, and base stations. Usually, these computing devices can be abstracted as computer systems. Computer systems include both hardware components such as processors and memory, as well as software components such as operating systems and applications.

[0003] With the evolution of technology, computing devices can provide more and more functions. Take mobile phones as an example. From early feature phones to today's smart phones, the multimedia processing capabilities of mobile phones are constantly improving, and the maximum mobile communication speed supported by mobile phones is also constantly improving. These basic technological advances have provided a solid foundation for the vigorous development of the mobile Internet industry and greatly enriched people's communication and life.

[0004] At the same time, the structure of computing devices is becoming more and more complex. On the one hand, the operating system (OS) of mobile phone platforms has evolved from the early Symbian operating system to the current Android operating system and iPhone OS (iOS). The openness of these new operating systems to third-party software has spawned a variety of mobile applications (Apps). On the other hand, in order to support stronger multimedia processing capabilities and higher mobile communication rates, the system structure of mobile phones is also constantly evolving, including a more powerful main computing system, a multi-mode integrated communication subsystem, and a large-capacity multi-cache storage subsystem.

[0005] The capacity and access rate of memory are crucial to the performance of computing devices. Therefore, it is necessary to provide a memory management solution that is more suitable for application requirements. Summary of the invention

[0006] Embodiments of the present application provide a memory management method, apparatus, and system to improve the performance of a computing device or reduce the cost of a computing device.

[0007] It should be understood that in the solutions provided in the embodiments of the present application, unless otherwise specified, memory generally refers to the main memory of the computer system. The main memory is used to temporarily store relevant data and program instructions required by the processor when running a program. The main memory generally refers to DRAM, but can also be SRAM, or other memories that can provide the same or similar functions.

[0008] It should be understood that in the solution provided in the embodiment of the present application, the computing device refers to a device that can be abstracted as a computer system. A computing device that supports wireless communication functions may be referred to as a wireless communication device. The wireless communication device may be the entire computing device, or may be a partial device in the computing device, such as a chip related to the wireless communication function, such as a system chip or a communication chip. Among them, the system chip is also referred to as a system on chip, or as a SoC chip. Specifically, the wireless communication device may be a terminal such as a smart phone, or may be a system chip or a communication chip that can be set in the terminal. In addition, the wireless communication device may be a wireless access network device such as a base station, or may be a related chip that can be set in the wireless access network device, such as a SoC chip or a communication chip. The communication chip may include a radio frequency processing chip and a baseband processing chip. The baseband processing chip is sometimes also referred to as a modem. In physical implementation, the communication chip may be integrated inside the SoC chip, or may not be integrated with the SoC chip. For example, the baseband processing chip is integrated in the SoC chip, and the radio frequency processing chip is not integrated with the SoC chip.

[0009] In a first aspect, a computer system is provided, comprising:

[0010] A main computing system for running a main operating system; a functional subsystem for running a secondary operating system; and a memory management device, coupled to the main computing system and the functional subsystem, for:

[0011] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem, wherein the memory address set includes one or more memory addresses; and send part of the memory addresses in the memory address set to the components of the functional subsystem.

[0012] In a second aspect, a wireless communication device is provided, including:

[0013] The application subsystem is used to run the main operating system; the communication subsystem is used to run the communication operating system; and the memory management hardware accelerator is coupled to the application subsystem and the communication subsystem respectively, and is used to:

[0014] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set includes one or more memory addresses; and send some memory addresses in the memory address set to components of the communication subsystem.

[0015] According to a third aspect, a wireless communication device is provided, including:

[0016] The communication subsystem is used to run the communication operating system; the memory management hardware accelerator is coupled to the application subsystem and the communication subsystem respectively, wherein the application subsystem is used to run the main operating system; the memory management hardware accelerator is used to:

[0017] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set includes one or more memory addresses; and send some memory addresses in the memory address set to components of the communication subsystem.

[0018] In a fourth aspect, a wireless communication device is provided, including:

[0019] An application processor, used to run a main operating system; a communication processor, used to run a real-time operating system of a communication subsystem; and a memory management device, electrically connected to the application processor and the communication processor, respectively, for:

[0020] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set includes one or more memory addresses; and send some memory addresses in the memory address set to components of the communication subsystem.

[0021] In a fifth aspect, a wireless communication device is provided, including:

[0022] A communication processor is used to run a real-time operating system of the communication subsystem; a memory management device is electrically connected to the application processor and the communication processor, respectively, wherein the application processor is used to run a main operating system; and the memory management device is used to:

[0023] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set includes one or more memory addresses; and send some memory addresses in the memory address set to components of the communication subsystem.

[0024] In a sixth aspect, a memory management method is provided, the method being executed by a memory management device, the memory management device being coupled to a computing main system and a functional subsystem respectively, the computing main system being used to run a main operating system, the functional subsystem being used to run a secondary operating system, the method comprising:

[0025] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem, wherein the memory address set includes one or more memory addresses; and send part of the memory addresses in the memory address set to the components of the functional subsystem.

[0026] In a seventh aspect, a memory management device is provided, wherein the memory management device is coupled to a computing main system and a functional subsystem respectively, the computing main system is used to run a main operating system, and the functional subsystem is used to run a secondary operating system, and the memory management device includes:

[0027] The first memory management module is used to obtain a memory address set corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem, and the memory address set includes one or more memory addresses; the second memory management module is used to send part of the memory addresses in the memory address set to the components of the functional subsystem.

[0028] In an eighth aspect, a memory management hardware accelerator is provided, wherein the memory management hardware accelerator is coupled to a computing main system and a functional subsystem respectively, the computing main system is used to run a main operating system, the functional subsystem is used to run a secondary operating system, and the memory management hardware accelerator includes:

[0029] Memory management accelerator hardware and a memory management accelerator driver; wherein the memory management accelerator driver includes a first driver that cooperates with the memory management accelerator hardware, a second driver that cooperates with the computing main system, and a third driver that cooperates with the functional subsystem; the memory management accelerator hardware and the memory management accelerator driver are collaboratively configured to:

[0030] Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem, wherein the memory address set includes one or more memory addresses; and send part of the memory addresses in the memory address set to the components of the functional subsystem.

[0031] It should be understood that the above-mentioned main computing system can be a subsystem that includes the computing or control core of the computer system, such as the application subsystem of a smart phone, in which the main operating system of the computer system runs. The main operating system can be a mobile platform operating system such as an Android operating system or an Apple mobile phone operating system, or it can be other operating systems such as a desktop computer, an Internet of Things device, and a cloud server. The program code of the main operating system is mainly stored in a large-capacity memory. When the computer system is powered on, the program code of the main operating system can be loaded into the memory first, and then loaded into the processing core of the application subsystem, such as the CPU. The main operating system can manage the software and hardware resources of the entire computer system, such as the management of the memory space fixedly allocated to the application subsystem.

[0032] It should be understood that the above-mentioned functional subsystems can be relatively independent subsystems such as a communication subsystem. Each functional subsystem can be responsible for a relatively independent function of a part of the computer system. The functional subsystem can have a separate operating system, which can be recorded as a secondary operating system relative to the main operating system. The program code of the secondary operating system can also be stored in a large-capacity memory. When the functional subsystem is powered on, the program code of the secondary operating system can be first loaded into the memory and then loaded into the processing core of the functional subsystem, such as the CPU or DSP. The secondary operating system can manage the software and hardware resources of the functional subsystem, such as the management of the memory space fixedly allocated to the functional subsystem.

[0033] It should be understood that, since the size of the dynamic memory space allocated by the main operating system to the functional subsystem (such as the communication subsystem) is adjustable, the size of the memory address set is also variable. The factors that change the size of the memory address set include: the size of the dynamic memory space, and the use of the memory addresses in the memory address set. For example, assuming that the main operating system first allocates a part of the memory space to the functional subsystem (such as the communication subsystem), the memory management hardware accelerator can obtain the memory addresses corresponding to this part of the memory space. The memory addresses corresponding to this part of the memory space constitute the memory address set. When the memory addresses corresponding to this part of the memory space have been used by the functional subsystem (such as the communication subsystem), or the main operating system has recovered some memory addresses from the memory address set, the number of memory addresses in the memory address set will decrease. Thereafter, assuming that the main operating system newly allocates another part of the memory space to the functional subsystem (such as the communication subsystem), the memory addresses corresponding to the newly allocated part of the memory space can also be included in the memory address set. Accordingly, the number of memory addresses in the memory address set will increase.

[0034] The communication operating system running in the communication subsystem may be a real-time operating system, such as Qualcomm's QuRT real-time operating system. The components of the communication subsystem may be a processing core (denoted as CCore) of the communication subsystem, a hardware accelerator (denoted as HAC) of the communication subsystem, a baseband processor (denoted as BBP) of the communication subsystem, or one or more components of other components of the communication subsystem that have memory usage requirements.

[0035] The application subsystem and the communication subsystem included in the wireless communication device may be partial components of the application subsystem and the communication subsystem. For example, the wireless communication device may include a processing core of the application subsystem, which is referred to as an application processor. The wireless communication device may include a processing core of the communication subsystem, which is referred to as a communication processor.

[0036] Based on the technical solution provided in any of the above aspects, the memory management device (such as a memory management hardware accelerator) is configured to obtain a set of memory addresses corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem (such as a communication subsystem). Since the size of the dynamic memory space allocated by the main operating system is adjustable, this is conducive to reducing the size of the memory space fixedly allocated to the functional subsystem. In addition, the application data (such as voice, video, text, etc.) stored by the components of the functional subsystem in the dynamic memory space allocated by the main operating system can be accessed by the computing main system (such as the application subsystem) without additional moving or copying operations, thereby saving a large amount of unnecessary memory access overhead, thereby reducing system power consumption and service delay. In addition, the memory management device is configured to send part of the memory addresses in the memory address set to the components of the communication subsystem. This part of the memory address that has been sent to the functional subsystem component can be used by the component as needed, without having to apply to the auxiliary operating system (such as the communication operating system) or the main operating system. Therefore, this part of memory addresses can be directly used by the component without applying to the auxiliary operating system, which is helpful to reduce the delay of memory allocation.

[0037] In the technical solution provided in any of the above aspects, the memory management device can be a general-purpose processor for running a computer program, or a memory management hardware accelerator. Since the driver of the memory management hardware accelerator is a lower-level software relative to the operating system (main operating system and auxiliary operating system) software. The response delay of the lower-level software is more controllable, so it is conducive to further reducing the delay of memory allocation.

[0038] In combination with the technical solution provided in any of the above aspects, in an optional implementation method, this part of the memory addresses of the components sent to the functional subsystem (such as the communication subsystem) can be stored in a first memory. Different components of the functional subsystem may correspond to different first memories. The first memory corresponding to each component may be a built-in memory of the component, such as a tightly coupled memory or a register. Since this part of the memory addresses is stored in the built-in memory of the component, if the component has a memory usage requirement, some memory addresses can be read directly from the built-in memory of the component, and the memory space corresponding to these memory addresses can be directly used. Therefore, compared to storing the memory addresses in other locations, such as in the memory, the delay of memory allocation can be further reduced.

[0039] In combination with the technical solution provided by any aspect or any optional implementation of the above-mentioned aspects, in an optional implementation, the memory management device (such as a memory management hardware accelerator) is configured to: send part of the memory addresses in the memory address set to the first memory based on the category of the components of the functional subsystem (such as the communication subsystem). For example, if the components of the first category have relatively large memory requirements, more memory addresses can be sent, and the component can select a built-in memory with a relatively large capacity. If the components of the second category have relatively small memory requirements, fewer memory addresses can be sent, and the component can select a built-in memory with a relatively small capacity. Among them, the relative size of the memory requirements of different component categories can be determined based on statistical data or historical experience. For example, the components of the 5G communication subsystem have greater memory requirements than the components of the 4G communication subsystem. Components with complex data processing tasks have greater memory requirements than components with simple data processing tasks.

[0040] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned multiple aspects, in an optional implementation method, the memory management device (such as a memory management hardware accelerator) is configured to: periodically send some memory addresses in the memory address set to the first memory. The period of sending memory addresses to the first memory can also be determined in combination with the capacity of the first memory or the category of the component where the first memory is located. For example, if the capacity of the first memory is relatively large, the period of sending memory addresses to the first memory can be relatively large. Conversely, if the capacity of the first memory is relatively small, the period of sending memory addresses to the first memory can be relatively small. For another example, the period of sending the first memory corresponding to the components of the 5G communication subsystem can be smaller, and the period of sending the first memory corresponding to the components of the 4G communication subsystem can be larger.

[0041] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned aspects, in an optional implementation method, the memory management device (such as a memory management hardware accelerator) is configured to: send part of the memory addresses in the memory address set to the first memory based on the triggering of a first event.

[0042] The first event may be detected by the first memory or a component served by the first memory, and after detecting the occurrence of the first event, the memory management device is notified. Alternatively, the first event may also be actively detected by the memory management device, such as detecting the read / write status of the first memory.

[0043] Specifically, the first event may include: the number of memory addresses stored in the first memory is lower than the first lower threshold. It should be understood that the number of memory addresses can be a natural number or a relative proportion. Correspondingly, the first lower threshold can also be a natural number or a relative proportion. Alternatively, the first event may also include: a first hardware interrupt request of a component of the functional subsystem (such as a communication subsystem). Of course, the first event may also include: a first software interrupt response of a component of the functional subsystem (such as a communication subsystem). Usually, the processing delay of a hardware interrupt response is lower than the delay of a software interrupt response.

[0044] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned aspects, in an optional implementation method, the component of the functional subsystem (such as a communication subsystem) also includes a second memory, and the second memory is used to store memory addresses received from the memory management device (such as a memory management hardware accelerator) and used by the components of the functional subsystem (such as a communication subsystem).

[0045] Among them, in a specific implementation, the first memory and the second memory can be different memories, or different storage spaces in the same memory. In addition, different components of the functional subsystem can correspond to different second memories, or different storage spaces of the same memory. As an optional alternative implementation, the second memory can also be placed in the memory management device. As another optional alternative implementation, the memory address received from the memory management device (such as a memory management hardware accelerator) and used by the components of the functional subsystem (such as a communication subsystem) can still be stored in the above-mentioned first memory.

[0046] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned aspects, in an optional implementation method, the memory management device (such as a memory management hardware accelerator) is also used to: receive the memory address stored in the second memory based on the triggering of a second event.

[0047] The second event may be different from the first event. The second event may be detected by the second memory or a component served by the second memory, and after detecting the occurrence of the second event, the memory management device is notified. Alternatively, the second event may also be actively detected by the memory management device, such as detecting the read / write status of the second memory.

[0048] Specifically, the second event may include: the number of memory addresses stored in the second memory is higher than a second upper threshold. The first lower threshold may also be a natural number or a relative proportion. Alternatively, the second event may include: a second hardware interrupt request of a component of the functional subsystem (such as a communication subsystem).

[0049] It should be understood that the second hardware interrupt request may be different from the aforementioned first hardware interrupt request, i.e., have a different hardware interrupt number. Of course, the second event may also include: a second software interrupt response of a component of the functional subsystem (such as a communication subsystem). There may also be multiple second software interrupt requests, each of which has its own software interrupt number.

[0050] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned multiple aspects, in an optional implementation method, the memory addresses in the memory address set are stored in a third memory. The third memory may be a built-in memory of the memory management device (such as a memory management hardware accelerator). In another optional implementation method, the third memory may be a memory connected to the memory management device (such as a memory management hardware accelerator) through an interconnect bus. In comparison, the use of the latter optional implementation method can save the overhead of the built-in memory in the memory management device; the use of the former optional implementation method can further improve the memory management device's ability to manage the memory addresses in the memory address set, thereby speeding up the memory allocation rate.

[0051] On this basis, the memory management device (such as a memory management hardware accelerator) can also be used to: detect the status information of the memory address set, and the status information of the memory address set is used to indicate the number of memory addresses in the memory address set. Accordingly, the memory management device (such as a memory management hardware accelerator) can also be used to: when it is detected that the number of memory addresses in the memory address set is lower than a third lower threshold, notify the main operating system to add some memory addresses to the memory address set. In addition, the memory management device (such as a memory management hardware accelerator) can also be used to: when it is detected that the number of memory addresses in the memory address set is higher than a third upper threshold, notify the main operating system to reclaim some memory addresses from the memory address set.

[0052] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned multiple aspects, in an optional implementation method, the memory address from the second memory is stored in the fourth memory based on the triggering reception of the second event; wherein the fourth memory can be a built-in memory of the memory management device (such as a memory management hardware accelerator) or a memory. Accordingly, the memory management device (such as a memory management hardware accelerator) can also be used to: when it is detected that the number of memory addresses in the fourth memory is higher than the fourth upper threshold, notify the main operating system to reclaim the memory address from the fourth memory.

[0053] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned aspects, in an optional implementation method, the memory management device (such as a memory management hardware accelerator) is used to: periodically obtain the memory address corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem (such as a communication subsystem), wherein the periodically obtained memory address is also included in the memory address set.

[0054] The period of obtaining the memory address corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem (such as the communication subsystem) is greater than the period of sending some memory addresses in the memory address set to the first memory.

[0055] In combination with the technical solution provided by any aspect or any optional implementation method in the above-mentioned aspects, in an optional implementation method, the memory addresses corresponding to the dynamic memory space allocated by the main operating system to the functional subsystem (such as the communication subsystem) are respectively stored in pointers of multiple different levels; wherein, pointers of the same level correspond to memory spaces of the same size, and pointers of different levels correspond to memory spaces of different sizes.

[0056] In combination with the technical solution provided in any aspect or any optional implementation of the above-mentioned aspects, in an optional implementation, the components of the memory management device (such as a memory management hardware accelerator) and the components of the functional subsystem (such as a communication subsystem) are integrated into the same chip. In another optional implementation, the components of the memory management device (such as a memory management hardware accelerator) and the components of the computing main system (such as an application subsystem) are integrated into the same chip. It should be understood that the integration mentioned here refers to the physical form of the chip during manufacturing, packaging and sales, and the components mainly refer to hardware components, and can be partial hardware components, and software components are not limited.

[0057] In combination with the technical solution provided in any aspect or any optional implementation method of the above-mentioned aspects, in an optional implementation method, the components of the functional subsystem (such as a communication subsystem) include: a processing core of the functional subsystem (such as a communication subsystem), a hardware accelerator of the functional subsystem (such as a communication subsystem), or one or more components in a sub-functional processor of the functional subsystem (such as a baseband processor of the communication subsystem).

[0058] In a ninth aspect, a computer-readable storage medium is provided, wherein a program code is stored in the computer-readable storage medium, and when the program code is executed by a computer or a processor, a memory management method or a memory management device of any one of the multiple technical solutions provided in the sixth aspect, the seventh aspect, and the above-mentioned various optional implementations is implemented. Wherein, when the memory management device is a memory management hardware accelerator, the program code stored in the computer-readable storage medium may be a driver or firmware of the memory management hardware accelerator.

[0059] In a tenth aspect, a computer program product is provided. When the program code contained in the computer program product is executed by a computer or a processor, any one of the memory management methods or memory management devices in the multiple technical solutions provided in the sixth aspect, the seventh aspect, and the above-mentioned various optional implementations is implemented. Wherein, when the memory management device is a memory management hardware accelerator, the program code contained in the computer program product may be a driver or firmware of the memory management hardware accelerator.

[0060] It should be understood that the above-mentioned various technical solutions provide various types of memories, including a first memory, a second memory, a third memory, and a fourth memory. Among them, the first memory and the second memory can be understood as serving one or some components of the functional subsystem, and will be introduced in conjunction with the pointer subgroup as an example in the following specific implementation. The third memory and the fourth memory can be understood as serving the entire functional subsystem, and will be introduced in conjunction with the pointer group as an example in the following specific implementation.

[0061] It should be understood that since the main operating system is often a non-real-time operating system, the software delay of the main operating system is relatively large, and the delay requirements of the functional subsystem are often relatively high. Therefore, the above-mentioned various technical solutions mainly adopt a two-level memory management mechanism. Among them, the first-level memory management mechanism is mainly the interaction between the memory management device and the main operating system, and the second-level memory management mechanism is mainly the interaction between the memory management device and the components of the functional subsystem. The use of a two-level memory management mechanism is conducive to decoupling the memory allocation delay from the response delay of the main operating system, and the memory allocation delay can be improved by optimizing the second-level memory management mechanism. Among them, the interaction frequency between the memory management device and the components of the functional subsystem can be greater than, or even much greater than (for example, several orders of magnitude greater), the interaction frequency between the memory management device and the main operating system. Correspondingly, the storage capacity of the first memory or the second memory can also be less than, or even much less than (for example, several orders of magnitude smaller), the storage capacity of the third memory or the fourth memory.

[0062] It should be understood that the above-mentioned various technical solutions also provide a variety of thresholds associated with the number of memory addresses, including: a first lower threshold, a second upper threshold, a third lower threshold, a third upper threshold and a fourth upper threshold. It should be understood that these thresholds are not mutually exclusive and can be used in combination. Since the number of memory addresses can be a natural number or a relative proportion, such as a percentage. Accordingly, these thresholds can also be natural numbers or relative proportions. For any of these thresholds, when the number of memory addresses is equal to the threshold, it can be considered to be a critical state. For a critical state, it can be considered that the threshold judgment condition is met and the corresponding subsequent operation is performed, or it can be considered that the threshold judgment condition is not met and the corresponding subsequent operation is not performed. In addition, in order to prevent the ping-pong effect of the threshold judgment operation, additional conditions, such as hysteresis conditions, can be set for each threshold judgment. Taking the first lower threshold as an example, in addition to satisfying that the number of memory addresses is less than the first lower threshold, it can also be required that the state lasts for a short period of hysteresis time before it is considered to meet the threshold judgment condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0064] Figure 2 A schematic diagram of a memory hierarchy structure of a computer system provided in an embodiment of the present application;

[0065] Figure 3 A schematic diagram of the structure of a storage subsystem of a computer system provided in an embodiment of the present application;

[0066] Figure 4 A schematic diagram of a hierarchical structure of a computer system provided in an embodiment of the present application;

[0067] Figure 5 A schematic diagram of the structure of a wireless communication device provided in an embodiment of the present application;

[0068] Figure 6 A memory allocation diagram of a wireless communication device provided in an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the structure of another wireless communication device provided in an embodiment of the present application;

[0070] Figure 8 A schematic diagram of an interactive framework of a memory management solution provided in an embodiment of the present application;

[0071] Fig. 9 Another memory allocation diagram of a wireless communication device provided in an embodiment of the present application;

[0072] Fig.10 A schematic diagram of the structure of another wireless communication device provided in an embodiment of the present application;

[0073] Fig.11 A schematic diagram of storage of a memory pointer provided in an embodiment of the present application;

[0074] Fig.12 A schematic diagram of another memory pointer storage provided in an embodiment of the present application;

[0075] Fig.13 A flowchart of a memory management method provided in an embodiment of the present application;

[0076] Fig.14 A flowchart of another memory management method provided in an embodiment of the present application.

[0077] It should be understood that the size and shape of each block diagram in the above structural diagram are for reference only and should not constitute an exclusive interpretation of the embodiment of the present invention. The relative position and inclusion relationship between the blocks presented in the structural diagram are only schematic representations of the structural association between the blocks, and do not limit the physical connection method of the embodiment of the present invention. DETAILED DESCRIPTION

[0078] The technical solution provided by the present application is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the examples of the present application are mainly to illustrate the possible implementation methods of the technical solution of the present application and should not be interpreted as the only limitation on the technical solution of the present application. It is known to those of ordinary skill in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present application is also applicable to similar technical problems.

[0079] It should be understood that the memory management solutions provided in the embodiments of the present application include memory management methods, devices and systems. Since the principles of solving the problems in these technical solutions are the same or similar, some repetitions may not be repeated in the following specific embodiments, but it should be considered that these specific embodiments have been referenced to each other and can be combined with each other.

[0080] Figure 1 A schematic diagram of the structure of a computer system provided in an embodiment of the present application. Figure 1 As shown, the computer system includes a central processing unit (CPU) 101, a memory (memory or storage) 102, an input / output (I / O) device 103, and an interconnectivity bus 104 connecting the CPU 101, the memory 102 and the I / O device 103. It should be understood that for the purpose of simplicity, Figure 1 , a CPU, a memory and three I / O devices are shown. However, in the computer system provided by the embodiment of the present application, the number of each of the CPU, memory and I / O device can be one or more. In addition, the interconnection bus 104 can also be a plurality of buses, or even a collection of multiple types of buses.

[0081] CPU, also known as central processing unit, is the engine that executes program instructions. As the name implies, CPU is the core component of the computer system's calculation and control. Memory is the storage component of the computer system, used to store data and program instructions. The bus is the data channel that runs through the various components in the computer system, used to transfer data information between these components of the computer system. I / O devices are the data channels for input and output between the computer system and the outside world, used to obtain input information from the outside or output information to the outside world.

[0082] The bus is usually designed to transfer fixed-length byte (byte) blocks, that is, words. The number of bytes in a word (word length) is a basic parameter of the computer system. Taking a personal computer (PC) as an example, the word length of a common bus is 4 bytes (32 bits) or 8 bytes (64 bits). Common I / O devices include keyboards, mice, handles, monitors, microphones, and speakers. In particular, disks or solid-state drives are also considered an I / O device. In addition, the network that communicates with the computer system can also be considered an I / O device.

[0083] A CPU is usually a processor that supports a certain instruction set architecture (ISA). Common ISAs include complex instruction set computing (CISC) architecture represented by x86, and reduced instruction set computing (RISC) architecture represented by ARM (Advanced RISC Machine or Acorn RISC Machine), MIPS (Microprocessor without Interlocked Pipeline Stages), and Power. The CPU generally includes a register file, a program counter (PC), and an arithmetic logic unit (ALU).

[0084] Among them, ALU is the execution unit of the CPU, which is mainly used to implement basic arithmetic and logical operations such as addition, multiplication, negation, and shift. The register stack is also translated as a register file, which consists of some registers with very small capacity but extremely fast access speed, and can be used to temporarily store a small amount of instructions, data, and addresses. The program counter is also called the instruction pointer or instruction address register, which is mainly used to store the address of the instruction to be executed by the CPU. The size and number of registers are part of the ISA specification, and the common register size is 32 bits or 64 bits. In an example process, the CPU determines the address of the instruction to be executed based on the program counter, and the instruction and related data are loaded into the register stack. Then, the CPU uses the arithmetic logic unit to complete the operation corresponding to the instruction, and the operation result can be temporarily stored in the register stack. In addition, the CPU can also calculate the address of the next instruction and temporarily store the address in the program counter. Finally, the CPU continues to execute the next instruction, thereby realizing the automatic operation of the program.

[0085] Memories can be divided into volatile memory and non-volatile memory (NVM). Volatile memory refers to memory that loses the data stored inside when the power supply is interrupted. At present, volatile memory is mainly random access memory (RAM), including static random access memory (SRAM) and dynamic random access memory (DRAM). Non-volatile memory refers to memory that does not lose the data stored inside even if the power supply is interrupted. Common non-volatile memories include read-only memory (ROM), optical disks, magnetic disks, solid-state drives, and various memory cards based on flash memory technology.

[0086] Generally speaking, the access rate and unit capacity cost of volatile memory are much higher than those of non-volatile memory. In order to take into account the requirements of faster access rate and larger storage capacity, computer systems usually use multiple memories at the same time to form a memory hierarchy. The basic idea of ​​the memory hierarchy is that the memory with faster access rate (referred to as upper memory) is closer to the CPU, and the memory with larger storage capacity (referred to as lower memory) is farther away from the CPU. The upper memory can usually be used as a cache for the lower memory.

[0087] Figure 2 A schematic diagram of a memory hierarchy structure of a computer system provided in an embodiment of the present application. Figure 2 As shown, the registers are at the top, denoted as level 0 or L0. The next level of memory after the registers is the CPU cache, also known as cache for short. The CPU cache can have multiple levels, such as level 1, level 2, or level 3. Figure 2 The three levels of CPU cache are shown in the figure, denoted as L1 to L3. Registers and CPU cache generally use SRAM, but the access rate of registers is usually faster. The typical access rate of SRAM is on the order of several nanoseconds (ns). The next level of memory after the CPU cache is DRAM, denoted as L4. The typical access rate of DRAM is on the order of tens of nanoseconds. The next level of memory after DRAM is flash memory. The typical access rate of flash memory is on the order of tens of microseconds (microsecnd, μs). The next level of memory after flash memory is disk. The typical access rate of disk is on the order of several milliseconds (millisecond, ms). Flash memory and disk are usually used as local mass storage devices of the computer system, denoted as L5. In addition to local mass storage devices, current computer systems can also be configured with remote mass storage devices, such as cloud storage. From Figure 2 It is not difficult to see that in the memory hierarchy of a computer system, from top to bottom, the typical access rate of memory is getting slower and slower, but fortunately the unit capacity cost is also getting lower and lower.

[0088] Figure 3 A schematic diagram of the structure of a storage subsystem of a computer system provided in an embodiment of the present application. Figure 3 As shown, the CPU cache 3011 and the register stack 3012 are integrated inside the CPU 301, the main memory 302 is connected to the CPU 301 through the interconnection bus 304, and the mass storage device 303, as an I / O device, is connected to the CPU 301 through the I / O interface 305 and the interconnection bus 304.

[0089] Among them, the main memory (main memory or primary storage) is referred to as the main memory. As the name implies, it is the main memory in the computer system, which is used to temporarily store the relevant data and program instructions required by the CPU to run the program. The main memory is generally DRAM, and sometimes also includes SRAM such as registers and CPU cache. Large-capacity storage devices, also known as secondary storage or auxiliary storage, are generally flash memory or disks. Large-capacity storage devices can store operating systems and application software for a long time. However, since the access rate of large-capacity storage devices is too different from the clock cycle of the CPU, it is not suitable for direct access by the CPU. Therefore, when it is necessary to run an operating system or application, the relevant data and program instructions need to be copied from the large-capacity storage device to the main memory, and the main memory temporarily stores the data and instructions required for the CPU to run in order to meet the CPU's fast access requirements.

[0090] Obviously, the performance of the main memory determines the performance of the computer system to a large extent. Therefore, the main memory is an indispensable internal component of the computer system, also known as internal memory or memory. Correspondingly, the mass storage device is also called external memory, which can be set outside the computer system. However, as the demand for mass storage is still growing, mass storage devices are currently very important components of computer systems and are usually also set inside computer systems.

[0091] While taking into account the reading rate, the total amount of main memory is always expected to be larger in order to meet the memory space requirements of the entire wireless communication device. However, currently, due to cost constraints, the total amount of main memory is still significantly smaller than the storage space of large-capacity storage devices. Taking smartphones as an example, the total amount of memory of smartphones is usually between hundreds of megabytes (MB) and several gigabytes (GB), such as 512MB, 1GB, 2GB, 3GB, 4GB, 6GB or even 8GB or higher, while the storage space of large-capacity storage devices is generally between tens of GB and hundreds of GB, such as 32GB, 64B, 128GB, 256GB or even 512GB or higher.

[0092] It should be understood that in the embodiments of the present application, unless otherwise specified, memory generally refers to the main memory of the computer system. Specifically, the memory can use synchronous DRAM (synchronous DRAM, SDRAM) with double data rate (double data rate, DDR), referred to as DDR memory or DDR. Ordinary SDRAM only transmits data once in one clock cycle, while DDR SDRAM can transmit data at least twice in one clock cycle, so it is called double data rate. DDR memory includes DDR memory that complies with DDR1, DDR2, DDR3 and DDR4 and their subsequent evolution standards formulated by the Joint Electron Device Engineering Council (Joint Electron Device Engineering Council, JEDEC), and also includes DDR memory called mobile DDR (mobile DDR, MDDR) or low power DDR (low power DDR, LPDDR or LP-DDR).

[0093] Figure 4 A schematic diagram of a hierarchical structure of a computer system provided in an embodiment of the present application. Figure 4 As shown in the figure, in the hierarchical structure of a computer system, hardware is at the bottom layer and software is at the top layer. Among them, the operating system is the system software that manages the hardware and software resources of the computing device, and can be regarded as a layer of system software between the application and the hardware. The operating system can usually provide basic functions such as memory management, I / O device management, and user operation interface. All attempts by the application to operate the hardware must go through the operating system. The introduction of the operating system as an intermediate software layer can, on the one hand, provide a simple and consistent mechanism for the application to use the complex and diverse underlying hardware, and on the other hand, prevent the underlying hardware from being abused by some out-of-control applications.

[0094] Moreover, as the functions supported by computer systems become more and more abundant, some important functions are often implemented by relatively independent subsystems. These subsystems can have their own operating systems, which makes it possible for a computer system to have multiple operating systems. Among them, the main operating system runs in the main system of the computer system to manage the software and hardware resources of the computer system. The auxiliary operating system can also run in the subsystem to manage the software and hardware resources of the subsystem.

[0095] Taking mobile phones as an example, the main operating system of the current mobile phone platform is generally Android or Apple operating system. The main operating system can manage the software and hardware resources of the entire mobile phone and provide users with a graphical operating interface. At the same time, in order to support the evolving radio access technology (radio access technology, RAT), there is usually a carefully designed communication subsystem inside the mobile phone. An operating system different from the main operating system can run in the communication subsystem. The operating system running in the communication subsystem is recorded as a communication operating system in the embodiment of the present application. The communication operating system is generally a real-time operating system (real time operating system, RTOS), while the operating systems of mobile phone platforms such as Android and Apple are not considered to be real-time operating systems. In operating system theory, "real-time" usually refers to a specific operation, such as a memory allocation operation, and the time consumed will not exceed the time limit promised by the operating system. Therefore, the use of a real-time operating system in the communication subsystem is conducive to better meeting the low latency requirements of certain wireless communication services.

[0096] During the operation of a computer system, whether it is an application or a subsystem, a part of the memory space is always needed. When an application or subsystem of a computer system is running, the operating system usually allocates a part of the memory space for it. For the operating system, memory management can be divided into dynamic memory management and static memory management. In the dynamic memory management scheme, the part of the memory space allocated by the operating system to the application or subsystem can be called dynamic memory space or dynamic memory. When the dynamic memory space is not used by the application or subsystem, it can be reallocated by the operating system for use by other applications or subsystems. In the static memory management scheme, the part of the memory space allocated by the operating system to the application or subsystem can be called static memory space or static memory. Even if the static memory space is not used by the application or subsystem, it cannot be used by other subsystems or applications.

[0097] With the continuous evolution of computer systems, there are more and more subsystems of computer systems, and these subsystems have higher and higher demands for memory. The following will take the communication subsystem of a wireless communication device as an example to explain in detail some memory management solutions provided in the embodiments of the present application. These memory management solutions help to better meet the demands of the subsystems of the computer system for memory. For example, the memory management solutions provided by some optional embodiments of the present application can reduce the latency of memory allocation, which is conducive to meeting the demands of subsystems with particularly strict latency requirements for memory. The memory management solutions provided by other optional embodiments of the present application can provide more available memory, which is conducive to saving memory costs or improving memory usage efficiency. It should be understood that the communication subsystem is only an example of a subsystem of a computer, and the solutions provided in the embodiments of the present application may also be applicable to other subsystems of a computer.

[0098] Figure 5 A schematic diagram of the structure of a wireless communication device provided in an embodiment of the present application.

[0099] It should be understood that in the embodiment of the present application, the wireless communication device is a computing device with wireless communication function. The wireless communication device can be a terminal in a wireless communication system or a wireless access network device such as a base station. Figure 5 The terminal and base station shown can serve as an example of a mobile communication system based on the technical specifications of the 3rd Generation Partnership Project (3GPP), and may also cover wireless communication systems based on other wireless communication standards, such as the 802 series of the Institute of Electrical and Electronics Engineers (IEEE), such as 802.11, 802.15, 802.20 and other wireless communication standards.

[0100] The terminal may also be referred to as user equipment (UE), mobile station (MS) or subscriber unit (SU). The terminal may be, but is not limited to, a mobile phone, a tablet computer, a laptop computer, a wearable device (smart watch, smart bracelet, smart helmet, smart glasses, etc.), and other communication devices with wireless access capabilities, such as various IoT devices, including smart home devices (smart meters, smart appliances, etc.), smart vehicles, etc. The base station may be a fifth generation (5 th The general Node B (gNB) in the fourth generation (4th The base station is an evolutionary Node B (eNB or eNodeB) in the 4G (4th Generation) mobile communication system, as well as base stations in other possible wireless access technologies. The base station can also have a variety of physical forms and transmission powers, such as macro base stations or micro base stations.

[0101] like Figure 5 As shown, the wireless communication device includes an application subsystem 501, a memory 502, and a communication subsystem 503. The application subsystem 501 and the communication subsystem 503 are connected to the memory 502 via an interconnect bus, and both can use the memory space provided by the memory 502. Among them, the application subsystem 501 can be used as the main control system or main computing system of the wireless communication device, for running the main operating system and application programs, managing the software and hardware resources of the entire wireless communication device, and providing a user operation interface for the user. The communication subsystem 503 is used to run the communication operating system and communication function software, manage the software and hardware resources of the communication subsystem, and provide wireless communication functions for the user.

[0102] The application subsystem 501 may include one or more processing cores. Figure 5 What is shown is a multi-core application subsystem, including core 1 (C-1), core 2 (C-2), core 3 (C-3) and core n (Cn), where n is a positive integer. Among them, n is only for illustrative purposes, and the value can be less than 4, such as 2 or 1, or greater than or equal to 4, such as 4 or 8 or 10 or 12. The capabilities of different cores can also be different, such as different main frequencies. Each core can have its own dedicated cache, and multiple cores can also have a shared cache. In addition, the application subsystem 501 may also include driver software related to other subsystems.

[0103] The communication subsystem 503 can be further divided into a radio frequency (RF) subsystem and a baseband (BB) subsystem. The RF subsystem is mainly used to process RF signals. Figure 5The RF module is used to represent it. Specifically, the RF subsystem may include electronic devices such as antennas, switches, low noise amplifiers, power amplifiers, mixers, oscillators, filters and processors to provide a receiving path and a transmitting path. The receiving path is used to receive the RF signal through the antenna, process the RF signal (such as amplification, filtering and down-conversion) to obtain an intermediate frequency or baseband signal, and pass it to the baseband subsystem. The receiving channel is used to receive the intermediate frequency or baseband signal from the baseband subsystem, process the intermediate frequency or baseband signal (such as up-conversion, amplification and filtering) to obtain a RF signal, and finally radiate the RF signal into space through the antenna.

[0104] The baseband subsystem may include one or more processing cores, analog-to-digital conversion devices, baseband processors (BBPs), hardware accelerators (HACs), and caches. For illustrative purposes, Figure 5 The baseband processor, processing core, hardware accelerator and cache are shown in FIG. It should be understood that the types and numbers of these electronic devices are not limited in the embodiments of the present application, and the baseband subsystem may not include Figure 5 Some of the components shown (such as HAC), or including Figure 5 Some components (such as analog-to-digital converter components) are not shown. The analog-to-digital converter components include an analog-to-digital converter (ADC) that converts analog signals into digital signals and a digital-to-analog converter (DAC) that converts digital signals into analog signals.

[0105] The baseband processor can be used to extract useful information or data bits from the digital signal originating from the base station, or to convert the information or data bits originating from the application subsystem into a digital signal to be sent to the base station. These information or data bits can be data representing user data or control information such as voice, text, video, etc. Specifically, the baseband processor can implement baseband signal processing operations such as modulation and demodulation, encoding and decoding. In addition, for different wireless access technologies, such as 5G new radio (NR) and 4G long term evolution (LTE), they often have different baseband signal processing operations. Therefore, in order to support the integration of multiple mobile communication modes, multiple processing cores and even multiple baseband processors can be included at the same time.

[0106] Hardware accelerators can be used to implement some sub-functions with high processing overhead, such as data packet assembly and parsing, data packet encryption and decryption, etc. These sub-functions can also be implemented using general-purpose processors, but due to performance or cost considerations, it may be more appropriate to use hardware accelerators. Therefore, the type and number of hardware accelerators can be specifically selected based on demand. In a specific implementation, one or a combination of field programmable gate arrays (FPGA) and application specific integrated circuits (ASIC) can be used to implement it. Of course, one or more processing cores can also be used in the hardware accelerator.

[0107] It should be understood that in the embodiments of the present application, each processing core of the wireless communication device may represent a processor, which may be a general-purpose processor or a processor designed for a specific field. For example, the processor may be a CPU or a digital signal processor (DSP). When necessary, the processor may also be a microcontroller (MCU), a graphics processing unit (GPU), an image signal processor (ISP), an audio signal processor (ASP), and various processors for artificial intelligence (AI) applications, including but not limited to a neural network processing unit (NPU), a tensor processing unit (TPU), and a processor referred to as an AI engine.

[0108] In practical applications, based on the needs of application scenarios, wireless communication devices may use a combination of different numbers and types of processing cores. In addition, the functional division of the radio frequency subsystem and the baseband subsystem in the communication subsystem 503 may also be adjusted. For example, the functions of part of the radio frequency subsystem may be integrated into the baseband subsystem, or vice versa.

[0109] In one implementation, the RF subsystem may include an independent antenna, an independent RF front-end (RF frontend, RFFE) device, and an independent RF processing chip. RF processing chips are sometimes also referred to as receivers, transmitters, or transceivers. Antennas, RF front-end devices, and RF processing chips can all be manufactured and sold separately. Of course, the RF subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, some devices belonging to the RF front end are integrated into the RF processing chip.

[0110] In one implementation, the baseband subsystem can be used as an independent chip, which can be called a modem. Among them, the hardware components of the baseband subsystem can be manufactured and sold in units of modems. Since the baseband processor is the core component of wireless communication, the modem is sometimes also called a baseband chip or a baseband processor. In another implementation, the baseband subsystem can be further integrated into a SoC chip and manufactured and sold in units of SoC chips. In addition, the software components of the baseband subsystem can be built into the hardware components when leaving the factory, or can be imported into the hardware components from other non-volatile memories after leaving the factory, or these software components can be updated and upgraded online through the network.

[0111] During operation, the communication subsystem may perform a large amount of data processing operations, which will occupy a certain amount of memory space. In addition, since wireless communication services have high requirements for low latency, if the main operating system of the wireless communication device dynamically allocates memory to the communication subsystem, the memory allocation delay may be large, resulting in failure to meet the low latency requirements of certain wireless communication services. Therefore, in order to meet the low latency requirements of wireless communication services, a portion of the memory space can be fixedly allocated to the communication subsystem and directly managed by the communication operating system.

[0112] Figure 6 A schematic diagram of memory allocation for a wireless communication device provided in an embodiment of the present application.

[0113] like Figure 6As shown in the left half, the total memory of the wireless communication device is fixedly divided into three parts, which are recorded as "Others", "Application Subsystem" and "Communication Subsystem" from top to bottom. Among them, "Others" means that this part of the memory space has other uses, such as being reserved for other subsystems. "Application Subsystem" means that this part of the memory space is allocated to the application subsystem for use, which is recorded as A1. Usually, the memory space allocated to the application subsystem is the largest. This part of the memory space is directly managed by the main operating system running in the application subsystem, and is allocated to the application programs and some subsystems running in the wireless communication device as needed. It should be understood that Figure 6 The memory division shown is for illustration only, and the memory of the wireless communication device may be divided in other ways, such as the memory being divided into two parts, four parts or more parts.

[0114] "Communication subsystem" means that this part of memory space is allocated to the communication subsystem for use, denoted as C1. This part of memory space allocated to the communication subsystem is generally directly managed by the communication operating system and is often invisible to the main operating system. In other words, even if the communication subsystem does not use all the allocated memory space, it cannot be allocated by the main operating system to other subsystems or applications for use. Therefore, in this sense, this part of memory space fixedly allocated to the communication subsystem is also equivalent to static memory space for the main operating system.

[0115] In addition, in order to ensure the performance of wireless communication services, the size of the memory space allocated to the communication subsystem is usually determined by referring to the peak rate of wireless communication. However, during the operation of wireless communication devices, the time at the peak rate of wireless communication is generally small. Therefore, the actual utilization rate of the memory space allocated to the communication subsystem may not be high, which will lead to a waste of memory space in a statistical sense.

[0116] Figure 6 The right half shows the statistical waste of memory space. The solid line represents the amount of memory allocated to the communication subsystem, denoted as C1, and the dotted line represents the amount of memory actually used by the communication subsystem, denoted as C2. Figure 6 It can be seen that between time t1 and t2, the amount of memory C2 actually used by the communication subsystem is always less than the amount of memory C1 fixedly allocated to the communication subsystem. The difference between C1 and C2 represents the amount of memory that is not fully utilized. And, statistically speaking, the degree of waste of memory space is proportional to the size of the memory space fixedly allocated to the communication subsystem.

[0117] Taking mobile phones as an example, the peak mobile data rate of 4G networks can reach 1.2 Gigabits per second (Gbps). In order to store this mobile data, at least 150MB of memory space is required. For mobile phones that support 4G networks, it may not be a big problem to allocate 150MB of memory space for the 4G communication subsystem. However, the peak mobile data rate of 5G networks can reach 10Gbps. In order to store so much mobile data, at least 1.25GB of memory space is required. Therefore, allocating 1.25GB of memory space for the 5G communication subsystem will significantly increase the demand for the memory capacity of the mobile phone, thereby increasing the memory cost.

[0118] In addition, when the communication subsystem receives a large amount of application data (such as voice, video, text, etc.), the communication subsystem needs to pass this application data to the application subsystem. From a memory perspective, the application data temporarily stored in the memory space corresponding to the communication subsystem needs to be moved or copied to the memory space corresponding to the application subsystem. These move or copy operations will bring a large amount of memory access overhead, increase system power consumption and service latency. In some cases, when the amount of application data to be transmitted is too large, a large amount of memory access overhead may exceed the maximum memory access bandwidth, resulting in the failure of wireless communication services.

[0119] Figure 7 A schematic diagram of the structure of another wireless communication device provided in an embodiment of the present application. Figure 5 Based on the wireless communication device shown, a memory management accelerator (MMA) is shown, wherein the memory management accelerator is used to provide memory management operations for the communication subsystem, and can partially replace the memory management function of the operating system (communication operating system or main operating system).

[0120] like Figure 7 As shown, the wireless communication device includes an application subsystem 701, a memory 702, a communication subsystem 703 and a memory management accelerator 704 connected through an interconnect bus. The application subsystem 701 can be used to run the main operating system, manage the software and hardware resources of the wireless communication device, and especially manage the memory space of the application subsystem. The communication subsystem can run the communication operating system and communication function software, manage the software and hardware resources of the communication subsystem, and especially manage the memory space of the communication subsystem. Figure 7 In the example, the processing core of the application subsystem 701 is recorded as ACore, and the processing core of the communication subsystem 703 is recorded as CCore. It should be understood that Figure 7The application subsystem 701, memory 702 and communication subsystem 703 (including RF, HAC and BBP) correspond to Figure 5 The application subsystem 501, memory 502 and communication subsystem 503 shown in the figure can be referred to the above description for relevant details, and the repeated contents will not be repeated.

[0121] In an embodiment of the present application, the memory management accelerator is a hardware accelerator, which includes hardware components but may also include software components. The hardware components and software components may together constitute a memory management accelerator subsystem, referred to as a memory management accelerator or MMA subsystem. Among them, the hardware components of the memory management accelerator include processing devices for calculations, such as one or more of ASICs, FPGAs, or processing cores, and the hardware components of the memory management accelerator may also include memories, such as registers, caches, tightly coupled memories (TCM), etc. The software components of the memory management accelerator can be used to adapt the hardware components of the memory management accelerator, work in conjunction with the hardware components, and jointly provide memory management operations for the communication subsystem.

[0122] Therefore, in the embodiment of the present application, the memory management accelerator can be a separate hardware component or a combination of a hardware component and a software component. In addition, the hardware component of the memory management accelerator can be a newly added hardware component in the wireless communication device, and the processing pressure of the original components in the wireless communication device should not be increased as much as possible. The hardware component of the memory management accelerator can also reuse the original hardware component in the wireless communication device, and realize the function of the memory management accelerator provided in the embodiment of the present application by upgrading the software component. The memory management accelerator can be either a separate IC chip or integrated in a communication chip or an SoC chip.

[0123] Memory management accelerator can also have other names, such as: memory management hardware accelerator (MMHA or MMHAC), memory accelerator (MA), memory hardware accelerator (MHA or MHAC), memory acceleration engine (MAE), memory allocation accelerator (MAA), memory allocation hardware accelerator (MAHA or MAHAC), memory access accelerator (MAA) or memory access hardware accelerator (MAHA or MAHAC), etc.

[0124] It should be understood that the memory management accelerator can also be applied to other computer systems to provide memory management operations for other subsystems of the computer system to obtain the same or similar technical effects. The following will take the memory management accelerator used to provide memory management operations for the communication subsystem as an example to further introduce the memory management solution provided in the embodiment of the present application.

[0125] based on Figure 7 The MMA subsystem 704 shown, the embodiment of the present application also provides two memory management mechanisms. Among them, the first memory management mechanism mainly involves the interaction between the MMA subsystem and the application subsystem, and can be used to allocate a part of the memory space for the communication subsystem from the memory space managed by the application subsystem, which can be recorded as S1. The second memory management mechanism mainly involves the interaction between the MMA subsystem and the communication subsystem, and can be used to allocate part of the memory space for some components of the communication subsystem (such as CCore, etc.) from the memory space S1, which can be recorded as S2. The following will further introduce the two memory management mechanisms provided in the embodiment of the present application in conjunction with the accompanying drawings.

[0126] Figure 8 A schematic diagram of an interactive framework of a memory management solution provided in an embodiment of the present application. Figure 8 In the figure, ACore represents the application subsystem running the main operating system, MMA represents the MMA subsystem, and CCore represents the components of the communication subsystem. The interaction between ACore and MMA is recorded as 1st MMS, i.e. the first memory management mechanism. The interaction between MMA and CCore is recorded as 2nd MMS, i.e. the second memory management mechanism.

[0127] In the first memory management mechanism, the MMA subsystem can first interact with the application subsystem to obtain the memory space S1 allocated by the main operating system for the communication subsystem. This process can be recorded as "pre-allocation S1". Among them, the size of the memory space S1 allocated by the main operating system for the communication subsystem can be dynamically adjusted, and there is no need to refer to the peak rate of wireless communication to fix the division or statically reserve more memory space. In order to ensure that the size of the available memory space of the communication subsystem is appropriate, the MMA subsystem can monitor the available memory in the memory space S1, and then interact with the application subsystem to adjust the size of the memory space S1 accordingly. This process can be recorded as "update S1". For example, when the wireless communication data rate is high, the MMA subsystem can find that the available memory in the memory space S1 is insufficient, and can send an application to the main operating system so that the main operating system allocates more memory and increases the size of the memory space S1. In addition, when the wireless communication data rate is low, the MMA subsystem can find that there is too much available memory in the memory space S1, and can notify the main operating system so that the main operating system can recycle excess memory and reduce the size of the memory space S1.

[0128] Therefore, by adopting the first memory management mechanism, the MMA subsystem can dynamically adjust the size of the memory space allocated by the main operating system to the communication subsystem, thereby avoiding the waste of memory space. In addition, since the memory space is dynamically allocated by the main operating system, the application data (such as voice, video, text, etc.) stored in the memory space by the communication subsystem can be accessed by the application subsystem without additional moving or copying operations, thus saving a lot of unnecessary memory access overhead, thereby reducing system power consumption and service delay.

[0129] In the second memory management mechanism, the MMA subsystem can interact with the communication subsystem and allocate the required memory space to the communication subsystem in real time. "Real time" here can be understood as the latency of memory allocation can meet the actual needs of the business. In order to ensure that the memory needs of the communication subsystem can be met in a timely manner, in an optional implementation, the memory management accelerator can pre-allocate part of the memory space S2 from the memory space S1 for some components of the communication subsystem (such as CCore). This process can be recorded as "pre-allocating S2". The capacity of this part of the memory space S2 does not exceed the capacity of the memory space S1, and is pre-allocated by the MMA subsystem to some components of the communication subsystem for these components to use as needed. In another optional implementation, the memory management accelerator can provide a hardware access mechanism to some components of the communication subsystem (such as BBP), so that these components can directly obtain the memory corresponding to S1 by accessing the MMA hardware. Therefore, when these components in the communication subsystem need to use memory, they can give priority to using this part of memory space S2, or obtain the memory corresponding to S1 through MMA hardware access without applying to the communication operating system, thereby speeding up the memory allocation speed of the communication subsystem.

[0130] In addition, in order to ensure that the available memory in the memory space S2 pre-allocated to the communication subsystem is sufficient, the MMA subsystem can monitor the available memory in the memory space S2 and interact with the components of the communication subsystem to replenish the available memory in the memory space S2 in a timely manner. This process can be recorded as "updating S2". For example, when the memory management accelerator finds that the available memory in the memory space S2 is insufficient, the memory management accelerator can add some more available memory from the memory space S1 to the communication subsystem to increase the available memory in the memory space S2. In addition, when the memory management accelerator finds that the available memory in the memory space S2 is sufficient, the memory management accelerator can also temporarily postpone replenishing the available memory for the communication subsystem.

[0131] For a component of the communication subsystem, even if the memory space S2 pre-allocated to the component is small, as long as the frequency of updating S2 is high enough and there is always available memory in the memory space S2, the memory usage requirements of the component can be met. For example, assuming that the peak memory access bandwidth of a component of the communication subsystem is 10GB per second, and the memory space S2 pre-allocated to the component is 1MB, then the peak memory access bandwidth rate of 10GB per second of the component can be basically met by only ensuring that the frequency of updating S2 is greater than 10 times per millisecond.

[0132] Fig. 9 Another memory allocation diagram of a wireless communication device provided in an embodiment of the present application. The wireless communication device may be Figure 7For the wireless communication device shown, the memory partition diagram can be used to represent the memory allocation situation when the wireless communication device adopts the above two memory management mechanisms.

[0133] and Figure 6 Similar, in Fig. 9 In the left half, the total memory of the wireless communication device is also fixedly divided into three parts, which are recorded as "others", "application subsystems" and "communication subsystems" from top to bottom. Among them, "others" also means that this part of the memory space has other uses, such as being reserved for other subsystems. "Application subsystem" also means that this part of the memory space is fixedly allocated to the application subsystem for use, recorded as A1'. "Communication subsystem" also means that this part of the memory space is fixedly allocated to the communication subsystem for use, recorded as C1'.

[0134] Compare Figure 6 and Fig. 9 It can be seen that Fig. 9 The size of the memory space C1' allocated to the "communication subsystem" is Figure 6 The size of the memory space C1 allocated to the "communication subsystem" is not the same. In addition, Fig. 9 The memory space A1' of the "application subsystem" is further subdivided into a piece of memory space, which is recorded as "dynamically allocated" S1. As the name implies, the size of the "dynamically allocated" memory space S1 can be adjusted dynamically. The "dynamically allocated" memory space S1 can be used to represent the memory space S1 allocated by the main operating system to the communication subsystem in the first memory management mechanism mentioned above. In addition, in the memory space S1, a part of the memory space S2 is also shown, which is used to represent the part of the memory space S2 pre-allocated to the components of the communication subsystem in the second memory management mechanism mentioned above.

[0135] Since the dynamically allocated memory space S1 and the fixedly allocated memory space C1' are both used by the communication subsystem, Fig. 9 The fixed memory space C1' can be significantly smaller than Figure 6 In addition, since the size of memory space S1 can be adjusted dynamically, when the wireless communication data rate is low, the size of memory space S1 can be reduced accordingly. From a statistical point of view, the sum of the memory capacity of S1 and C1' will still be less than Figure 6 C1 of the fixed divided memory space can thus improve the waste of memory space.

[0136] Fig. 9 The right half shows the improvement of this memory space waste. Figure 6The amount of memory originally fixedly allocated to the communication subsystem shown in is still recorded as C1. The thin dotted line represents the amount of memory actually used by the communication subsystem, which is still recorded as C2. The thick solid line represents the memory capacity S1 dynamically allocated to the communication subsystem when the first memory management mechanism mentioned above is adopted. The dotted line represents the memory capacity C1' fixedly allocated to the communication subsystem when the first memory management mechanism mentioned above is adopted. Fig. 9 It can be seen that between time t1' and t2', the memory capacity S1 dynamically allocated to the communication subsystem can be dynamically adjusted as the memory capacity C2 actually used by the communication subsystem changes. In addition, the sum of the memory capacity S1 dynamically allocated to the communication subsystem and the memory capacity C1' fixedly allocated to the communication subsystem at this time is less than the fixed memory capacity C1 in most cases.

[0137] It should be understood that in the embodiment of the present application, the MMA subsystem can simultaneously adopt the above two memory management mechanisms to form a two-level memory management scheme, wherein the first-level memory management scheme adopts the above first memory management mechanism, and the second-level memory management scheme adopts the above second memory management mechanism.

[0138] In addition, the MMA subsystem may also adopt only one of the memory management mechanisms. In an optional implementation, the MMA subsystem uses the first memory management mechanism to interact with the application subsystem, and can adjust the size of the dynamic memory space S1. This part of the memory space can be allocated in the communication subsystem by the communication operating system. Using this optional implementation method, the memory capacity overhead, system power consumption and service delay of the communication subsystem can also be reduced. In another optional implementation, the MMA subsystem can also manage the memory space statically reserved or fixedly allocated to the communication subsystem, and use the second memory management mechanism to partially replace the memory management function of the communication operating system. The MMA subsystem pre-allocates part of the memory to the components of the communication subsystem, or the MMA hardware replaces the communication operating system software to perform memory allocation, which can also speed up the memory allocation speed of the communication subsystem.

[0139] Fig.10 A schematic diagram of the structure of another wireless communication device provided in an embodiment of the present application. The wireless communication device is Figure 7 Based on the memory management accelerator in the wireless communication device shown, some optional implementation methods of the embodiment of the present application are further introduced. The relevant details can refer to the above description, and the repeated content will not be repeated.

[0140] like Fig.10As shown, MMA hardware (HW) 1004, together with multiple MMA drivers distributed in the application subsystem 1001 and the communication subsystem 1003, constitute an MMA subsystem. It should be understood that for the purpose of simplicity, the MMA driver is not shown in the MMA hardware 1004. In the embodiment of the present application, the MMA hardware can still have MMA drivers and high-level software that enable the MMA hardware to work. These MMA drivers can be used to cooperate with the MMA hardware to implement the memory management solution provided in the embodiment of the present application, especially the memory management method.

[0141] ACore of application subsystem 1001, CCore of communication subsystem 1003 and HAC all show high level software (HL SW) and MMA driver. MMA driver can be considered as a kind of low-level software or underlying software, which can provide an interface for high-level software to interact with underlying hardware. It should be understood that high-level software and MMA driver in ACore, CCore and HAC can be different. For example, the high-level software in ACore can represent the main operating system and various application programs running in ACore, the high-level software in CCore can represent the communication operating system and communication function software program running in CCore, and the high-level software in HAC can represent the software program running in the hardware accelerator. The MMA driver in ACore of application subsystem 1001 can provide an interface for the high-level software of the application subsystem to interact with MMA hardware. Similarly, the MMA driver in CCore and HAC of communication subsystem 1003 can provide an interface for the high-level software of each to interact with MMA hardware. These MMA drivers may not be exactly the same.

[0142] The main operating system running in the ACore of the application subsystem 1001, such as the Android operating system or the Apple operating system, can dynamically allocate a portion of memory space from the memory space managed by the application subsystem to the communication subsystem 1003, which is recorded as S1. This portion of memory space S1 is managed by the MMA subsystem. Accordingly, as an implementation method, the MMA driver in the ACore can include a prestore module for pre-storing memory to the MMA subsystem, and a reclaim module for reclaiming memory from the MMA subsystem.

[0143] In an embodiment of the present application, a memory space can be identified by a memory address. In addition, there may be multiple memory addresses corresponding to the memory space, and each memory address may correspond to a portion of the memory space in the memory space. Among them, a memory address may represent a single-byte or multi-byte memory space. The memory address may be the memory address corresponding to the first byte in a multi-byte memory space. The specific number of multi-bytes may be determined by other parameters, such as the level or type of the memory address. The memory space corresponding to the memory address may be uniquely determined by the starting address of the memory space and the length of the memory space. In addition, a memory space may be determined without the aid of other parameters. Assume that the memory space size corresponding to some memory addresses is set to a certain number of bytes by default, such as 128 bytes. Then each of these memory addresses can uniquely determine a 128-byte memory space.

[0144] In a computer system, memory can be organized into an array based on bytes. Each byte of memory can have a unique corresponding physical address (PA). Naturally, one way to access memory is to use the physical address directly, which is called physical addressing. In addition, memory can also be accessed using virtual addressing. When using virtual addressing, each byte of memory can have a virtual address (VA) corresponding to the physical address. When using a virtual address to access memory, this virtual address will be converted into the corresponding physical address before being sent to the memory. The task of converting a virtual address to a physical address is called address translation.

[0145] At present, computer systems usually use hardware called memory management unit (MMU) and data structure called page table to implement address translation function. Among them, MMU is sometimes called paged memory management unit (PMMU), which is hardware used to process virtual address and physical address conversion. Page table, sometimes called paging table, is a data structure used to represent the mapping relationship or correspondence between virtual address and physical address.

[0146] It should be understood that in the embodiments of the present application, the memory space can be either a physically continuous section of memory space in the memory or a physically discontinuous section of memory space in the memory. The memory address can be either a physical address of the memory or a virtual address of the memory. When the memory address is a virtual address of the memory, the wireless communication device in the embodiments of the present application may also include hardware components and software components for implementing address translation functions, such as MMU and page tables. Accordingly, these hardware components and software components for implementing address translation functions may also cooperate with the memory management accelerator provided in the embodiments of the present application to provide an address translation function for the memory management accelerator.

[0147] In a computer system, the term pointer is usually used to represent a memory address. In the context of computer science, a pointer can be understood as an object or variable in a programming language, which is used to represent or store a memory address. The value of a pointer is the memory address, which is equivalent to the pointer pointing to a specific location in the memory. The part of the memory space corresponding to the memory address represented by the pointer can be used to store application data such as video and text. The embodiments of the present application use the terms "pointer" or "memory pointer" indiscriminately to represent the memory addresses involved in the memory management solution provided in the embodiments of the present application.

[0148] In the embodiment of the present application, the memory pointer can have a variety of different types (type) or levels (level). Among them, the pointers of the same type or the same level correspond to the memory space of the same size or the same granularity, and the pointers of different types or different levels correspond to the memory space of different sizes or different granularities. For example, the memory pointer can have 3 levels, the memory pointer of the first level corresponds to the memory space of 256 bytes in memory size, the memory pointer of the second level corresponds to the memory space of 512 bytes in memory size, and the memory pointer of the third level corresponds to the memory space of 1024 bytes in memory size. Among them, the memory pointer of each level (such as the first level) can only store the memory address of the starting byte in the corresponding memory space (such as 256 bytes). The memory address of the starting byte, combined with the memory size corresponding to the memory pointer level, can uniquely determine this memory space. Storing only the memory address of the starting byte in the memory pointer is conducive to reducing the size of the memory pointer, thereby saving the storage space required for storing the memory pointer. It should be understood that this is only an example, and the memory pointer in the embodiment of the present application may also have other possible implementation methods, such as adjusting the number of levels of memory pointers, adjusting the memory size corresponding to the levels of memory pointers, or adjusting the memory address stored in the memory pointer.

[0149] Based on the concept of memory pointers, the main operating system running in the ACore of the application subsystem 1001 can first pre-store some memory pointers for the MMA subsystem, and then supplement or recycle some memory pointers accordingly according to the notification or request of the MMA subsystem, such as an interrupt request (IRQ). The interrupt request can be either a hardware interrupt request or a software interrupt request. The main operating system supplements some memory pointers, which means that the main operating system sends some more memory pointers to the MMA subsystem to increase the size of the memory space that can be used by the communication subsystem. The main operating system recycles some memory pointers, which means that the main operating system receives some memory pointers from the MMA subsystem. The memory space corresponding to these memory pointers recovered from the MMA subsystem can be reallocated by the main operating system, such as to other subsystems or applications, and of course, it can also be reallocated to the communication subsystem.

[0150] For ease of description, the memory pointers pre-stored and supplemented by the main operating system for the MMA subsystem can be recorded as pointer group 1, and pointer group 1 can correspond to the memory space S1 dynamically allocated by the aforementioned main operating system for the communication subsystem. Among them, pointer group 1 can include a variety of different levels of memory pointers, and each level of memory pointer can have multiple, and each memory pointer is used to represent a section of memory space in memory space S1. As an example, pointer group 1 can include one or more levels of memory pointers corresponding to 64 bytes (abbreviated as B), 128B, 256B, 512B, 1024B (abbreviated as 1KB), 2KB, 4KB, 8KB or 16KB. It should be understood that the use of memory pointers of different levels is conducive to providing memory of different granularities more timely and accurately to meet the needs of the communication subsystem.

[0151] As an optional implementation, pointer group 1 can be stored in the memory 1002 of the wireless communication device, and the MMA subsystem is connected to the memory 1002 via an interconnect bus. As another optional implementation, pointer group 1 can also be stored in the built-in memory of the MMA subsystem, and these built-in memories can be memories built into the MMA hardware such as TCM or registers. In comparison, the former optional implementation can save the overhead of the built-in memory in the MMA subsystem; the latter optional implementation can further improve the management capability of the MMA subsystem for pointer group 1, thereby accelerating the memory allocation rate.

[0152] The MMA subsystem can record some memory pointers in pointer group 1 as pointer subgroup 11, and send or push them in advance to some components of the communication subsystem 1003. Pointer group 11 can correspond to the memory space S2 pre-allocated by the aforementioned MMA subsystem for some components of the communication subsystem. These components can be recorded as communication components CC1, such as CCore and HAC. When there is a need to use memory, the communication component CC1 can directly use the memory corresponding to pointer subgroup 11 without having to apply for memory from the communication operating system, thereby speeding up the memory allocation. Correspondingly, these components of the communication subsystem 1003 (such as CCore and HAC) can also be provided with a memory, such as TCM or register, to store this part of the memory pointer pushed by the MMA subsystem. The MMA drivers of these components of the communication subsystem 1003 (such as CCore and HAC) can respectively maintain the memory pointers in their respective built-in memories, and are responsible for providing the memory required for various data processing to their respective high-level software.

[0153] Of course, the MMA hardware can still retain some memory pointers in the pointer group 1, which are recorded as pointer subgroup 12. The pointer subgroup 12 can be stored in the memory of the MMA hardware, such as the TCM or register of the MMA hardware, and does not need to be sent or pushed to the communication subsystem 1003 in advance. Other components of the communication subsystem 1003 can be recorded as communication components CC2 (such as BBP). When there is a need to use memory, the communication component CC2 can access the MMA hardware, such as the TCM or register of the MMA hardware, to obtain the memory pointer in the pointer subgroup 12. Since these components of the communication subsystem 1003 obtain memory by accessing the MMA hardware, there is no need to apply for memory through the communication operating system, so the speed of memory allocation can also be accelerated. Correspondingly, these components of the communication subsystem 1003 (such as BBP) and the internal of the MMA hardware can also be respectively set with relevant communication interface circuits, registers and software components, etc., to support the needs of these components of the communication subsystem 1003 to access the MMA hardware.

[0154] It should be understood that the maintenance of these memory pointers by the MMA subsystem can speed up the rate at which the components of the communication subsystem obtain memory allocation. Both the communication component CC1 that obtains the memory pointer in advance and the communication component CC2 that obtains the memory pointer by accessing the MMA hardware can benefit from the operation of the MMA subsystem to maintain the memory pointer. Therefore, in the embodiment of the present application, the MMA subsystem manages the dynamic memory space allocated by the main operating system to the communication subsystem, partially replacing the memory management function of the main operating system or the communication operating system, which can speed up the memory allocation rate and better meet the low latency requirements of the wireless communication service, thereby improving the performance of the wireless communication device.

[0155] After the above-mentioned memory pointers are used by the components of the communication subsystem, these used memory pointers can continue to remain in the original pointer group or pointer subgroup, or can be included in a new pointer group or pointer subgroup. For example, after a memory pointer in pointer subgroup 11 is used, the memory pointer can continue to remain in pointer subgroup 11. Alternatively, the memory pointer can be included in a new pointer subgroup, for example, recorded as pointer subgroup 21. Among them, the memory pointers in pointer subgroup 11 can be recorded as allocated for use. These memory pointers have been allocated to the components of the communication subsystem and are available for use by the components inside the components of the communication subsystem. The memory pointers in pointer subgroup 21 can be recorded as used for release. These memory pointers have been used by the components of the communication subsystem and can be released by the components and recovered from the components by the MMA subsystem.

[0156] Similarly, the memory pointers recovered from the components of the communication subsystem to the MMA subsystem can be retained in the original pointer group or assigned to a new pointer group, for example, recorded as pointer group 2. Among them, the memory pointers in pointer group 1 can be recorded as preliminarily allocated and awaiting final allocation. These memory pointers have been preliminarily allocated to the MMA subsystem by the main operating system, and will be finally allocated to the components of the communication subsystem by the MMA subsystem. The memory pointers in pointer group 2 can be recorded as preliminarily recovered and awaiting final recovery. These memory pointers have been preliminarily recovered from the components of the communication subsystem to the MMA subsystem, and can be finally recovered from the MMA subsystem by the main operating system.

[0157] In comparison, if the memory pointers used by the components of the communication subsystem are classified into a new pointer subgroup or a new pointer group outside the original pointer subgroup or pointer group, it is beneficial to speed up the memory recovery rate and reduce the memory capacity overhead. If the memory pointers used by the components of the communication subsystem are retained in the original pointer subgroup or pointer group, it is beneficial to reduce the computational overhead required for memory recovery and memory reallocation.

[0158] It should be understood that in the embodiments of the present application, for ease of expression, the set of memory pointers allocated or recovered within the scope of the MMA subsystem is recorded as a pointer group, and the set of memory pointers allocated or recovered within the scope of the components of the communication subsystem is recorded as a pointer subgroup. Pointer groups or pointer subgroups may also have other names. For example, pointer groups are also referred to as pointer sets, pointer resource pools, pointer resource large pools, memory pointer large sets, etc. Pointer subgroups are also referred to as pointer subsets, pointer resource subpools, pointer resource small pools, memory pointer small sets, etc.

[0159] In the embodiment of the present application, the storage and management of memory pointers have a direct impact on the effect of the memory management scheme. The number of memory pointers in a pointer group is generally greater than the number of memory pointers in a pointer subgroup. Accordingly, the capacity requirement of the memory used to store the pointer group is generally greater than the capacity requirement of the memory used to store the pointer subgroup. The following will further introduce the storage and management scheme of the memory pointer provided in the embodiment of the present application in conjunction with the accompanying drawings.

[0160] In an optional implementation, the memory used to store the memory pointers in the pointer group may be a built-in memory of the MMA subsystem, such as a TCM or register of the MMA hardware. Specifically, all memory pointers of the pointer group may be stored in the built-in memory of the MMA subsystem.

[0161] In another optional implementation, the memory used to store the memory pointers in the pointer group may be a next-level memory of the MMA subsystem, such as the memory of a wireless communication device. All memory pointers of the pointer group may be stored in the memory. The built-in memory of the MMA subsystem does not need to store all memory pointers of the pointer group. The built-in memory of the MMA subsystem may be used to store status information of the pointer group. For example, this status information may be used to indicate the empty or full status of the pointer group, or may be used to indicate the position of the memory pointer in the pointer group, etc. In addition, the built-in memory of the MMA subsystem may also store a small number of memory pointers in the pointer group.

[0162] In comparison, the former optional implementation method can speed up the memory allocation rate because the memory pointer is directly stored in the built-in memory of the MAA subsystem, such as TCM or register, without considering the conflict and overhead of memory access. Considering that the unit capacity cost of TCM or register is relatively high, the latter optional implementation method can enable the MMA subsystem to use a relatively small capacity TCM or register, thereby reducing the cost of the MMA subsystem.

[0163] On this basis, considering that the storage capacity requirement of the pointer subgroup is relatively small, all memory pointers in the pointer subgroup can be stored in the built-in memory of the components of the communication subsystem, such as TCM or registers. However, all memory pointers in the pointer subgroup can also be stored in the built-in memory of the MMA system or the memory of the wireless communication device. The built-in memory of the components of the communication subsystem can be used to store the status information of the pointer subgroup. For example, this status information can be used to indicate the empty and full status of the pointer subgroup, and can also be used to indicate the position of the memory pointer in the pointer subgroup. In addition, the built-in memory of the components of the communication subsystem can also store a small number of memory pointers in the pointer group.

[0164] As an optional implementation, when the memory pointers of the pointer group and the pointer subgroup are specifically stored in the memory, a cyclic buffer data structure can be selected. A cyclic buffer, also known as a circular buffer, a circular queue, a cyclic buffer or a ring buffer, is a data structure used to represent a fixed-size, head-to-tail connected buffer, suitable for caching data streams. Generally, a circular buffer requires four pointers: the actual start position in the memory; the actual end position in the memory, which can also be replaced by the buffer length; the start position of the valid data stored in the buffer (read pointer); the end position of the valid data stored in the buffer (write pointer). In this case, the read pointer and write pointer of the circular buffer can be used to indicate the empty and full status of the pointer group or pointer subgroup, as well as the position of the available memory pointer.

[0165] It should be understood that in the embodiment of the present application, storing the status information of a pointer group or a pointer subgroup does not conflict with storing all the memory pointers of a pointer group or a pointer subgroup, and the two can be combined with each other. Even if all the memory pointers of a pointer group or a pointer subgroup are stored in a memory, the memory can still store the status information of the pointer group or the pointer subgroup. Moreover, even if a memory does not store the memory pointers in a pointer group or a pointer subgroup, the memory can still store the status information of the pointer group or the pointer subgroup. For example, the built-in memory of the MMA system can also be used to store the status information of one or more pointer subgroups so as to timely discover the empty and full status of the pointer subgroup. When the MMA subsystem finds that a certain pointer subgroup (such as pointer subgroup 12) is in the "empty" state, the MMA subsystem can promptly add memory pointers to the pointer subgroup. When the MMA subsystem finds that a certain pointer subgroup (such as pointer subgroup 21) is in the "full" state, the MMA subsystem can promptly recycle the memory pointer from the pointer subgroup.

[0166] Fig.11 A schematic diagram of a memory pointer storage provided in an embodiment of the present application. The wireless communication device may be Figure 7 or Fig.10 The wireless communication device shown. The wireless communication device can use the above-mentioned first optional implementation method to store the memory pointer in the pointer group. Fig.11As shown, the pointer group is stored in the MMA hardware, and the pointer subgroup is stored in the component of the communication subsystem (taking CCore as an example). The pointer group can be the pointer group 1 in the above embodiment, can be the pointer group 2, or can be the pointer group 1 and the pointer group 2. The pointer subgroup can be the pointer subgroup 11 in the above embodiment, can be the pointer subgroup 21, or can be the pointer subgroup 11 and the pointer subgroup 21.

[0167] Fig.11 In the figure, the dotted box in the MMA hardware is used to represent the memory pointer in the pointer group, which may correspond to the TCM or register or other on-chip storage device in the MMA hardware. The pointer group may include memory pointers of different levels. Fig.11 The pointer group shown in the figure includes memory pointers of various levels corresponding to memory sizes of 64B, 128B, 256B, 512B, 1KB and 2KB. Two registers are also shown in the MMA hardware, which are denoted as R1 and R2. R1 and R2 can represent partial registers of multiple registers in the MMA hardware. Among them, R1 can be used to store the status information of the pointer group, and R2 can be used to store the status information of the pointer subgroup. In addition, high-level software and MMA drivers are also shown in the MMA hardware. The high-level software and MMA drivers in the MMA hardware can be used to manage the memory pointers in the pointer group, for example, to monitor the empty and full status of the pointer group and the pointer subgroup, and to replenish or recycle the memory pointer in time.

[0168] The dotted box in CCore is used to represent the memory pointer in the pointer subgroup, which can correspond to the TCM or register or other on-chip storage device in CCore. Among them, the pointer subgroup can also include multiple different levels of memory pointers. Fig.11 It is shown in the figure that the pointer subgroup includes multiple levels of memory pointers corresponding to memory sizes of 64B, 128B and 256B respectively. A register is also shown in CCore, denoted as R0. R0 can represent part of the multiple registers in CCore. Among them, R0 can also be used to store the status information of the pointer subgroup. In addition, high-level software and MMA drivers are also shown in CCore. The high-level software and MMA drivers in CCore can be used to manage the memory pointers in the pointer subgroup, for example, use the memory pointer according to the memory requirements of the software and hardware of CCore, monitor the empty and full status of the pointer subgroup, and promptly notify the MMA subsystem to replenish or recycle the memory pointer.

[0169] Fig.12 A schematic diagram of another memory pointer storage provided in an embodiment of the present application. The wireless communication device may also be Figure 7 or Fig.10 The wireless communication device shown in FIG. The wireless communication device may adopt the latter optional implementation method to store the memory pointer in the pointer group. Fig.12 As shown, the pointer group is stored in the memory, and the pointer subgroup is stored in the component of the communication subsystem (taking HAC as an example). The pointer group can be the pointer group 1 in the above embodiment, can be the pointer group 2, or can be the pointer group 1 and the pointer group 2. The pointer subgroup can be the pointer subgroup 11 in the above embodiment, can be the pointer subgroup 21, or can be the pointer subgroup 11 and the pointer subgroup 21.

[0170] Fig.12 In the example, the dotted box in the memory is used to represent the memory pointer in the pointer group. The pointer group may include memory pointers of different levels. Fig.12 It is shown in the figure that the pointer group includes memory pointers of various levels corresponding to memory sizes of 128B, 256B, 512B, 1KB, 2KB and 4KB respectively.

[0171] The dotted box in HAC is used to represent the memory pointer in the pointer subgroup. Among them, the pointer subgroup can also include multiple different levels of memory pointers. Fig.12 It is shown that the pointer subgroup includes multiple levels of memory pointers corresponding to memory sizes of 512B, 1KB and 2KB respectively. A register is also shown in HAC, denoted as R3. R3 can represent a part of multiple registers in HAC. Among them, R3 can also be used to store the status information of the pointer subgroup.

[0172] The BBP also shows an MMA driver and a register, denoted as R4. R4 can represent a portion of multiple registers in the BBP. The MMA driver and register R4 can be used to support the BBP to directly access the MMA hardware to obtain the memory pointer in pointer group 1.

[0173] The MMA hardware shows high-level software, MMA driver, TCM and three registers, which are respectively denoted as R5, R6 and R7. R5, R6 and R7 can represent some registers of multiple registers in the MMA hardware. Among them, R5 can be used to store the status information of the pointer group, and R6 can be used to store the status information of the pointer subgroup. R7 can be used to store some status information required for some components of the communication subsystem (such as BBP) to access the MMA hardware. TCM can be used to store a part of the memory pointers of the pointer group stored in the memory, and these memory pointers can correspond to the pointer subgroup 12 in the aforementioned embodiment, which can be obtained by some components of the communication subsystem (such as BBP) by accessing the MMA hardware.

[0174] Based on the computing device, wireless communication device, MMA hardware and MMA driver of the MMA subsystem provided in the aforementioned embodiments, the embodiments of the present application also provide some memory management methods. These memory management methods can be implemented by hardware components, or by software components, or by the cooperation of hardware components and software components. When these memory management methods need to use software components, such as high-level software in MMA hardware, and multiple MMA drivers distributed in the application subsystem, communication subsystem and MMA hardware, these memory management methods can represent the algorithm of the software program, and the steps of the method can respectively represent the functional modules of the algorithm.

[0175] Fig.13 A flow chart of a memory management method provided in an embodiment of the present application. The memory management method can be executed by the MMA subsystem in the aforementioned embodiment. The MMA subsystem is coupled to the application subsystem and the communication subsystem respectively, wherein the application subsystem is used to run the main operating system, and the communication subsystem is used to run the communication operating system. Since the MMA subsystem can be fully or partially integrated in the communication subsystem or the application subsystem, the method can also be considered to be executed by the baseband chip, SoC chip or wireless communication device in the aforementioned embodiment.

[0176] like Fig.13 As shown, the method comprises the following steps:

[0177] S001. Obtain a memory address set corresponding to a dynamic memory space allocated by a main operating system to a communication subsystem; the memory address set includes one or more memory addresses.

[0178] S002. Send some memory addresses in the memory address set to components of the communication subsystem.

[0179] Among them, step S002 may include at least one of the following two optional schemes: periodically sending some memory addresses in the memory address set to the components of the communication subsystem, or sending some memory addresses in the memory address set to the components of the communication subsystem based on the triggering of the first event.

[0180] It should be understood that these two optional solutions do not conflict and can be used in combination. For example, the former periodic sending of memory addresses is used as a regular operation, and the latter event-triggered sending of memory addresses is used as a supplementary operation. The operation is executed first when the condition is met first.

[0181] Specifically, the first event may include one or more of the following events:

[0182] The number of memory addresses in the component of the communication subsystem is lower than a first lower threshold; a first hardware interrupt request of the component of the communication subsystem; and a first software interrupt request of the component of the communication subsystem.

[0183] It should be understood that there may be multiple first hardware interrupt requests, and each first hardware interrupt request has its own hardware interrupt number. Different hardware interrupt numbers may correspond to different operations of the memory management device, such as sending different numbers of memory addresses. Different components of the functional subsystem may correspond to different first memories. Moreover, different first memories may correspond to different first hardware interrupt requests, i.e., have different hardware interrupt numbers. There may also be multiple first software interrupt requests, and each first software interrupt request has its own software interrupt number.

[0184] Fig.14 A flowchart of another memory management method provided in an embodiment of the present application. The memory management method can also be executed collaboratively by the MMA subsystem in the aforementioned embodiment, such as MMA hardware and MMA driver. The memory address is represented by a memory pointer, the above memory address set corresponds to a pointer group, and the part of the memory address sent to the component of the communication subsystem corresponds to a pointer subgroup.

[0185] As shown in the figure, after the MMA subsystem obtains the pointer group from the main operating system, it allocates part of the memory pointers in the pointer group to the pointer subgroup. Thereafter, in order to ensure that the number of memory pointers in the pointer group and the pointer subgroup is appropriate, the MMA subsystem can detect the state of the pointer group and the state of the pointer subgroup respectively. Taking the state of the pointer group and the pointer subgroup as an example, including the "empty" state and the "full" state, when the state of the pointer group is "empty", the MMA subsystem notifies the main operating system to add memory pointers to the pointer group; when the state of the pointer group is "full", the MMA subsystem notifies the main operating system to recycle memory pointers from the pointer group. In addition, when the state of the pointer subgroup is "empty", the MMA subsystem sends a memory pointer from the pointer group to the pointer subgroup; when the state of the pointer subgroup is "full", the MMA subsystem sends a memory pointer from the pointer subgroup to the pointer group.

[0186] It should be understood that in the embodiments of the present application, the "empty" state does not require that the number of memory pointers in a pointer group or a pointer subgroup is 0. The "empty" state may indicate that the number of memory pointers in a pointer group or a pointer subgroup is lower than a certain lower threshold or thresholds. Correspondingly, the "full" state may also indicate that the number of memory pointers in a pointer group or a pointer subgroup is higher than a certain upper threshold or thresholds. Different pointer groups and different pointer subgroups may have their own thresholds, and each pointer group or each pointer subgroup may have multiple thresholds, including multiple upper thresholds and multiple lower thresholds. In addition, it should be understood that the conditions for judging the state of a pointer group (such as an empty state and a full state) (such as a lower threshold and an upper threshold) may not be the same as the conditions for judging the state of a pointer subgroup.

[0187] For example, if the number of memory pointers in a certain pointer group is less than 30%, the pointer group can be considered to be in an "empty" state; if the number of memory pointers in the pointer group is greater than 80%, the pointer group can be considered to be in a "full" state; if the number of memory pointers in the pointer group is between 30% and 80%, the pointer group can be considered to be in other states, such as a "suitable" state. Assuming that the number of memory pointers in a certain pointer subgroup is less than 50%, the pointer subgroup can be considered to be in a "full" state; if the number of memory pointers in the pointer subgroup is greater than 90%, the pointer subgroup can be considered to be in a "full" state; if the number of memory pointers in the pointer subgroup is between 50% and 90%, the pointer subgroup can be considered to be in other states, such as a "suitable" state. It should be understood that the numerical values ​​here are only examples, and the embodiments of the present application may also have other schemes.

[0188] The terms "first", "second", "third", "fourth", etc. in the embodiments of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or precedence. In addition, the terms "including" and "having" and any variations thereof are intended to indicate non-exclusive inclusion, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units listed literally, but may include other steps or units that are not listed literally or inherent to these processes, methods, products or devices.

[0189] It should be understood that in the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0190] It should be understood that in this application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of this application. The term "coupling" mentioned in this application is used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components.

[0191] In the above embodiments of the present application, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, etc.) or wireless (e.g., infrared, radio, microwave, etc.) means to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk and a tape; it may be an optical medium, for example, a DVD; it may also be a semiconductor medium, for example, a solid-state drive (SSD), etc.

[0192] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wireless communication device, characterized in that: include: Application subsystem, used to run the main operating system; A communication subsystem, used to run a communication operating system, wherein the components of the communication subsystem include a first memory; A memory management hardware accelerator is coupled to the application subsystem and the communication subsystem respectively, and is used to: Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set includes one or more memory addresses; Based on the category of the component of the communication subsystem, some memory addresses in the memory address set are sent to the first memory, and the first memory is used to store the memory addresses received from the memory management hardware accelerator.

2. The wireless communication device according to claim 1, wherein: The memory management hardware accelerator is used to: Periodically sending some memory addresses in the memory address set to the first memory.

3. The wireless communication device according to claim 1, wherein: The memory management hardware accelerator is used to: Sending some memory addresses in the memory address set to the first memory based on the triggering of a first event.

4. The wireless communication device according to claim 3, wherein: The first event includes: The number of memory addresses stored in the first memory is lower than a first lower threshold.

5. The wireless communication device according to claim 3, wherein: The first event includes: A first hardware interrupt request from a component of the communication subsystem.

6. The wireless communication device according to any one of claims 1 to 5, characterized in that: The components of the communication subsystem also include a second memory, which is used to store memory addresses received from the memory management hardware accelerator and used by the components of the communication subsystem.

7. The wireless communication device according to claim 6, wherein: The memory management hardware accelerator is further used for: Receive a memory address stored in the second memory based on the triggering of a second event.

8. The wireless communication device according to claim 7, wherein: The second event includes: The number of memory addresses stored in the second memory is higher than a second upper threshold.

9. The wireless communication device according to claim 8, wherein: The second event includes: A second hardware interrupt request from a component of the communication subsystem.

10. The wireless communication device according to any one of claims 1 to 5 and 7 to 9, characterized in that: The memory addresses in the memory address set are stored in the built-in memory of the memory management hardware accelerator.

11. The wireless communication device according to any one of claims 1 to 5 and 7 to 9, characterized in that: The memory address set is stored in a memory connected to the memory management hardware accelerator via an interconnect bus.

12. The wireless communication device according to any one of claims 1 to 5 and 7 to 9, characterized in that: The memory management hardware accelerator is further used for: Detecting status information of the memory address set, where the status information of the memory address set is used to indicate the number of memory addresses in the memory address set.

13. The wireless communication device according to claim 12, wherein: The memory management hardware accelerator is further used for: When it is detected that the number of memory addresses in the memory address set is lower than a third lower threshold, the main operating system is notified to add some memory addresses to the memory address set.

14. The wireless communication device according to claim 12, wherein: The memory management hardware accelerator is further used for: When it is detected that the number of memory addresses in the memory address set is higher than a third upper threshold, the main operating system is notified to reclaim part of the memory addresses from the memory address set.

15. The wireless communication device according to any one of claims 7 to 9, characterized in that: Based on the triggered reception of the second event, the memory address from the second memory is stored in a fourth memory; Wherein, the fourth memory is a built-in memory of the memory management hardware accelerator.

16. The wireless communication device according to claim 15, wherein: The memory management hardware accelerator is further used for: When it is detected that the number of memory addresses in the fourth memory is higher than a fourth upper threshold, the main operating system is notified to reclaim memory addresses from the fourth memory.

17. The wireless communication device according to any one of claims 1 to 5 and 7 to 9, characterized in that: The memory management hardware accelerator is used to: The memory address corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem is periodically obtained, wherein the periodically obtained memory address is also included in the memory address set.

18. The wireless communication device according to claim 17, wherein: A period for obtaining a memory address corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem is greater than a period for sending a portion of the memory addresses in the memory address set to the first memory.

19. The wireless communication device according to any one of claims 1 to 5, 7 to 9, 13 to 14, 16 and 18, characterized in that: The memory addresses corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem are respectively stored in pointers of multiple different levels; Among them, pointers of the same level correspond to memory spaces of the same size, and pointers of different levels correspond to memory spaces of different sizes.

20. The wireless communication device according to any one of claims 1 to 5, 7 to 9, 13 to 14, 16 to 18, characterized in that: The components of the memory management hardware accelerator and the components of the communication subsystem are integrated into the same chip.

21. The wireless communication device according to any one of claims 1 to 5, 7 to 9, 13 to 14, 16 to 18, characterized in that: The components of the communication subsystem include: a processing core of the communication subsystem, a hardware accelerator of the communication subsystem, or one or more components in a baseband processor of the communication subsystem.

22. The wireless communication device according to any one of claims 1 to 5, 7 to 9, 13 to 14, 16 to 18, characterized in that: The wireless communication device is a smart phone.

23. The wireless communication device according to any one of claims 1 to 5, 7 to 9, 13 to 14, 16 and 18, characterized in that: The wireless communication device is a system-on-chip (SoC) of a smart phone.

24. A memory management method, the method being executed by a memory management hardware accelerator, the memory management hardware accelerator being coupled to an application subsystem and a communication subsystem respectively, the application subsystem being used to run a main operating system, the communication subsystem being used to run a communication operating system, the components of the communication subsystem comprising a first memory, characterized in that: The method comprises: Acquire a memory address set corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem, wherein the memory address set includes one or more memory addresses; Based on the category of the component of the communication subsystem, some memory addresses in the memory address set are sent to the component of the communication subsystem, and the first memory is used to store the memory addresses received from the memory management hardware accelerator.

25. The method of claim 24, wherein: The sending of some memory addresses in the memory address set includes: Periodically sending a portion of the memory address set to components of the communication subsystem.

26. The method of claim 24, wherein: The sending of some memory addresses in the memory address set includes: Sending some memory addresses in the memory address set to components of the communication subsystem based on the triggering of a first event.

27. The method of claim 26, wherein: The first event includes: The number of memory addresses in the components of the communication subsystem is below a first lower threshold.

28. The method of claim 26, wherein: The first event includes: A first hardware interrupt request from a component of the communication subsystem.

29. The method according to any one of claims 24 to 28, characterized in that: The method further comprises: Receive a memory address from the memory management hardware accelerator that is used by a component of the communication subsystem and that is used based on a trigger of a second event.

30. The method of claim 29, wherein: The second event includes: The number of memory addresses used by components of the communication subsystem and originating from the memory management hardware accelerator is higher than a second upper threshold.

31. The method of claim 29, wherein: The second event includes: A second hardware interrupt request from a component of the communication subsystem.

32. The method according to any one of claims 24 to 28, 30 to 31, characterized in that: The method further comprises: Detecting status information of the memory address set, where the status information of the memory address set is used to indicate the number of memory addresses in the memory address set.

33. The method of claim 32, wherein: The method further comprises: When it is detected that the number of memory addresses in the memory address set is lower than a third lower threshold, the main operating system is notified to add some memory addresses to the memory address set.

34. The method according to claim 32 or 33, characterized in that: The method further comprises: When it is detected that the number of memory addresses in the memory address set is higher than a third upper threshold, the main operating system is notified to reclaim part of the memory addresses from the memory address set.

35. The method according to any one of claims 24 to 28, 30 to 31, characterized in that: The method further comprises: The memory address corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem is periodically obtained, wherein the periodically obtained memory address is also included in the memory address set.

36. The method of claim 35, wherein: The period of obtaining the memory address corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem is greater than the period of sending some memory addresses in the memory address set to the components of the communication subsystem.

37. The method according to any one of claims 24 to 28, 30 to 31, 33 and 36, characterized in that: The method further comprises: The memory addresses corresponding to the dynamic memory space allocated by the main operating system to the communication subsystem are respectively stored in pointers of multiple different levels; Among them, pointers of the same level correspond to memory spaces of the same size, and pointers of different levels correspond to memory spaces of different sizes.

38. A computer-readable storage medium, characterized in that: Program codes are stored, and when the program codes are executed by a computer or a processor, they are used to implement the method according to any one of claims 24 to 37.

39. A computer program product, characterized in that The method comprises a program code, which, when executed by a computer or a processor, is used to implement the method according to any one of claims 24 to 37.

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