Pixel

Abstract

The present invention discloses a pixel. The pixel includes: a light-emitting element; a first transistor including a first electrode coupled to a power supply and a second electrode coupled to the light-emitting element; a first capacitor between a second node and a third node; a second transistor between the third node and a data line and turned on by a scan signal; a third transistor between the first node and the second node and turned on by a first control signal; a fourth transistor between the power supply or a reference power supply and the third node and turned on by a second control signal; a fifth transistor between the power supply and the first electrode of the first transistor and turned on by an emission control signal; a sixth transistor between the second node and the light-emitting element and turned on by a previous emission control signal; and a second capacitor between the power supply and the first node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0088437, filed on Jul. 22, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device, and more particularly, to a pixel and a display device including the pixel. Background Art

[0004] A display device is an output device for presenting information in a visual form. Generally, a display device includes a plurality of pixels, and each of the pixels emits light based on a data signal supplied to a driving transistor.

[0005] A method for driving a display device at a low frequency (e.g., 1 Hz) can be used to minimize power consumption. However, when a display device is driven at a low frequency, the displayed image may flicker. To prevent image flicker, a technique for minimizing leakage of data signals stored in pixels can be employed.

[0006] In addition to low-frequency driving, the display device can be driven at a high frequency (e.g., 120 Hz) to achieve high-resolution images or stereoscopic images. However, in order to ensure image quality above a certain level when the display device is driven at high speed, sufficient time should be ensured to compensate for the threshold voltage of the drive transistor. Summary of the Invention

[0007] An exemplary embodiment of the present invention provides a pixel, comprising: a light-emitting element; a first transistor configured to control a driving current, the first transistor comprising a first electrode electrically coupled to a first power supply and a second electrode electrically coupled to the light-emitting element; a first capacitor coupled between a second node and a third node, wherein the second node is connected to the second electrode of the first transistor; a second transistor coupled between the third node and a data line and configured to be turned on in response to a scan signal; a third transistor coupled between the first node and the second node and configured to be turned on in response to a first control signal, wherein the first node is connected to a gate electrode of the first transistor; a fourth transistor coupled between the first power supply and the third node and configured to be turned on in response to the second control signal; a fifth transistor coupled between the first power supply and the first electrode of the first transistor and configured to be turned on in response to an emission control signal; a sixth transistor coupled between the second node and the light-emitting element and configured to be turned on in response to a previous emission control signal; and a second capacitor coupled between the first power supply and the first node.

[0008] When the third transistor and the fourth transistor are turned on, the second transistor and the sixth transistor may be turned off.

[0009] The pixel may further include: a seventh transistor coupled between the light emitting element and the initialization power source and configured to be turned on in response to the third control signal.

[0010] The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be P-channel metal oxide semiconductor (PMOS) transistors, and the third transistor and the seventh transistor may be N-channel metal oxide semiconductor (NMOS) transistors.

[0011] The first control signal and the third control signal may be the same signal supplied through the same control line.

[0012] The second control signal may be the same as the transmit control signal.

[0013] The voltage of the initialization power supply can be supplied to the light-emitting element in the first period, the voltage of the initialization power supply can be supplied to the first node in the second period, the first transistor can be diode-coupled based on the voltage of the first power supply in the third period, and the second transistor can be turned on in the fourth period so that the data signal is supplied to the third node through the data line.

[0014] The third transistor may maintain a turned-on state during the first period, the second period, the third period, and the fourth period in response to the first control signal.

[0015] In the first period and the third period, the fifth transistor may be turned on and the sixth transistor may be turned off; and in the second period, the fifth transistor may be turned off and the sixth transistor may be turned on.

[0016] The emission control signal may be shifted by k horizontal periods from the previous emission control signal, where k is an integer greater than or equal to 3.

[0017] In the first period, the sixth transistor may be turned off; and in the second period, the third transistor, the sixth transistor, and the seventh transistor may be turned on.

[0018] The first transistor, the second transistor, the fifth transistor, and the sixth transistor may be PMOS transistors, and the third transistor, the fourth transistor, and the seventh transistor may be NMOS transistors.

[0019] The first control signal and the third control signal may be the same signal supplied through the same control line, and the second control signal may be shifted from the first control signal by k horizontal periods, where k is an integer greater than or equal to 3.

[0020] The emission control signal may be shifted by k horizontal periods from the previous emission control signal, where k is an integer greater than or equal to 3.

[0021] The first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be PMOS transistors, and the third transistor may be an NMOS transistor.

[0022] The second control signal and the third control signal may be the same signal supplied through the same control line.

[0023] The pixel may further include an eighth transistor coupled between the second node and the first capacitor and configured to be turned on in response to the first control signal.

[0024] The pixel may further include an eighth transistor coupled between the second node and the first capacitor and configured to be turned on in response to a scan signal.

[0025] An exemplary embodiment of the present invention provides a display device, comprising: a display panel including a plurality of pixels; a first scan driver configured to supply scan signals to the pixels through a plurality of scan lines; a second scan driver configured to supply control signals to the pixels through a plurality of control lines; an emission driver configured to supply emission control signals to the pixels through a plurality of emission control lines; and a data driver configured to supply data voltages to the display panel through a plurality of data lines, wherein at least one of the pixels comprises: a light emitting element; a first transistor configured to control a drive current, the first transistor comprising a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light emitting element; a first capacitor coupled between a second node and a third node, wherein the second node is connected to the first transistor; a second electrode; a second transistor coupled between the third node and the data line and configured to be turned on by a scan signal; a third transistor coupled between the first node and the second node and configured to be turned on by a control signal, wherein the first node is connected to the gate electrode of the first transistor; a fourth transistor coupled between the first power supply and the third node and configured to be turned on by an emission control signal; a fifth transistor coupled between the first power supply and the first electrode of the first transistor and configured to be turned on by the emission control signal; a sixth transistor coupled between the second node and the light-emitting element and configured to be turned on by a previous emission control signal; a second capacitor coupled between the first power supply and the first node; and a seventh transistor coupled between the light-emitting element and the initialization power supply and configured to be turned on by a control signal.

[0026] An exemplary embodiment of the present invention provides a pixel, comprising: a light-emitting element; a first transistor comprising a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light-emitting element; a second transistor coupled to a data line and configured to be turned on by a scan signal; a first capacitor coupled between the second electrode of the first transistor and the second transistor; a third transistor coupled between the gate electrode of the first transistor and the first capacitor and configured to be turned on by a first control signal; a fourth transistor coupled between the first power source and the first capacitor; a fifth transistor coupled between the first power source and the first electrode of the first transistor and configured to be turned on in response to an emission control signal, wherein the gate electrode of the fifth transistor is connected to the gate electrode of the fourth transistor; a sixth transistor coupled between the first capacitor and the light-emitting element and configured to be turned on by a previous emission control signal; and a second capacitor coupled between the first power source and the gate electrode of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention.

[0028] Figure 2A is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0029] Figure 2B Is used to illustrate Figure 2A A circuit diagram of an example of coupling of a pixel.

[0030] Figure 3A 、 Figure 3B and Figure 3C Is used to illustrate Figure 2A and Figure 2B A timing diagram of an example of pixel operation.

[0031] Figure 4 Is used to illustrate Figure 1 A timing diagram showing an example of the operation of the display device.

[0032] Figure 5 It is an icon Figure 2A A circuit diagram of an example of a pixel.

[0033] Figure 6 is a circuit diagram illustrating an example of a pixel according to an exemplary embodiment of the present invention.

[0034] Figure 7A Is used to illustrate Figure 6 A timing diagram of an example of pixel operation.

[0035] Figure 7B Is used to illustrate Figure 6 A timing diagram of an example of pixel operation.

[0036] Figure 8 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0037] Figure 9 Is used to illustrate Figure 8 A timing diagram of an example of pixel operation.

[0038] Figure 10 It is an icon Figure 2A A circuit diagram of an example of a pixel.

[0039] Figure 11 It is an icon Figure 2A A circuit diagram of an example of a pixel. DETAILED DESCRIPTION

[0040] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar elements may be represented by the same reference numerals, and therefore, repeated description of the same or similar elements may be omitted.

[0041] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention.

[0042] refer to Figure 1 , the display device 1000 may include a display panel 100 , a first scan driver 200 , a second scan driver 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0043] In an exemplary embodiment of the present invention, the display device 1000 may further include a power supply for supplying a voltage of a first power supply VDD, a voltage of a second power supply VSS, and a voltage of a third power supply (or initialization power supply Vint) to the display panel 100. The power supply may supply a voltage of a low power supply or a high power supply to the first scan driver 200, the second scan driver 300, and / or the emission driver 400 to determine a gate-on level or a gate-off level of a scan signal, a control signal, and / or an emission control signal. The low power supply may have a voltage level lower than a voltage level of a high power supply. However, this is merely an example, and at least one of the voltage of the first power supply VDD, the voltage of the second power supply VSS, the voltage of the initialization power supply Vint, the voltage of the low power supply, and the voltage of the high power supply may be supplied from the timing controller 600 or the data driver 500.

[0044] According to an exemplary embodiment of the present invention, a first power supply VDD and a second power supply VSS may generate a voltage for driving a light-emitting element. In an exemplary embodiment of the present invention, the voltage of the second power supply VSS may be lower than the voltage of the first power supply VDD. For example, the voltage of the first power supply VDD may be a positive voltage, and the voltage of the second power supply VSS may be a negative voltage.

[0045] The initialization power supply Vint can be used to initialize the pixel PX. For example, the driving transistor and / or the light emitting element included in the pixel PX can be initialized by the voltage of the initialization power supply Vint. The voltage of the initialization power supply Vint can be a negative voltage.

[0046] The display panel 100 may include a plurality of scan lines SL, a plurality of control lines CL, a plurality of emission control lines EL, and a plurality of data lines DL, and may include a plurality of pixels PX coupled to the scan lines SL, the control lines CL, the emission control lines EL, and the data lines DL. In an exemplary embodiment of the present invention, a pixel PX arranged in an n-th pixel row and an m-th pixel column may be coupled to a scan line SLn corresponding to the n-th pixel row, a control line CLn corresponding to the n-th pixel row, an emission control line ELn corresponding to the n-th pixel row, an emission control line ELn-k corresponding to the n-th pixel row, and a data line DLm corresponding to the m-th pixel column (where n and m are natural numbers, and k is a natural number equal to or less than 10).

[0047] The timing controller 600 may generate a first drive control signal SCS1, a second drive control signal SCS2, a third drive control signal ECS, and a fourth drive control signal DCS in response to a synchronization signal supplied from the outside. The first drive control signal SCS1 may be supplied to the first scan driver 200, the second drive control signal SCS2 may be supplied to the second scan driver 300, the third drive control signal ECS may be supplied to the emission driver 400, and the fourth drive control signal DCS may be supplied to the data driver 500. In addition, the timing controller 600 may rearrange the input image data supplied from the outside to form image data RGB, and may supply the image data RGB to the data driver 500.

[0048] The first driving control signal SCS1 may include a first scanning start pulse and a clock signal. The first scanning start pulse may control a first timing of the scanning signal. The clock signal of the first driving control signal SCS1 may be used to shift the first scanning start pulse.

[0049] The second drive control signal SCS2 may include a second scan start pulse (e.g., a start pulse of the control signal) and a clock signal. The second scan start pulse may control the first timing of the control signal. The clock signal of the second drive control signal SCS2 may be used to shift the second scan start pulse. In an exemplary embodiment of the present invention, the control signal may be a scan signal (e.g., a second scan signal) different from the scan signal (e.g., the first scan signal) output from the first scan driver 200.

[0050] The third drive control signal ECS may include an emission control start pulse and a clock signal. The emission control start pulse may control the first timing of the emission control signal. The clock signal of the third drive control signal ECS may be used to shift the emission control start pulse.

[0051] The fourth drive control signal DCS may include a source start pulse and a clock signal. The source start pulse controls the time when data sampling starts. The clock signal of the fourth drive control signal DCS may be used to control the sampling operation.

[0052] The first scan driver 200 may receive a first drive control signal SCS1 from the timing controller 600 and supply a scan signal to the scan line SL based on the first drive control signal SCS1. For example, the first scan driver 200 may sequentially supply a scan signal (e.g., a first scan signal) to the scan line SL (e.g., a first scan line) at intervals of one horizontal period 1H. When the scan signal is sequentially supplied, the pixel PX is selected in units of horizontal lines (or in units of pixel rows), thereby supplying a data signal to the pixel PX. According to an exemplary embodiment of the present invention, the scan signal may have a pulse width equal to or greater than one horizontal period 1H.

[0053] The scan signal may be set to a gate-on level (eg, a low voltage). When the gate-on level scan signal is supplied, a transistor included in the pixel PX and configured to receive the scan signal may be set to a turned-on state.

[0054] The second scan driver 300 may receive a second drive control signal SCS2 from the timing controller 600 and supply a control signal (e.g., a second scan signal) to the control line CL (e.g., the second scan line) based on the second drive control signal SCS2. For example, the second scan driver 300 may sequentially supply the control signal to the control line CL at intervals longer than one horizontal period 1H (e.g., at intervals of two horizontal periods 2H). When the control signal is supplied from the second scan driver 300, the pixel PX may perform an operation for compensating for a threshold voltage and / or perform an initialization operation.

[0055] In an exemplary embodiment of the present invention, the second scan driver 300 may supply control signals to consecutive pixel rows simultaneously. For example, the second scan driver 300 may supply the same control signal to the nth control line CLn and the n+1th control line CLn+1 simultaneously (see Figure 2B ). In other words, the second scan driver 300 may shift and supply the control signal in units of two or more control lines, and consecutive pixel rows corresponding to the control lines may share the same control signal.

[0056] In this case, the number of stages included in the second scan driver 300 to shift and output the control signal may be less than the number of stages included in the first scan driver 200 .

[0057] However, this is merely an example, and the second scan driver 300 may supply control signals to the pixel rows at different timings.

[0058] The control signal may be set to a gate-on level (eg, a low voltage). When the gate-on level control signal is supplied, a transistor included in the pixel PX and configured to receive the control signal may be set to a turned-on state.

[0059] The emission driver 400 may receive the third driving control signal ECS from the timing controller 600 and supply the emission control signal to the emission control line EL based on the third driving control signal ECS. For example, the emission driver 400 may sequentially supply the emission control signal to the emission control line EL.

[0060] In an exemplary embodiment of the present invention, the emission driver 400 may supply emission control signals to consecutive pixel rows simultaneously. For example, the emission driver 400 may supply the same control signal to the nth emission control line ELn and the n+1th emission control line ELn+1 simultaneously (see FIG. Figure 2B ). In other words, the emission driver 400 may shift and supply the emission control signal in units of two or more emission control lines, and consecutive pixel rows corresponding to the emission control lines may share the same emission control signal.

[0061] In this case, the number of stages included in the emission driver 400 to shift and output the emission control signal may be less than the number of stages included in the first scan driver 200 .

[0062] The emission control signal may be set to a gate-on level (e.g., a low voltage). When the gate-on level emission control signal is supplied, a transistor included in the pixel PX and configured to receive the emission control signal may be turned on. Otherwise, the transistor may be set to an off state.

[0063] The emission control signal is used to control the emission time of the pixel PX. To achieve this, the pulse width of the emission control signal can be set to be greater than the pulse width of the scan signal. In an exemplary embodiment of the present invention, during one frame period, the emission control signal can have multiple periods in which the emission control signal is set to a gate-off level (e.g., a high voltage).

[0064] Each of the first scan driver 200, the second scan driver 300, and the emission driver 400 can be mounted on a substrate using a thin film manufacturing process. Furthermore, each of the first scan driver 200 and the second scan driver 300 can be placed on opposite sides of the display panel 100. The emission driver 400 can also be placed on opposite sides of the display panel 100.

[0065] The data driver 500 may receive a fourth drive control signal DCS and image data RGB from the timing controller 600. The data driver 500 may supply data signals to the data lines DL in response to the fourth drive control signal DCS. The data signals supplied to the data lines DL may be supplied to pixels PX selected based on the scan signals. To achieve this, the data driver 500 may supply data signals to the data lines DL in synchronization with the scan signals.

[0066] Figure 2A is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0067] For ease of description, Figure 2A The pixels 10 arranged in an n-th horizontal line (or an n-th pixel row) and coupled to an m-th data line DLm are illustrated.

[0068] According to an exemplary embodiment of the present invention, the previous emission control line ELn-k may supply the same emission control signal as that supplied to the emission control line coupled to the nk-th pixel row.

[0069] refer to Figure 2A The pixel 10 may include a light emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0070] A first electrode of the light-emitting element LD may be electrically coupled to the second electrode (e.g., drain electrode) of the first transistor T1, and a second electrode of the light-emitting element LD may be coupled to the second power supply VSS. For example, the first electrode of the light-emitting element LD may be coupled to the fourth node N4, and one electrode of the sixth transistor T6 and one electrode of the seventh transistor T7 may be coupled to the fourth node N4.

[0071] The light-emitting element LD can generate light having a predetermined brightness in response to the amount of current (e.g., driving current) supplied from the first transistor T1. In an exemplary embodiment of the present invention, the light-emitting element LD may be an organic light-emitting diode including an organic emission layer. In this case, the first electrode of the light-emitting element LD may be an anode electrode, and the second electrode of the light-emitting element LD may be a cathode electrode. Conversely, the first electrode of the light-emitting element LD may be a cathode electrode, and the second electrode of the light-emitting element LD may be an anode electrode.

[0072] In another exemplary embodiment of the present invention, the light emitting element LD may be an inorganic light emitting element formed of an inorganic material. Alternatively, the light emitting element LD may be formed such that a plurality of inorganic light emitting elements are coupled in parallel and / or in series between the second power supply VSS and the second electrode of the first transistor T1.

[0073] The first transistor T1 may be electrically coupled between a first power supply VDD and a first electrode of the light-emitting element LD. The first transistor T1 may generate a drive current and supply the drive current to the light-emitting element LD. A gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 functions as a drive transistor for the pixel 10. The first transistor T1 may control the amount of current flowing from the first power supply VDD via the light-emitting element LD to the second power supply VSS in response to a voltage applied to the first node N1.

[0074] The first capacitor C1 may be coupled between the third node N3 and the second node N2 corresponding to the second electrode of the first transistor T1. The first capacitor C1 may store a voltage difference between the second node N2 and the third node N3.

[0075] The second capacitor C2 may be coupled between the first power source VDD and the first node N1. The second capacitor C2 may store a voltage difference between the first power source VDD and the first node N1.

[0076] When the data signal of the pixel 10 is written, the first node N1 and the second node N2 may have voltages based on a ratio between the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 through charge sharing between the first capacitor C1 and the second capacitor C2.

[0077] The second transistor T2 may be coupled between the data line DLm and the third node N3. The second transistor T2 may include a gate electrode configured to receive a scan signal. For example, the gate electrode of the second transistor T2 may be coupled to the scan line SLn (in other words, the nth scan line). The second transistor T2 is turned on when the scan signal is supplied to the scan line SLn, thereby electrically coupling the data line DLm to the third node N3. Therefore, a data voltage (or data signal) can be transmitted from the data line DLm to the third node N3.

[0078] The third transistor T3 may be coupled between a second node N2 (e.g., the drain electrode of the first transistor T1) and a first node N1 corresponding to the gate electrode of the first transistor T1. The third transistor T3 may include a gate electrode configured to receive a first control signal. For example, the gate electrode of the third transistor T3 may be coupled to a control line CLn (in other words, an nth control line). The third transistor T3 is turned on when the first control signal is supplied to the control line CLn, thereby electrically coupling the first node N1 to the second node N2. When the third transistor T3 is turned on, the voltage of the initialization power supply Vint is supplied to the first node N1, or the first transistor T1 may be diode-coupled. When the first transistor T1 is diode-coupled, the threshold voltage of the first transistor T1 may be compensated.

[0079] Therefore, the first transistor T1 may generate a driving current based on the data signal and the capacitances of the first capacitor C1 and the second capacitor C2, as shown in the following formula (1):

[0080] Id=k[a(Vdd–Vdata)] 2 , a=CC2 / (CC1+CC2) (1)

[0081] Here, Id may represent a driving current, k may represent a characteristic of the first transistor T1, Vdd may represent a voltage of the first power supply VDD, Vdata may represent a data signal, CC1 may represent a capacitance of the first capacitor C1, and CC2 may represent a capacitance of the second capacitor C2. The light emitting element LD may emit light having a brightness corresponding to the driving current Id.

[0082] exist Figure 2A In the present invention, for ease of description, the signal line coupled to the gate electrode of the third transistor T3 and the signal supplied to the gate electrode of the third transistor T3 are described as the control line CLn and the first control signal, respectively. However, the control line CLn may be a scan line different from the scan line SLn. In addition, the first control signal may be a scan signal different from the scan signal supplied to the scan line SLn.

[0083] The fourth transistor T4 may be coupled between the first power supply VDD and the third node N3. The fourth transistor T4 may include a gate electrode configured to receive the second control signal.

[0084] In an exemplary embodiment of the present invention, the gate electrode of the fourth transistor T4 can be coupled to the emission control line ELn (in other words, the nth emission control line). In this case, the second control signal can be the emission control signal. The fourth transistor T4 is turned on when the emission control signal is supplied to the emission control line ELn. In this case, the voltage of the first power supply VDD is supplied to the third node N3 through the fourth transistor T4. Therefore, the voltage of the third node N3 can be initialized to the voltage of the first power supply VDD.

[0085] In an exemplary embodiment of the present invention, the fourth transistor T4 may be coupled between a reference power source Vref different from the first power source VDD and the third node N3. In this case, when the fourth transistor T4 is turned on, the voltage of the third node N3 may be initialized to the voltage of the reference power source Vref.

[0086] In addition, while the threshold voltage of the first transistor T1 is being compensated, the fourth transistor T4 can be turned on. Therefore, the voltage of the first power supply VDD or the reference power supply Vref (in other words, the direct current (DC) voltage) can be used to compensate for the threshold voltage of the first transistor T1. Therefore, the conduction bias variation of the first transistor T1 caused by the difference between the grayscales of adjacent frames and / or adjacent pixel rows can be eliminated or not noticed.

[0087] The fifth transistor T5 may be coupled between the first power supply VDD and the first electrode of the first transistor T1. The first electrode of the first transistor T1 may be a source electrode. The fifth transistor T5 may include a gate electrode configured to receive an emission control signal. For example, the gate electrode of the fifth transistor T5 may be coupled to the emission control line ELn. The fifth transistor T5 is turned on when the emission control signal is supplied, thereby coupling the first electrode of the first transistor T1 to the first power supply VDD.

[0088] The sixth transistor T6 may be coupled between the light emitting element LD and a second node N2 corresponding to the second electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode configured to receive a previous emission control signal. For example, the gate electrode of the sixth transistor T6 may be coupled to a previous emission control line ELn-k (e.g., the nth emission control line).

[0089] For example, the previous emission control line ELn-k may be a line branching from the n-3th emission control line. In this case, each of the threshold voltage compensation period and the initialization period may correspond to approximately three horizontal periods (3H). Alternatively, the previous emission control line ELn-k may be the n-6th emission control line. In this case, each of the threshold voltage compensation period and the initialization period may correspond to approximately six horizontal periods (6H). However, this is merely an example, and the previous emission control line is not limited thereto. For example, the previous emission control line may be determined based on the time required to compensate for the threshold voltage, the number of pixel rows controlled simultaneously, the resolution, and the length of one horizontal period (1H).

[0090] The sixth transistor T6 is turned on when the emission control signal is supplied to the previous emission control line ELn-k, thereby electrically coupling the second node N2 to the fourth node N4.

[0091] When both the fifth transistor T5 and the sixth transistor T6 are turned on, the light emitting element LD can emit light having a brightness corresponding to the voltage of the first node N1. In an exemplary embodiment of the present invention, when the fifth transistor T5 is turned on and when the sixth transistor T6 is turned off, the threshold voltage of the first transistor T1 can be compensated.

[0092] The seventh transistor T7 may be coupled between the light emitting element LD and the initialization power supply Vint. The seventh transistor T7 may include a gate electrode configured to receive a third control signal.

[0093] In an exemplary embodiment of the present invention, the gate electrode of the seventh transistor T7 may be coupled to the control line CLn. The seventh transistor T7 and the third transistor T3 may be transistors of the same type. In addition, the first control signal and the third control signal may be the same signal supplied through the same control line CLn.

[0094] The seventh transistor T7 is turned on when a control signal (eg, a third control signal) is supplied to the control line CLn, thereby supplying the voltage of the initialization power supply Vint to the fourth node N4. Therefore, the voltage of the fourth node N4 may be initialized to the voltage of the initialization power supply Vint.

[0095] The period during which the second transistor T2 is turned on and the period during which the fourth transistor T4 and the fifth transistor T5 are turned on do not overlap. For example, when the third transistor T3 to the fifth transistor T5 are turned on, the threshold voltage of the first transistor T1 is compensated, and when the second transistor T2 and the third transistor T3 are turned on, data can be written. Therefore, the threshold voltage compensation period and the data writing period can be separated from each other.

[0096] In an exemplary embodiment of the present invention, the first transistor T1 as a driving transistor may be a P-channel metal oxide semiconductor (PMOS) transistor, such as Figure 2A and Figure 2B In addition, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be PMOS transistors of the same type as the first transistor T1. For example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be low-temperature polysilicon (LTPS) thin film transistors.

[0097] The third transistor T3 and the seventh transistor T7 may be N-channel metal oxide semiconductor (NMOS) transistors. For example, the third transistor T3 and the seventh transistor T7 may be oxide semiconductor thin film transistors including an active layer formed of an oxide semiconductor. Since N-type oxide semiconductor thin film transistors have better leakage current characteristics than LTPS thin film transistors, the third transistor T3 and the seventh transistor T7 that are turned on when the threshold voltage is compensated and / or initialization is performed may be formed of N-type oxide semiconductor thin film transistors.

[0098] Therefore, leakage current is greatly reduced in the third transistor T3 and the seventh transistor T7, and thus, even if the driving frequency is lower than 30 Hz, it is possible to drive the pixel PX and display an image.

[0099] Figure 2B Is used to illustrate Figure 2A is a circuit diagram of an example of the coupling of a pixel shown in .

[0100] refer to Figure 2A and Figure 2B , the n-th pixel PXn arranged in the n-th pixel row and the (n+1)-th pixel PXn+1 arranged in the (n+1)-th pixel row may have the same pixel structure.

[0101] Description will be made based on the assumption that both the n-th pixel PXn and the (n+1)-th pixel PXn+1 are coupled to the m-th data line DLm.

[0102] The nth scan signal Sn may be supplied to the nth scan line SLn connected to the nth pixel PXn, and the n+1th scan signal Sn+1 may be supplied to the n+1th scan line SLn+1 connected to the n+1th pixel PXn+1. The n+1th scan signal Sn+1 may be a scan signal shifted (e.g., delayed) by one horizontal period 1H from the nth scan signal Sn.

[0103] The p-th emission control signal Ep can be commonly supplied to the n-th emission control line ELn connected to the n-th pixel PXn and the n+1-th emission control line ELn+1 connected to the n+1-th pixel PXn+1 (where p is a natural number). In other words, both the n-th pixel PXn and the n+1-th pixel PXn+1 can be controlled by the same emission control signal Ep. Therefore, the number of emission control signals can be less than the number of scan signals supplied to the display panel during a single frame period.

[0104] For example, when a single emission control signal is commonly supplied to two emission control lines EL, the number of emission control signals may be half the number of scan signals.

[0105] According to an exemplary embodiment of the present invention, the p-th emission control signal Ep may be an emission control signal shifted (eg, delayed) by two horizontal periods 2H or more from the p-1-th emission control signal.

[0106] Similarly, the pq-th emission control signal Ep-q may be commonly supplied to the nk-th emission control line ELn-k connected to the n-th pixel PXn and the n-k+1-th emission control line ELn-k+1 connected to the n+1-th pixel PXn+1. In addition, the p-th emission control signal Ep may be an emission control signal shifted from the pq-th emission control signal Ep-q by q*2 horizontal periods (2qH) or more.

[0107] Hereinafter, the present invention will be described based on the assumption that n is greater than k and p is greater than q. However, the relationship between n and k and the relationship between p and q are arbitrarily set for the convenience of describing the timing of signal supply. Therefore, even when n is equal to or less than k, it can be understood that Figures 3A to 3C The timing at which the emission control signal is supplied is shifted, and then the emission control signal is supplied to each of the emission control lines (for example, ELn and ELn-k).

[0108] The pth control signal Cp may be commonly supplied to the nth control line CLn connected to the nth pixel PXn and the n+1th control line CLn+1 connected to the n+1th pixel PXn+1. In other words, the nth pixel PXn and the n+1th pixel PXn+1 may be controlled by the same control signal Cp.

[0109] For example, when a single control signal is commonly supplied to two control lines CL, the number of control signals may be half the number of scan signals.

[0110] According to an exemplary embodiment of the present invention, the p-th control signal Cp may be a control signal shifted (eg, delayed) by two horizontal periods 2H or more from the p-1-th control signal.

[0111] In other words, the scan line can be controlled for each pixel row, and the emission control line EL and the control line CL can be controlled for each preset number of consecutive pixel rows. Therefore, the display device 1000 having a driving frequency higher than 60 Hz can be easily implemented at high speed.

[0112] However, this is merely an example, and the control signal may be sequentially supplied to the pixel rows at intervals of one horizontal period 1H.

[0113] Figure 3A Is used to illustrate Figure 2A and Figure 2B A timing diagram of an example of the operation of a pixel is shown in FIG.

[0114] refer to Figure 2A 、 Figure 2B and Figure 3A , the pth emission control signal Ep may be supplied to the nth emission control line ELn, the nth scan signal Sn may be supplied to the nth scan line SLn, and the pth control signal Cp (e.g., the first control signal) may be supplied to the nth control line CLn. In addition, the previous emission control signal Ep-q may be supplied to the previous emission control line ELn-k. Furthermore, the n+1th scan signal Sn+1 is supplied to the n+1th scan line SLn+1.

[0115] In the following, for the convenience of description, the nth emission control line ELn and the emission control line ELn can be used interchangeably, the pth emission control signal Ep and the emission control signal Ep can be used interchangeably, the nth scan line SLn and the scan line SLn can be used interchangeably, the nth scan signal Sn and the scan signal Sn can be used interchangeably, the nth control line CLn and the control line CLn can be used interchangeably, and the pth control signal Cp and the control signal Cp can be used interchangeably.

[0116] In addition, the emission control signal Ep, the previous emission control signal Ep-q, and the control signal Cp may be commonly supplied to the n-th pixel PXn and the (n+1)-th pixel PXn+1.

[0117] In an exemplary embodiment of the present invention, the emission control signal Ep may be a scanning signal shifted by approximately k horizontal periods (kH) from the previous emission control signal Ep-q. Furthermore, the previous emission control signal Ep-q may be the same as the emission control signal supplied to the n-th pixel row. For example, k may be set to 3 or 6.

[0118] Figure 3A The timing diagram of φ shows a partial waveform during one frame period. In a period in which both the emission control signal Ep and the previous emission control signal Ep-q have the gate-on level (eg, in the fifth period P5), the pixel 10 may emit light.

[0119] like Figure 3A As shown in , the emission control signal Ep may have two gate-off periods during one frame period.

[0120] Since the third transistor T3 and the seventh transistor T7 are NMOS transistors, the gate-on level of the control signal Cp supplied to the third transistor T3 and the seventh transistor T7 can be a high voltage. On the contrary, since the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are PMOS transistors, the gate-on level of the scan signal Sn and the emission control signals Ep and Ep-q supplied to the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a low voltage.

[0121] At the first time point t1, the previous emission control signal Ep-q changes from the gate-on level to the gate-off level, and the sixth transistor T6 can be turned off. Since the fourth transistor T4 remains on, the voltage of the first power supply VDD (or reference power supply Vref) can be supplied to the third node N3.

[0122] In addition, at the first time point t1, the control signal Cp changes from the gate-off level to the gate-on level, and the third transistor T3 and the seventh transistor T7 can be turned on. In an exemplary embodiment of the present invention, the control signal Cp can maintain the gate-off level after the fourth period P4. Therefore, the third transistor T3 and the seventh transistor T7 can remain in the on state until the fourth period P4.

[0123] During a first period P1 from the first time point t1 to the second time point t2, the voltage of the initialization power source Vint may be supplied to the fourth node N4. In other words, the first period P1 may be a first initialization period for initializing the anode voltage of the light emitting element LD.

[0124] According to an exemplary embodiment of the present invention, the control signal Cp may be changed to the gate-on level after the previous emission control signal Ep-q is changed from the gate-on level to the gate-off level. The time difference between the first time point t1 and the second time point t2 prevents the light emitting element LD from irrationally emitting light when the seventh transistor T7 is turned on.

[0125] At the second time point t2, the previous emission control signal Ep-q can be changed from the gate-off level to the gate-on level, and the emission control signal Ep can be changed from the gate-on level to the gate-off level. At the second time point t2, the fourth transistor T4 and the fifth transistor T5 can be turned off, and the sixth transistor T6 can be turned on. Therefore, the voltage of the initialization power supply Vint can be supplied to the gate electrode of the first transistor T1 (in other words, the first node N1) through the third transistor T3 and the sixth transistor T6.

[0126] During the second period P2 from the second time point t2 to the third time point t3, the previous emission control signal Ep-q may have a waveform opposite to that of the emission control signal Ep. For example, the previous emission control signal Ep-q may be low and the emission control signal Ep may be high. Therefore, the second period P2 may be a second initialization period for initializing the anode voltage of the light-emitting element LD and the gate voltage of the first transistor T1.

[0127] At the third time point t3, the previous emission control signal Ep-q can be changed from the gate-on level to the gate-off level, and the emission control signal Ep can be changed from the gate-off level to the gate-on level. Therefore, the fourth transistor T4 and the fifth transistor T5 can be turned on, and the sixth transistor T6 can be turned off. Since the third transistor T3 is in the on state, the first transistor T1 can be diode-coupled. The second capacitor C2 can store a voltage corresponding to the threshold voltage (Vth) of the first transistor T1.

[0128] During the third period P3 from the third time point t3 to the fourth time point t4, the first transistor T1 is diode-coupled. Therefore, the threshold voltage of the first transistor T1 can be compensated. In other words, the third period P3 can be a threshold voltage compensation period.

[0129] In addition, in the third period P3, the threshold voltage of the first transistor T1 can be compensated by using the voltage of the first power supply VDD as a constant voltage source. Since the operation of compensating the threshold voltage of the first transistor T1 is performed based on a fixed voltage rather than a data signal (e.g., a data voltage) that can be changed according to pixel rows and / or frames, the bias applied to the first transistor T1 does not change much, and thus the hysteresis of the first transistor T1 can be minimized.

[0130] As described above, in the second period P2 and the third period P3 , the emission control signal Ep may have a waveform opposite to that of the previous emission control signal Ep-q.

[0131] At the fourth time point t4, the emission control signal Ep may be changed from the gate-on level to the gate-off level, and the fourth transistor T4 and the fifth transistor T5 may be turned off. At the fourth time point t4, the emission control signal Ep may have the same level as the previous emission control signal Ep-q.

[0132] At the fifth time point t5, the nth scan signal Sn may be changed from the gate-off level to the gate-on level, and the second transistor T2 of the nth pixel PXn may be turned on. Therefore, the data signal DATA may be supplied to the third node N3 of the nth pixel PXn.

[0133] In addition, during the fourth period P4 from the fifth time point t5 to the sixth time point t6, the nth scan signal Sn and the n+1th scan signal Sn+1 may be sequentially supplied. Therefore, the data signal DATA may be sequentially written into the nth pixel PXn (in response to the nth scan signal Sn) and the n+1th pixel PXn+1 (in response to the n+1th scan signal Sn+1). Therefore, a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 and the data signal DATA may be stored in the first capacitor C1 and the second capacitor C2 of each of the nth pixel PXn and the n+1th pixel PXn+1 according to the charge sharing principle. In other words, the fourth period P4 may be a data write period.

[0134] In an exemplary embodiment of the present invention, the pulse width of the scan signal Sn may be one horizontal period 1H. Figure 3A As shown in , the fourth period P4 may be equal to or greater than about two horizontal periods 2H. In addition, the pulse width of the (n+1)th scan signal Sn+1 may be one horizontal period 1H.

[0135] After the fourth period P4, the previous emission control signal Ep-q may be changed to a gate-on level, and the control signal Cp may be changed to a gate-off level. Therefore, the sixth transistor T6 may be turned on, and the third and seventh transistors T3 and T7 may be turned off.

[0136] In addition, Figure 3A , the control signal Cp is illustrated as being changed to the gate-off level after the n+1th scan signal Sn+1 is changed to the gate-off level, but the time when the control signal Cp is changed to the gate-off level may be the same as the time when the n+1th scan signal Sn+1 is changed to the gate-off level.

[0137] At the seventh time point t7, the emission control signal Ep changes from the gate-off level to the gate-on level, and the fourth transistor T4 and the fifth transistor T5 can be turned on. Therefore, the light-emitting element LD of each of the nth pixel PXn and the n+1th pixel PXn+1 can emit light based on the voltage stored in the second capacitor C2. For example, the light-emitting element LD can emit light in response to the driving current based on formula (1).

[0138] As described above, the pixel 10 (e.g., any one of PXn and PXn+1) according to an exemplary embodiment of the present invention can use the voltage of the first power supply VDD as a constant voltage source to compensate for the threshold voltage of the first transistor T1. Therefore, the conduction bias variation that may be caused by the threshold voltage compensation operation using the data signal can be avoided. In addition, the operation for compensating the threshold voltage of the first transistor T1 (in other words, the drive transistor) (e.g., the operation performed in the third period P3) can be separated from the data write operation (in other words, the data write operation performed in the fourth period P4). Therefore, the threshold voltage compensation period P3 can be freely adjusted by adjusting the waveform of the emission control signal Ep. Therefore, sufficient time for compensating the threshold voltage of the drive transistor can be ensured in a display device that applies high-speed drive. Therefore, the demultiplexer for supplying the data signal in the high-speed drive technology is omitted. Therefore, the dead zone (e.g., the border) can be minimized, and the manufacturing cost of the display device can be reduced. In addition, since some transistors can be implemented as NMOS transistors that are robust to current leakage, the pixel 10 according to an exemplary embodiment of the present invention can also be applied to low-frequency drive.

[0139] In addition, the first capacitor C1 can be coupled to the second capacitor C2 through the drain electrode of the first transistor T1. Therefore, the influence of the reduction of the voltage of the first power supply VDD and / or the voltage of the data signal on the driving current provided by the first transistor T1 can be reduced.

[0140] Therefore, the pixel 10 and the display device 1000 including the pixel 10 according to an exemplary embodiment of the present invention may display an image in response to various driving frequencies and may improve the quality of the image.

[0141] Figure 3B Is used to illustrate Figure 2A and Figure 2B A timing diagram of an example of the operation of a pixel is shown in FIG.

[0142] Since in addition to the timing of the control signal Cp supplied to the third transistor T3 and the seventh transistor T7, Figure 3B The pixel operation is Figure 3A The operations of the pixels are the same, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0143] refer to Figure 2A 、 Figure 2B and Figure 3B , a turn-on bias may be applied to the first transistor T1 in the first period P1 ′.

[0144] In the first period P1', the emission control signal Ep is applied, and the previous emission control signal Ep-q and the control signal Cp are not supplied. Therefore, when the fourth transistor T4 and the fifth transistor T5 are turned on, the sixth transistor T6 can be turned off. Here, the high voltage of the first power supply VDD can be supplied to the first electrode (e.g., the source electrode) of the first transistor T1. Therefore, in the first period P1', the first transistor T1 can have an on-bias state.

[0145] In the second period P2 , the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 may be initialized.

[0146] The third period P3 is a threshold voltage compensation period, and the fourth period P4 is a data writing period.

[0147] The on-bias is applied to the first transistor T1 in the first period P1 ′, so that the hysteresis characteristic (in other words, threshold voltage shift) of the first transistor T1 may be improved.

[0148] Figure 3C Is used to illustrate Figure 2A and Figure 2B A timing diagram of an example of the operation of a pixel is shown in FIG.

[0149] Since in addition to the pulse width of each of the scan signals Sn and Sn+1, Figure 3C The pixel operation is Figure 3A The operations of the pixels are the same, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0150] refer to Figure 2A 、 Figure 2B and Figure 3C , the pulse width of the scanning signal can be longer than one horizontal period 1H.

[0151] In an exemplary embodiment of the present invention, the pulse width of each of the nth scan signal Sn and the (n+1)th scan signal Sn+1 may be two horizontal periods 2H. Figure 3C As shown in , the previous data signal and the current data signal may be sequentially supplied to the third node N3 of the pixel PXn and the third node N3 of the pixel PXn+1. Since the second transistor T2 is turned off after the current data signal is supplied, the light emitting element LD may emit light in response to the current data signal Dm.

[0152] In addition, when the nth scan signal Sn maintains the gate-on level, the current data signal is supplied after the previous data signal. In this case, sufficient time for supplying the current data signal can be ensured. For example, the fourth period P4' for writing data can be shorter than Figure 3A and Figure 3B The fourth period P4 is long.

[0153] In addition, the (n+1)th scan signal Sn+1 may partially overlap with the nth scan signal Sn. For example, when the pulse width of each of the scan signals Sn and Sn+1 is two horizontal periods 2H, the (n+1)th scan signal Sn+1 and the nth scan signal Sn may overlap during one horizontal period 1H of the two horizontal periods 2H. Therefore, the light emitting element LD of the (n+1)th pixel PXn+1 may emit light in response to a data signal subsequent to the current data signal.

[0154] However, this is merely an example, and the pulse width of the scan signal may be three horizontal periods (3H), four horizontal periods (4H), or more depending on the driving frequency and / or resolution.

[0155] In addition, in the fourth period P4', periods during which adjacent pixel rows are driven may overlap. Therefore, the pixel 10 and the driving method thereof can be easily applied to the high-resolution display device 1000 and its high-speed driving.

[0156] Figure 4 Is used to illustrate Figure 1 A timing diagram showing an example of the operation of the display device.

[0157] refer to Figure 1 、 Figure 2B 、 Figure 3A and Figure 4 , the emission control signal and the control signal may be commonly supplied every two pixel rows. In addition, each of the emission control signal and the control signal may be sequentially output at intervals of a predetermined shift period SP.

[0158] In addition, the kth signal line (e.g., emission control line, control line or scan line) for supplying the kth signal (e.g., emission control signal, control signal or scan signal) can be understood as a signal line coupled to the pixels included in the kth pixel row.

[0159] The first emission control signal E1 can be commonly supplied to the first emission control line EL1 and the second emission control line EL2. Similarly, the first control signal C1 can be supplied to the first control line CL1 and the second control line CL2. Therefore, the shift period SP can be approximately two horizontal periods 2H. However, this is merely an example, and the shift period SP can be set to match the number of pixel rows to which the emission control signal (and control signal) are commonly supplied. For example, when the first emission control signal E1 is commonly supplied to the first to third emission control lines EL1, EL2, and EL3, the shift period SP can be approximately three horizontal periods 3H.

[0160] Scan signals (eg, S1 to S8) may be sequentially supplied to the scan lines SL1 to SL8 at intervals of one horizontal period 1 H. In other words, a shift period SP of each of the emission control signal and the control signal is longer than that of the scan signal.

[0161] In addition, when the display device 1000 includes i pixel rows (where i is a natural number), the first scan driver 200 can output i scan signals, the second scan driver 300 can output i / 2 control signals, and the emission driver 400 can output i / 2 emission control signals. Therefore, the power consumption of the display device 1000 driven at high speed can be reduced.

[0162] Figure 5 It shows Figure 2A A circuit diagram of an example of a pixel.

[0163] Since in addition to the types of the third transistor T3 and the seventh transistor T7, Figure 5 The pixels have Figure 2A The pixels have the same configuration and operation, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0164] refer to Figure 5 , the pixel 10 ′ may include a light emitting element LD, first to seventh transistors T1 to T7 , a first capacitor C1 and a second capacitor C2 .

[0165] In an exemplary embodiment of the present invention, all of the first to seventh transistors T1 to T7 may be PMOS transistors. For example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be LTPS thin film transistors.

[0166] Therefore, the control signal can have Figures 3A to 3B The control signal Cp shown in FIG is the opposite waveform. Figure 5The pixel 10' in FIG. 1 has an active layer formed by the LTPS process, so the manufacturing process can be simplified.

[0167] Figure 6 is a circuit diagram illustrating an example of a pixel according to an exemplary embodiment of the present invention.

[0168] Since in addition to the configuration of the fourth transistor T4, Figure 6 The pixels have Figure 2A The pixels have the same configuration and operation, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions will be omitted.

[0169] refer to Figure 6 , the pixel 11 may include a light emitting element LD, first to seventh transistors T1 to T7 , a first capacitor C1 and a second capacitor C2 .

[0170] In an exemplary embodiment of the present invention, the first transistor T1 , the second transistor T2 , the fifth transistor T5 , and the sixth transistor T6 may be PMOS transistors, and the third transistor T3 , the fourth transistor T4 , and the seventh transistor T7 may be NMOS transistors.

[0171] The gate electrode of the fourth transistor T4 may be coupled to a previous control line CLn-k instead of the emission control line ELn. For example, the previous control line CLn-k may be the same as the control line coupled to the n-th pixel row. The second control signal supplied to the gate electrode of the fourth transistor T4 may be a signal shifted by k horizontal periods from the first control signal supplied to the gate electrode of the third transistor T3.

[0172] However, this is merely an example, and the second control signal supplied to the gate electrode of the fourth transistor T4 is not limited to the signal supplied to the previous control line CLn-k. For example, the fourth transistor T4 can be turned on by any control signal supplied earlier than the scan signal supplied to the scan line SLn. Therefore, the fourth transistor T4 is turned on before data is written. In this case, the voltage of the third node N3 can be initialized to the voltage of the first power supply VDD or the voltage of the reference power supply Vref.

[0173] In addition, the display device 1000 may further include an additional driving circuit (eg, a stage) configured to generate a second control signal and sequentially output the second control signal in units of pixel rows.

[0174] and Figure 2A Unlike the pixel 10 shown in FIG, the fourth transistor T4 of the pixel 11 can be turned off during the emission period P_E. In addition, the leakage current in the fourth transistor T4 can be reduced, and the low-frequency driving characteristics can be improved.

[0175] Figure 7A Is used to illustrate Figure 6 A timing diagram of an example of pixel operation.

[0176] Since in addition to the previous control signal Cp-q supplied to the fourth transistor T4, Figure 7A The pixel operation shown in Figure 3A The operations of the pixels shown in are the same, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0177] refer to Figure 6 and Figure 7A , one frame period may include a first initialization period P_I1 , a second initialization period P_I2 , a compensation period P_C, a data writing period P_W, and an emission period P_E.

[0178] The previous control signal Cp-q (eg, the second control signal) may be a signal shifted from the control signal Cp (eg, the first control signal) by k horizontal periods.

[0179] The period in which the previous control signal Cp-q has the gate-on level may be the first initialization period P_I1. In other words, in the first initialization period P_I1, the fourth transistor T4 is turned on. Therefore, the voltage of the first power supply VDD (or reference power supply Vref) may be supplied to the third node N3.

[0180] During the second initialization period P_I2, the previous emission control signal Ep-q, the previous control signal Cp-q, and the control signal Cp may have a gate-on level. The second initialization period P_I2 may overlap with the first initialization period P_I1. During the second initialization period P_I2, the emission control signal Ep and the scan signal Sn may have a gate-off level. Therefore, during the second initialization period P_I2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned on. Therefore, the anode voltage of the light-emitting element LD and the gate voltage of the first transistor T1 can be initialized by the voltage of the initialization power supply Vint. In the second initialization period P_I2, both the anode voltage of the light-emitting element LD and the gate voltage of the first transistor T1 can be initialized.

[0181] During the compensation period P_C, which also overlaps with the first initialization period P_I1, the emission control signal Ep, the previous control signal Cp-q, and the control signal Cp may have a gate-on level. During the compensation period P_C, the previous emission control signal Ep-q and the scan signal Sn may have a gate-off level. Therefore, during the compensation period P_C, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on, and the sixth transistor T6 is turned off. In this case, the threshold voltage of the first transistor T1 can be compensated. The compensation period P_C can be adjusted according to the duration of the gate-on period of the emission control signal Ep.

[0182] During the data write period P_W, the scan signal Sn and the control signal Cp may have a gate-on level. During the data write period P_W, the previous emission control signal Ep-q, the emission control signal Ep, and the previous control signal Cp-q may have a gate-off level. Therefore, the second transistor T2 and the third transistor T3 may be turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be turned off. During the data write period P_W, the voltage of the data signal DATA may be stored in the pixel 11. For example, the voltage of the data signal DATA may be stored in the order of Dn-1, Dn, and Dn+1.

[0183] During the emission period P_E, the previous emission control signal Ep-q and the emission control signal Ep may have a gate-on level. During the emission period P_E, the scan signal Sn, the previous control signal Cp-q, and the control signal Cp may have a gate-off level. During the emission period P_E, the fifth transistor T5 and the sixth transistor T6 may be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be turned off. Therefore, the light emitting element LD may emit light in response to the current data signal Dn.

[0184] Figure 7B Is used to illustrate Figure 6 A timing diagram of an example of the operation of a pixel is shown in FIG.

[0185] Since in addition to the operation in the third initialization period P_I3, Figure 7B The pixel operation shown in Figure 7A The operations of the pixels shown in are the same, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0186] refer to Figures 6 to 7B , one frame period may include a first initialization period P_I1 , a second initialization period P_I2 , a third initialization period P_I3 , a compensation period P_C, a data writing period P_W, and an emission period P_E.

[0187] In an exemplary embodiment of the present invention, before the second initialization period P_I2, a third initialization period P_I3 may be further included in which the gate-off period of the previous emission control signal Ep-q overlaps the gate-off period of the emission control signal Ep. Therefore, in the third initialization period P_I3, the fifth transistor T5 and the sixth transistor T6 are turned off, and the voltage of the initialization power supply Vint may be supplied only to the fourth node N4.

[0188] In other words, in the third initialization period P_I3 , only the anode voltage of the light emitting element LD may be initialized.

[0189] Figure 8 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0190] Since in addition to the configuration of the seventh transistor T7 and the fourth transistor T4, Figure 8 The pixels shown in Figure 2A The pixels shown in FIG. 1 have the same configuration and operation, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0191] refer to Figure 8 , the pixel 12 may include a light emitting element LD, first to seventh transistors T1 to T7 , a first capacitor C1 and a second capacitor C2 .

[0192] In an exemplary embodiment of the present invention, the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be PMOS transistors, and the third transistor T3 may be an NMOS transistor.

[0193] A gate electrode of the third transistor T3 may be coupled to the first control line CL1n. The third transistor T3 may be turned on in response to a first control signal supplied to the first control line CL1n.

[0194] A gate electrode of the fourth transistor T4 and a gate electrode of the seventh transistor T7 may be coupled to a second control line CL2n for supplying the same second control signal.

[0195] When only the third transistor T3 is an NMOS transistor, the semiconductor layers forming the corresponding active patterns of the other transistors except the third transistor T3 may be formed as one body. Figure 2A or Figure 6 The pixel 10 or 11 shown in the process is manufactured by a simple process Figure 8 Pixel 12 is shown in FIG.

[0196] Figure 9Is used to illustrate Figure 8 A timing diagram of an example of the operation of a pixel is shown in FIG.

[0197] Since in addition to the second control signal C2p supplied to the fourth transistor T4 and the seventh transistor T7, Figure 9 The pixel operation shown in Figure 3C The operations of the pixels shown in are the same, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0198] refer to Figure 8 and Figure 9 , one frame period may include a first initialization period P_I1 , a second initialization period P_I2 , a compensation period P_C, a data writing period P_W, and an emission period P_E.

[0199] In an exemplary embodiment of the present invention, a gate-on level of the second control signal C2p supplied to the second control line CL2n may be a low voltage, and a gate-on level of the first control signal C1p supplied to the first control line CL1n may be a high voltage.

[0200] The period in which the second control signal C2p has a gate-on level may be the first initialization period P_I1. In other words, in the first initialization period P_I1, the fourth transistor T4 is turned on. In this case, the voltage of the first power supply VDD or the reference power supply Vref may be supplied to the third node N3.

[0201] During the second initialization period P_I2 , the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 may be initialized.

[0202] During the compensation period P_C, the threshold voltage of the first transistor T1 can be compensated. Subsequently, during the data writing period P_W, the voltage of the current data signal Dn can be stored in the nth pixel, and the voltage of the next data signal Dn+1 can be stored in the n+1th pixel. During the emission period P_E, the fifth transistor T5 and the sixth transistor T6 are turned on so that the light emitting element LD can emit light.

[0203] As described above, the compensation period P_C in which the threshold voltage is compensated can be separated from the data writing period P_W in which the data signal DATA is written. Therefore, a sufficient compensation period P_C can be ensured, and a demultiplexer for supplying a data signal for high-speed driving can be omitted.

[0204] Figure 10 It shows Figure 2A A circuit diagram of an example of a pixel.

[0205] Since in addition to the configuration of the eighth transistor T8, Figure 10 The pixels shown in Figures 2A to 3C The pixels shown in FIG. 1 have the same configuration and operation, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0206] refer to Figure 10 , the pixel 13 may include a light emitting element LD, first to eighth transistors T1 to T8 , a first capacitor C1 and a second capacitor C2 .

[0207] The eighth transistor T8 may be coupled between the second node N2 and the first capacitor C1. A gate electrode of the eighth transistor T8 may be coupled to the control line CLn. In other words, a gate electrode of the eighth transistor T8 and a gate electrode of the third transistor T3 may be coupled to the control line CLn.

[0208] In an exemplary embodiment of the present invention, the eighth transistor T8 may be of the same type as the third transistor T3. For example, both the third transistor T3 and the eighth transistor T8 may be NMOS transistors.

[0209] like Figure 3A As shown in FIG, the control signal Cp supplied to the control line CLn may have a gate-on level during the first to fourth periods P1 to P4.

[0210] The eighth transistor T8 can be turned off in the period between the fourth period P4 and the fifth period P5, and can maintain the off state during the fifth period P5 as the emission period. In other words, the eighth transistor T8 can prevent the second node N2 from being electrically coupled to the first capacitor C1 after the data signal DATA is written and before emission.

[0211] However, this is merely an example, and the eighth transistor T8 only needs to be turned off after the fourth period P4 (in other words, the data writing period). Therefore, the control signal supplied to the gate electrode of the eighth transistor T8 is not limited to the control signal Cp.

[0212] During the fifth period P5, electrical coupling between the drain electrode of the first transistor T1 and the first capacitor C1 can be blocked. Therefore, unexpected changes in the voltage of the second node N2 caused by the first capacitor C1 during the emission period can be prevented, and the light emitting element LD can emit light more stably.

[0213] Figure 11 It shows Figure 2A A circuit diagram of an example of a pixel.

[0214] Since in addition to the configuration of the gate electrode of the eighth transistor T8, Figure 11 The pixels shown in Figure 10The pixels shown in FIG. 1 have the same configuration and operation, so the same reference numerals are used for the same or similar elements, and thus, repeated descriptions may be omitted.

[0215] refer to Figure 11 , the pixel 14 may include a light emitting element LD, first to eighth transistors T1 to T8 , a first capacitor C1 and a second capacitor C2 .

[0216] The eighth transistor T8 may be coupled between the second node N2 and the first capacitor C1. A gate electrode of the eighth transistor T8 may be coupled to the scan line SLn. In other words, the gate electrode of the eighth transistor T8 may be coupled to the scan line SLn that is also coupled to the gate electrode of the second transistor T2.

[0217] In an exemplary embodiment of the present invention, the eighth transistor T8 may be of a different type than the third transistor T3. For example, the eighth transistor T8 may be a PMOS transistor of the same type as the second transistor T2.

[0218] The eighth transistor T8 is turned on during the fourth period P4, which is a data writing period, to transmit the data signal DATA to the second node N2. The eighth transistor T8 can prevent the second node N2 from being electrically coupled to the first capacitor C1 after the data signal DATA is written and before emission. Therefore, it is possible to prevent the voltage of the second node N2 from being accidentally changed by the first capacitor C1 during the emission period, and the light-emitting element LD can emit light more stably.

[0219] According to an exemplary embodiment of the present invention, a pixel and a display device including the pixel can compensate for a threshold voltage using a voltage of a first power source as a constant voltage source. Therefore, it is possible to improve and eliminate display defects such as motion blur caused by a change in on-bias (and hysteresis characteristics causing a threshold voltage drift) caused by conventional threshold voltage compensation operations using data signals.

[0220] In addition, the operation for compensating the threshold voltage of the first transistor (in other words, the drive transistor) can be separated from the data writing operation, and the threshold voltage compensation period can be freely adjusted by adjusting the waveform of the emission control signal. Therefore, it is possible to ensure sufficient time to compensate for the threshold voltage in a display device that applies high-speed drive. In addition, the demultiplexer for supplying data signals required for high-speed drive is omitted. Therefore, the dead zone (e.g., border) can be minimized and the manufacturing cost of the display device can be reduced.

[0221] Furthermore, since some transistors are implemented as NMOS transistors that are robust to current leakage, the pixel and the display device including the pixel can be easily applied even when the display device is driven at a low frequency.

[0222] Although the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A pixel comprising: Light-emitting element; a first transistor configured to control a driving current, the first transistor comprising a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light emitting element, wherein the first power source is a constant voltage source; a first capacitor coupled between a second node and a third node, wherein the second node is directly connected to the second electrode of the first transistor, and the second electrode of the first transistor is a source or a drain of the first transistor; a second transistor coupled between the third node and the data line and configured to be turned on in response to a scan signal; a third transistor coupled between a first node and the second node and configured to be turned on in response to a first control signal, wherein the first node is connected to a gate electrode of the first transistor; a fourth transistor coupled between the first power supply or the reference power supply and the third node and configured to be turned on in response to a second control signal; a fifth transistor coupled between the first power source and the first electrode of the first transistor and configured to be turned on in response to an emission control signal; a sixth transistor coupled between the second node and the light emitting element and configured to be turned on in response to a previous emission control signal; as well as a second capacitor coupled between the first power source and the first node, In which, the voltage of the initialization power supply is supplied to the light-emitting element in a first period, the voltage of the initialization power supply is supplied to the first node in a second period, the first transistor is diode-coupled based on the voltage of the first power supply in a third period, and the second transistor is turned on in a fourth period so that the data signal is supplied to the third node through the data line.

2. The pixel according to claim 1, wherein When the third transistor and the fourth transistor are turned on, the second transistor and the sixth transistor are turned off.

3. The pixel according to claim 1, further comprising: a seventh transistor coupled between the light emitting element and the initialization power source and configured to be turned on in response to a third control signal.

4. The pixel according to claim 3, wherein The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-channel metal oxide semiconductor transistors, and the third transistor and the seventh transistor are N-channel metal oxide semiconductor transistors.

5. The pixel according to claim 4, wherein The first control signal and the third control signal are the same signal supplied through the same control line, and The second control signal is the same as the transmission control signal. The pixel according to claim 1 , wherein: The third transistor maintains a turned-on state during the first period, the second period, the third period, and the fourth period in response to the first control signal.

7. The pixel according to claim 1, wherein: In the first period and the third period, the fifth transistor is turned on and the sixth transistor is turned off; and In the second period, the fifth transistor is turned off, and the sixth transistor is turned on.

8. The pixel according to claim 1, wherein The emission control signal is shifted from the previous emission control signal by k horizontal periods, where k is an integer greater than or equal to 3.

9. The pixel according to claim 3, wherein: During the first period, the sixth transistor is turned off; and In the second period, the third transistor, the sixth transistor, and the seventh transistor are turned on.

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