Word Line Capacitance Balance

Abstract

The present application relates to word line capacitance balancing. A memory device may include a group of memory blocks, wherein one or more memory blocks may be located at a boundary of the group. Each boundary memory block may have a word line coupled to a driver and a memory cell subarray, and may also include a load balancing component (e.g., a capacitive component) coupled to the driver. In some examples, the load balancing component may be coupled to an output line (e.g., a word line) of the driver or an input (e.g., a line providing a source signal) of the driver. The load balancing component may adapt the load output from the driver to the memory cell subarray so that the load of the memory block at the boundary may be similar to the load of other memory blocks not at the boundary.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 518,824, filed by Villa et al. on July 22, 2019, entitled “WORDLINE CAPACITANCE BALANCING,” which is assigned to its assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to word line capacitance balancing. Background Art

[0004] The following relates generally to a system including at least one memory device, and more particularly to word line capacitance balancing.

[0005] Memory devices are widely used to store information in a variety of electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, usually represented by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (such as FeRAM) can maintain its stored logic state for a long time, even in the absence of external power. Volatile memory devices (such as DRAM) lose their storage state when disconnected from the external power supply. FeRAM is able to achieve densities similar to volatile memory, but can be non-volatile due to the use of ferroelectric capacitors as storage devices.

[0007] For some memory devices, memory cell subarrays (eg, memory blocks) may be arranged so that the circuitry of some memory blocks experiences a different load than the circuitry of other memory blocks. This inconsistent loading across respective memory blocks can lead to higher error rates and other problems. Summary of the invention

[0008] An apparatus is described. The apparatus may include: a memory block located at a boundary of a plurality of memory blocks and including a memory cell array; a word line coupled to the memory cell array and a driver, the word line being associated with a total capacitive load; and a capacitive component coupled to the driver to adapt a load output from the driver to the memory cell array, the load including at least a portion of the total capacitive load.

[0009] Another apparatus is described. The apparatus may include: a first line coupled to an input of a driver; a second line coupled to an output of the driver, the second line being associated with a total capacitive load; a plurality of memory cells coupled to the second line; and a capacitive component coupled to the second line, the capacitive component adapting a load outputted from the driver to the plurality of memory cells, the load comprising at least a portion of the total capacitive load.

[0010] Another apparatus is described. The apparatus may include: a plurality of memory blocks of a memory array, wherein a first memory block of the plurality of memory blocks is configured as a memory block of a first type that shares an electrical connection with two other memory blocks in the memory array, and wherein a second memory block of the plurality of memory blocks is configured as a memory block of a second type that shares an electrical connection with one other memory block in the memory array; and a capacitive component that accommodates at least a portion of a total capacitive load to the second memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting word line capacitance balancing according to examples disclosed herein is described.

[0012] Figure 2

[0046] An example of a memory die supporting word line capacitance balancing according to examples disclosed herein is illustrated.

[0013] Figure 3A and 3B Examples of hysteresis curves supporting word line capacitance balancing according to examples disclosed herein are illustrated.

[0014] Figure 4A and 4B An example of a memory block supporting word line capacitance balancing according to examples disclosed herein is illustrated.

[0015] Figure 4C An example of a set of memory blocks supporting word line capacitance balancing according to examples disclosed herein is illustrated.

[0016] Figure 5A and 5BAn example of a memory block supporting word line capacitance balancing according to examples disclosed herein is illustrated.

[0017] Figure 6 An example of a voltage timing diagram that supports word line capacitance balancing according to examples disclosed herein is illustrated. DETAILED DESCRIPTION

[0018] An array of memory cells within a memory device may include a plurality of memory blocks, wherein a memory block may be the smallest subarray of adjacent memory cells in the array. In general, the circuitry or circuit components of a subarray of memory cells may be shared between adjacent memory blocks. In some cases, a shared memory block (e.g., at a boundary or edge of a sequence of memory blocks and immediately adjacent to other components, such as components at the periphery of a peripheral component) may have a specific closed configuration that implements the same functionality and device operation at the edge memory block as other memory blocks not located at the edge. For example, the circuitry including word lines and word line drivers may be configured to be shared between adjacent subarrays, while the circuitry of a memory block located at the boundary of the array may be configured differently when adjacent to another subarray.

[0019] However, such memory blocks located at the boundary may have discontinuities due to the electrical connection to a single other memory block. As an example, the load on the word lines of the boundary memory blocks may be different (e.g., less than) the load on the word lines of the non-boundary memory blocks. These different loads may result in different operation of the boundary memory blocks than the non-boundary memory blocks, for example, where the smaller load may result in faster resistance-capacitance (RC) timing for some blocks but not other blocks. In some cases, this inconsistent operation across different memory blocks may affect the efficiency and reliability of the memory device.

[0020] As described herein, new capacitive components can be used to adjust the capacitive load (e.g., word lines) of a boundary memory block so that the capacitive load is balanced with the capacitive load (e.g., with the word lines) of other non-boundary memory blocks. For example, a capacitive component (e.g., a capacitor, an RC circuit) can be coupled with a word line of a boundary memory block, which can change or adapt (e.g., increase) the capacitive load of the word line to (e.g.,) match the load of the word line associated with the non-boundary memory block. In other cases, the capacitive component can be coupled with an input line to provide a source signal of a driver of a boundary memory block word line. In such cases, the output of the driver on the word line can be balanced with other word lines located at a memory block not on the boundary. Additionally or alternatively, the input of the driver of the boundary memory block word line can be configured to achieve the same increase in capacitance of the word line. For example, the capacitive component can be coupled with an access line to the source signal of the driver of the boundary memory block word line. In other examples, the driver providing the source signal can have its resistance configured to adjust the capacitive load at the line of the source signal. In any case, by increasing the capacitance of the boundary memory block word lines, the entire memory cell array can operate consistently, even at memory blocks and corresponding memory cells at the edge of the array having different circuitry configurations. The described techniques can also enable matching of the RC delays of each memory cell in the respective memory blocks.

[0021] First, in reference Figure 1 Features of the present invention are described in the context of the memory system and memory die described in reference to FIG. Figure 4A , 4B Features of the present invention are described in the context of the memory blocks described in , 5A and 5B. Further by reference to Figure 6 The voltage timing diagram is described for illustration and reference Figure 6 Voltage timing diagrams are described to illustrate these and other features of the present invention.

[0022] Figure 1 An example of a system 100 utilizing one or more memory devices according to examples disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0023] System 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet, a smart phone, a cell phone, a wearable device, an Internet-connected device, or the like. Memory device 110 may be a component of a system configured to store data of one or more other components of system 100. In some examples, system 100 implements machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0024] At least a portion of system 100 may be an example of a host device. This host device may be an example of a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cell phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, or the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some examples, system 100 is a graphics card.

[0025] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may operate to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0026] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support the desired or specified data storage capacity. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0027] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may use a bus 140 to electronically communicate with each other.

[0028] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, the processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a single chip system (SoC), etc.

[0029] BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0030] Peripheral component 130 may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components understood by those skilled in the art to be peripheral devices.

[0031] I / O controller 135 may manage data communications between processor 120 and peripheral device 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0032] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with other devices or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0033] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0034] The components of system 100 may be composed of general or special purpose circuitry designed to implement their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to implement the functions described herein. For example, and as described in further detail herein, capacitive components (such as capacitors, RC circuits, or the like) may be coupled at various locations within system 100, where the capacitive components may adjust the output of a driver (e.g., on a word line). In some cases, the capacitive components may be configured to alter or adapt the capacitive load associated with a subarray of memory cells located at the edge of a memory array (e.g., memory array 170) based on the location of the capacitive components relative to other components. For example, the capacitive components may enable the capacitive load to be relatively consistent and balanced across different memory blocks throughout the array.

[0035] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., a grid), where each memory cell is configured to store at least one bit of digital data. In some cases, the memory array 170 may include multiple sub-arrays or groups of adjacent memory cells. Furthermore, the smallest grouping of adjacent cells (e.g., without any kind of separation) may be referred to as a memory block or patch. Reference Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0036] The memory device 110 may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked one above the other or next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a level, a tier, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., more than two, more than three, more than four, more than five, more than six, more than seven, more than eight). This may increase the number of memory cells that may be positioned on a substrate compared to a single 2D memory device, which in turn may reduce production costs or improve the performance of the memory array, or both. In some 3D memory devices, different levels may share at least one common access line, such that some levels may share at least one of a word line, a digit line, and / or a plate line.

[0037] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enables the memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command instructing the memory device 110 to store certain data on behalf of a component of the system 100 (e.g., the processor 120) or a read command instructing the memory device 110 to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, or the like.

[0038] A local memory controller 165 (e.g., located at the memory die 160) can be configured to control the operation of the memory die 160. In addition, the local memory controller 165 can be configured to communicate with the device memory controller 155 (e.g., receive and transmit data and / or commands). The local memory controller 165 can support the device memory controller 155 in controlling the operation of the memory device 110 described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 can perform the various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0039] The external memory controller 105 may be configured to enable information, data, and / or commands to be communicated between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 do not need to know the details of the operation of the memory device. The components of the system 100 may make requests (e.g., read commands or write commands) to the external memory controller 105, which the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0040] In some cases, the external memory controller 105 or other components of the system 100 or its functions described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120).

[0041] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to act as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115. Additional signal paths may be coupled with the terminals of the channel to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or components thereof (e.g., internal to memory die 160)) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0042] The channels 115 (and associated signal paths and terminals) may be dedicated to transmitting a specific type of information. In some cases, the channels 115 may be aggregate channels and thus may include multiple individual channels. For example, the data channels 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc. The signals transmitted through the channels may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be recorded on the rising edge of the clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. The signals transmitted through the channels may use single data rate (SDR) signaling. For example, one symbol of the signal may be recorded for each clock cycle.

[0043] In some cases, channels 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channels 186 may include a read command with an address of desired data. In some cases, CA channels 186 may be recorded on rising clock signal edges and / or falling clock signal edges. In some cases, CA channels 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0044] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channels 188 may be configured to transmit one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal paths of the CK channels 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channels 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., the CK_t signal and the CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. Therefore, the clock signal CK may be referred to variously as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, or the like).

[0045] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer information written to memory device 110 (e.g., bidirectional) or information read from memory device 110.

[0046] In some cases, the channel 115 may include one or more other channels 192 dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0047] In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., a WCK_t signal and a WCK_c signal) may provide a timing reference that is typically used for access operations of the memory device 110 (e.g., a timing reference for both read operations and write operations). Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., a WCK_t signal and a WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, or the like).

[0048] Channel 115 may use a variety of different architectures to couple external memory controller 105 and memory device 110. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer (such as a silicon interposer), or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0049] A variety of different modulation schemes may be used to modulate the signals transmitted over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. Each symbol of the binary symbol modulation scheme may be configured to represent one digital data bit (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0050] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one digital data bit (e.g., the symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0051] Figure 2 An example of a memory die 200 according to examples disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 is programmable to store two or more states. For example, the memory cell 205 may be configured to store one digital logic bit at a time (e.g., a logic 0 and a logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one digital logic bit at a time (e.g., a logic 00, a logic 01, a logic 10, or a logic 11).

[0052] The memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) representing digital data. In a FeRAM architecture, the memory cell 205 may include a capacitor including a ferroelectric material to store a charge and / or polarization representing a programmable state. In a DRAM architecture, the memory cell 205 may include a capacitor including a dielectric material to store a charge representing a programmable state.

[0053] Operations such as reading and writing may be performed on memory cell 205 by activating or selecting access lines such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, or the like may be interchangeable without loss of understanding or operation. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the corresponding line.

[0054] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210, digit lines 215, and / or plate lines 220. A single memory cell 205 at an intersection thereof may be accessed by biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying a voltage to the word lines 210, digit lines 215, or plate lines 220).

[0055] Access to the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from a local memory controller 265 and activate a word line 210 based on the received row address. The column decoder 230 may receive a column address from a local memory controller 265 and activate a digit line 215 based on the received column address. The plate driver 235 may receive a plate address from a local memory controller 265 and activate a plate line 220 based on the received plate address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M, a plurality of digit lines 215 labeled DL_1 to DL_N, and a plurality of plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Thus, the memory cells 205 at their intersections may be accessed by activating word lines 210, digit lines 215, and plate lines 220 (e.g., WL_1, DL_3, and PL_1). In a two-dimensional or three-dimensional configuration, the intersection of word line 210 and digit line 215 can be referred to as the address of memory cell 205. In some cases, the intersection of word line 210, digit line 215, and plate line 220 can be referred to as the address of memory cell 205.

[0056] Memory cell 205 may include a logic storage component, such as capacitor 240, and a switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0057] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switching component 245. Capacitor 240 can be in electronic communication with digit line 215 using switching component 245. For example, when switching component 245 is deactivated, capacitor 240 can be isolated from digit line 215, and when switching component 245 is activated, capacitor 240 can be coupled to digit line 215. In some cases, switching component 245 is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source is greater than or less than the threshold voltage of the transistor. In some cases, switching component 245 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switching component 245 and can activate / deactivate switching component 245 based on the voltage applied to word line 210.

[0058] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with the gate of the switching element 245 of the memory cell 205 and may be configured to control the switching element 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching element. In some cases, the word line 210 may be shared between adjacent memory blocks in a memory device. For example, the word line 210 may be in electrical communication with memory cells of multiple adjacent memory blocks.

[0059] In other cases, such as where a memory block is located at the edge of the memory array, the word line 210 may not be shared with components of another memory block. Therefore, and as described herein, the word line 210 may also be coupled with a capacitive component that accommodates at least a portion of the total capacitive load of the output of the driver to the word line 210. The load may be adjusted by the capacitive component to balance relative to (e.g., match, be similar to) the load of another word line 210 of a memory block that is not located at the edge of the memory array. In such cases, the RC timing may also be adjusted to enable the memory cells 205 coupled to the word line 210 to operate in unison.

[0060] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled with the digit line 215 during portions of an access operation. For example, the word line 210 and the switching component 245 of the memory cell 205 can be configured to selectively couple and / or isolate the capacitor 240 and the digit line 215 of the memory cell 205. In some architectures, the memory cell 205 can be in electronic communication with the digit line 215 (e.g., continuously).

[0061] Plate line 220 may be a conductive line in electronic communication with memory cell 205 for performing access operations on memory cell 205. Plate line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of capacitor 240. Plate line 220 may be configured to bias capacitor 240 along with digit line 215 during access operations of memory cell 205.

[0062] The sensing component 250 may be configured to determine a state (e.g., a polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine a logic state of the memory cell 205 based on the detected state. In some cases, the charge stored by the memory cell 205 may be very small. Thus, the sensing component 250 may include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation and may generate a signal corresponding to a logic 0 or a logic 1 based on the detected charge. During a read operation, the capacitor 240 of the memory cell 205 may output a signal (e.g., release the charge) to its corresponding digit line 215. The signal may cause a voltage change of the digit line 215. The sensing component 250 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 255 (e.g., a reference voltage). The sensing component 250 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digital line 215 has a higher voltage than the reference signal 255, the sensing component 250 can determine that the storage state of the memory cell 205 is a logic 1, and if the digital line 215 has a lower voltage than the reference signal 255, the sensing component 250 can determine that the storage state of the memory cell 205 is a logic 0. The sensing component 250 can include various transistors or amplifiers to detect and amplify the signal difference. The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., to the input / output 260), and can indicate the detected logic state to another component of the memory device 110 including the memory die 200 (e.g., directly or using a local memory controller 265). In some cases, the sensing component 250 can be in electronic communication with the row decoder 225, the column decoder 230, and / or the plate driver 235.

[0063] The local memory controller 265 may control the operation of the memory cell 205 through various components such as the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250. The local memory controller 265 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 225, column decoder 230, and plate driver 235 and sensing component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be configured to: Figure 1 The local memory controller 265 may receive one or more commands and / or data, translate the commands and / or data into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transmit data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 265 may generate row, column, and / or plate line address signals to activate the target word lines 210, the target digit lines 215, and the target plate lines 220. The local memory controller 265 may also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or changed and may be different for the various operations discussed when operating the memory die 200.

[0064] In some cases, local memory controller 265 can be configured to perform a precharge operation on memory die 200. The precharge operation can include precharging one or more components and / or access lines of memory die 200 to one or more predetermined voltage levels. In some examples, portions of memory cells 205 and / or memory die 200 can be precharged between different access operations. In some examples, digit lines 215 and / or other components can be precharged prior to a read operation.

[0065] In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. Local memory controller 265 may apply a specific signal (eg, voltage) to digit line 215 and a specific signal (eg, voltage) to plate line 220 during a write operation to store a specific state in capacitor 204 of memory cell 205, the specific state indicating a desired logic state.

[0066] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in a memory cell 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify a target memory cell 205 on which a read operation is to be performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 may trigger the sensing component 250 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 255. Based on the comparison, the sensing component 250 may determine the logic state stored on the memory cell 205. As part of a read operation, the local memory controller 265 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller).

[0067] In some memory architectures, accessing the memory cell 205 can degrade or destroy the logical state stored in the memory cell 205. For example, a read operation performed on a ferroelectric memory cell can destroy the logical state stored in the ferroelectric capacitor. In another example, a read operation performed in a DRAM architecture can partially or completely discharge the capacitor of the target memory cell. The local memory controller 265 can perform a rewrite operation or a refresh operation to return the memory cell to its original logical state. The local memory controller 265 can rewrite the logical state to the target memory cell after the read operation. In some cases, the rewrite operation can be considered as part of the read operation. In addition, activating a single access line such as a word line 210 can interfere with the state stored in some memory cells that are in electronic communication with the access line. Therefore, a rewrite operation or a refresh operation can be performed on one or more memory cells that may not be accessed.

[0068] Figure 3A and 3B An example of nonlinear electrical properties of a ferroelectric memory cell with hysteresis curves 300-a and 300-b according to various examples disclosed herein is illustrated. Hysteresis curves 300-a and 300-b illustrate example ferroelectric memory cell write and read processes, respectively. Hysteresis curves 300-a and 300-b depict the nonlinear electrical properties of a ferroelectric memory cell according to a voltage difference V stored in a ferroelectric capacitor (e.g., reference Figure 2 The charge Q on capacitor 240) is described.

[0069] Ferroelectric materials are characterized by a spontaneous electric polarization, that is, they maintain a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. The electrical polarization within a ferroelectric capacitor causes a static charge at the surface of the ferroelectric material and attracts an opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electrical polarization can be maintained for a relatively long time (even indefinitely) in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to capacitors used in, for example, DRAM arrays. This can reduce the need to perform refresh operations.

[0070] In some cases, the ferroelectric memory cell array may include one or more memory blocks, wherein the corresponding memory blocks may represent the smallest sub-array or compact group of adjacent memory cells that are not interrupted (e.g., by a socket or other separation). In addition and as described in further detail herein, a group of sequential memory blocks may be arranged in a direction (e.g., linearly) and may include one or more memory blocks located at the edge of the group, wherein the edge memory block is electrically connected to another memory block in the group. It should be noted that when referring to a memory block located at the edge, such memory blocks may be similarly referred to herein as being located at a boundary, periphery, edge, critical or other similar terms, and it should be understood that these terms are interchangeable. Such edge memory blocks may also include capacitive components dedicated to edge memory blocks and capable of balancing the load of access lines associated with edge memory blocks. More specifically, the capacitive component may include a capacitor that balances the capacitive load output from a driver coupled to one or more ferroelectric memory cells (e.g., via a word line). In such cases, the capacitive load added by the capacitive component can correspond to the capacitance of one or more ferroelectric memory cells of the edge memory block.In other cases, the capacitance of the capacitive component can be configured based on one or more other components within the memory device.

[0071] Hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of a capacitor. For example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Similarly, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. In addition, the voltage in hysteresis curves 300-a and 300-b represents the voltage difference across the capacitor and is directional. For example, a positive voltage can be achieved by applying a positive voltage to the terminal in question (such as a cell plate) and maintaining the second terminal (such as the bottom of the cell) at ground (or about zero volts (0V)). A negative voltage can be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal, that is, a positive voltage can be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to produce the voltage difference shown in hysteresis curves 300-a and 300-b.

[0072] As depicted in hysteresis curve 300-a, the ferroelectric material can maintain positive or negative polarization with zero voltage difference, resulting in two possible charge states: charge state 305 and charge state 310. Figure 3A and 3B In the example of , charge state 305 represents a logical 0 and charge state 310 represents a logical 1. In some examples, the logical values ​​of the respective charge states can be inverted to accommodate other schemes for operating the memory cell.

[0073] A logical 0 or 1 can be written to a memory cell by controlling the electrical polarization of the ferroelectric material and, therefore, the charge on the capacitor terminals, via an applied voltage. For example, applying a net positive voltage 315 across the capacitor causes charge to accumulate until charge state 305-a is reached. After removing voltage 315, charge state 305-a changes along path 320 until it reaches charge state 305 at zero voltage. Similarly, charge state 310 is written by applying a net negative voltage 325, which results in charge state 310-a. After removing negative voltage 325, charge state 310-a changes along path 330 until it reaches charge state 310 at zero voltage. Charge states 305-a and 310-a may also be referred to as remanent polarization (Pr) values, i.e., the polarization (or charge) that remains after an external bias (e.g., voltage) is removed. The coercive voltage is the voltage at which the charge (or polarization) is zero.

[0074] To read or sense the storage state of a ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge Q changes, and the extent of the change depends on the initial charge state, i.e., the final stored charge (Q) depends on the initial stored charge state 305-b or 310-b. For example, hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. A voltage 335 may be applied across capacitor 240, as shown in FIG. Figure 2 Discussion. In other cases, a fixed voltage may be applied to the cell plate, and although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may change along path 340. Likewise, if charge state 310-b was initially stored, it changes along path 345. The final position of charge state 305-c and charge state 310-c depends on one or more factors including the specific sensing scheme and circuitry.

[0075] In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to a digit line and voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. The voltage measured at the sensing component may not be equal to voltage 335, but may depend on the voltage of the digit line. Therefore, the position of the final charge states 305-c and 310-c on the hysteresis curve 300-b may depend on the capacitance of the digit line and may be determined by load line analysis, i.e., charge states 305-c and 310-c may be defined relative to the capacitance of the digit line. Therefore, the voltage of the capacitor (voltage 350 or voltage 355) may be different and may depend on the initial state of the capacitor.

[0076] The initial state of the capacitor can be determined by comparing the digital line voltage to a reference voltage. The digital line voltage can be the difference between voltage 335 and the final voltage across the capacitor (voltage 350 or voltage 355), i.e., the difference between voltage 335 and voltage 350 or the difference between voltage 335 and voltage 355. The reference voltage can be generated so that its magnitude is between two possible voltages of two possible digital line voltages to determine the storage logic state, i.e., if the digital line voltage is higher or lower than the reference voltage. After comparison by the sensing component, it can be determined whether the sensed digital line voltage is higher or lower than the reference voltage, and the storage logic value (i.e., logic 0 or 1) of the ferroelectric memory cell can be determined.

[0077] In some cases, the ferroelectric memory cell may maintain an initial logic state after a read operation. For example, if charge state 305-b is stored, the charge state may change to charge state 305-c along path 340 during a read operation, and after removing voltage 335, the charge state may return to initial charge state 305-b by changing along path 340 in the opposite direction. In some cases, the ferroelectric memory cell may lose its initial logic state after a read operation. For example, if charge state 310-b is stored, the charge state may change to charge state 305-c along path 345 during a read operation, and after removing voltage 335, the charge state may relax to charge state 305-b by changing along path 340.

[0078] Hysteresis curve 300-b illustrates an example of reading a memory cell configured to store charge state 305-b and charge state 310-b. For example, read voltage 335 may be applied as a voltage difference via digit line 215 and plate line 220, as shown in FIG. Figure 2 Description. Hysteresis curve 300-b may illustrate a read operation in which read voltage 335 is a negative voltage difference Vcap (e.g., where Vbottom-Vplate is negative). A negative read voltage across the capacitor may be referred to as a "plate high" read operation in which plate line 220 is initially brought to a high voltage and digit line 215 is initially at a low voltage (e.g., ground voltage). Although read voltage 335 is shown as a negative voltage across ferroelectric capacitor 240, in an alternative operation, the read voltage may be a positive voltage across ferroelectric capacitor 240, which may be referred to as a "plate low" read operation.

[0079] When memory cell 205 is selected (e.g., by activating reference Figure 2When the switching element 245 described above is switched, a read voltage 335 can be applied across the ferroelectric capacitor 240. After the read voltage 335 is applied to the ferroelectric capacitor 240, charge can flow into or out of the ferroelectric capacitor 240 via the digit line 215 and the plate line 220, and can result in different charge states depending on whether the ferroelectric capacitor 240 is in the charge state 305-a (e.g., logic 1) or in the charge state 310-a (e.g., logic 0).

[0080] Figure 4A and 4B Examples of memory blocks 400-a and 400-b supporting word line capacitance balancing according to examples disclosed herein are illustrated, respectively. According to the techniques disclosed herein, a memory device may include a number of memory blocks (e.g., patches), wherein each of the memory blocks includes an array portion and a circuit portion. For each memory block, the array portion may include a number of memory cells (e.g., memory cell subarrays), and the circuit portion may include circuitry for operating the memory cells (e.g., layers) of the array portion. Such circuitry may include driver circuitry, sensing circuitry, or the like, and may include circuitry included in Figure 4A and 4B For reference Figure 4A and 4B Describes the various components.

[0081] For example, a memory device may include a plurality of memory blocks in a sequence, row, or other configuration. In some examples, circuit systems or circuit components may be shared between corresponding blocks at a memory device, such as between adjacent blocks in a sequence of memory blocks. In such cases, control circuit systems for sensing the timing of components may be shared by adjacent memory blocks. In other cases, such circuit systems may be dedicated to some memory blocks. In particular, based on the location of the memory blocks, the memory blocks may be configured with circuit systems configured for specific locations of the memory blocks. In some cases, corresponding drivers may be used to drive circuit systems shared by several adjacent memory blocks.

[0082] In some cases, adjacent memory blocks may experience different loads (e.g., capacitive loads) based on their respective positions in a sequence of memory blocks. For example, a memory block located at a boundary or edge of a sequence of memory blocks may share circuitry with only one other memory block in the sequence. Thus, an edge memory block may experience a different (e.g., less) load than an individual (e.g., default) memory block that is not located at the edge and shares circuitry with more than one other memory block in the sequence.

[0083] As an example, Figure 4A4. The example of memory block 400-a is illustrated, which may be a memory block located at a boundary or edge of a sequence of memory blocks. Memory block 400-a may be coupled to another memory block that is not located at the edge of the sequence of memory blocks (e.g., reference Figure 4B Memory block 400-b is depicted, which may be referred to herein as a default memory block). Memory block 400-a may contain a driver 415-a, which may be an example of an inverter, a word line decoder, or an amplifier (such as a current sense amplifier), or the like.

[0084] In some cases, driver 415-a may receive signals from access lines 405-a and 410-a, which may correspond to source and gate signals of driver 415-a, respectively. The output of driver 415-a may be coupled to word line 420-a accordingly, which may provide signaling to memory cells 425-a and 430-a of memory block 400-a. In some cases, the source signal received on access line 405-a may be a signal output from a separate driver associated with a different memory block, or may be part of a shared circuit system between adjacent memory blocks. In one example, a sequence of memory blocks may include multiple segments and multiple sets of shared circuit systems. However, at memory block 400-a, there may be no additional circuit systems shared between subsequent memory blocks (because there are no subsequent memory blocks in the sequence).

[0085] Driver 415-a may output a number of signals to drive current onto word line 420-a. In some examples, the signals output from driver 415-a may be associated with signals obtained from access lines 405-a and 410-a. In some cases, memory cells 425-a and 430-a may be a single memory cell, or may correspond to different levels (or layers) of memory cells. Memory cells 425-a and 430-a may contribute to a load (e.g., a capacitive load) present at driver 415-a and word line 420-a. Thus, the capacitive load may be based on the number of memory cells coupled to word line 420-a. In some cases and as described in further detail below, memory block 400-a may be adaptably configured to mitigate inconsistencies in capacitive loading on word line 420-a due to the location of memory block 400-a (e.g., relative to other memory blocks, such as memory block 400-b). For example, memory block 400-a may be configured to include a load balancing component 445 that is operable to balance the load on word line 420-a with the loads on other word lines coupled to other sub-arrays (e.g., the load on word line 420-b of memory block 400-b, as described below with reference to Figure 4BIn some cases, the load balancing component may be an example of a capacitor, an RC circuit, or other component that may be coupled to the circuitry of the memory block 400-a in various ways (e.g., as described below with reference to Figure 5A and 5B As an example, a load balancing component may additionally or alternatively be coupled to access line 405-a and may add a load to the input of driver 415-a to balance the load of word line 420-a. In any case, the load balancing component may increase the load of the access line coupled to the memory cells of the memory block.

[0086] Figure 4B is an example of a memory block 400-b (eg, a default memory block), which may be located between two other memory blocks in a sequence (rather than at a boundary or edge of a sequence of memory blocks, and as described in reference to Figure 4C In some examples, memory block 400-b may be coupled to two other default memory blocks in the sequence, or may alternatively be coupled to one other default memory block and one edge memory block (e.g., memory block 400-a). Figure 4A 1. As described, memory block 400-b may include a driver 415-b coupled to access line 405-b that provides a source signal (e.g., from another driver, decoder, or inverter) and access line 410-b that provides a gate signal (e.g., associated with a reference voltage). In addition, in other examples, the source signal received on access line 405-b may be a signal output from a separate driver associated with a different memory block, or may be part of a shared circuit system between adjacent memory blocks. In one example, a sequence of memory blocks may include multiple segments and multiple sets of shared circuit systems. At memory block 400-b, the circuit system may be shared between adjacent blocks.

[0087] Driver 415-b may output a number of signals to drive current onto word line 420-b. Word line 420-b may be coupled to one or more memory cells, such as memory cells 425-b, 430-b, 435-b, and 440-b. In some cases, memory cells 425-b, 430-b, 435-b, and 440-b may be a single memory cell, or may alternatively be respective layers of memory cells. In some examples, memory cells 425-b and 430-b may constitute a first memory block (or first sub-array), and memory cells 435-b and 440-b may constitute a second memory block (or second sub-array), wherein circuitry including, for example, driver 415-b and word line 420-b may be shared between the first memory block and the second memory block. Thus, memory cells 425-b, 430-b, 435-b, and 440-b can contribute to a load (e.g., a capacitive load) present at word line 420-b, and the load can be based on the number of memory cells coupled to word line 420-b. As illustrated, the capacitive load on word line 420-b can be greater than (e.g., twice) the capacitive load on word line 420-a (see FIG. 1 ). Figure 4A 4. Description of the drawings) because word line 420-b may be coupled to two adjacent memory blocks, while word line 420-a may be coupled to one adjacent memory block. In some cases, load balancing component 445 may be configured based on the load experienced by word line 420-b (e.g., based on load contributions (capacitive or otherwise) from memory cells 425-b, 430-b, 435-b, and 440-b).

[0088] The load difference experienced by word lines 420-a and 420-b at edge memory block 400-a and default memory block 400-b can present many challenges to operating a memory device. For example, the load difference can cause the edge memory block to operate according to a resistance-capacitance (RC) time delay that is different from (e.g., faster than) the default block. In some cases, a smaller load (compared to default memory block 400-b) present at edge memory block 400-a can result in a faster RC time delay at edge memory block 400-a. The memory block delay time difference across the edge and default memory blocks can cause many inconsistencies in device operation. For example, an inconsistent increase in RC delay can induce changes in other parameters such as reference timing and sensing operations. Therefore, configuring the edge memory block to operate in a manner similar to the default memory block can provide many benefits.

[0089] Figure 4CAn example of a group of memory blocks 401 supporting word line capacitance balancing according to examples disclosed herein is illustrated. In particular, the memory block group 401 shows a sequence of adjacent memory blocks 450 (e.g., memory blocks 450-a through 450-n) that each include a subarray of memory cells 455. In addition, the memory block group 401 may include one or more edge memory blocks, such as edge memory block 450-a and edge memory block 450-n, which may be reference Figure 4A The memory block 400-a described and / or referenced Figure 5A and 5B 4. In addition, the memory block group 401 may include one or more default memory blocks, such as default memory blocks 450-b to 450-e, which may each be a reference Figure 4B 4. Some memory blocks 450 in the memory block group 401 may share circuitry, such as one or more drivers 460 and word lines 465. For example, each of the default memory blocks 450-b and 450-c may share the same driver 460-b and word line 465-b for the memory cells associated with the default memory blocks 450-b and 450-c.

[0090] As described herein, edge memory blocks (e.g., memory blocks 450-a and 450-n) may further include additional load balancing components 470 (e.g., load balancing component 470-a and load balancing component 470-b). Each load balancing component 470 may be a reference Figure 4A The examples of load balancing components 445 described herein and may also be referenced Figure 5A and 5B 4. The capacitive components 530-a and 530-b are described in detail. For example, the load balancing component may include a capacitor or an RC circuit or other circuitry that adds a load (e.g., a capacitive load) to the word line 465. By including a load balancing component 470 (e.g., a capacitive component) at the edge memory blocks 450-a and 450-n of the memory block group, the capacitive load of the word lines 465-a and 465-n at the edge memory blocks can be balanced with the capacitive load at the word lines 465-b and 465-c of the default memory blocks 450-b through 450-e. In some examples, the load balancing component can be configured based on components included in or coupled to the sub-arrays of the memory cells 455 of each memory block 450 to achieve consistent operation (e.g., the same RC delay) across the memory block group 401.

[0091] Figure 5A and 5B1 and 2 illustrate examples of memory blocks 500-a and 500-b supporting word line capacitance balancing according to examples disclosed herein. Memory blocks 500-a and 500-b may illustrate addition of memory blocks to edge memory blocks (e.g., reference Figure 4A An example of a capacitive component of a memory bank 400 - a ) is depicted that achieves a balanced capacitive load across a group of memory banks.

[0092] For example, Figure 5A is an example of a memory block 500-a, which may be a memory block located at a boundary or edge of a sequence of memory blocks. In some examples, the memory block 500-a may be associated with a default memory block (e.g., a reference Figure 4B Memory block 500-a may further include one or more drivers 505-a and 520-a, which may be examples of inverters or amplifiers (e.g., current sense amplifiers). In some cases, driver 505-a may drive a signal on access line 510-a, and driver 520-a may receive a signal using access line 510-a. Additionally, driver 520-a may receive a number of other signals as inputs using access line 515-a. In some cases, driver 505-a may be associated with different memory blocks, or may be part of shared circuitry between memory blocks.

[0093] Driver 520-a can output a signal to drive a current onto word line 525-a, where word line 525-a can be coupled to one or more memory cells or memory cell layers. The memory cells can contribute to a load (e.g., a capacitive load) present at word line 525-a. The load can be based on the number of memory cells coupled to word line 525-a, and in some examples can be different from (e.g., less than) the load experienced at associated word lines coupled to other memory blocks that are not located at the edge of the sequence of memory blocks.

[0094] In one example, a sequence of memory blocks may include multiple segments and a shared circuit system group. In some cases, a sequence of memory blocks includes several (e.g., seven) adjacent sub-arrays or blocks, each of which includes an associated circuit system located below one or more of the blocks. In some cases, the circuit system may be shared between adjacent memory blocks in the sequence, and in other cases, the circuit system may be dedicated to a given memory block in the sequence. For example, the first memory block and the last memory block in the sequence (e.g., an edge memory block) may be configured with a specific start or termination component so that the associated circuit system remains consistent between different memory blocks in the array. Some circuit components (e.g., a word line decoder of a sequence of blocks) may be shared between two adjacent blocks in a memory device. However, the first and last patches may include word line decoders and termination components of other shared circuit systems that cannot be shared across the edge of the array. In another embodiment, the termination component may be a separate edge array or edge block that can be configured based on the location of the memory block.

[0095] In some cases, the word lines (e.g., word line 525-a) and drivers (e.g., driver 520-a) of the edge blocks may be coupled with capacitor 530-a so that the word line load at the edge block is the same as the word lines and drivers coupled with the default block. The word lines and drivers at the default memory block may drive word lines associated with two neighboring blocks, where driver 520-a of the edge block may drive one word line 525-a associated with one neighboring block. However, word line 525-a may be coupled with a capacitive load (e.g., capacitor 530-a) that is equal to the capacitive load contributed by the additional blocks. In some examples, the additional capacitive load may balance the load between the default block and the edge block so that the capacitive load is the same across all blocks in the sequence of blocks.

[0096] The difference in capacitive load present at the word lines of the default and edge blocks may additionally cause a difference in RC delay. In some cases, additional capacitive load may be coupled with the driver 520-a at the edge memory block to match the RC delay and associated load at the corresponding word line of the default block. In some examples, the value of the capacitive load contributed by a memory cell to a word line may be represented by C. This capacitance value may be added such that the load contributed by 2 memory cells coupled to the word line is 2C, the load contributed by 3 memory cells is 3C, and so on. Figure 5A In the example of , the additional load may be a capacitor 530-a placed at the word line 525-a. To balance the word lines of the edge blocks, a capacitor may be used to add an additional capacitive load (e.g., 2C). The capacitive load at the word line 525-a may also be modified by other methods, such as including an RC circuit or other types of capacitive components not explicitly described herein.

[0097] Figure 5B is another example of a memory block 500-b, which may be a memory block located at a boundary or edge of a sequence of memory blocks. In some examples, the memory block 500-b may be coupled to a default memory block (e.g., reference Figure 4B 500-b). Memory block 500-b may include 520-b, where another driver 505-b may drive a source signal or current on access line 510-b, and driver 520-b may receive a signal using access line 510-b. Additionally, driver 520-b may receive another input signal, such as a gate signal, on access line 515-b. In some cases, driver 505-b may be associated with a different memory block, or may be part of shared circuitry between memory blocks.

[0098] Driver 520-b may output a number of signals to drive current onto word line 525-b. Word line 525-b may be coupled to one or more memory cells or memory cell layers. Memory cells may contribute to a load (e.g., a capacitive load) present at word line 525-b. The load may be based on the number of memory cells coupled to word line 525-b, and in some examples may be different (e.g., less than) the load experienced at associated word lines coupled to other memory blocks that are not located at the edge of the sequence of memory blocks.

[0099] The difference in capacitive load present at the word lines of the default and edge blocks may additionally cause RC delay differences. In some cases, for example, the RC delays at the respective word lines may be matched by adding an additional capacitive load (e.g., 2C) to the driver 505-b of the edge memory block. Figure 5B In the example of , the additional load may be capacitor 530 - b placed at access line 510 - b .

[0100] Figure 6 An example of a voltage timing diagram 600 that supports word line capacitance balancing according to examples disclosed herein is illustrated. The voltage timing diagram 600 can illustrate the voltage value trends of various signals at a memory device over time. In some cases, the gate signal 605 can be a signal input at the gate of a word line driver, and can be used, for example, for reference Figure 4A , 4B , 5A and 5B described access lines 410 and 515. In some cases, the source signal 610 may use the reference Figures 4A to 5B The source signal 610 may be transmitted via the access lines 405 and 510 described above. In some cases, the source signal 610 may drive a word line, or may be another signal output from a driver of an access line. In addition, the word line signal 615 may use a reference Figures 4A to 5B The word lines 420 and 525 are described for transmission.

[0101] The voltage timing diagram 600 shows a voltage associated with a word line signal 615 that follows (e.g., tracks) the voltage of a source signal 610 over time at a memory block. For a default memory block, there may be a voltage and time difference between the source signal 610 and the word line signal 615. In some cases, this difference may be attributed to voltage drops and corresponding delays at various drivers coupled to the source line and the word line. However, the voltage timing diagram 600 may represent the same voltage tracking for both the default memory block and the boundary memory block, which include load balancing components (e.g., capacitive components) coupled to the drivers of the word lines and the memory cells of the boundary memory block, as described herein. In other words, even though the boundary memory block may be configured differently (e.g., located at an edge and coupled to one other memory block), the added capacitive load may achieve the same voltage tracking for the boundary memory block as the default memory block.

[0102] In some cases, additional resistance may be added to the driver of the source signal, or alternatively, additional capacitive loads (such as capacitors) may be added to the source signal. In some examples, adding additional resistance or additional capacitive loads at the source line that transmits the source signal may minimize the voltage and time difference between the source signal 610 and the word line signal 615. This added resistance or capacitance of the edge memory block may also enable the RC delay of the edge memory block to be the same as the RC delay of the default memory block. In other words, the word line signal 615 may track the source signal 610 faster by adding additional capacitors, and may provide a tighter match between the source signal 610 and the word line signal 615.

[0103] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, portions from two or more of the methods may be combined.

[0104] An apparatus is described. The apparatus may include: a memory block located at a boundary of a group of memory blocks and including a memory cell array; a word line coupled to the memory cell array and a driver, the word line being associated with a total capacitive load; and a capacitive component coupled to the driver to adapt a load output from the driver to the memory cell array, the load including at least a portion of the total capacitive load.

[0105] In some examples, the group of memory blocks may include operations, features, components, or instructions for: a first subset of memory blocks, each memory block in the first subset being adjacent to two other memory blocks in the group; and a second subset of memory blocks, each memory block in the second subset being adjacent to one other memory block in the group, wherein the second subset includes the memory blocks located at the boundary.

[0106] In some examples, the memory blocks at the boundary share electrical connections with memory blocks in the first subset. In some examples, each memory block in the first subset shares electrical connections with two memory blocks in the first subset or with a first memory block in the first subset and a second memory block in the second subset.

[0107] In some examples, the capacitive component may be associated with a first capacitance that is greater than a second capacitance of a memory cell in the memory cell array. In some examples, the first capacitance may be twice the second capacitance. In some examples, each memory block in the first subset may be configured according to a first RC delay, and each memory block in the second subset may be configured according to a second RC delay. In some examples, the first RC delay may be longer than the second RC delay.

[0108] In some examples, the total capacitive load includes capacitance associated with the word line and additional capacitance associated with the capacitive component. In some examples, the capacitive component includes a capacitor or an RC circuit. In some examples, the load includes a capacitive load added to the input of the driver and includes at least a portion of the total capacitive load. In some examples, the capacitive component balances the load output from the driver based on a load common to a group of word lines of the memory cell array. Some examples of the device may include a group of drivers, wherein each driver in the group of drivers may be associated with at least two adjacent memory blocks in the group of memory blocks.

[0109] In some examples, a first word line associated with a first memory block in the first subset of memory blocks has the same total capacitive load as a second word line associated with a second memory block in the second subset of memory blocks, the second word line and the second memory block being coupled with the capacitive component.

[0110] An apparatus is described. The apparatus may include: a first line coupled to an input of a driver; a second line coupled to an output of the driver, the second line being associated with a total capacitive load; a group of memory cells coupled to the second line; and a capacitive component coupled to the second line, the capacitive component adapting a load output from the driver to the group of memory cells, the load comprising at least a portion of the total capacitive load.

[0111] In some instances, the second line comprises a word line of the group of memory cells. In some instances, the group of memory cells comprises a memory block located at a boundary of a sequence of memory blocks. In some instances, the capacitive component adds a first capacitance to the total capacitive load at the second line, the first capacitance being the same as a second capacitance from the group of memory cells. In some instances, the capacitive component increases at least a portion of the total capacitive load output from the driver. In some instances, the total capacitive load associated with the first line is the same as the total capacitive load associated with the second line, the second line being coupled to the capacitive component.

[0112] An apparatus is described. The apparatus may include: a set of memory blocks of a memory array, wherein a first memory block in the set of memory blocks is configured as a memory block of a first type that shares an electrical connection with two other memory blocks in the memory array, and wherein a second memory block in the set of memory blocks is configured as a memory block of a second type that shares an electrical connection with one other memory block in the memory array; and a capacitive component that accommodates at least a portion of a total capacitive load to the second memory block.

[0113] In some examples, each of the first memory block and the second memory block includes a driver coupled to a word line, each driver driving at least a portion of the total capacitive load at the word line, and wherein a first load at a first word line of the first memory block can be the same as a second load at a second word line of the second memory block based on the capacitive component.

[0114] In some examples, the capacitive component can be coupled to a driver of the second memory block, and wherein the second load can adapt an output from the driver to the second memory block based on the capacitive component. In some examples, the first memory block is associated with a first RC delay, and the second memory block can be associated with a second RC delay that matches the first RC delay based on the capacitive component.

[0115] In some examples, the set of memory blocks extends linearly in a direction on the memory array, and wherein a set of memory blocks of the first type may be bounded by a memory block of the second type. In some examples, the first memory block shares the electrical connection with two corresponding memory blocks configured as the first type or a memory block configured as the first type and a memory block configured as the second type. Some examples may further include that one or more memory blocks configured as the second type may be located at an edge of the set of memory blocks.

[0116] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0117] As used herein, the term "virtual ground" refers to a node of a circuit that maintains a voltage of approximately zero volts (0V) but is not directly coupled to ground. Thus, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" means connecting to approximately 0V.

[0118] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components may be considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0119] The term "coupling" refers to a condition that transitions from an open circuit relationship between components (where signals are currently unable to be transmitted between components through conductive paths) to a closed circuit relationship between components (where signals can be transmitted between components through conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between other components through conductive paths that previously did not allow signals to flow.

[0120] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components from one another, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0121] As used herein, the term "layer" refers to a stratum or sheet of a geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer may include different elements, components, and / or materials. In some cases, a layer may be composed of two or more sub-layers. In some figures, two dimensions of a three-dimensional layer are depicted for illustration.

[0122] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0123] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0124] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0125] In the accompanying drawings, similar components or features may have the same reference symbol. In addition, various components of the same type may be distinguished by following the reference symbol with a dash and a second symbol that distinguishes the similar components. If only the first reference symbol is used in the specification, the description may apply to any of the similar components having the same first reference symbol, regardless of the second reference symbol.

[0126] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0127] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of the software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. In addition, as used herein (included in the claims), the "or" used in a list of items (e.g., a list of items starting with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on..." should not be interpreted as a reference conditional closed set. For example, without departing from the scope of the present invention, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same manner as the phrase "based at least in part on..."

[0128] The description herein is provided to enable one skilled in the art to make or use the present invention. Various modifications of the present invention will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present invention. Therefore, the present invention is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, include: a plurality of memory blocks, comprising a first memory block and a second memory block, the second memory block being located at a boundary of the plurality of memory blocks and comprising a memory cell array; a word line coupled to the memory cell array and the driver, the word line being associated with a second capacitive load; and a capacitive component coupled to the word lines and the output of the driver and isolated from the first memory block, the capacitive component adapting a load output from the driver to the memory cell array based at least in part on a difference between the second capacitive load and a first capacitive load associated with one or more word lines coupled to the first memory block, the load including at least a portion of the second capacitive load.

2. The memory device according to claim 1 , wherein the plurality of memory blocks comprises a sequence of memory blocks extending linearly in one direction and further include: a first subset of memory blocks, each memory block in the first subset being adjacent to two other memory blocks in the plurality of memory blocks, wherein the first subset includes the first memory block; and A second subset of memory blocks, each memory block in the second subset being adjacent to one other memory block in the plurality of memory blocks, wherein the second subset includes the second memory block located at the boundary.

3. The memory device of claim 2, wherein the second memory bank at the boundary shares an electrical connection with memory banks in the first subset.

4. The memory device of claim 2, wherein each memory block in the first subset shares an electrical connection with two memory blocks in the first subset or a memory block in the first subset and a memory block in the second subset.

5. The memory device of claim 1, wherein the capacitive component is associated with a first capacitance that is greater than a second capacitance of a memory cell in the memory cell array. The memory device of claim 5 , wherein the first capacitance is twice the second capacitance.

7. The memory device of claim 1, wherein the first memory block is configured according to a first RC delay and the second memory block is configured according to a second RC delay.

8. The memory device of claim 7, wherein the first RC delay is longer than the second RC delay.

9. The memory device of claim 1, wherein the second capacitive load comprises a capacitance associated with the word line and an additional capacitance associated with the capacitive component.

10. The memory device of claim 1, wherein the capacitive component comprises a capacitor or a resistor-capacitor (RC) circuit.

11. The memory device of claim 1, wherein the load is added to an input of the driver and comprises at least a portion of the second capacitive load.

12. The memory device of claim 1, wherein a first word line associated with the first memory block has a same total capacitive load as the word line coupled to the capacitive component, the first memory block being isolated from the capacitive component.

13. The memory device of claim 1, wherein the capacitive component balances the load output from the driver based at least in part on a load common to a plurality of word lines of the memory cell array.

14. The memory device of claim 1, further comprising: include: A plurality of drivers, wherein each driver of the plurality of drivers is associated with at least two adjacent memory blocks of the plurality of memory blocks.

15. A memory device, include: a first line coupled to an input of the driver; a second line coupled to the output of the driver, the second line being associated with a second capacitive load; a first plurality of memory cells and a second plurality of memory cells, the second plurality of memory cells being coupled to the second line; and a capacitive component coupled to the second line and isolated from the first plurality of memory cells, the capacitive component adapting a load output from the driver to the second plurality of memory cells based at least in part on a difference between the second capacitive load and a first capacitive load associated with one or more word lines coupled to the first plurality of memory cells, the load comprising at least a portion of the second capacitive load.

16. The memory device of claim 15, wherein the second line comprises a word line for the second plurality of memory cells.

17. The memory device of claim 15, wherein the second plurality of memory cells comprises a memory block located at a boundary of a sequence of memory blocks.

18. The memory device of claim 15, wherein the capacitive component adds a first capacitance to the second capacitive load at the second line, the first capacitance being the same as a second capacitance from the second plurality of memory cells.

19. The memory device of claim 15, wherein a total capacitive load associated with the first line is the same as the total capacitive load associated with the second line, the second line being coupled with the capacitive component.

20. The memory device of claim 15, wherein the capacitive component increases at least a portion of the second capacitive load.

21. A memory device, include: a plurality of memory blocks of a memory array, wherein a first memory block of the plurality of memory blocks is configured as a memory block of a first type that shares electrical connections with two other memory blocks of the memory array, and wherein a second memory block of the plurality of memory blocks is configured as a memory block of a second type that shares electrical connections with one other memory block of the memory array; and a capacitive component coupled to a driver of the second memory block and isolated from the first memory block, the capacitive component being based at least in part on a second memory line associated with an access line of the second memory block; At least a portion of the second capacitive load is adapted based on a difference between a capacitive load and a first capacitive load associated with an access line of the first memory block.

22. A memory device according to claim 21, wherein each of the first memory block and the second memory block includes a driver coupled to a word line, each driver driving at least a portion of a total capacitive load at the word line, and wherein a first load at a first word line of the first memory block is the same as a second load at a second word line of the second memory block at least partially based on the capacitive component.

23. The memory device of claim 21, wherein a second load adapts an output from the driver to the second memory bank based at least in part on the capacitive component.

24. The memory device of claim 21, wherein the first memory bank is associated with a first resistance-capacitance (RC) delay and the second memory bank is associated with a second RC delay that matches the first RC delay based at least in part on the capacitive component.

25. The memory device of claim 21, wherein the plurality of memory blocks extend linearly in a direction across the memory array, and wherein a group of memory blocks of a first type are delimited by memory blocks of the second type.

26. The memory device of claim 21, wherein the first memory block shares the electrical connection with two corresponding memory blocks configured as the first type or a memory block configured as the first type and a memory block configured as the second type.

27. The memory device of claim 21, wherein one or more memory blocks configured as the second type are located at an edge of the plurality of memory blocks.

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