A field emission cathode ultra-thin refractory metal grid and preparation method thereof

Abstract

The present invention discloses an ultra-thin refractory metal grid for a field emission cathode, comprising: a grid substrate, comprising a grid through-hole array in the central region of the grid substrate; a grid support ring, located on the grid substrate, and the two are welded together; wherein the material of the grid substrate is a refractory metal. The grid has an ultra-thin thickness and can be applied to the cold cathode of millimeter wave and terahertz vacuum electronic devices to achieve good comprehensive performance of the devices. The present invention also provides a method for preparing the ultra-thin refractory metal grid for a field emission cathode.

Description

Technical Field

[0001] The present invention relates to the field of vacuum microelectronics, and more specifically, to an ultra-thin refractory metal grid for a field emission cathode and a preparation method thereof. Background Art

[0002] Field emission cathodes do not require external heating energy and light energy. By simply applying a strong electric field to suppress the cathode surface potential barrier, the barrier height and width can be reduced, allowing the electrons in the emitter to escape through the tunnel effect. Compared with traditional thermal emission cathodes, field emission cold cathodes compatible with micromachining technology have the characteristics of low power consumption, small size, fast response speed, room temperature operation, and high current density, and are expected to be used in traditional vacuum electronic devices to achieve better performance.

[0003] The gate of the field emission cathode for extracting electrons mainly has two structural forms: a self-aligned integrated structure or a non-integrated external structure. The self-aligned integrated structure is represented by the Spindt cathode or other similar structure cathodes. The US invention patent with publication number US 6369496B1 describes Figure 1 As shown in the figure, the gates are all made by micro-machining technology, and the distance from the cathode emission surface is in micrometers or sub-micrometers, and the cathode emission array units correspond to the micro-gates one by one. However, due to process reasons, the structure of the integrated gate is difficult to achieve uniformity over a large area, and non-uniform emission will limit the increase in the total cathode current; and because the cathode-gate spacing is very close, it is easy to produce inter-electrode sparks, resulting in short-circuit failure of the emitter and the gate, and the overall reliability is not high.

[0004] Invention patents with publication numbers CN105428185A and CN105551911A describe non-integrated gate-controlled cathode structures, such as Figure 2 As shown in the figure, the lead-out grid is a metal sheet with a thickness of tens to hundreds of microns, less than 1 mm away from the cathode, the grid array aperture is tens to hundreds of microns, and the wire diameter is tens of microns. The precisely corresponding grid and cathode emitter array can effectively reduce the gate interception of electrons, reduce the gate heat dissipation, and improve the electron utilization efficiency. The farther the cathode emitter and the gate spacing can greatly reduce the risk of short circuit between the cathode and the gate. Non-integrated gate-controlled field emission cathodes are used in vacuum electronic devices and have good comprehensive advantages.

[0005] Given that high-frequency electromagnetic waves have the characteristics of high radiation frequency, small divergence angle and high signal-to-noise ratio, high-frequency vacuum electronic devices have obvious advantages in national economic development, security protection, scientific and technological innovation, as well as in defense fields such as radar detection, intersatellite high-speed communication, high-resolution imaging and electronic countermeasures. The development trend of vacuum electronic devices towards high-frequency ends such as millimeter waves, submillimeter waves and even terahertz waves is very obvious.

[0006] Millimeter wave and terahertz vacuum electronic devices are very small in size, which requires not only high processing accuracy and surface finish of tiny parts, but also a well-focused very fine electron beam, that is, a cathode with a small emission surface and high current density is desired. For non-integrated gate field emission cathodes, the smaller cathode emission surface requires a significant reduction in the grid aperture, grid wire diameter and grid thickness. For example, for a 220GHz vacuum electronic device, the typical design value of the cathode lead grid is a grid aperture of 80-120 microns, and a grid wire diameter and thickness of 20 microns. As the device frequency increases, the grid thickness will be further reduced from tens of microns to a few microns. As the size and thickness of the grid are greatly reduced, its corresponding heat capacity decreases, and the grid's ability to resist electron bombardment is weakened, so the grid material tends to be a high-temperature resistant refractory metal.

[0007] The typical processing technology for metal grids at present is to use laser drilling or photolithography. However, when the thickness of the metal sheet is reduced to tens to several microns, its strength is already poor. The flatness deformation caused by insufficient strength makes it difficult to ensure high-quality planar photolithography without support throughout the process. Even if the laser drilling method can be used in a reinforcement-before-processing manner, high temperature will still cause local deformation. This deformation, as well as the edge burrs and vaporized evaporation re-deposition caused by the process, cannot be ignored at this scale. Therefore, the thickness of the maturely prepared grids at present is basically not less than 50 microns.

[0008] The latest UV-LIGA process and wet etching silicon mold metal coating technology can achieve metal film structures from micrometers to millimeters. However, due to the limitations of stress and high temperature resistance of photoresist, metals prepared by UV-LIGA process can only be electroplated, and the processing materials are limited to copper, chromium, nickel and other electroplating materials, and it is difficult to involve refractory metals. Due to the etching inclination angle, wet etching of silicon molds cannot achieve complete anisotropy, that is, it cannot achieve steep gate hole sidewalls.

[0009] In view of this, it is indeed necessary to provide a stable structure for realizing an ultra-thin refractory metal grid and a method for preparing such a grid, which can be suitable for the cold cathode of millimeter-wave and terahertz vacuum electronic devices to achieve good comprehensive performance of the device. Summary of the invention

[0010] Based on the above facts, the first object of the present invention is to provide an ultra-thin refractory metal grid for a field emission cathode, which can have an ultra-thin thickness and can be suitable for the cold cathode of millimeter wave and terahertz vacuum electronic devices to achieve good comprehensive performance of the device.

[0011] The second object of the present invention is to provide a method for preparing an ultra-thin refractory metal grid for a field emission cathode, which effectively solves the problem in the prior art that it is still difficult to prepare an ultra-thin refractory metal grid for a field emission cathode.

[0012] In order to achieve the above first object, the present invention adopts the following technical scheme:

[0013] A field emission cathode ultra-thin refractory metal grid, comprising:

[0014] A grid substrate comprising a grid through-hole array in a central region of the grid substrate;

[0015] A grid support ring is located on the grid substrate, and the two are welded together;

[0016] Wherein, the material of the grid substrate is refractory metal.

[0017] Furthermore, the material of the grid substrate is selected from one of tungsten, molybdenum and tantalum.

[0018] Furthermore, the grid substrate has a thickness of 40 micrometers to 5 micrometers.

[0019] Furthermore, the grid support ring is located at the edge of the grid substrate, avoiding the grid through-hole array.

[0020] Furthermore, the inner ring of the grid support ring has an inclination angle of 30-70 degrees.

[0021] Furthermore, the grid support ring is made of refractory metal.

[0022] Furthermore, the grid support ring is made of tungsten.

[0023] Furthermore, the light transmittance of the gate through-hole array is 70%-90%.

[0024] Furthermore, in the gate through hole array, the shapes of the gate through holes are closely packed square, circular, triangular, regular hexagonal or spoke grid.

[0025] In order to achieve the above second purpose, the present invention adopts the following technical solutions:

[0026] A method for preparing an ultra-thin refractory metal grid for a field emission cathode comprises the following steps:

[0027] providing a composite substrate including a silicon device layer;

[0028] coating a photoresist on the silicon device layer;

[0029] Exposing and developing the photoresist to form a photoresist mold located in the center area of ​​the silicon device layer, the pattern of which corresponds one-to-one to the required gate through-hole array pattern;

[0030] Etching the exposed silicon device layer, and then removing the photoresist mold to obtain a silicon mold;

[0031] Depositing a refractory metal on the surface of the silicon mold;

[0032] Thinning the mixed layer formed by the silicon mold and the refractory metal until the thickness of the refractory metal reaches the required thickness of the grid substrate;

[0033] welding a grid support ring to the refractory metal;

[0034] The remaining silicon mold and the composite substrate residue are removed to obtain the field emission cathode ultra-thin refractory metal grid.

[0035] Furthermore, the composite substrate is an SOI wafer, and the structure is a silicon support layer / insulating layer / silicon device layer, or the composite substrate is a non-silicon support layer / silicon device layer structure.

[0036] Furthermore, the thickness of the silicon support layer or the non-silicon support layer is 400 microns to 1000 microns.

[0037] Furthermore, the thickness of the insulating layer is 1 micrometer to 2 micrometers.

[0038] Furthermore, the thickness of the silicon device layer is greater than the thickness of the required grid substrate, and the thickness of the silicon mold is greater than the thickness of the grid substrate.

[0039] Furthermore, the thickness of the silicon device layer is 45 microns to 5 microns.

[0040] Furthermore, the photoresist is a thick photoresist used in MEMS technology, preferably AZ4620 photoresist or KMPR photoresist.

[0041] Furthermore, the etching method is an inductively coupled plasma etching technology.

[0042] Furthermore, the deposition method is chemical vapor deposition.

[0043] Furthermore, the welding method is vacuum diffusion welding.

[0044] The beneficial effects of the present invention are as follows:

[0045] The field emission cathode ultra-thin refractory metal grid provided by the present invention realizes an ultra-thin grid substrate structure with a thickness of tens of microns to several microns. The grid support ring effectively keeps the ultra-thin grid substrate from being easily deformed, and can focus the extracted electron beam by relying on the inner ring inclination angle. The ultra-thin grid is combined with the grid hole aperture and grid wire diameter with correspondingly reduced size, which can meet the needs of devices with increasing frequencies. The grid is made of refractory metal material, which can withstand higher temperatures caused by electron bombardment and is not easily deformed and damaged, and can be better applied to the cold cathode of millimeter wave and terahertz vacuum electronic devices.

[0046] In the preparation method provided by the present invention, the ultra-thin grid substrate is completed by chemical vapor deposition on a nearly ideal flat substrate. The substrate is always firmly attached to the substrate during the entire process, and the high flatness ensures the high quality of the micro-machined graphics; the grid substrate is separated from the substrate only after it is firmly welded to the grid support ring, and its flatness is highly retained during the transfer process and the subsequent assembly process.

[0047] In the preparation method provided by the present invention, the through-hole array of the grid is directly deposited and formed on a silicon model etched by inductively coupled plasma, so that high-quality gate through-holes with steep characteristic dimensions precisely controlled can be formed, and edge burrs caused by the laser processing process and isotropic side corrosion inclination angles caused by the photolithography etching process will not be generated, and a refractory metal structure that cannot be achieved by UV-LIGA can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0049] Figure 1 A schematic diagram of an integrated self-aligned gate Spindt cathode structure is shown.

[0050] Figure 2 A schematic diagram of a non-integrated metal grid field emission cold cathode structure is shown.

[0051] Figure 3 The schematic diagram of the structure of the ultra-thin refractory metal grid for the field emission cathode of the present invention is shown.

[0052] Figures 3A-3G The present invention shows a schematic diagram of the preparation process of the ultra-thin refractory metal grid for the field emission cathode: 3A-providing a composite substrate containing a silicon device layer, 3B-coating a photoresist on the silicon device layer and exposing and developing, 3C-etching the silicon device layer and removing the resist to form a silicon mold, 3D-depositing a refractory metal grid material on the surface of the mold, 3E-grinding and polishing the deposited layer / silicon mold mixed layer to obtain a grid substrate, 3F-placing a machined grid support ring on the grid substrate and welding them together, 3G-etching to remove the support layer / insulating layer and silicon mold residue to obtain the grid.

[0053] Figure 1In the figure, the component numbers are respectively represented as: 101 - cathode base, 102 - cathode tip cone, 103 - insulating layer, 104 - gate substrate, 105 - gate through hole.

[0054] Figure 2 In the figure, the component numbers are respectively represented as: 201 - cathode substrate, 202 - cathode array, 203 - insulating layer, 204 - gate substrate, 205 - gate through hole.

[0055] Figure 3 , Figures 3A-3G In the figure, the component numbers are respectively represented as follows: 300 - field emission cathode ultra-thin refractory metal grid, 301 - support layer, 302 - insulation layer, 303 - silicon device layer, 304 - photoresist, 305 - silicon mold, 306 - gate deposition layer, 307 - grid substrate, 308 - grid support ring, 309 - gate through hole. DETAILED DESCRIPTION

[0056] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present invention.

[0057] Example 1

[0058] like Figure 3 As shown, this embodiment provides a field emission cathode ultra-thin refractory metal grid 300, which includes: a grid substrate 307, including a grid through hole array 309 in the central area of ​​the grid substrate 307; a grid support ring 308, located on the grid substrate 307, and the two are welded together; wherein the material of the grid substrate 307 is refractory metal.

[0059] Exemplarily, refractory metals suitable for the grid substrate 307 in this embodiment include, but are not limited to, tungsten, molybdenum, tantalum, etc. In this embodiment, molybdenum is preferred.

[0060] In this embodiment, the thickness of the grid substrate 307 ranges from 40 microns to 5 microns according to the frequency bands of millimeter wave and terahertz devices. Exemplary thicknesses include but are not limited to 35 microns to 5 microns, 35 microns to 10 microns, 35 microns to 15 microns, 35 microns to 20 microns, 30 microns to 5 microns, 30 microns to 10 microns, and the grid through hole array 309, in order to achieve the best electron extraction effect, the through hole shape is selected from close-packed square, circular, triangular, regular hexagonal or spoke grid shape, and the transmittance is 70%-90%. Combined with the preferred thickness of the grid substrate 307 of 20 microns, in this embodiment, the regular hexagonal through hole is preferred, the hexagonal side length is preferably 60 microns, the grid wire diameter is preferably 20 microns, and the corresponding transmittance is 70%. The area occupied by the grid through hole array 309 is determined according to the actual cold cathode area. In this embodiment, the preferred area is a circular area with a radius of 2 mm.

[0061] The grid support ring 308 is located at the edge of the grid substrate 307, avoiding the grid through-hole array 309. The grid support ring 308 and the grid substrate 307 are welded together, and its main function is to firmly support the grid substrate 307 to keep it flat and not deformed, to help dissipate heat and focus the extracted electron beam. Typically, the size of the grid support ring 308 is in the order of millimeters. In this embodiment, the grid support ring 308 preferably has an inner diameter of 5 mm at the bottom, an outer diameter of 9 mm at the bottom, and a support ring height of 2 mm.

[0062] The grid support ring 308 is preferably selected from materials suitable for vacuum devices such as tungsten, molybdenum, tantalum and stainless steel. In this embodiment, tungsten or molybdenum is preferred.

[0063] The inner ring tilt angle of the grid support ring 308 can affect the electric field distribution, thereby converging and extracting the electron beam. Typically, the inner ring tilt angle of the grid support ring 308 is in the range of 30-70 degrees. In this embodiment, the inner ring tilt angle is preferably 60 degrees.

[0064] like Figures 3A-3G As shown, an embodiment of the present invention further provides a method for preparing an ultra-thin refractory metal grid for a field emission cathode, the method comprising the following steps:

[0065] Step 1) providing a composite substrate 301 / 302 / 303 containing a silicon device layer 303 .

[0066] The composite substrate 301 / 302 / 303 is the basis of the entire process flow and is required to have high flatness, high parallelism and high finish. The support layer 301 in the composite substrate 301 / 302 / 303 is the entire process bearing layer. The materials that meet the requirements include silicon wafers, silicon oxide wafers, glass wafers and some metal substrates that have been precisely polished; the silicon device layer 303 is used to form a silicon mold 305, which is located on the surface of the composite substrate; the insulating layer 302 is used to isolate the support layer 301 and the silicon device layer 303. When the support layer 301 is made of non-silicon material, the insulating layer 302 can be omitted. In this embodiment, the composite substrate 301 / 302 / 303 is preferably a commercially available standard SOI substrate, that is, the support layer 301 and the silicon device layer 303 are both silicon, and the insulating layer 302 is silicon dioxide.

[0067] The typical thickness of the SOI substrate support layer 301 is 400 microns to 1000 microns, and in this embodiment, 500 microns is preferred; the typical thickness of the SOI substrate insulating layer 302 is 1 micron to 2 microns, and in this embodiment, 1 micron is preferred; the thickness of the silicon device layer 303 should be slightly larger than the required thickness of the grid substrate 307, and in this embodiment, 45 microns is preferred, and 22 microns is more preferred.

[0068] Step 2) coating photoresist 304 on the silicon device layer 303 and exposing and developing the same.

[0069] A photoresist 304 is applied to the central area of ​​the silicon device layer 303 and exposed and developed to form a photoresist 304 pattern, that is, a photoresist mold is formed, which serves as a mask for the subsequent silicon etching process to form a silicon mold 305 for depositing a gate metal layer 306. The shape and position of the photoresist 304 pattern correspond to the subsequent silicon mold 305 and the gate through-hole array 309. In this embodiment, the photoresist 304 is preferably a commercially available AZ4620 positive photoresist from Clariant. The typical range of thickness of AZ4620 positive photoresist in one spin coating is 3 microns to 10 microns, which can withstand a silicon etching process with a thickness of 300 microns to 1000 microns. In this embodiment, the thickness of the photoresist 304 is preferably 5 microns.

[0070] The exposure process of the photoresist 304 adopts a typical ultraviolet exposure technology, and a specific part of the photoresist 304 is exposed through mask masking, and through a subsequent development process, the exposed part is removed using the developer AZ400K of the AZ4620 photoresist, and the unexposed part is retained to form a photoresist 304 pattern. The photoresist 304 pattern corresponds to the gate through-hole array 309 pattern one by one. In this embodiment, the photoresist 304 pattern is a regular hexagonal column array, with a hexagonal side length of 60 microns, a column height of 5 microns, and a spacing of 20 microns between each column, which is equivalent to the wire diameter width of the gate through-hole array 309.

[0071] Step 3) etching the silicon device layer 303 and removing the photoresist to form a silicon mold 305.

[0072] The etching of the silicon device layer 303 and the removal of the photoresist to form the silicon mold 305 is performed by using the photoresist 304 pattern as a mask, etching the silicon device layer 303 until the insulating layer 302, and then removing the photoresist 304 pattern to obtain the silicon mold 305 (i.e., the silicon device layer remaining after etching, it can be seen that the thickness of the silicon mold 305 is the same as the thickness of the silicon device layer 303). The etching of silicon can be performed by isotropic wet etching, anisotropic wet etching and anisotropic dry etching. Considering that in order to obtain a grid through-hole array 309 with steep side walls, in this embodiment, the etching of the silicon device layer 303 is preferably performed by an inductively coupled plasma etching technology of anisotropic dry etching. The etching process uses the photoresist 304 pattern as a mask, and through the alternating effects of sulfur hexafluoride atmosphere etching and octafluorocyclobutane atmosphere protection, the etching penetrates the silicon device layer 303 and accurately terminates at the insulating layer 302, forming a silicon mold 305 with steep side walls and consistent height.

[0073] In this embodiment, the photoresist 304 masking layer is preferably removed by using the photoresist stripping agent AZ400T which is matched with the AZ4620 photoresist, and is immersed at room temperature until it is completely removed.

[0074] In this embodiment, the pattern of the silicon mold 305 corresponds to the pattern of the gate through hole array 309 one by one, and the thickness of the silicon mold 305 is higher than the thickness of the required grid substrate 307. The silicon mold 305 is preferably a regular hexagonal column array, with a hexagonal side length of 60 microns, a column height of 22 microns, and a spacing of 20 microns between each column, which is equivalent to the wire diameter width of the gate through hole array 309.

[0075] Step 4) depositing a refractory metal on the surface of the silicon mold 305 to form a gate deposition layer 306 .

[0076] The gate deposition layer 306 is formed by depositing a refractory metal on the surface of the silicon mold 305. The refractory metal material is deposited on the silicon mold 305 as a substrate. The gate deposition layer 306 formed exists in the pattern gap and surface of the silicon mold 305, and is used to form the grid substrate 307 later. In this embodiment, the gate deposition layer 306 is preferably molybdenum, and the deposition process is preferably a chemical vapor deposition method. The metal molybdenum deposition layer is generated by reacting a molybdenum hexafluoride atmosphere and a hydrogen atmosphere at a high temperature of about 500°C. The chemical vapor deposition process of refractory metals requires a relatively high temperature, so that the deposition mold cannot use the more typical photoresist material in the MEMS process, which is also the reason why the UV-LIGA process cannot be used in the preparation method of the present invention.

[0077] In order to ensure the preferred overall thickness of the grid substrate 307 (for example, 20 microns), over-deposition is preferably performed in this embodiment (that is, the deposited thickness is higher than the required thickness of the grid substrate 307) to ensure that the thickness of the gate deposition layer 306 is approximately higher than the required thickness of the grid substrate 307 (for example, 23 microns) and completely covers the silicon mold 305.

[0078] Step 5) Thinning the gate deposition layer 306 / silicon mold 305 mixed layer to obtain a grid substrate 307.

[0079] The thinning method is preferably grinding and polishing. The grinding process is to quickly reduce the thickness of the thin film layer to obtain a parallel and flat substrate surface, and the polishing process is to obtain a substrate surface with no micro-convex burrs and high finish by slightly removing the material. The high finish surface is necessary for the application of field emission cold cathode. In this embodiment, the grinding and polishing process is preferably a typical chemical mechanical polishing method in MEMS technology, which relies on large abrasive particles and high grinding disc speed to implement grinding, and small abrasive particles and low grinding disc speed to implement polishing.

[0080] In this embodiment, chemical mechanical grinding is preferably performed first to reduce the thickness of the gate deposition layer 306 / silicon mold 305 mixed layer to a thickness slightly higher than the required grid substrate 307, preferably 21 microns; and then chemical mechanical polishing is performed to obtain a smooth gate deposition layer 306 / silicon mold 305 mixed layer surface, and the thickness is controlled to the thickness required for the required grid substrate 307, preferably 20 microns, to obtain a grid substrate 307 with remnants of the silicon mold 305.

[0081] Step 6) Weld the grid support ring 308 and the grid substrate 307 together.

[0082] The purpose of welding the grid support ring 308 and the grid substrate 307 together is to stabilize the grid substrate 307 with the grid support ring 308 to ensure that it remains unchanged during subsequent processes and packaging applications. The grid support ring 308 is prepared by traditional mechanical processing in this embodiment. The welding method can typically use brazing, laser welding and diffusion welding with mature vacuum device processes. In this embodiment, considering that the grid support ring 308 and the grid substrate 307 are made of the same material, molybdenum, the welding process is preferably vacuum diffusion welding. Align the grid support ring 308 with the center of the grid through-hole array 309, place the grid support ring 308 on the grid substrate 307, fix it with a clamp, place them together in a vacuum to apply pressure and high temperature, and weld the grid support ring 308 and the grid substrate 307 together.

[0083] Step 7) etching and removing the support layer 301 / insulating layer 302 and the silicon mold 305 to obtain the grid 300 .

[0084] The etching to remove the remaining support layer 301 / insulating layer 302 and silicon mold 305 to obtain the grid 300 is to separate the prepared grid 300 from the substrate. The removal method is to dissolve the support layer 301 / insulating layer 302 and silicon mold 305 by wet etching, or only dissolve the remaining insulating layer 302 and silicon mold 305 in the process, so that the support layer 301 is peeled off from the grid 300.

[0085] The selection of etching solution should be considered to be able to react quickly and not damage the grid 300. In this embodiment, a 30% potassium hydroxide solution is preferably used to etch the support layer 301 and the silicon mold 305 residue, and a standard BOE solution is preferably used to etch the insulating layer 302 to complete the preparation of the grid 300.

[0086] This embodiment obtains a cold cathode grid of a terahertz vacuum electronic device formed by a grid support ring and a grid substrate. The grid support ring ensures that the ultra-thin grid substrate does not deform, and at the same time assists the grid in heat dissipation, and relies on a 60-degree inclination angle to influence the electric field to converge the extracted electron beam. The grid substrate is 20 microns thick, and the central area of ​​the substrate with a diameter of 4 mm is densely covered with a through hole array. The through hole shape is a regular hexagon with a side length of 60 microns, the grid wire diameter is 20 microns, and the corresponding light transmittance is 70%. The grid can be used for field emission cold cathodes with a cathode area diameter of 4 mm or less.

[0087] Example 2

[0088] Example 1 is repeated, except that, in step 2), the photoresist 304 formed by exposure and development has a square column shape with a side length of 80 microns and a spacing of 10 microns between each column; in step 3), the silicon device layer 303 is photoetched to form a silicon mold 305 with a square column shape with a side length of 80 microns and a spacing of 10 microns between each column. Other conditions remain unchanged. The result of the grid 300 obtained in this example is similar to that of Example 1, except that the gate transparent array hole 309 is a square hole array with a transmittance of 80%.

[0089] Example 3

[0090] Example 1 is repeated, except that in step 1), the thickness of silicon device layer 303 is changed to 12 microns; in step 4), the thickness of gate deposition layer 306 is changed to 13 microns; in step 5), the grinding thickness of gate deposition layer 306 / silicon mold 305 mixed layer is changed to 11 microns, and the polishing thickness is changed to 10 microns, and other conditions remain unchanged. The result of grid 300 obtained in this example is similar to that of Example 1, except that the thickness of grid substrate 307 is 10 microns.

[0091] The method of the present invention breaks through the limitations that conventional laser processing or photolithography etching methods can only produce grids with a thickness of more than 50 microns, and that the UV-LIGA process can only produce electroplating-related metal materials. It can produce ultra-thin refractory metal grids with any thickness in the range of 5-50 microns (for example, 5-20 microns), and the grid plane is not easy to deform, the surface finish is better than 100nm, and the edges of the through-hole array are steep, smooth and burr-free, which can meet the needs of cold cathodes in ultra-high frequency to terahertz vacuum electronic devices.

[0092] The grid made by this method, carbon nanotube cold cathode and metal anode form a triode for electron emission test. The results show that for a structure configuration with a cathode diameter of 4 mm, a grid thickness of 20 microns and a transmittance of 80%, when the electric field intensity drawn from the cathode surface is 5V / μm in a DC state, the anode collects 9.4 mA of current, the grid intercepts 3.7 mA of current, and the actual effective output current ratio can reach 71.8%, indicating that the grid can be used for field emission cold cathodes with a cathode area diameter of 4 mm or less. The grids obtained in other embodiments can also achieve similar effects and can be used for field emission cold cathodes with a cathode area diameter of 4 mm or less.

[0093] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. A method for preparing a field emission cathode refractory metal grid, characterized in that: The field emission cathode refractory metal grid comprises: A grid substrate comprising a grid through-hole array in a central region of the grid substrate; A grid support ring is located on the grid substrate, and the two are welded together; Wherein, the material of the grid substrate is refractory metal; The method for preparing the field emission cathode refractory metal grid comprises the following steps: providing a composite substrate including a silicon device layer; coating a photoresist on the silicon device layer; Exposing and developing the photoresist to form a photoresist mold located in the center area of ​​the silicon device layer, the pattern of which corresponds one-to-one to the required gate through-hole array pattern; Etching the exposed silicon device layer, and then removing the photoresist mold to obtain a silicon mold; Depositing a refractory metal on the surface of the silicon mold; Thinning the mixed layer formed by the silicon mold and the refractory metal until the thickness of the refractory metal reaches the required thickness of the grid substrate; welding a grid support ring to the refractory metal; The remaining silicon mold and the composite substrate residue are removed to obtain the field emission cathode refractory metal grid.

2. The preparation method according to claim 1, characterized in that: The material of the grid substrate is selected from tungsten, molybdenum and tantalum.

3. The preparation method according to claim 1, characterized in that: The thickness of the grid substrate is 40 microns to 5 microns.

4. The preparation method according to claim 1, characterized in that: The grid support ring is located at the edge of the grid substrate, avoiding the grid through-hole array.

5. The preparation method according to claim 1, characterized in that: The inner ring of the grid support ring has an inclination angle of 30-70 degrees.

6. The preparation method according to claim 1, characterized in that: The material of the grid support ring is selected from one or more of refractory metals and stainless steel.

7. The preparation method according to claim 1, characterized in that: The material of the grid support ring is tungsten or molybdenum.

8. The preparation method according to claim 1, characterized in that: The light transmittance of the gate through-hole array is 70%-90%.

9. The preparation method according to claim 1, characterized in that In the gate through hole array, the shapes of the gate through holes are closely packed square, circular, triangular, regular hexagonal or spoke grid.

10. The preparation method according to claim 1, characterized in that: The composite substrate is an SOI wafer, and the structure is a silicon support layer / insulating layer / silicon device layer, or the composite substrate is a non-silicon support layer / silicon device layer structure.

11. The preparation method according to claim 10, characterized in that: The thickness of the silicon support layer or the non-silicon support layer is 400 microns to 1000 microns.

12. The preparation method according to claim 10, characterized in that: The thickness of the insulating layer is 1 micron to 2 microns.

13. The preparation method according to claim 1, characterized in that: The thickness of the silicon device layer is greater than the required thickness of the grid substrate, and the thickness of the silicon mold is greater than the thickness of the grid substrate.

14. The preparation method according to claim 1, characterized in that: The thickness of the silicon device layer is 45 micrometers to 5 micrometers.

15. The preparation method according to claim 1, characterized in that: The photoresist is a thick photoresist used in MEMS technology.

16. The preparation method according to claim 15, characterized in that: The photoresist is AZ4620 photoresist or KMPR photoresist.

17. The preparation method according to claim 1, characterized in that: The etching method is an inductively coupled plasma etching technology.

18. The preparation method according to claim 1, characterized in that: The deposition method is chemical vapor deposition.

19. The preparation method according to claim 1, characterized in that: The welding method is vacuum diffusion welding.

20. The field emission cathode refractory metal grid prepared by the preparation method according to any one of claims 1 to 19.

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