Three-gate charge transfer block structure in time-of-flight pixels

Abstract

This application relates to a three-gate charge transfer block structure in a time-of-flight pixel. The pixel circuit includes a photodiode in a semiconductor material to accumulate image charge in response to incident light. The three-gate charge transfer block is coupled to a single shared channel region containing the semiconductor material. A transfer gate, a shutter gate, and a switch gate are positioned close to the single shared channel region. The transfer gate transfers the image charge accumulated in the photodiode to the single shared channel region in response to a transfer signal. The shutter gate transfers the image charge in the single shared channel region to a floating diffuser in the semiconductor material in response to a shutter signal. The switch gate is configured to couple the single shared channel region to a charge storage structure in the semiconductor material in response to a switch signal.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more specifically, but not exclusively, to time-of-flight image sensors. Background Technology

[0002] As 3D applications continue to proliferate in fields such as imaging, film, gaming, computing, user interfaces, facial recognition, object recognition, and augmented reality, interest in 3D cameras is increasing. A typical passive approach to creating 3D images is to use multiple cameras to capture stereo or multiple images. Using stereo images, objects in the images can be triangulated to create 3D images. One drawback of this triangulation technique is its difficulty in creating 3D images using small setups, as a minimum separation distance must be maintained between each camera to create a 3D image. Furthermore, this technique is complex and therefore requires significant computing power to create 3D images in real time.

[0003] For applications requiring real-time 3D image acquisition, active depth imaging systems based on time-of-flight measurements are sometimes used. Time-of-flight cameras typically employ a light source that directs light to an object, a sensor that detects the light reflected from the object, and a processing unit that calculates the distance to the object based on the round-trip time of the light.

[0004] A persistent challenge in acquiring 3D images is balancing the expected performance parameters of a time-of-flight camera with the physical size and power constraints of the system. For example, high-performance time-of-flight systems have considerably high power requirements because time-of-flight cameras typically operate at very high frequencies and require fast charge transfer times. These challenges are further complicated by external parameters (e.g., the camera's expected frame rate, depth resolution, and lateral resolution) as well as internal parameters (e.g., the sensor's quantum efficiency, fill factor, jitter, and noise). Summary of the Invention

[0005] According to one aspect of this application, a pixel circuit is provided. The pixel circuit includes: a photodiode disposed in a semiconductor material layer to accumulate image charge in response to light incident on the photodiode; a three-gate charge transfer block coupled to the photodiode, wherein the three-gate charge transfer block includes a single shared channel region disposed in the semiconductor material layer; a transfer gate disposed adjacent to the single shared channel region, wherein the transfer gate is configured to transfer the image charge accumulated in the photodiode to the single shared channel region in response to a transfer signal; a shutter gate disposed adjacent to the single shared channel region, wherein the shutter gate is configured to transfer the image charge in the single shared channel region to a floating diffuser disposed in the semiconductor material layer in response to a shutter signal; and a switch gate disposed adjacent to the single shared channel region, wherein the switch gate is configured to couple the single shared channel region to a charge storage structure disposed in the semiconductor material layer in response to a switch signal.

[0006] According to another aspect of this application, a light sensing system is provided. The light sensing system includes: a light source that emits light toward an object; a pixel array optically coupled to sense emitted light reflected from the object, wherein the pixel array comprises a plurality of pixels, wherein each of the pixels includes: a photodiode disposed in a semiconductor material layer to accumulate image charge in response to reflected light incident on the photodiode; and a three-gate charge transfer block coupled to the photodiode, wherein the three-gate charge transfer block includes: a single shared channel region disposed in the semiconductor material layer; and a transfer gate disposed adjacent to the single shared channel region, wherein the transfer gate is configured to transfer the photodiode in response to a transfer signal. The image charge accumulated in the diode is transferred to the single shared channel region; a shutter gate is configured to be close to the single shared channel region, wherein the shutter gate is configured to transfer the image charge in the single shared channel region to a floating diffuser disposed in the semiconductor material layer in response to a shutter signal; a switch gate is configured to be close to the single shared channel region, wherein the switch gate is configured to couple the single shared channel region to a charge storage structure disposed in the semiconductor material layer in response to a switch signal; and a control circuit is coupled to control the light source and the pixel array to sense the emitted light reflected from the object to the pixel array.

[0007] According to another aspect of this application, a method for sensing light using a pixel is provided. The method includes: illuminating a photodiode disposed in a semiconductor material layer with light reflected from an object; accumulating charge generated in the photodiode in response to the light reflected from the object during an integration period of the pixel; transferring the charge from the photodiode to a first single shared channel region in the semiconductor material layer of a first tri-gate charge transfer block coupled to the photodiode in response to a first transfer signal activating a first transfer gate, wherein the first single shared channel region is shared among the first transfer gate, a first shutter gate, and a first switch gate of the first tri-gate charge transfer block; transferring the charge from the first single shared channel region to a first floating diffuser region in response to a first shutter signal activating the first shutter gate; converting the charge in the first floating diffuser region into a first pixel output signal using a first source follower transistor coupled to the first floating diffuser region; and reading the first pixel output signal during a readout period of the pixel occurring after the integration period of the pixel. Attached Figure Description

[0008] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following drawings, wherein, unless otherwise specified, the same reference numerals refer to the same parts in the various views.

[0009] Figure 1 This is a block diagram illustrating an example of a time-of-flight optical sensing system according to the teachings of this disclosure, the time-of-flight optical sensing system comprising an example three-gate charge transfer block structure having a centrally collecting photodiode in a time-of-flight pixel.

[0010] Figure 2A This is a schematic diagram illustrating an example of a time-of-flight optical pixel circuit in accordance with the teachings of this disclosure, which includes an example three-gate charge transfer block structure.

[0011] Figure 2B This is a schematic diagram illustrating another example of a time-of-flight optical pixel circuit in accordance with the teachings of this disclosure, which includes an example three-gate charge transfer block structure.

[0012] Figure 3 This is a top view of an example of a time-of-flight optical pixel circuit in a semiconductor material comprising an example three-gate charge transfer block structure having an example centrally collected photodiode, in accordance with the teachings of this disclosure.

[0013] Figure 4A This is a cross-sectional view of an example of a time-of-flight optical pixel circuit comprising an example centrally collected photodiode in a semiconductor material, in accordance with the teachings of this disclosure.

[0014] Figure 4B This is an example potential contour plot showing the charge transfer path in a cross-sectional view of an example time-of-flight optical pixel circuit comprising an example centrally collected photodiode in a semiconductor material, in accordance with the teachings of this disclosure.

[0015] Figure 4C This is a cross-sectional view of another example of a time-of-flight optical pixel circuit containing an example centrally collected photodiode in a semiconductor material, in accordance with the teachings of this disclosure.

[0016] Figure 4D This is a cross-sectional view showing more details of an example of a vertical transfer gate structure in an example time-of-flight optical pixel circuit contained in a semiconductor material, in accordance with the teachings of this disclosure.

[0017] Figures 5A to 5F This is an example timing diagram illustrating the operation of an example of a time-of-flight optical sensing system according to the teachings of this disclosure, the optical sensing system comprising an example three-gate charge transfer block structure having a centrally collecting photodiode in a time-of-flight pixel.

[0018] In the various views of the accompanying drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will understand that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate less obstructed observation of the views of these various embodiments of the invention. Detailed Implementation

[0019] This document describes an example of a three-gate charge transfer block structure and corresponding circuitry in a time-of-flight pixel structure with a centrally collecting photodiode. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0020] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one instance of the invention. Therefore, the phrases "in one example" or "in one embodiment" appearing in various places throughout the specification do not necessarily refer to the same example. Furthermore, in one or more examples, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0021] Several technical terms are used throughout this specification. These terms have their general meanings in their respective fields, and unless specifically defined herein, the context in which they are used will explicitly suggest otherwise. It should be noted that component names and symbols are used interchangeably in this document (e.g., Si vs. silicon); however, they have the same meaning.

[0022] As will be discussed, in the various embodiments disclosed herein, a time-of-flight optical sensing system or image sensor is disclosed that offers reduced power consumption and improved charge transfer speed for each individual pixel compared to known photogate indirect time-of-flight (iTOF) pixel structures, without increasing pixel size. For example, a known type of photogate iTOF pixel structure uses large, long finger photogates and switches between activated photogates to perform potential modulation, thereby generating a potential gradient to fully deplete the lightly doped silicon substrate during integration. Typically, for higher accuracy, known iTOF pixel structures operate at high modulation frequencies (e.g., 30 MHz–100 MHz). This type of large, long photogate generates high capacitance during operation, thus subjecting high power consumption requirements (e.g., ~1.2 W), especially at high frequencies.

[0023] Another known iTOF pixel structure uses a high alternating current to switch between two photogates that are far apart. Because a high alternating current is required to flow through a high-resistivity silicon substrate, a large IR drop occurs, resulting in high power consumption for this iTOF pixel structure. Furthermore, power consumption increases significantly at higher operating frequencies. In addition, the image charge transfer path in these types of known iTOF pixel structures is also long, which increases the response time of the iTOF pixel structure.

[0024] Furthermore, it is known that the photogates in iTOF pixel structures require large pixel areas, which negatively impacts the fill factor and pixel miniaturization. Additionally, it is known that the photogates in iTOF pixel structures occupy a certain amount of space per pixel, which reduces the size of the photodiode and limits the full-well capacity (FWC) of the photodiode pixel.

[0025] Figure 1This is a block diagram illustrating an example of a time-of-flight optical sensing system 100 according to the teachings of this disclosure. The time-of-flight optical sensing system 100 includes a light source 102, a lens 116, an image sensor 120 (containing multiple pixels, such as a first pixel 122), and control circuitry 124. As will be discussed in more detail below, according to the teachings of the present invention, the multiple pixels included in the image sensor 120 comprise an example three-gate charge transfer block structure having a centrally collecting photodiode in the time-of-flight pixel to perform indirect time-of-flight (iTOF) measurements. The control circuitry 124 is coupled to the light source 102 and the image sensor 120. The image sensor 120 is positioned at a focal length f from the lens 116. 透镜 Place.

[0026] As shown in the example, the light source 102 and lens 116 are positioned at a distance L from the object 130. It should be understood that... Figure 1 Not shown to scale, and in one instance, the focal length f 透镜 This is substantially less than the distance L between lens 116 and object 130. Therefore, it should be understood that, for the purposes of this disclosure, according to the teachings of the present invention, distance L and distance L + focal length f are... 透镜 The purposes of time-of-flight measurement are essentially the same. As shown, image sensor 120 and control circuitry 124 are represented as separate components. However, in one instance, it should be understood that image sensor 120 and control circuitry 124 may be fully integrated onto a single-chip sensor on the same stack. In other instances, image sensor 120 and control circuitry 124 may be integrated onto a non-stacked standard planar sensor. Furthermore, it should be understood that control circuitry 124 may include one or more time-to-digital converters. In some instances, each pixel may include one or more avalanche photodiodes (e.g., single-photon avalanche diodes), which may be associated with a corresponding one of the one or more time-to-digital converters. It should also be understood that in some instances, individual time-to-digital converters may be associated with any predetermined number of pixels. Furthermore, it should be understood that each pixel may have a corresponding memory for storing digital bits or signals used to count photons detected from the avalanche photodiodes.

[0027] In the depicted example, the time-of-flight optical sensing system 100 is a 3D camera that calculates image depth information of the scene to be imaged (e.g., object 130) based on indirect time-of-flight (iTOF) measurements from the image sensor 120. In some instances, it should be understood that while the time-of-flight optical sensing system 100 is capable of sensing 3D images, it can also be used to capture 2D images. In various instances, the time-of-flight optical sensing system can also be used to capture high dynamic range (HDR) images.

[0028] Continuing with the depicted example, each pixel of a plurality of pixels in image sensor 120 determines depth information for a corresponding portion of object 130, enabling the generation of a 3D image of object 130. In the depicted example, the depth information is determined by measuring the delay / phase difference 106 between emitted light 104 and received reflected light 110 to indirectly determine the round-trip time of light traveling from light source 102 to object 130 and back to time-of-flight optical sensing system 100. The depth information may be based on an electrical signal generated by image sensor 120 (e.g., first pixel 122), which is then transferred to a storage node.

[0029] As shown, a light source 102 (e.g., a light-emitting diode, a vertical cavity surface-emitting laser, etc.) is configured to emit light 104 (e.g., emitted light waves) at a distance L toward an object 130. The emitted light 104 is then reflected from the object 130 as reflected light 110 (e.g., reflected light waves), some of which propagate at a distance L toward the time-of-flight light sensing system 100 and are incident as image light onto an image sensor 120. Each pixel (e.g., a first pixel 122) of the plurality of pixels included in the image sensor 120 includes a photodetector (e.g., one or more photodiodes, avalanche photodiodes, or single-photon avalanche diodes) to detect the image light and convert it into an electrical signal (e.g., signal electrons, image charge, etc.).

[0030] As shown in the illustrated example, the round-trip time of the light wave 104 from the light source 102 to the object 130 and then reflected back to the image sensor 120 can be determined using the following relationship in equations (1) and (2):

[0031]

[0032]

[0033] Where c is the speed of light, which is approximately equal to 3 × 10⁻⁶. 8 m / s, and T TOF Corresponding to round-trip time, which is the amount of time it takes for light to travel to and from an object, such as... Figure 1 As shown in the diagram. Therefore, once the round-trip time is known, the distance L can be calculated and then used to determine the depth information of object 130.

[0034] Control circuitry 124 is coupled to image sensor 120 (containing first pixel 122) and light source 102, and includes logic and memory that, when executed, causes time-of-flight optical sensing system 100 to perform operations for determining round-trip time. The determination of round-trip time may be based at least in part on a timing signal generated by control circuitry 124. For indirect time-of-flight (iTOF) measurements, the timing signal represents the delay / phase difference 106 between the light waves when light source 102 emits light 104 and when the photodetector detects reflected light 110.

[0035] In some instances, the time-of-flight optical sensing system 100 is included in a handheld device (e.g., a mobile phone, tablet, camera, etc.) having size and power limitations determined at least in part based on the size of the device. Alternatively, or additionally, the time-of-flight optical sensing system 100 may have specific desired device parameters, such as frame rate, depth resolution, lateral resolution, etc.

[0036] Figure 2A This is a schematic diagram illustrating one example of a time-of-flight optical pixel circuit 222 comprising an exemplary three-gate charge transfer block structure, in accordance with the teachings of this disclosure. It should be understood that... Figure 2A The pixel circuit 222 can be Figure 1 An example of pixel 122 of image sensor 120 is shown, and similarly named and numbered elements as described above are coupled and function similarly below. Figure 2AAs shown, pixel circuit 222 includes photodiode 232, which is configured to accumulate image charge in response to light incident on photodiode 232. As will be discussed in more detail below, in one example, photodiode 232 is a centrally collecting photodiode disposed in a semiconductor material, having a doped distribution that creates a potential distribution that pushes photogenerated image charge carriers toward the surface of the semiconductor material towards the center of photodiode 232. In the illustrated example, according to the teachings of the invention, three-gate charge transfer blocks 234A and 234B are coupled to photodiode 232 to collect photogenerated image charge carriers from photodiode 232 with low power consumption at an improved charge transfer rate. As shown in the depicted example, three-gate charge transfer block 234A is also coupled to floating diffuser 246A and charge storage structure 244A. Similarly, three-gate charge transfer block 234B is also coupled to floating diffuser 246B and charge storage structure 244B. In the depicted example, charge storage structures 244A and 244B are capacitors coupled to receive a gating signal. As will be discussed, in one example, the gating signal can be configured to pulse between a first value and a second value to overflow the charge stored in charge storage structures 244A and 244B to floating diffusers 246A and 246B via tri-gate charge transfer blocks 234A and / or 234B, as an alternative to the charge transfer for readout according to the teachings of the present invention.

[0037] The tri-gate charge transfer block 234A includes a transfer gate 236A coupled to a photodiode 232, a shutter gate 240A coupled to a floating diffuser 246A, and a switch gate 238A coupled to a charge storage structure 244A. Figure 2A This diagram illustrates a source transfer gate 236A coupled to a photodiode 232, a shutter gate 240A with a drain coupled to a floating diffusion section 246A, and a switch gate 238A with a drain coupled to a charge storage structure 244A. The transfer gate 236A, shutter gate 240A, and switch gate 238A are electrically coupled. All three gates are positioned close to each other and share a single shared channel region 250A in the semiconductor material (e.g., ...). Figure 2A(Indicated by the dashed circle marked 250A). Therefore, the single shared channel region 250A of the three-gate charge transfer block 234A is a shared extended channel region of the transfer gate 236A, shutter gate 240A, and switch gate 238A. Alternatively, the transfer gate 236A, shutter gate 240A, and switch gate 238A share a single region. It can be noted that there may be no junction or source / drain doping between the transfer gate 236A, shutter gate 240A, and switch gate 238A. In one embodiment, the single shared channel region shared between the transfer gate 236A, shutter gate 240A, and switch gate 238A may be an undoped region. In another embodiment, the single shared channel region shared between the transfer gate 236A, shutter gate 240A, and switch gate 238A may be a doped region. The conductivity of a single shared channel region 250A is modulated or determined by the bias potential of the coupled combination of the transfer gate 236A, the shutter gate 240A, and the switch gate 238A.

[0038] Thus, the image charge in a single shared channel region 250A is simultaneously in the drain of transistor gate 236A, in the source of shutter gate 240A, and in the source of switch gate 238A. Because the distance of the image charge path through the three-gate charge transfer block 234A is very short according to the teachings of the present invention, the transfer speed of image charge through the three-gate charge transfer block 234A is improved.

[0039] In operation, the transfer gate 236A is configured to transfer the image charge accumulated in the photodiode 232 to a single shared channel region 250A in response to the transfer signal TX1, the shutter gate 240A is configured to transfer the image charge in the single shared channel region 250A to the floating diffuser 246A in response to the shutter signal SHUTTER, and the switch gate 238A is configured to couple the single shared channel region 250A to the charge storage structure 244A in response to the switch signal SW1.

[0040] In one example, during exemplary integrated operation, the transfer gate 236A and shutter gate 240A are biased to be turned on when the switch gate 238A is turned off, lowering the barrier of the conductive channel formed between the transfer gate 236A and the shutter gate 240A to allow electron transfer or tunneling. Simultaneously, the barrier of the conductive channels formed between the transfer gate 236A and the switch gate 238A, and between the shutter gate 240A and the switch gate 238A, is high, such that charge is transferred from the transfer gate 236A to the floating diffuser 246A only through the conductive channel formed between the transfer gate 236A and the shutter gate 240A, and no charge flows to the switch gate 238A. Those skilled in the art will understand that the transfer operation of the fragmented channel region can be controlled by modulating the bias potential applied to the transfer gate 236A, the switch gate 238A, and the shutter gate 240A.

[0041] The three-gate charge transfer block 234B shares many similarities with the three-gate charge transfer block 234A. As shown in the figure, the three-gate charge transfer block 234B includes a transfer gate 236B coupled to a photodiode 232, a shutter gate 240B coupled to a floating diffuser 246B, and a switch gate 238B coupled to a charge storage structure 244B. The transfer gate 236B includes a source coupled to the photodiode 232, the shutter gate 240B includes a drain coupled to the floating diffuser 246B, and the switch gate 238B includes a drain coupled to the charge storage structure 244B. The transfer gate 236B, shutter gate 240B, and switch gate 238B are all positioned close to and share a single shared channel region 250B in the semiconductor material (e.g., ...). Figure 2A (Indicated by the dashed circle marked 250B). Therefore, the single shared channel region 250B of the three-gate charge transfer block 234B is a single shared channel region between the transistor gate 236B, the shutter gate 240B, and the switch gate 238B. Similarly, the conductivity of the single shared channel region 250B is modulated or determined by the coupled bias potential of the transfer gate 236B, the shutter gate 240B, and the switch gate 238B. Thus, the image charge in the single shared channel region 250B is simultaneously in the drain of the transistor gate 236B, in the source of the shutter gate 240B, and in the source of the switch gate 238B.

[0042] In operation, the transfer gate 236B is configured to transfer the image charge accumulated in the photodiode 232 to a single shared channel region 250B in response to the transfer signal TX2, the shutter gate 240B is configured to transfer the image charge in the single shared channel region 250B to the floating diffuser 246B in response to the shutter signal SHUTTER, and the switch gate 238B is configured to couple the single shared channel region 250B to the charge storage structure 244A in response to the switch signal SW2.

[0043] Figure 2A The example shown illustrates that pixel circuit 222 also includes a reset transistor 252A coupled between a voltage supply AVDD (e.g., 2.8V to 3.3V) and a floating diffuser 246A. The reset transistor 252A is coupled to reset the floating diffuser 246A in response to a reset signal RST1. A source follower transistor 254A is coupled to the floating diffuser 246A and is coupled to generate a pixel output signal PIXOUT1 in response to image charge in the floating diffuser 246A. A row select transistor 256A is coupled to the source follower transistor 254A and a current source 258A, as shown. In operation, the row select transistor 256A is coupled to output the pixel output signal PIXOUT1 from the source follower transistor 254A in response to the row select signal RS1.

[0044] Similarly, Figure 2A The example shown illustrates that pixel circuit 222 also includes a reset transistor 252B coupled between voltage supply AVDD and floating diffuser 246B. Reset transistor 252B is coupled to reset floating diffuser 246B in response to reset signal RST2. Source follower transistor 254B is coupled to floating diffuser 246B and is coupled to generate pixel output signal PIXOUT2 in response to image charge in floating diffuser 246B. Row select transistor 256B is coupled to source follower transistor 254B and current source 258B, as shown. In operation, row select transistor 256B is coupled to output pixel output signal PIXOUT2 from source follower transistor 254B in response to row select signal RS2.

[0045] In one example, pixel circuit 222 also includes an overflow transistor 242 coupled between voltage supply AVDD and photodiode 232. In operation, overflow transistor 242 is configured to discharge excess image charge from photodiode 232 in response to an overflow signal OFG. Therefore, it should be understood that because image charge generated by ambient light during readout operation can be discharged through overflow transistor 242, overflow transistor 242 can help improve the performance of pixel circuit 222 under bright sunlight outdoor conditions. For example, after an integration cycle, pixel circuit 222 begins a readout cycle to read charge from memory. However, during the readout cycle, light still incident on photodiode 232, which may interfere with image charge reading. Thus, overflow transistor 242 can be turned on during the readout cycle to discharge these charges to the drain node of overflow transistor 242.

[0046] In one example, pixel circuit 222 also includes a common-mode transistor 248 coupled between floating diffuser 246A and floating diffuser 246B. In operation, common-mode transistor 248 is configured to reset the common-mode level between floating diffuser 246A and floating diffuser 246B in response to a common-mode reset signal COM, to help reduce noise in pixel circuit 222. Specifically, it should be understood that many factors can cause a potential difference between floating diffuser 246A and floating diffuser 246B, such as process variations, transistor mismatch, offset variations, etc. To help eliminate noise that may be caused by the potential difference or offset between floating diffuser 246A and floating diffuser 246B, a common-mode level can be provided by enabling and disabling (e.g., turning on and off) common-mode transistor 248 shortly after the signals from floating diffuser 246A and floating diffuser 246B are sampled.

[0047] In operation, pixel circuit 222 can be reset to precharge its components to initial values ​​before the start of the integration cycle. In one example, during the initial precharge or reset cycle, overflow gate 242, transfer gates 236A and 236B, reset transistors 252A and 252B, switching gates 238A and 238B, and shutter gates 240A and 240B are all enabled to precharge or reset the charges in photodiode 232, charge storage structures 244A and 244B, and floating diffusers 246A and 246B to initial values. Those skilled in the art will understand that the initial values ​​can be configured based on the supply voltage and power consumption requirements of pixel circuit 222.

[0048] Then, the integration period can begin in response to the light illuminating the photodiode 232 (e.g., from...). Figure 1 The reflected light 110 from the object 130 causes an image charge to be generated in the photodiode 232. The accumulated image charge generated in the photodiode 232 is transferred from the photodiode 232 to a single shared channel region 250A of the tri-gate charge transfer block 234A via transfer gate 236A in response to transfer signal TX1. Furthermore, the accumulated image charge generated in the photodiode 232 can also be transferred from the photodiode 232 to a single shared channel region 250B of the tri-gate charge transfer block 234B via transfer gate 236B in response to transfer signal TX2. Transfer gates 236A and 236B are switched on and off to collect the charge generated by the photodiode 232 in response to incident light (e.g., reflected light 110). In one example, transfer signals TX1 and TX2 are pulse signals configured to have different phases, driving transfer gates 236A and 236B with different delays during the integration period to measure the incident light (e.g., reflected light 110). Figure 1The phase shift information of the reflected light 110 in the image sensor is used to determine the distance between the object (e.g., object 130) and the pixel 222 circuit of the image sensor. In one example, the driving voltages (e.g., the signal levels of transfer signals TX1 and TX2) of transfer gates 236A and 236B can range from 1.0V to 2.0V.

[0049] Then, the image charge in the single shared channel region 250A and the single shared channel region 250B can be transferred to the floating diffusion section 246A and the floating diffusion section 246B respectively through the shutter gate 240A and the shutter gate 240B in response to the corresponding SHUTTER signal.

[0050] In various embodiments, the full-well capacity (FWC) of the pixel circuit 222 can also be adjusted by the switching gates 238A and 238B in response to corresponding switching signals SW1 and SW2 to adjust the conversion gain of the pixel circuit 222 to adapt to lighting conditions. For example, by enabling the switching gates 238A and 238B during the integration period, image charge can be stored in the charge storage structures 244A and 244B and the floating diffusers 246A and 246B, which increase the FWC to decrease the conversion gain of the pixel circuit 222 under bright outdoor conditions. Alternatively, by disabling the switching gates 238A and 238B, image charge is not stored in the charge storage structures 244A and 244B, which reduces the FWC to increase the conversion gain of the pixel circuit 222 under dimmer indoor conditions. Therefore, it should be understood that, according to the teachings of the present invention, the pixel circuit 222 can be adapted to indoor and / or outdoor conditions to sense high dynamic range (HDR) image data in response to switching signals SW1 and SW2.

[0051] The image charge in the floating diffuser 246A is converted into a pixel output signal PIXOUT1 by the source follower transistor 254A, while the image charge in the floating diffuser 246B is converted into a pixel output signal PIXOUT2 by the source follower transistor 254B. During the readout cycle of the pixel circuit 222, the pixel output signal PIXOUT1 can be read out by enabling the row selection transistor 256A in response to the row selection signal RS1, and / or the pixel output signal PIXOUT2 can be read out by enabling the row selection transistor 256B in response to the row selection signal RS2.

[0052] In exemplary operation, the standardized output pixel values ​​can also be provided to pixel circuit 222 by generating correlated double sampling (CDS) pixel outputs for PIXOUT1 and PIXOUT2 using the sampling reset signal. For this purpose, the CDS pixel output values ​​of PIXOUT1 and PIXOUT2 can be determined by measuring the charge in the floating diffusers 246A and 246B twice, and then determining the difference between each of the two measurements and the sampling reset signal to eliminate noise such as kTC noise. One of the measurements is sampled after the floating diffusers 246A and 246B are reset, in response to the activation of reset transistors 252A and 252B in response to reset signals RST1 and RST2, respectively. After the image charge accumulated in photodiode 232 is transferred to the floating diffusers 246A and 246B via transfer gates 236A and 236B in response to transfer signals TX1 and TX2, and via shutter gates 240A and 240B in response to the corresponding SHUTTER signals, the other measurements are sampled. In various instances, according to the teachings of the present invention, the reset reads from the floating diffusion units 246A and 246B can be sampled before or after the signal values ​​from the floating diffusion units 246A and 246B are sampled.

[0053] Figure 2B This is a schematic diagram illustrating another example of a time-of-flight optical pixel circuit 222 comprising an exemplary three-gate charge transfer block structure, in accordance with the teachings of this disclosure. It should be understood that... Figure 2B The pixel circuit 222 can be Figure 2A Pixel circuit 222 and / or such Figure 1 Another example of pixel 122 of image sensor 120 shown in the figure, and similarly named and numbered elements described above are coupled and function similarly below. Also note that Figure 2B The example circuit shown is Figure 2A The example circuits shown have many similarities. It should be understood that, for the sake of brevity and to avoid obscuring the teachings of the invention, they will not be described in detail further. Figure 2A and Figure 2B Common components among the example circuits. However, Figure 2B The example circuit shown is Figure 2A One difference between the example circuits in the examples is that, Figure 2B In the example circuit shown, charge storage structures 244A' and 244B' are shown as capacitors configured for metal-oxide-semiconductor transistors, such as MOS capacitors (MOSCAPs) rather than capacitors.

[0054] In particular, Figure 2BThe example depicted illustrates that the drain and source terminals of switch gate 238A are coupled together to provide a MOSCAP charge storage structure 244A', and the drain and source terminals of switch gate 238B are coupled together to provide a MOSCAP charge storage structure 244B'. Therefore, in operation, switch gate 238A is configured to couple a single shared channel region 250A to the charge storage structure provided by MOSCAP 244A' in response to a switching signal SW1, and switch gate 238B is configured to couple a single shared channel region 250B to the charge storage structure provided by MOSCAP 244B' in response to a switching signal SW2.

[0055] Figure 3 This is a top view of an example of a time-of-flight optical pixel circuit 322 in a semiconductor material comprising an example three-gate charge transfer block structure having an example centrally collected photodiode, in accordance with the teachings of this disclosure. It should be understood that... Figure 3 The pixel circuit 322 can be Figures 2A to 2B Pixel 222 and / or such Figure 1 An example of pixel 122 of image sensor 120 is shown, and similarly named and numbered elements as described above are coupled and function similarly below. Figure 3 As shown, pixel circuit 322 includes a photodiode 332 disposed in semiconductor material layer 370 to accumulate image charge in response to light incident on photodiode 332. A three-gate charge transfer block 334A is coupled to photodiode 332. The three-gate charge transfer block 334A includes a single shared channel region 350A disposed in semiconductor material layer 370. In this example, the single shared channel region 350A is a single shared channel region shared by transfer gate 336A, shutter gate 340A, and switch gate 338A. Therefore, transfer gate 336A is positioned close to the single shared channel region 350A, and transfer gate 336A is configured to transfer the image charge accumulated in photodiode 332 to the single shared channel region 350A in response to transfer signal TX1. A shutter gate 340A is positioned close to a single shared channel region 350A, and the shutter gate 340A is configured to transfer image charge in the single shared channel region 350A to a floating diffuser 346A disposed in the semiconductor material layer 370 in response to a shutter signal SHUTTER. A switch gate 338A is positioned close to the single shared channel region 350A, and the switch gate 338A is configured to couple the single shared channel region 350A to a charge storage structure 344A disposed in the semiconductor material layer 370 in response to a switch signal SW1.

[0056] As shown in the example, pixel circuit 322 also includes a tri-gate charge transfer block 334B coupled to photodiode 332. It should be understood that tri-gate charge transfer block 334B is similar to tri-gate charge transfer block 334A because charge transfer block 334B includes a single shared channel region 350B disposed in semiconductor material layer 370. Transfer gate 336B, shutter gate 340B, and switch gate 338B are positioned close to the single shared channel region 350B. In this example, the single shared channel region 350B is a single shared channel region shared by transfer gate 336B, shutter gate 340B, and switch gate 338B. Transfer gate 336B, shutter gate 340B, and switch gate 338B are electrically coupled to the single shared channel region 350B. Transfer gate 336B is configured to transfer image charge accumulated in photodiode 332 to the single shared channel region 350B in response to transfer signal TX2. The shutter gate 340B is configured to transfer photogenerated image charge in a single shared channel region 350B to a floating diffuser 346B disposed in the semiconductor material layer 370 in response to the shutter signal SHUTTER. The switch gate 338B is configured to couple the single shared channel region 350B to a charge storage structure 344B disposed in the semiconductor material layer 370 in response to the switch signal SW2.

[0057] Figure 3 The example shown also illustrates row selection gates 356A and 356B, source follower gates 354A and 354B, reset gates 352A and 352B, and common-mode gate 348 of pixel circuitry 322 arranged above semiconductor material layer 370 surrounding photodiode 332. Additionally, overflow gate 342 is also disposed above semiconductor material layer 370 and coupled to photodiode 332 in response to overflow signal OFG to discharge excess image charge from photodiode 332.

[0058] In one exemplary operation, the charge storage structure is used to enhance the full-well capacity, for example, for outdoor imaging applications. During integration, switching gates 338A and 338B are turned on by switching signals SW1 and SW2, respectively, while transfer gates 336A and 336B are pulsed to alternately turn on by transfer signals TX1 and TX2. When transfer gate 336A is pulsed on and transfer gate 336B is pulsed off, photogenerated charge is transferred from photodiode 332 through a single shared channel region 350A between transfer gate 336A and switching gate 338A to charge storage structure 344A. When transfer gate 336B is pulsed on and transfer gate 336A is pulsed off, photogenerated charge is transferred from photodiode 332 through a single shared channel region 350B between transfer gate 336B and switching gate 338B to charge storage structure 344B. At the end of integration, overflow gate 342 is turned on in response to overflow signal OFG to discharge excess image charge from photodiode 332. During readout, transfer gates 336A and 336B are turned off, while switch gates 338A and 338B and shutter gates 340A and 340B are turned on to facilitate the transfer of image charge to floating diffusers 346A and 346B. Image charge stored in charge storage structure 344A is transferred to floating diffuser 346A via a single shared channel region 350A between switch gate 338A and shutter gate 340A. Image charge stored in charge storage structure 344B is transferred to floating diffuser 346B via a single shared channel region 350B between switch gate 338B and shutter gate 340B.

[0059] In one exemplary operation, only the floating diffuser is used for small full-well capacity and high conversion gain, such as for indoor imaging applications. During integration, switch gates 338A and 338B are turned off, and shutter gates 340A and 340B are turned on using the shutter signal SHUTTER, while transfer gates 336A and 336B are pulsed to alternately turn on using transfer signals TX1 and TX2. When transfer gate 336A is pulsed on and transfer gate 336B is pulsed off, photogenerated charge is transferred from photodiode 332 through a single shared channel region 350A between transfer gate 336A and shutter gate 340A to the floating diffuser 346A. When transfer gate 336B is pulsed on and transfer gate 336A is pulsed off, photogenerated charge is transferred from photodiode 332 through a single shared channel region 350B between transfer gate 336B and shutter gate 340B to the floating diffuser 346B. At the end of integration, the overflow gate 342 is turned on in response to the overflow signal OFG to discharge excess image charge from the photodiode 332. During readout, the image charge stored in the floating diffusers 346A and 346B is read out, respectively.

[0060] As shown in the illustrated example and will be described in further detail below, it should be understood that photodiode 332 is a centrally located photodiode disposed in semiconductor layer 370, having a doping distribution that creates a potential distribution that pushes photogenerated image charge carriers toward the surface of semiconductor layer 370 toward the center of photodiode 332. For example, in the illustrated example and will be described in further detail below, photodiode 332 is illuminated through the back surface of semiconductor layer 370. Image charge is photogenerated in photodiode 332, and the doping distribution and structure of photodiode 332 push the image charge accumulated in photodiode 332 toward the front surface of semiconductor layer 370 near the center of photodiode 332, below or beneath transfer gates 336A and 336B. In one example, the cross-sectional area of ​​the doped region of photodiode 332 closest to the back surface of semiconductor layer 370 is a wider cross-sectional area, which in Figure 3 This is shown by dashed line 332-2. In this example, the cross-sectional area of ​​the doped region of the photodiode 332, which is closest to the front side of the semiconductor material layer 370, is relatively narrow. Figure 3 It is shown in dashed line 332-1.

[0061] In one example, and as will be discussed in further detail below, pixel circuit 322 further includes vertical transfer gate structures 360A and 360B, which extend from the front side of the semiconductor material layer 370 beneath the transfer gates 336A and 336B toward the back side of the semiconductor material layer 370 and into the photodiode 332, respectively. In various examples, the vertical transfer gate structures 360A and 360B can be implemented using highly doped semiconductor materials, polysilicon, etc., to transfer photogenerated image charge from the underlying photodiode 332 to the corresponding tri-gate charge transfer blocks 334A and 334B.

[0062] To illustrate, Figure 4A This is a cross-sectional view of an example pixel circuit 422 comprising an example centrally collected photodiode in a semiconductor material, in accordance with the teachings of this disclosure. It should be understood that... Figure 4A The pixel circuit 422 can be used along... Figure 3 The dashed line A'-A has 322 pixels and / or Figures 2A to 2B Pixel circuit 222 and / or Figure 1 The image sensor 120 shown is a cross-sectional view of an example of pixel 122, and similarly named and numbered elements described above are coupled and function similarly below. Figure 4AAs shown, pixel circuit 422 includes photodiode 432 disposed in semiconductor material layer 470. As illustrated, transfer gates 436A and 436B and switch gates 438A and 438B are arranged along the front surface 474 of semiconductor material layer 470. In one example, transfer gates 436A and 436B and switch gates 438A and 438B are formed of polysilicon, while semiconductor material layer 470 is formed of a p-type epitaxial silicon wafer. As shown, transfer gate 436A can be formed of a vertical transfer gate and includes a vertical transfer structure 460A. Transfer gate 436B can be formed of a vertical transfer gate and includes a vertical transfer structure 460B. Vertical transfer structures 460A and 460B can be formed of a highly doped semiconductor material with impurities, for example, doping the semiconductor material to form a highly doped n-type region. The highly doped n-type region can be formed by doping with arsenic (As) or phosphorus (P) at various implantation energies to a high concentration. In one example, semiconductor material 470 includes a p-type epitaxial silicon layer (or a p-type semiconductor substrate), and photodiode 432 includes an n-type dopant implanted into the p-type epitaxial silicon layer of semiconductor material layer 470. In other examples, it should be understood that the polarity of the dopant can be switched so that photodiode 432 can be formed from p-type dopant implanted into the n-type epitaxial silicon layer (or n-type semiconductor substrate) of semiconductor material layer 470. Those skilled in the art will understand that the n-type photodiode dopant can include arsenic (As), phosphorus (P), or other n-type dopant. The p-type dopant can include boron, indium, or other p-type dopant.

[0063] In the illustrated example, the cross-sectional area of ​​the portion 432-2 of the photodiode 432 closest to the back surface 472 of the semiconductor material layer 470 is a wide cross-sectional area, and the cross-sectional area of ​​the portion 432-1 of the photodiode 432 closest to the front surface 474 of the semiconductor material layer 470 is a narrow cross-sectional area. In one example, during manufacturing, a wider aperture n-type photodiode mask is used to implant the photodiode 432 into the semiconductor material layer 470 using deep n-type photodiode implantation, and a smaller or narrower aperture n-type photodiode mask is used to perform medium / shallow n-type photodiode implantation.

[0064] Figure 4AThe examples depicted also demonstrate that the photodiode 432 in the semiconductor material layer 470 has a gradient doping distribution. For example, in one example, the semiconductor material layer 470 is a p-type semiconductor substrate layer with a doping concentration in the range of approximately 1E12 to 1E14 atoms per cubic centimeter, and the doping distribution of the doped regions of the photodiode 432 has a doping concentration of approximately 1E12 atoms per cubic centimeter at the portion 432-2 of the photodiode 432 closest to the back surface 472 of the semiconductor material layer 470, gradually increasing to approximately 1E15 atoms per cubic centimeter at the middle portion of the photodiode 432 between the back surface 472 and the front surface 474 of the semiconductor material layer 470. In this example, the doping concentration continues to gradually increase to 1E16 atoms per cubic centimeter near the front surface 474 of the semiconductor material layer 470 below the transfer gates 436A and 436B, as shown in the figure. As illustrated in the depicted example, the potential in the photodiode 432 thus gradually increases from the back surface 472 of the semiconductor material layer 470 to the vicinity of the front surface 474. It should be understood that the specific doping concentration provided herein is for illustrative purposes, and different specific doping concentrations may be considered in other examples based on the teachings of the invention.

[0065] During operation, light 410 (e.g., from...) Figure 1 The reflected light 110 from the object 130 is guided through the back surface 472 of the semiconductor material layer 470 and enters the photodiode 432. In the photodiode 432, image charge carriers generated in response to the incident reflected light 410 are... Figure 4A The electron is shown as "e-". In the depicted example, it should be understood that the shape and concentration of the dopant in the photodiode 432 create a potential distribution that pushes image charge carriers up toward the front surface 474 and toward the center of the photodiode 432 near the front surface 474 below the transfer gates 436A and 436B.

[0066] To illustrate, Figure 4B A potential contour plot according to a teaching example of this disclosure is shown, illustrating the charge transfer path of image charge carriers e- in a cross-sectional view of pixel circuit 422. It should be understood that... Figure 4B The potential contour map shown in the image can be Figure 4A The example shown is a cross-sectional view of the potential contour plot of the example pixel circuit 422, and similarly named and numbered elements described above are coupled and function similarly below. Figure 4BAs shown, reflected light 410 is guided through the back surface 470 of the semiconductor material layer 472 and enters the photodiode 432, which carries photogenerated image charge carriers. The potential distribution of the photodiode 432 shown pushes the image charge carriers upwards toward the front surface 474 and the center near the front surface 474, as... Figure 4B The white dashed line indicates this.

[0067] Return to reference Figure 4A In one example of the depicted embodiment, pixel 422 further includes transfer gates 436A and 436B having vertical transfer gate structures 460A and 460B, which extend from the front surface 474 of the semiconductor material layer 470 beneath the transfer gates 436A and 436B toward the back surface 472 of the semiconductor material layer 470 and into the photodiode 432, as shown in the figure. In the depicted embodiment, the vertical transfer gate structures 460A and 460B are formed with highly doped regions containing dopants having the same polarity as the dopant (e.g., n-type dopant) of the photodiode 432. For example, in an instance where the photodiode 432 is formed by an n-type dopant implanted into a p-type epitaxial layer, each of the vertical transfer gate structures 436A and 436B is a highly doped region with an n-type vertical injection channel having a doping concentration in the range of approximately 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter at the front surface 474 of the semiconductor material layer 470.

[0068] In operation, by applying appropriate transfer signals TX1 and TX2 to transfer gates 436A and 436B respectively, and applying switching signals SW1 and SW2 to switching gates 438A and 438B respectively, image charge carriers e- are pumped out from photodiode 432 near the front surface 474. For example, Figure 4A An example path is shown along which image charge carriers e- are pumped from photodiode 432 through vertical transfer gate structure 460B and along dashed line B'-B along transfer gate 436B and switching gate 438B, as illustrated.

[0069] In one example, when the transfer gate 436A is turned on in response to the transfer signal TX1, the potential gradient established by the doping distribution of the photodiode 432 pushes one or more accumulated photogenerated image charges to the front surface 474 of the semiconductor material layer 470 through the vertical transfer gate structure 460A to the transfer gate 436A, and transfers them to the associated floating diffusion region (e.g., Figure 3The floating diffusion region 346A). Similarly, when the transfer gate 436B is turned on in response to the transfer signal TX2, the potential gradient established by the doping distribution of the photodiode 432 pushes one or more accumulated photogenerated image charges to the front surface 474 of the semiconductor material layer 470 from the vertical transfer gate structure 460B to the transfer gate 436B, and transfers them to the floating diffusion region (e.g., Figure 3 (Floating diffuser 346B).

[0070] Figure 4C This is a cross-sectional view of another example pixel circuit 422A, which incorporates a centrally collected photodiode in a semiconductor material according to the teachings of the present invention. It should be understood that... Figure 4C The pixel circuit 422A can be Figure 4A Another example of pixel circuit 422, and the similarly named and numbered elements described above are coupled and function similarly below. It should be further noted that... Figure 4C The example cross section shown is... Figure 4A The cross-sections of the examples shown have many similarities, and for the sake of brevity and to avoid obscuring the teachings of the invention, they will not be described in detail again. Figure 4A and Figure 4C The common elements between the cross-sections of the instances. However, Figure 4C The example cross section shown is... Figure 4A One difference between the cross-sections of the examples shown is that, Figure 4C The example cross-section shown in the figure illustrates that vertical transfer gate structures 462A and 462B are formed of polysilicon, which extends from the front surface 474 of the semiconductor material layer 470 towards the back surface 472 of the semiconductor material layer 470 and into the photodiode 432. Thus, the vertical transfer gate structures 462A and 462B form a vertical transfer gate (VTG), which reduces the impact of image charge transfers when the transfer signals TX1 and TX2 switch off the transfer gates 436A' and 436B'. Figure 4A The diagram illustrates a potential charge overflow problem that may occur when the pump channel overflows back to photodiode 432. It should be understood that, in the case of… Figure 4C The polysilicon vertical transfer gate structures 462A and 462B shown in the figure provide a vertical transfer gate, and the inverted channel contact photodiode 432 is doped with a region that allows the image charge transfer operation to be well controlled by applying gate bias to transfer gates 436A' and 436B' through transfer signals TX1 and TX2, respectively.

[0071] Figure 4DFigure 475 is a cross-sectional view showing more details of an example of a vertical transfer gate structure incorporated in an example pixel circuit in a semiconductor material according to the teachings of this disclosure. It should be understood that... Figure 4D The vertical transfer gate structure 462B shown in cross-sectional view 475 can be illustrated in more detail. Figure 4C Another example of the vertical transfer gate structure 462B, and similarly named and numbered elements described above are coupled and function similarly below. Figure 4D As illustrated in the example, the vertical transfer gate structure 462B is a trench structure extending from the transfer gate 436B' on the front surface of the semiconductor material layer 470 toward the back surface of the semiconductor material layer 470 and into the photodiode 432. The vertical transfer gate structure 462B can be filled with polysilicon. Similarly, the transfer gate 436B' can also be formed of polysilicon. Figure 4D In the example depicted, an insulating layer 476 is disposed between the semiconductor material layer 470 and the vertical transfer gate structure 462B, and between the semiconductor material layer 470 and the transfer gate 436B'. In one example, the vertical transfer gate structure 462B can be formed by etching a trench opening extending from the transfer gate 436B' on the front surface of the semiconductor material layer 470 toward the back surface of the semiconductor material layer 470. Subsequently, an insulating layer 476 is deposited to cover the sidewalls of the trench structure and the front surface of the semiconductor material layer 470. Then, polysilicon material is patterned and deposited to fill the trench structure and form the vertical transfer gate structure 462B and the transfer gate 436B'.

[0072] In one instance, it should be understood that the insulating layer 476 is formed with a thin gate oxide. In another instance, the insulating layer 476 may be formed of a dielectric material with a dielectric constant greater than 3.9, such as hafnium oxide, aluminum oxide, etc.

[0073] Figures 5A to 5F This is a timing diagram 564 illustrating various examples of operation of a time-of-flight optical sensing system according to the teachings of this disclosure, the optical sensing system comprising an example three-gate charge transfer block structure having a centrally collecting photodiode in a time-of-flight pixel. It should be understood that the timing diagrams can be referenced above regarding... Figures 1 to 4D The components discussed, and similarly named and numbered components described above, are coupled and function similarly below.

[0074] like Figure 5AAs shown, an instance of pixel operation in 3D depth mode begins with a precharge reset cycle, during which the elements in the pixel are precharged or reset to their initial values. Therefore, during the initial precharge or reset cycle, the overflow signal OFG 542, transfer signals TX1 536A and TX2 536B, reset signals RST1 and RST2 552, switch signals SW1 and SW2 538, and shutter signal 240 are all pulsed high, while the strobe signal 544, line selection signals RS1 546A and RS2 546B, and common-mode reset signal COM 548 remain low.

[0075] During the integration period, transfer signals TX1 536A and TX2 536B are alternately pulsed, which sequentially and repeatedly transfer or pump photogenerated charge from the photodiode to the first single shared channel region or the second single shared channel region during the pixel's integration period. Additionally, switching signals SW1 and SW2 538 and shutter signal 540 are enabled during the integration period, causing the charge transferred from the photodiode to be stored accordingly in the floating diffuser and in the charge storage structure during the integration period. An additional overflow signal OFG 542 is pulsed low during integration, allowing charge to be collected in the corresponding floating diffuser through the respective first single shared channel region or the second single shared channel region. The pixel's full-well capacity and associated charge-to-voltage conversion gain can be determined by the capacitance of the associated charge storage structure and the floating diffuser. Therefore, according to the teachings of the present invention, in the described example, the pixel is set to high FWC and low conversion gain.

[0076] During the readout cycle, the overflow signal OFG 542 is enabled, which allows the overflow transistor to discharge excess image charge from the photodiode. Therefore, in bright, sunny outdoor conditions, pixel performance can be improved, as image charge generated by ambient light during readout can be discharged through the overflow transistor. Row selection signals RS1 546A and RS2 546B are enabled, enabling the readout of pixel output signals PIXOUT1 and PIXOUT2 from the pixel. The pixel output signals are sampled and held to sample the pixel's signal output value, as indicated by the SHS 568 pulse. In this example, the floating diffuser is then reset, as indicated by the pulses of reset signals RST1 and RST2 552. In one example, the common-mode reset signal COM548 can also optionally be pulsed, since the reset signals RST1 and RST2 552 are pulsed to reset the floating diffuser to a common reset level, such as the supply voltage of the voltage supply. In this example, the pixel output signal is then sampled and held again to sample the pixel's reset output value, as indicated by the SHR 566 pulse. Therefore, it should be understood that, according to the teachings of the invention, for example by including... Figure 1 The differential amplifier circuit in the control circuit 124 can calculate the difference between the sampled signal output value and the sampled reset signal value to determine the pixel output value.

[0077] Those skilled in the art should understand that, Figure 5A In the operation shown, the pixel output signal associated with the photogenerated image charge is sampled before the reset signal is sampled, and therefore the image signal level is uncorrelated with the reset signal level. Therefore, correlated double sampling (CDS) operation can be omitted. However, since the image charge memory is shared with the charge memory structure during the image signal readout cycle when the switch signals SW1 and SW2 538 are enabled after the reset of the floating diffuser, the full-well capacity of the photodiode can be maximized, making it suitable for outdoor imaging applications.

[0078] like Figure 5B As shown, another example of pixel operation in 3D depth mode begins with a precharge reset cycle, during which the elements in the pixel are precharged or reset to their initial values. Therefore, during the initial precharge or reset cycle, the overflow signal OFG 542, transfer signals TX1 536A and TX2 536B, reset signals RST1 and RST2 552, switch signals SW1 and SW2 538, and shutter signal 540 are all pulsed high, while the strobe signal 544, line selection signals RS1 546A and RS2 546B, and common-mode reset signal COM 548 remain low.

[0079] During the integration period, transfer signals TX1 536A and TX2 536B are alternately pulsed, which sequentially and repeatedly transfer or pump photogenerated charge from the photodiode to the first single shared channel region or the second single shared channel region during the pixel's integration period. Additionally, switching signals SW1 and SW2 538 remain disabled, while shutter signal 540 is enabled during the integration period. Therefore, during the integration period, the charge transferred from the photodiode is stored in two floating diffusers, not in the charge storage structure. Thus, according to the teachings of the present invention, the pixel is set to low FWC and high conversion gain in the described example, which is suitable for indoor imaging applications.

[0080] During the readout cycle, the overflow signal OFG 542 is enabled, which allows the overflow transistor to discharge excess image charge from the photodiode. Therefore, image charge generated by ambient light can be discharged through the overflow transistor during the readout cycle. During the readout cycle, the shutter signal 540 and line selection signals RS1 546A and RS2 546B are enabled, enabling the readout of pixel output signals PIXOUT1 and PIXOUT2 from the pixels. Pixel output signals PIXOUT1 and PIXOUT2 are sampled and held during readout to sample the signal output value of the pixel, as indicated by the SHS 568 pulse. In this example, the floating diffuser is then reset, as indicated by the pulses of reset signals RST1 and RST2 552. In one example, the common-mode reset signal COM 548 can also optionally be pulsed, since the reset signals RST1 and RST2 552 are pulsed to reset the floating diffuser to a common reset level, such as the supply voltage of the voltage supply. In this example, the pixel output signals PIXOUT1 and PIXOUT2 are then sampled and held again to sample the pixel's reset output value, as indicated by the SHR 566 pulse. Those skilled in the art will understand that... Figure 5B In the operation shown, the pixel output signal associated with the photogenerated image charge is sampled before the reset signal is sampled, therefore the correlated double sampling (CDS) operation can be omitted. It should be understood that, according to the teachings of the present invention, for example by including... Figure 1 The differential amplifier circuit in the control circuit 124 can calculate the difference between the sampled signal output value and the sampled reset signal value to determine the pixel output value.

[0081] It should be understood, for example, that it can be done through Figure 1 The control circuit 124 controls the pixels for outdoor applications in environments with brighter lighting conditions, such as... Figure 5A As shown, it can be operated selectively, or used indoors in environments with dim lighting settings, such as... Figure 5B The operation is selective as shown.

[0082] like Figure 5C As shown, another example of pixel operation in 3D depth mode begins with a precharge reset cycle, during which the elements in the pixel are precharged or reset to their initial values. Therefore, during the initial precharge or reset cycle, the overflow signal OFG 542, transfer signals TX1 536A and TX2 536B, reset signals RST1 and RST2 552, switch signals SW1 and SW2 538, and shutter signal 540 are all pulsed high, while the strobe signal 544, line selection signals RS1 546A and RS2 546B, and common-mode reset signal COM 548 remain low.

[0083] During the integration period, transfer signals TX1 536A and TX2 536B are alternately pulsed, which sequentially and repeatedly transfer or pump photogenerated charge from the photodiode to the first single shared channel region or the second single shared channel region during the pixel's integration period. Furthermore, the shutter signal 540 remains disabled during the integration period, while the switching signals SW1 and SW2 538 are enabled. Therefore, in the depicted example, the charge transferred from the photodiode during the integration period is stored in the charge storage structure, but not in the floating diffuser.

[0084] During the readout cycle, the overflow signal OFG 542 is enabled, which allows the overflow transistor to discharge excess image charge from the photodiode. Therefore, in bright, sunny outdoor conditions, pixel performance can be improved, as image charge generated by ambient light during readout can be discharged through the overflow transistor. In this example, switch signals SW1 and SW2 538 are initially disabled during the readout cycle, isolating the charge stored in the charge storage structure from the floating diffuser. Therefore, unwanted image charge stored in the floating diffuser region during integration time can be flushed out before signal readout. The shutter signal 540 and line selection signals RS1 546A and RS2 546B are enabled, enabling the readout of pixel output signals PIXOUT1 and PIXOUT2 from the pixel. The floating diffuser is then reset, as indicated by the pulses of reset signals RST1 and RST2 552. In one example, the common-mode reset signal COM 548 is also pulsed because reset signals RST1 and RST2 552 are pulsed to reset the floating diffuser to a common reset level, such as the supply voltage of the voltage supply. After the reset, switch signals SW1 and SW2 538 are then enabled in this example, allowing the charge stored in the charge storage structure during integration to now be transferred to the floating diffuser. Pixel output signals PIXOUT1 and PIXOUT2 are then sampled and held to sample the signal output value of the pixel, as indicated by the SHS 568 pulse. In this example, after sampling the signal output value to reset the common-mode level between the first and second floating diffusers, the common-mode reset signal COM 548 is pulsed again. In this example, pixel output signals PIXOUT1 and PIXOUT2 are then sampled and held again to sample the reset output value of the pixel, as indicated by the SHR 566 pulse. Those skilled in the art will understand that in Figure 5C In the illustrated operation, the pixel output signal associated with the photogenerated image charge is sampled before the reset signal is sampled, therefore the associated double processing operation can be omitted. It should also be further understood that, according to the teachings of the present invention, for example by including... Figure 1The differential amplifier circuit in the control circuit 124 can determine the difference between the sampling reset signal value and the sampling signal output value to determine the pixel output value. (Selectable...) Figure 5C The operation shown maximizes the full-well capacity, i.e., the combined capacity of the charge storage structure and the floating diffuser, but with a lower conversion gain, making it suitable for outdoor imaging applications.

[0085] like Figure 5D As shown, another example of pixel operation in 3D depth mode begins with a precharge-reset cycle, during which the elements in the pixel are precharged or reset to their initial values. Therefore, during the initial precharge or reset cycle, the overflow signal OFG 542, transfer signals TX1 536A and TX2 536B, reset signals RST1 and RST2 552, switch signals SW1 and SW2 538, and shutter signal 540 are all pulsed high, while the row selection signals RS1 546A and RS2 546B and the common-mode reset signal COM 548 remain low. In this example, the strobe signal 544 is set to a first voltage level.

[0086] During the integration period, transfer signals TX1 536A and TX2 536B are alternately pulsed, which sequentially and repeatedly transfer or pump photogenerated charge from the photodiode to the first single shared channel region or the second single shared channel region during the pixel's integration period. Furthermore, the shutter signal 540 remains disabled during the integration period, while the switching signals SW1 and SW2 538 are enabled. Therefore, in the depicted example, the charge transferred from the photodiode during the integration period is stored in the charge storage structure, but not in the floating diffuser. In this example, the gating signal 544 coupled to the charge storage structure remains set to a first voltage level during integration.

[0087] During the readout cycle, the overflow signal OFG 542 is enabled, which allows the overflow transistor to discharge excess image charge from the photodiode. Therefore, in bright, sunny outdoor conditions, pixel performance can be improved, as image charge generated by ambient light during readout can be discharged through the overflow transistor. In this example, during the readout cycle, switch signals SW1 and SW2 538 are disabled, disconnecting the switch gate to isolate the charge stored in the charge storage structure from the floating diffuser. The shutter signal 540 and line selection signals RS1 546A and RS2 546B are enabled, enabling the readout of pixel output signals PIXOUT1 and PIXOUT2 from the pixel. The floating diffuser is then reset as indicated by the pulses of reset signals RST1 and RST2 552. In one example, the common-mode reset signal COM 548 is also pulsed, as reset signals RST1 and RST2 552 are pulsed to reset the floating diffuser to a common reset level, such as the supply voltage of the voltage supply. In this example, pixel output signals PIXOUT1 and PIXOUT2 are then sampled and held to sample the pixel's reset output value, as indicated by the SHR 566 pulse. After the pixel's reset output value has been sampled, strobe signal 544 is pulsed or switched from a first voltage level to a second voltage level, as shown, causing the charge stored in the first charge storage structure and the second charge storage structure to overflow through the first and second switch gates to the first and second floating diffusers, which are kept disabled by switch signals SW1 and SW2 538 during the pixel's readout cycle. In this example, the second voltage level of strobe signal 544 is lower than the first voltage level. The first voltage level of strobe signal 544 can be configured based on the supply voltage of the voltage supply, and the second voltage level of strobe signal 544 can be configured based on the light intensity and the amount of charge stored therein, as well as the threshold voltage of the switch gate, so that the image charge stored at the charge storage structure can overflow and be transferred to the floating diffuser through a single shared channel region between the switch gate and the shutter gate. Then the pixel output signals PIXOUT1 and PIXOUT2 are sampled and held again to sample the signal output value of the pixel, as indicated by the SHS 568 pulse. Those skilled in the art will understand that... Figure 5D In the operation shown, according to the teachings of the present invention, after the reset signal is sampled, the pixel output signal associated with the photogenerated image charge is sampled, so that a correlated double sampling (CDS) operation can be performed to determine the difference between the sampled reset signal value and the sampled signal output value, thereby determining the CDS pixel output value.

[0088] In one embodiment, a wider pixel dynamic range can be achieved by sampling the readout signal multiple times with different conversion gains. The conversion gain can be varied by selectively turning on the switch gate and the shutter gate. For example, during a first readout time interval, the switch gate and the shutter gate can be turned on to provide a low conversion gain for signal output readout, since the pixel's conversion gain will be determined by the capacitance of the charge storage structure and the floating diffuser. During a second readout time interval, the switch gate can be turned off while the shutter gate is turned on to provide a medium-level conversion gain for signal output readout, since the pixel's conversion gain will be determined by the capacitance of the shutter gate and the floating diffuser. During a third readout time interval, the switch gate and the shutter gate can be turned off to provide a high conversion gain for signal output, since the pixel's conversion gain in the third time interval will be determined by the capacitance of the floating diffuser.

[0089] like Figure 5E As shown, an example of pixel operation in 2D intensity mode begins with a precharge reset cycle, during which the elements in the pixel are precharged or reset to their initial values. Therefore, during the initial precharge or reset cycle, the overflow signal OFG 542, transfer signals TX1 536A and TX2 536B, reset signals RST1 and RST2 552, switch signals SW1 and SW2 538, and shutter signal 540 are all pulsed high, while the strobe signal 544, line selection signals RS1 546A and RS2 546B, and common-mode reset signal COM 548 remain low.

[0090] During the integration period, transfer signal TX1 536A is enabled, while transfer signal TX2 536B is disabled. Therefore, it should be understood that in the depicted example, the first transfer transistor and the first floating diffuser are used to generate the first output pixel value PIXOUT1. When transfer signal TX1 536A is enabled, during the pixel's integration period, photogenerated charge from the photodiode is transferred to the first single shared channel region. Additionally, switching signals SW1 and SW2 538 remain disabled, while shutter signal 540 is enabled during the integration period. Therefore, during the integration period, the charge transferred from the photodiode is stored in the first floating diffuser but not in the charge storage structure. Therefore, according to the teachings of the present invention, in the described example, the pixel is set to low FWC and high conversion gain.

[0091] During the readout cycle, the overflow signal OFG 542 is enabled, which allows the overflow transistor to discharge excess image charge from the photodiode. Therefore, pixel performance can be improved because image charge generated by ambient light during the readout cycle can be discharged through the overflow transistor. During the readout cycle, the shutter signal 540 and line selection signals RS1 546A and RS2 546B are enabled, enabling the readout of the pixel output signal PIXOUT1. The pixel output signal is sampled and held during the readout cycle to sample the pixel's signal output value, as indicated by the SHS 568 pulse. In this example, the floating diffuser is then reset, as indicated by the pulses of reset signals RST1 and RST2 552. In one example, the common-mode reset signal COM 548 can also optionally be pulsed, since the reset signals RST1 and RST2 552 are pulsed to reset the floating diffuser to a common reset level, such as the supply voltage of the voltage supply. In this example, the pixel output signal is then sampled and held again to sample the pixel's reset output value, as indicated by the SHR 566 pulse. Those skilled in the art will understand that... Figure 5E In the operation shown, the pixel output signal associated with the charge of the photogenerated image is sampled before the remaining signal is sampled, so the associated double sampling operation can be omitted. It should be further understood that, according to the teachings of the present invention, for example by including... Figure 1 The differential amplifier circuit in the control circuit 124 can calculate the difference between the sampled signal output value and the sampled reset signal value to determine the pixel output value.

[0092] like Figure 5F As shown, another example of pixel operation in 2D intensity mode begins with a precharge reset period, during which the elements in the pixel are precharged or reset to their initial values. Therefore, during the initial precharge or reset cycle, the overflow signal OFG 542, transfer signals TX1 536A and TX2 536B, reset signals RST1 and RST2 552, switch signals SW1 and SW2 538, and shutter signal 540 are all pulsed high, while the strobe signal 544, line selection signals RS1 546A and RS2 546B, and common-mode reset signal COM 548 remain low.

[0093] During the integration period, transfer signal TX1 536A is enabled, while transfer signal TX2 536B is disabled. Therefore, it should be understood that in the depicted example, the first transfer transistor and the first floating diffuser are used to generate the first output pixel value PIXOUT1. When transfer signal TX1 536A is enabled, during the pixel's integration period, photogenerated charge from the photodiode is transferred to the first single shared channel region. Furthermore, switching signals SW1 and SW2 538 and shutter signal 540 remain disabled during the integration period. Therefore, during the integration period, the charge transferred from the photodiode is stored in the transfer gate capacitance, but not in the charge storage structure or the floating diffuser. Therefore, according to the teachings of the present invention, in the described example, the pixel is set to low FWC and high conversion gain.

[0094] During the readout cycle, the overflow signal OFG 542 is enabled, which allows the overflow transistor to discharge excess image charge from the photodiode. Therefore, pixel performance can be improved because image charge generated by ambient light during the readout cycle can be discharged through the overflow transistor. In this example, the transfer gate signal 536A remains high during the readout cycle, so that the charge transferred from the photodiode during the integration cycle is stored in the transfer gate capacitance. During the readout cycle, the switch signals SW1 and SW2 538 are also disabled, which disconnect the switch gate to isolate the charge stored in the transfer gate capacitance from the charge storage structure. The shutter signal 540 and the line selection signals RS1 546A and RS2 546B are enabled, enabling the pixel output signal PIXOUT1 to be read from the pixel. The floating diffuser is then reset, as indicated by the pulses of the reset signals RST1 and RST2 552. In this example, the pixel output signals PIXOUT1 and PIXOUT2 are then sampled and held to sample the pixel's reset output value, as indicated by the SHR 566 pulse. As shown in the figure, after the reset output value of the pixel has been sampled, the shutter signal 540 is pulsed, causing the charge stored in the first transfer gate capacitor to be transferred to the first floating diffuser. Then, the pixel output signals PIXOUT1 and PIXOUT2 are sampled and held again to sample the signal output value of the pixel, as indicated by the SHS 568 pulse. Therefore, it should be understood that, according to the teachings of the present invention, because the sampled pixel output signal is related to the sampled reset signal, the difference between the sampled reset signal value and the sampled signal output value can be determined by a correlated double sampling operation to determine the CDS pixel output value.

[0095] Those skilled in the art should understand that Figures 5A to 5F The operation shown can be controlled by the control circuitry of the time-of-flight optical sensing system (e.g., Figure 1The control circuit 124 is used to implement this. The control circuit may contain logic for controlling the operation of the light source and the image sensor with multiple pixels. The control circuit may further include built-in memory (e.g., random access memory, erasable read-only memory, etc.), and the memory can be programmed to cause the control circuit to perform... Figures 5A to 5F The operation described herein. As mentioned above, the control circuit can be an application-specific integrated circuit (ASIC – custom-designed for time-of-flight optical sensing systems), a general-purpose processor that can be programmed in a variety of different ways, or a combination of both.

[0096] The foregoing description of illustrative examples of the invention includes the content described in the abstract and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention have been described herein for illustrative purposes, various modifications are possible within the scope of the invention, as will be recognized by those skilled in the art.

[0097] Based on the detailed description above, these modifications can be made to the invention. The terminology used in the following claims should not be construed as limiting the invention to the specific instances disclosed in the specification. Rather, the scope of the invention is determined entirely by the appended claims, which will be interpreted according to the established principles of claim interpretation.

Claims

1. A pixel circuit comprising: a photodiode disposed in a layer of semiconductor material to accumulate image charge in response to light incident on the photodiode; a first three-gate charge transfer block coupled to the photodiode, wherein the first three-gate charge transfer block comprises: a first single shared channel region disposed in the layer of semiconductor material; a first transfer gate disposed proximate to the first single shared channel region, wherein the first transfer gate is configured to transfer the image charge accumulated in the photodiode to the first single shared channel region in response to a first transfer signal; a first shutter gate disposed proximate to the first single shared channel region, wherein the first shutter gate is configured to transfer the image charge in the first single shared channel region to a first floating diffusion disposed in the layer of semiconductor material in response to a first shutter signal; and a first switch gate disposed proximate to the first single shared channel region, wherein the first switch gate is configured to couple the first single shared channel region to a first charge storage structure disposed in the layer of semiconductor material in response to a first switch signal; and a second three-gate charge transfer block coupled to the photodiode, wherein the second three-gate charge transfer block comprises: a second single shared channel region disposed in the layer of semiconductor material; a second transfer gate disposed proximate to the second single shared channel region, wherein the second transfer gate is configured to transfer the image charge accumulated in the photodiode to the second single shared channel region in response to a second transfer signal; a second shutter gate disposed proximate to the second single shared channel region, wherein the second shutter gate is configured to transfer the image charge in the second single shared channel region to a second floating diffusion disposed in the layer of semiconductor material in response to a second shutter signal; and a second switch gate disposed proximate to the second single shared channel region, wherein the second switch gate is configured to couple the second single shared channel region to a second charge storage structure disposed in the layer of semiconductor material in response to a second switch signal.

2. The pixel circuit of claim 1, wherein the first charge storage structure comprises a capacitor, wherein the first switch gate is configured to couple the first single shared channel region to the capacitor to regulate a full well capacity (FWC) of the pixel circuit in response to the first switch signal.

3. The pixel circuit of claim 2, wherein the capacitor is a metal-oxide semiconductor capacitor (MOSCAP) storage structure comprising the first switch gate, wherein the first switch gate is configured to regulate the FWC of the pixel circuit in response to the first switch signal.

4. The pixel circuit of claim 1, further comprising an overflow transistor coupled between a voltage supply and the photodiode, wherein the overflow transistor is configured to drain excess image charge from the photodiode in response to an overflow signal.

5. The pixel circuit of claim 1, further comprising: a reset transistor coupled between a voltage supply and the first floating diffusion, wherein the reset transistor is coupled to reset the first floating diffusion in response to a reset signal; a source follower transistor coupled to the first floating diffusion, wherein the source follower transistor is coupled to generate a pixel output signal in response to the image charge in the first floating diffusion; and a row select transistor coupled to the source follower transistor, wherein a row select signal is coupled to output the pixel output signal from the source follower transistor in response to a row select signal.

6. The pixel circuit of claim 1, further comprising a common mode transistor coupled between the first floating diffusion and the second floating diffusion, wherein the common mode transistor is configured to reset a common mode level between the first floating diffusion and the second floating diffusion in response to a common mode reset signal.

7. The pixel circuit of claim 1, further comprising: a second reset transistor coupled between a voltage supply and the second floating diffusion, wherein the second reset transistor is coupled to reset the second floating diffusion in response to a second reset signal; a second source follower transistor coupled to the second floating diffusion, wherein the second source follower transistor is coupled to generate a second pixel output signal in response to the image charge in the second floating diffusion; and a second row select transistor coupled to the second source follower transistor, wherein a second row select signal is coupled to output the second pixel output signal from the second source follower transistor in response to the second row select signal.

8. The pixel circuit of claim 1, wherein the first single shared channel region and the second single shared channel region comprise a doped region.

9. The pixel circuit of claim 1, wherein the first single shared channel region and the second single shared channel region comprise an undoped region.

10. The pixel circuit of claim 1, wherein the layer of semiconductor material comprises a semiconductor substrate layer, the semiconductor substrate layer including dopants having a first polarity, and wherein the photodiode includes a doped region, the doped region including dopants having a second polarity disposed in the semiconductor substrate layer.

11. The pixel circuit of claim 10, wherein the semiconductor substrate layer including the dopants having the first polarity comprises a p-type semiconductor substrate layer, and wherein the doped region including the dopants having the second polarity comprises an n-type doped region disposed in the p-type semiconductor substrate layer.

12. The pixel circuit of claim 11, wherein the light incident on the photodiode is directed through a backside surface of the semiconductor material layer into the n-type doped region, wherein a cross-sectional area of the n-type doped region decreases from a wide cross-sectional area of a portion of the n-type doped region proximate to the backside surface of the semiconductor material layer to a narrow cross-sectional area of a portion of the n-type doped region proximate to a frontside surface of the semiconductor material layer.

13. The pixel circuit of claim 12, wherein a doping profile of the dopant in the n-type doped region is a gradient doping profile that increases from the portion of the n-type doped region proximate to the backside surface of the semiconductor material layer to the portion of the n-type doped region proximate to the frontside surface of the semiconductor material layer.

14. The pixel circuit of claim 13, wherein the p-type semiconductor substrate layer has a doping concentration in the range of 1E12 to 1E14 atoms / cm 3 , wherein the portion of the n-type doped region nearest the backside surface of the semiconductor substrate layer has a doping concentration of 1E12 atoms / cm 3 , wherein the portion of the n-type doped region nearest the frontside surface of the semiconductor substrate layer has a doping concentration of 1E16 atoms / cm 3 , and wherein an intermediate portion of the n-type doped region between the frontside surface and the backside surface of the semiconductor substrate layer has a doping concentration of 1E15 atoms / cm 3 .

15. The pixel circuit of claim 10, wherein the first triple gate charge transfer block further comprises a vertical transfer gate structure in the semiconductor material layer, the vertical transfer gate structure extending into the semiconductor material layer from a frontside surface of the semiconductor material layer below the first transfer gate toward a backside surface of the semiconductor material layer and into the photodiode.

16. The pixel circuit of claim 15, wherein the vertical transfer gate structure comprises a highly doped region comprising dopants of the second polarity.

17. The pixel circuit of claim 16, wherein the highly doped region of the vertical transfer gate structure is an n-type vertical implant channel having a doping concentration in a range of 1E15 atoms / cm 3 to 1E18 atoms / cm 3 .

18. The pixel circuit of claim 15, wherein the first transfer gate comprises polysilicon, and wherein the vertical transfer gate structure comprises polysilicon extending into the semiconductor material layer from the first transfer gate on the frontside surface of the semiconductor material layer toward the backside surface of the semiconductor material layer and into the photodiode.

19. The pixel circuit of claim 18, further comprising an insulating layer disposed between the semiconductor material layer and the vertical transfer gate structure and between the semiconductor material layer and the first transfer gate.

20. A light sensing system comprising: a light source that emits light toward an object; a pixel array optically coupled to sense the emitted light reflected from the object, wherein the pixel array includes a plurality of pixels, wherein each of the pixels comprises: a photodiode disposed in a semiconductor material layer to accumulate image charge in response to the reflected light incident on the photodiode; a first triple gate charge transfer block coupled to the photodiode, wherein the first triple gate charge transfer block comprises: a first single shared channel region disposed in the semiconductor material layer; a first transfer gate disposed proximate to the first single shared channel region, wherein the first transfer gate is configured to transfer the image charge accumulated in the photodiode to the first single shared channel region in response to a first transfer signal; a first shutter gate disposed proximate to the first single shared channel region, wherein the first shutter gate is configured to transfer the image charge in the first single shared channel region to a first floating diffusion disposed in the semiconductor material layer in response to a first shutter signal; and a first switch gate disposed proximate to the first single shared channel region, wherein the first switch gate is configured to couple the first single shared channel region to a first charge storage structure disposed in the semiconductor material layer in response to a first switch signal; and a second three-gate charge transfer block coupled to the photodiode, wherein the second three-gate charge transfer block comprises: a second single shared channel region disposed in the semiconductor material layer; a second transfer gate disposed proximate to the second single shared channel region, wherein the second transfer gate is configured to transfer the image charge accumulated in the photodiode to the second single shared channel region in response to a second transfer signal; a second shutter gate disposed proximate to the second single shared channel region, wherein the second shutter gate is configured to transfer the image charge in the second single shared channel region to a second floating diffusion disposed in the semiconductor material layer in response to a second shutter signal; and a second switch gate disposed proximate to the second single shared channel region, wherein the second switch gate is configured to couple the second single shared channel region to a second charge storage structure disposed in the semiconductor material layer in response to a second switch signal; a control circuit coupled to control the light source and the array of pixels to sense the emitted light reflected from the object to the array of pixels.

21. The light sensing system of claim 20, wherein the first charge storage structure comprises a capacitor, wherein the first switch gate is configured to couple the first single shared channel region to the capacitor to adjust a full well capacity (FWC) of the pixel in response to the first switch signal.

22. The light sensing system of claim 21, wherein the capacitor is a metal-oxide-semiconductor capacitor (MOSCAP) storage structure comprising the first switch gate, wherein the first switch gate is configured to adjust the FWC of the pixel in response to the first switch signal.

23. The light sensing system of claim 20, wherein each of the pixels further comprises an overflow transistor coupled between a voltage supply and the photodiode, wherein the overflow transistor is configured to drain excess image charge from the photodiode in response to an overflow signal.

24. The light sensing system of claim 20, wherein each of the pixels further comprises: a reset transistor coupled between a voltage supply and the first floating diffusion, wherein the reset transistor is coupled to reset the first floating diffusion in response to a reset signal; a source follower transistor coupled to the first floating diffusion, wherein the source follower transistor is coupled to generate a pixel output signal in response to the image charge in the first floating diffusion; and a row select transistor coupled to the source follower transistor, wherein a row select signal is coupled to output the pixel output signal from the source follower transistor in response to the row select signal.

25. The light sensing system of claim 20, further comprising a common mode transistor coupled between the first floating diffusion and the second floating diffusion, wherein the common mode transistor is configured to reset a common mode level between the first floating diffusion and the second floating diffusion in response to a common mode reset signal.

26. The light sensing system of claim 20, wherein each of the pixels further comprises: a second reset transistor coupled between a voltage supply and the second floating diffusion, wherein the second reset transistor is coupled to reset the second floating diffusion in response to a second reset signal; a second source follower transistor coupled to the second floating diffusion, wherein the second source follower transistor is coupled to generate a second pixel output signal in response to the image charge in the second floating diffusion; and a second row select transistor coupled to the second source follower transistor, wherein a second row select signal is coupled to output the second pixel output signal from the second source follower transistor in response to the second row select signal.

27. The light sensing system of claim 20, wherein the first single shared channel region and the second single shared channel region comprise a doped region.

28. The light sensing system of claim 20, wherein the first single shared channel region and the second single shared channel region comprise an undoped region.

29. The light sensing system of claim 20, wherein the control circuit is coupled to sense a time of flight of the emitted light reflected from the object to the pixel array by detecting a phase difference between the emitted light and the emitted light reflected from the object to the pixel array.

30. A method of sensing light using a pixel, the method comprising: illuminating a photodiode disposed in a layer of semiconductor material with light reflected from an object; accumulating charge photo-generated in the photodiode in response to the light reflected from the object during an integration period of the pixel; transferring the charge from the photodiode to a first single shared channel region in the layer of semiconductor material of a first three-gate charge transfer block coupled to the photodiode in response to a first transfer gate being enabled in response to a first transfer signal, wherein the first single shared channel region is shared between the first transfer gate, a first shutter gate, and a first switch gate of the first three-gate charge transfer block; transferring the charge from the first single shared channel region to a first floating diffusion in response to the first shutter gate being enabled in response to a first shutter signal; transferring the charge from the first floating diffusion to a second floating diffusion in response to the first switch gate being enabled in response to a first switch signal; and outputting a pixel output signal from the second floating diffusion in response to a row select signal being coupled to the second source follower transistor. converting the charge in the first floating diffusion to a first pixel output signal using a first source follower transistor coupled to the first floating diffusion; reading the first pixel output signal during a readout period of the pixel that occurs after the integration period of the pixel; in response to a second transfer gate being enabled in response to a second transfer signal, transferring the charge from the photodiode to a second single shared channel region in the layer of semiconductor material of a second triple- gate charge transfer block coupled to the photodiode, wherein the second single shared channel region is shared between the second transfer gate, a second shutter gate, and a second switch gate of the second triple-gate charge transfer block; in response to the second shutter gate being enabled in response to a second shutter signal, transferring the charge from the second single shared channel region to a second floating diffusion; converting the charge in the second floating diffusion to a second pixel output signal using a second source follower transistor coupled to the second floating diffusion; and reading the second pixel output signal during the readout period of the pixel that occurs after the integration period of the pixel.

31. The method of claim 30, further comprising: in response to a first reset transistor being enabled in response to a first reset signal, resetting the first floating diffusion; after resetting the first floating diffusion, reading a first reset output value from the first floating diffusion; and determining a first pixel output value based on a difference between the first pixel output signal and the first reset output value.

32. The method of claim 31, wherein the resetting the first floating diffusion and the reading the first reset output value occur before the transferring the charge from the first single shared channel region to a first floating diffusion and the reading the first pixel output signal.

33. The method of claim 31, wherein the resetting the first floating diffusion and the reading the first reset output value occur after the transferring the charge from the first single shared channel region to a first floating diffusion and the reading the first pixel output signal.

34. The method of claim 33, further comprising in response to a common mode transistor coupled between the first floating diffusion and the second floating diffusion being enabled during the resetting the first floating diffusion, resetting a common mode level between the first floating diffusion and the second floating diffusion.

35. The method of claim 30, further comprising resetting the pixel during a pre-charge reset period of the pixel that occurs before the integration period of the pixel.

36. The method of claim 30, further comprising enabling an overflow transistor coupled between a voltage supply and the photodiode during the readout period of the pixel, wherein the overflow transistor is configured to drain excess image charge from the photodiode in response to an overflow signal.

37. The method of claim 30, wherein said transferring the charge from the photodiode to a first single shared channel region in the semiconductor material layer of a first triple- gate charge transfer block coupled to the photodiode and wherein said transferring the charge from the photodiode to a second single shared channel region in the semiconductor material layer of a second triple-gate charge transfer block coupled to the photodiode comprises: alternately transferring the charge from the photodiode to the first single shared channel region or the second single shared channel region in sequence repeatedly during the integration period of the pixel in response to the first transfer signal and the second transfer signal.

38. The method of claim 37, wherein the first transfer signal and the second transfer signal comprise sequences of oscillating pulses that are out of phase with each other during the integration period of the pixel.

39. The method of claim 30, wherein the transferring the charge from the first single shared channel region to a first floating diffusion and the transferring the charge from the second single shared channel region to a second floating diffusion occur during the integration period of the pixel and a readout period of the pixel.

40. The method of claim 30, wherein the transferring the charge from the first single shared channel region to a first floating diffusion and the transferring the charge from the second single shared channel region to a second floating diffusion occur after the integration period of the pixel and during a readout period of the pixel.

41. The method of claim 30, further comprising: enabling the first switch gate in response to a first switch signal to couple the first single shared channel region to a first charge storage structure disposed in the layer of semiconductor material in response to the first switch signal; enabling the second switch gate in response to a second switch signal to couple the second single shared channel region to a second charge storage structure disposed in the layer of semiconductor material in response to the second switch signal; disabling the first switch gate in response to the first switch signal to decouple the first single shared channel region from the first charge storage structure disposed in the layer of semiconductor material in response to the first switch signal; and disabling the second switch gate in response to the second switch signal to decouple the second single shared channel region from the second charge storage structure disposed in the layer of semiconductor material in response to the second switch signal.

42. The method of claim 41, wherein the enabling the first shutter gate in response to the first shutter signal, the enabling the second shutter gate in response to the second shutter signal, the enabling the first switch gate in response to the first switch signal, and the enabling the second switch gate in response to the second switch signal occur during the integration period of the pixel and the readout period.

43. The method of claim 41, wherein the enabling the first shutter gate in response to the first shutter signal, the enabling the second shutter gate in response to the second shutter signal, the disabling the first switch gate in response to the first switch signal, and the disabling the second switch gate in response to the second switch signal occur during the integration period of the pixel and the readout period.

44. The method of claim 41, further comprising: ​ disable the first shutter gate in response to the first shutter signal while enabling the first switch gate in response to the first switch signal to couple a first channel region to the first charge storage structure and transfer the charge from the first channel region to the first charge storage structure; and disable the second shutter gate in response to the second shutter signal while enabling the second switch gate in response to the second switch signal to couple a second channel region to the second charge storage structure and transfer the charge from the second channel region to the second charge storage structure.

45. The method of claim 44, wherein the disable the first shutter gate in response to the first shutter signal, the disable the second shutter gate in response to the second shutter signal, the enable the first switch gate in response to the first switch signal, and the enable the second switch gate in response to the second switch signal occur during the integration period of the pixel.

46. The method of claim 44, wherein the enable the first shutter gate in response to the first shutter signal and the enable the second shutter gate in response to the second shutter signal occur during the readout period of the pixel.

47. The method of claim 46, wherein the disable the first switch gate in response to the first switch signal and the disable the second switch gate in response to the second switch signal occur during the readout period of the pixel.

48. The method of claim 47, further comprising pulsing a strobe signal coupled to the first charge storage structure and the second charge storage structure to overflow charge stored in the first charge storage structure and the second charge storage structure to the first floating diffusion and the second floating diffusion while disabling the first switch gate and the second switch gate during the readout period of the pixel.

49. The method of claim 41, further comprising: resetting the first floating diffusion in response to enabling a first reset transistor in response to a first reset signal; and resetting the second floating diffusion in response to enabling a second reset transistor in response to a second reset signal, wherein the enable the first switch gate in response to the first switch signal and the enable the second switch gate in response to the second switch signal occur after the reset the first floating diffusion and the reset the second floating diffusion during the readout period of the pixel.

50. The method of claim 49, further comprising: reading the first pixel output signal and the second pixel output signal after enabling the first switch gate and the second switch gate; resetting a common mode level between the first floating diffusion and the second floating diffusion in response to enabling a common mode transistor coupled between the first floating diffusion and the second floating diffusion; and reading first and second reset output values after resetting the common mode level between the first and second floating diffusion portions.

Images