Split-gate flash memory cell with improved read performance

Abstract

Embodiments of the present disclosure provide systems and methods for improving a read window in a split gate flash memory cell, for example, by biasing a control gate terminal with a non-zero (positive or negative) voltage during a cell read operation to improve or control the erased state read performance or programmed state read performance of the cell. A method of operating a split gate flash memory cell may include performing a program operation, performing an erase operation, and performing a read operation in the cell, wherein each read operation includes applying a first non-zero voltage to a word line, applying a second non-zero voltage to a bit line, and applying a third non-zero voltage V to a control gate. CGR .

Description

Technical Field

[0001] The present disclosure relates to split gate memory cells, and more particularly to systems and methods for improving the read window in split gate flash memory cells, such as by biasing the control gate terminal during a read operation to improve or control cell read performance. Background Art

[0002] Figure 1 A side cross-sectional view of a known split-gate flash memory cell 10 is shown, which includes a pair of floating gates 12A and 12B formed above a substrate 14, word lines 16A and 16B extending above floating gates 12A and 12B, respectively, and a control gate 20 extending above floating gates 12A and 12B. Oxide regions 18A and 18B are formed above floating gates 12A and 12B, respectively. Word lines 16A and 16B may, for example, represent odd-row word lines 16A and even-row word lines 16Bb, or vice versa. Doped source regions or junctions 24 may be formed in substrate 14 below control gates 20 and extend partially below each floating gate 12A and 12B, and a pair of doped bit line regions or junctions 24A and 24B may be formed in substrate 20 adjacent to word lines 16A and 16B.

[0003] Memory cell 10 may also include conductive contacts with word lines 16A and 16B, control gate 20, source region 24, and bit line regions 24A and 24B for applying voltages to various cell components to provide various memory cell functions, such as programming, erasing, and reading. As shown, these contacts may include word line contacts 30A and 30B, control gate contact 32, source contact 34, and bit line contacts 36A and 36B.

[0004] In some embodiments, the split-gate flash memory cell 10 is a SuperFlash cell (e.g., a SuperFlash ESF1+ cell) from Microchip Technology Inc., headquartered at 2355 W Chandler Boulevard, Chandler, Arizona 85224. Thus, in some embodiments, the split-gate flash memory cell 10 may include a cell as disclosed in U.S. Patent 8,711,636 or a variation thereof.

[0005] The split gate flash memory cell 10 can be programmed and erased by applying defined voltages at defined times to one or more of the following: the selected word line contact 30A or 30B (V WL ), control gate contact 32 (V CG ), source contact 34 (V SL ), and / or the selected bit line contact 36A or 36B (V BL), thereby providing (a) cell current Ir0 corresponding to the programmed state (“off” state) of the cell or (b) cell current Ir1 corresponding to the erased state (“on” state) of the cell. In addition, the cell current Ir1 can be controlled by supplying a current to the selected word line contact 30A or 30B (V WL ) and the adjacent bit line contact 36A or 36B (V BL ) applies a defined voltage to read the current programmed / erase state of the cell.

[0006] Figure 2 is a table showing exemplary voltages that may be applied to various contacts of a split gate flash memory cell 10 to perform program, erase, and read functions according to conventional cell operation. As shown, a conventional read function is performed via word line 16A or 16B and associated bit line 24A or 24B by applying a defined V WL and V BL is applied to the selected word line contact 30A or 30B and the associated bit line contact 36A or 36B, while no voltage is applied to the source contact 34 (V SL =0) or control gate contact 32 (V CG =0).

[0007] However, as discussed herein, the inventors have contemplated applying a selected non-zero voltage (positive or negative) (such as V CGR ) is applied to the control gate contact 32 to selectively tune the memory cell to improve or control read performance. Summary of the Invention

[0008] Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, for example, by biasing the control gate terminal with a non-zero (positive or negative) voltage during a cell read operation to improve or control the erased state read performance or programmed state read performance of the cell.

[0009] For example, a non-zero negative voltage V can be applied to the control gate at the expense of erased state read performance. CGR To improve the programming state reading performance of the cell. Similarly, a non-zero positive voltage V can be applied to the control gate at the expense of programming state reading performance. CGR To improve the erased state read performance of the cell. In view of these performance trade-offs, the V of any particular memory cell can be set based on the intended use and / or performance characteristics of the memory cell (e.g., such as endurance, read speed, etc.). CGR .

[0010] For example, for memory cells where erased state read performance is particularly important, V CGRFor example, for memory cells used in high cycle / high endurance target applications, V is set to a positive value based on the knowledge that erase performance typically degrades faster or to a greater extent than program performance. CGR Can be set to a positive value to improve long-term / high cycle erase read performance. Alternatively, for memory cells where programmed state read performance is particularly important, or for memory cells that can be poorly or poorly programmed, V CGR Can be set to negative values. In addition, different V CGR The values ​​may also be used for read operations via even rows WL and read operations via odd rows WL, for example, to compensate for asymmetries created during formation of the cell, such as based on the respective overlap (x or y direction) between one of the word lines 16A, 16B or the control gate 20 over the floating gates 12A and 12B (see Figure 1 for reference).

[0011] Some embodiments provide a device comprising a plurality of flash memory cells having different measured programmed and / or erased state current values, wherein the different VCGR Values ​​are set (eg, stored in corresponding trim bits) and applied to different flash memory cells in the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example aspects of the present disclosure are described below with reference to the accompanying drawings, in which:

[0013] Figure 1 A side cross-sectional view of a split-gate flash memory cell is shown, which includes a pair of floating gates, a word line extending over each floating gate, and a control gate extending over both floating gates.

[0014] Figure 2 is shown according to the conventional unit operation can be applied to Figure 1 1. A table of exemplary voltages for various contacts of a split-gate flash memory cell to perform program, erase, and read operations.

[0015] Figure 3A FIG. 1 is a diagram illustrating the application of a control gate voltage V when performing a program state (off state) read operation on an exemplary split gate flash memory cell according to one embodiment. C A diagram showing exemplary effects of .

[0016] Figure 3B and Figure 3C FIG. 1 is a diagram illustrating the application of a control gate voltage V when performing an erased state (on state) read operation on an exemplary split gate flash memory cell according to one embodiment. C A diagram showing exemplary effects of .

[0017] Figure 4AAn exemplary method or algorithm according to one embodiment of the present invention is shown for determining the control gate voltage V applied to a fabricated memory cell based on the initial programming current and / or erase current of the cell at the time of fabrication (e.g., determined in a sorting test). CGR .

[0018] Figure 4B The different control gate voltages V CGR Applies to read operations on different types of memory cells (eg, program flash cells and data flash cells).

[0019] Figure 5 shows that by placing the control gate read voltage V CGR The ability to tune to different values ​​read via even cells than via odd cells compensates for asymmetry in programmed cell read performance between even and odd cells (eg, even and odd word lines).

[0020] Figure 6 An exemplary system or device according to an exemplary embodiment is shown that includes a plurality of flash memory cells having control gates, and control electronics configured to apply a non-zero bias to the control gates during a read operation of the plurality of flash memory cells. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, for example, by biasing the control gate terminal during a read operation to improve or control the cell read performance, for example, by improving the erased state read performance or the programmed state read performance of the cell.

[0022] Figure 3A is a data chart 100 showing the Figure 1 The exemplary split gate flash memory cell 10 shown performs a read operation in a programmed state (off state) by controlling the gate voltage V CGR Example effects of biasing the control gate 20. Graph 100 shows the sense cell off-state current (Ir0, in μA) as a function of V applied during a programmed state read operation for reading at a well-programmed cell (programming voltage = 7.5 V) and a poorly programmed cell (programming voltage = 6.5 V). CGR And changes.

[0023] As is known in the art, programmed state read performance improves with lower sense off-state current (Ir0). Figure 3A shows that when the control gate voltage V CGRWhen the current Ir0 decreases and becomes negative, the sensed off-state current Ir0 decreases, resulting in an improved programming state reading operation. Figure 5 As mentioned, using negative V CGR It also reduces the asymmetry between even and odd WL row read operations, which is common in split-gate flash memory cells due to manufacturing tolerances or defects, especially on cells that are rarely programmed. CGR It is beneficial to improve the programming state reading Ir0 margin. In essence, negative V CGR The application of makes the cell appear to be well programmed even though it is not well programmed.

[0024] Figure 3B and Figure 3C FIG. 1 is a diagram illustrating application of a control gate voltage V to an exemplary split-gate flash memory cell during an erased state (on-state) read operation according to one embodiment. CGR Specifically, Figure 3B The graph 110 shows the relationship between the control gate voltage V CGR and varies with the word line voltage V WL The sensing on-state current Ir1 changes, and Figure 3C The graph 120 shows the relationship between the control gate voltage V CGR and varies with the word line voltage V WL The percentage increase of the sensed on-state current Ir1 changes.

[0025] As is known in the art, erased-state read performance improves as the sensed on-state current ( Ir1 ) increases. Figure 3B and Figure 3C shows that with V CGR As Ir1 increases (positive values), the sensed Ir1 increases, thereby improving the on-state (erased state) read margin. The increase in Ir1 and the resulting improvement in on-state readability may depend on the coupling ratio between control gate 20 and the associated floating gate 12A or 12B, which typically varies with the inter-poly oxide thickness. Figure 3B and Figure 3C It is also shown that by increasing the V applied during the on-state read operation CGR , can reduce the word line voltage V WL , while still providing the same CGR =0 provides the same or greater sensed on-state current Ir1 than the conventional read operation.

[0026] Figure 4A An exemplary method or algorithm 200 is shown according to one embodiment of the present invention for setting V based on the measured programming current and / or erase current of the cell. CGRThe trim bit determines the control gate voltage V to be applied to the fabricated memory cell. CGR In this embodiment, the initial programming current and erase current of the cell can be measured after manufacturing (e.g., during sorting test). ref low) and the reference cell current (I ref =high) can define a window for delivering a cell current distribution (e.g., on-state current versus off-state current). In the exemplary algorithm 200, the initial programmed state current of the cell is measured at 202, and the initial erased state current of the cell is measured at 204. At 210, the initial programmed state cell current is compared to a fixed current source (I ref_low ) 206 and at 212, the initial erased state cell current is compared with the reference cell current (I ref_high ) 208 for comparison. V is then adjusted at 214 using comparators 210 and 212 on both the erase side and the program side. CGR programmable value and sets the corresponding trim bit value at 216. For example, if the initial programming state current 202 is higher than the fixed reference current 206, the comparator 210 in the programming state will have an output logic 1 (high). This output can then drive the downstream comparator 214 to an output state of 1, which will force V CGR Trim bit will V CGR The voltage is programmed to a more negative value (e.g., using a programmable gate with a gradual / step change to V CGR until the output of the programming state comparator 210 flips to the logic 0 (low) state, and the V CGR value (or V before the 1→0 flip of the comparator 210 output CGR value) can be set to V CGR Trimming bit.

[0027] Therefore, the algorithm 200 may calculate or determine V CGR The value can be used to "shift" the on / off current window to optimize the reading performance as needed, and the V CGR The value can be set to V in the flash memory CGR Trim bits (e.g., using fuse bits). For example, set V CGR Setting the trim bit to a negative value (e.g., -2V) can reduce both the sensed program state current Ir0 and the erased state current Ir1. CGR Setting the trim bit to a negative value can improve programmed state read performance at the expense of erased state read performance. Similarly, setting V CGR Setting the trim bit to a positive value (e.g., 6V) increases both the sensed program state current Ir0 and the erased state current Ir1. CGRSetting the trim bits to a positive value can improve erased state read performance at the expense of programmed state read performance.

[0028] In view of the above trade-offs, the V of any particular memory cell may be set based on the intended use and / or performance characteristics of that memory cell (e.g., such as endurance, read speed, etc.). CGR .

[0029] For example, for memory cells where erased state read performance is particularly important, V CGR For example, for memory cells used in high cycle / high endurance target applications, V CGR Can be set to a positive value to improve long term / high cycle erase read performance.

[0030] Alternatively, for memory cells where programmed state read performance is particularly important, or for memory cells that can be poorly or poorly programmed, V CGR Can be set to a negative value.

[0031] In one embodiment, a device may include multiple flash memory cells having different measured program and / or erase state current values, such that different V values ​​may be set for different flash memory cells in the device. CGR value (e.g., stored in the corresponding trim bits).

[0032] Figure 4B shows different control gate voltages V for read operations on different types of memory cells (eg, program flash cells and data flash cells) according to one embodiment of the present invention. C Applications. Program Flash memory typically has lower endurance specifications than data Flash memory. Due to its larger size and construction, program Flash memory is typically more susceptible to certain disturbance mechanisms, such as column disturbance. These disturbance mechanisms can be reduced by reducing the off-state current (Ir0) at the expense of the on-state current (Ir1). As mentioned above, the endurance degradation in this cell occurs primarily in the on-state current Ir1, so it can be reduced by using a negative V CGR To allow for a lower initial (pre-durability) Ir1.

[0033] In contrast, for data flash memory, the panel is typically much smaller but has a higher endurance specification. Because endurance degradation occurs primarily in the on-state current Ir1, V CGR Can be set to a positive value to obtain a higher sensed Ir1, thereby compensating for endurance-related erase degradation.

[0034] Therefore, the V CGRCan be set based on the intended use of the unit. In one embodiment, the device may include CGR Various types of flash memory (eg, program flash and data flash) are set (eg, stored in corresponding trim bits).

[0035] As described above, in some embodiments, applying a non-zero V CGR The cell read current asymmetry between even cells and odd cells (e.g., even and odd word lines / rows that share a common control gate) can be reduced. Such asymmetry is common in split-gate flash memory cells, especially on cells that are rarely programmed, due to manufacturing tolerances or imperfections (e.g., regarding the degree of overlap between word lines and / or control gates over the floating gates). For example, odd / even row asymmetry can be generated during formation of the cell based on the respective overlap (in the x-direction or y-direction) between word lines 16A, 16B or control gate 20 over floating gates 12A and 12B (see FIG. Figure 1 For reference). Misalignment during manufacturing can result in large x-direction overlap for even rows compared to odd rows, and vice versa. This overlap asymmetry can result in different erase or program performance for the cell compared to neighboring cells sharing the same source junction. The V CGR to compensate for this asymmetry.

[0036] In some embodiments, the control system can be configured to apply a non-zero V for cell reads via both odd and even rows WL. CGR For example, the control system can be configured to apply the same non-zero V for readings via both odd and even WLs. CGR (Positive or negative V CGR ). For another example, the control system may be configured to apply a first non-zero V for reading via odd rows WL. CGR1 (Positive or negative V CGR ), and applying a different second non-zero V for reading via even rows WL CGR2 (with same or opposite polarity).

[0037] Figure 5 is a graph 300 showing exemplary cell current data for an exemplary memory cell, where V is applied for readings from even rows WL for both erased and programmed state readings. CGR = -2V, and no control gate voltage (V CGR =0V), as marked as "Tuning V CGR , Erase Read" and "Tuning V CGR, program read” data cluster. Graph 300 also shows example cell current data for the same memory cell without applying a control gate voltage (V CGR = 0V) for, as marked as "untuned V CGR , Erase Read" and "Untuned V CGR , as shown in the data cluster of "Programmed Read".

[0038] like Figure 5 As shown, with no control gate voltage (V CGR =0V), V is applied for reading via the even-numbered rows WL. CGR =-2V can reduce the asymmetry between odd and even rows of programmed state reading (eg, the difference in average sense cell current).

[0039] Figure 6 An exemplary electronic system or device 400 is shown in accordance with an exemplary embodiment. The electronic system or device 400 may include a group or array of flash memory cells 402 (indicated at 402A-402N as described below), logic instructions (e.g., embodied in software or firmware), control circuitry 406 for operating the flash memory cells 402 (e.g., by performing program, erase, and read operations), and any other suitable hardware, software, or firmware for providing the functionality of the corresponding electronic system or device 400.

[0040] The control circuit 406 may be configured to apply a non-zero (positive or negative) bias voltage V to the control gate during a read operation of the corresponding flash memory cell 402 for reading via one or both of the odd and even rows WL. CGR , for example, to improve the programming state reading performance or the erased state reading performance of the corresponding flash memory cell 402, as described above. The control gate read voltage V applied to the corresponding flash memory cell 402 CGR The trim bits 410 may be stored in memory as accessible to the memory control circuit 406 .

[0041] In some embodiments, the control circuit 406 can be configured to apply a different V for reading via odd rows WL compared to even rows WL. CGR , for example, as mentioned above about Figure 5 For example, the control circuit 406 can determine or control whether each corresponding read access is being made to an even row or an odd row, and control the voltage source driving the control gate accordingly. For example, with a non-zero V CGR drive (For example, V CGR=-2V) can indicate an even bit when the bit is 1 and 0V when the bit is 0. Control circuitry 406 can determine whether each read access is for an even or odd row using any technique known in the art (e.g., by multiplexing with the last (least significant or LSB) bit of a memory address counter) or other suitable technique.

[0042] In the illustrated example, the flash memory 402 may include multiple different groups or arrays of flash memory cells 402A-402N, where each group may include one or more flash memory cells, for example, split-gate flash memory cells, such as Figures 1 to 2 In one example embodiment, the flash memory cells 402A-402N may comprise SuperFlash cells (e.g., SuperFlash ESF1+ cells or variations thereof) from Microchip Technology Inc., headquartered at 2355 W Chandler Boulevard, Chandler, Arizona 85224.

[0043] In some embodiments, different groups or arrays of flash memory cells 402A-402N may have different usage characteristics or requirements (e.g., different endurance, read speed, or other usage requirements), different performance characteristics, different physical specifications, or may represent different batches of memory cells manufactured at different times or using different manufacturing parameters. Therefore, to compensate for such differences, or to achieve performance characteristics for different groups of memory cells 402A-402N, control circuitry 406 may adjust the selected control gate read voltage V CGR (or a selected V dedicated to odd or even row reading CGR value) is applied to each corresponding memory cell group 402A to 402N. Figure 6 As shown, a corresponding control gate read voltage value V may be stored for each corresponding flash memory cell group 402A-402N. CGR_A -V CGR_N , for example, as trim bits 410 stored in device memory. The control gate read voltage value V CGR_A -V CGR_N Any number of different voltage values ​​may be included, may include both negative and positive voltage values, and may also include at least one zero value. In other embodiments, a single control gate read voltage value V CGR For all flash memory cells 402 in the device.

[0044] In some embodiments, the device 400 may include a control gate voltage management circuit 420 configured to set and / or dynamically adjust one or more control gate read voltage values ​​V CGR_A -VCGR_N For example, the control gate voltage management circuit 420 may be configured to perform Figure 4A The method 200 is shown to measure the initial program / erase current value of each (or selected) memory cell and to set corresponding value(s) V based on such measurements and / or additional factors (e.g., usage characteristics or requirements, performance characteristics, physical specifications, etc.) of one or more corresponding memory cell groups 402A-402N. CGR Furthermore, in one embodiment, the control gate voltage management circuit 420 can be configured to dynamically adjust the control gate read voltage value V of at least one of the memory cell groups 402A-402N over time, for example based on monitored endurance data of the corresponding memory cells (e.g., using an erase cycle counter), or based on periodic program / erase current measurements made by the circuit 420. CGR .

Claims

1. A method for operating a flash memory cell, the flash memory cell comprising a floating gate, a source region, a word line, a bit line and a control gate, the method comprising: measuring at least one of a programmed state cell current or an erased state cell current of the flash memory cell; and A non-zero control gate voltage V is selected based at least on the measured programmed state cell current and / or erased state cell current. CGR ; performing a programming operation in the flash memory cell; performing an erase operation in the flash memory cell; and Performing read operations in the flash memory cell includes applying the non-zero control gate voltage V to the control gate during each read operation CGR , where a selected non-zero control gate voltage V CGR With V applied during each read operation CGR =0: (a) increasing the programming state read current margin while reducing the erase state read current margin, or (b) increasing the erase state read current margin while reducing the programming state read current margin.

2. The method of claim 1, wherein the flash memory cell comprises a split gate flash memory cell including a pair of floating gates, a respective word line formed over each respective floating gate, and a single control gate extending over the two floating gates.

3. The method of claim 2, wherein the split-gate flash memory cell comprises a SuperFlash ESF1+ cell.

4. The method of claim 1 , wherein a non-zero control gate voltage V is selected and applied. CGR This includes selecting and applying a negative voltage to the control gate during each read operation. 5 . The method of claim 4 , comprising applying a negative voltage of −1 V or less to the control gate during each read operation.

6. The method of claim 1, wherein a non-zero control gate voltage V is selected and applied. CGR This includes selecting and applying a positive voltage to the control gate during each read operation.

7. The method of claim 6, comprising applying a positive voltage of at least 1 V to the control gate during each read operation.

8. The method of claim 1 , wherein the non-zero control gate voltage V applied to the control gate during each read operation CGR With V applied during each read operation CGR =0 changes the sensing unit current compared to.

9. The method of claim 1 , comprising using a trim bit to select the non-zero control gate voltage V CGR .

10. The method of claim 1, wherein measuring at least one of a programmed state cell current or an erased state cell current of the flash memory cell comprises measuring at least one of an initial programmed state cell current or an initial erased state cell current of the flash memory cell after fabrication of the flash memory cell.

11. The method according to claim 1, comprising: Selecting the non-zero control gate voltage V CGR The initial non-zero value of and Dynamically adjust the non-zero control gate voltage V over time CGR The non-zero value of .

12. The method of claim 1 , wherein performing each read operation comprises: applying a first non-zero voltage to the word line; applying a second non-zero voltage to the bit line; and Applying the non-zero control gate voltage V to the control gate CGR . 13 . The method of claim 12 , wherein the second non-zero voltage applied to the bit line is the same voltage as the first non-zero voltage applied to the word line.

14. A method of operating a flash memory cell, the flash memory cell comprising at least one floating gate, at least one source region, an even word line, an odd word line, and a control gate, the method comprising: performing a programming operation in the flash memory cell; performing an erase operation in the flash memory cell; and A read operation is performed via the even word line, including setting the first control gate voltage V CGR_EVEN applied to the control gate; and Performing a read operation via the odd word lines includes converting a control gate voltage V having a voltage different from the first control gate voltage V via the odd word lines during each read operation. CGR_EVEN The value of the second control gate voltage V CGR_ODD applied to the control grid; The first control gate voltage V CGR_EVEN and the second control gate voltage V CGR_ODD At least one of is a non-zero voltage.

15. The method according to claim 14, wherein V CGR_EVEN and V CGR_ODD All are non-zero voltage.

16. The method according to claim 14, wherein V CGR_EVEN and V CGR_ODD One of them is 0V, so that no voltage is applied to the control gate during a read operation via the even word line or during a read operation via the odd word line.

17. A device for operating a flash memory cell, comprising: A plurality of flash memory cells, each flash memory cell comprising a floating gate, a source region, a word line, a bit line and a control gate; as well as A control circuit, the control circuit being configured to: measuring at least one of a programmed state cell current or an erased state cell current of each flash memory cell; and A non-zero control gate voltage V is selected based at least on the measured programmed state cell current and / or erased state cell current. CGR ; performing a programming operation in each flash memory cell; performing an erase operation in each flash memory cell; and A read operation is performed in each flash memory cell, wherein the control circuit is configured to set the non-zero control gate voltage V CGR is applied to the corresponding control gate, where a selected non-zero control gate voltage V CGR With V applied during each read operation CGR =0: (a) increasing the programming state read current margin while reducing the erase state read current margin, or (b) increasing the erase state read current margin while reducing the programming state read current margin.

18. The apparatus of claim 17, comprising a non-zero control gate voltage V stored in memory for the plurality of flash memory cells. CGR value.

19. The apparatus of claim 18, wherein different non-zero control gate voltages V CGR value.

20. The apparatus of claim 17, wherein: Each flash memory cell includes an even word line and an odd word line, and The control circuit is configured to: determining whether each of the read operations is associated with the even wordline or the odd wordline; For each read operation associated with the even word line, the first control gate voltage V CGR_EVEN applied to the control gate; and For each read operation associated with the odd word line, a control gate voltage V CGR_EVEN The value of the second control gate voltage V CGR_ODD applied to the control grid; The first control gate voltage V CGR_EVEN and the second control gate voltage V CGR_ODD At least one of is a non-zero voltage.

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